32K x 8 Radiation Hardened Programmable Read Only Memory (PROM) - 5 V 197A807 Product Description Features Radiation * Fabricated with Bulk CMOS 0.8 m Process * Total Dose Hardness through 2x105 rad(Si) * Neutron Hardness through 1x1012 N/cm2 * SEU Immune (No Latches) * Latchup Free Other * Read/Write Cycle Times 45 ns (-55 C to 125C) * SMD Number 5962R96891 * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V 10% Power Supply * Low Operating Power * Packaging Options * 28-Lead Flat Pack (0.500" x 0.720") General Description The 32K x 8 radiation hardened PROM is pinout, function and package compatible with commercial 28C256 series 32K x EEPROMs, such as SEEQ 28C256 and Atmel AT28C256. The PROM is fabricated with BAE SYSTEMS' QML-qualified radiation hardened technology, and is designed for use in systems operating in radiation environments. The radiation hardened Oxide-Nitride-Oxide (ONO) anti-fuse technology features 0.8 micron, 5 V transistors in the data path, and 1.0 micron, high voltage N and PFETs in the programming path circuitry. The PROM operates over the full military temperature range, requires a single 5 V 10% power supply, and is available with either TTL or CMOS compatible I/O. Power consumption is typically 15 mW/MHz in operation and is less than 10 mW/MHz in the low power disabled mode. The PROM operation is fully asynchronous, with an associated typical access time of 27 nanoseconds. Synchronous operation is also possible using CE as a clock. BAE SYSTEMS' enhanced bulk CMOS technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122 Functional Diagram A5 - A11 Row Decoders Memory Array A0 - A4 Column Decoders A12 - A14 Section Select Column Muxing and Sense Amps CE OE VPP* Control Logic I/O Buffers DQ0 - 7 *PROM Programming Voltage Signal Definitions A: 0-14 - Address input pins that select a particular eight-bit word within the memory array. DQ: 0-7 - Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. OE CE - Chip enable, when at a low level with OE at low level, allows normal operation. When at a high level, CE forces the data output drivers in a high impedance state. - Negative output enable, when at a high level, holds the data output drivers in a high impedance state. In programming mode, with OE high and CE low, data driver state is in "Data-In" to enable programming. Truth Table Mode Inputs(1),(2) Power (3) Standby Standby CE Low Low VDD High OE Low High X X VPP VDD VDD VDD VDD I/O Data-Out High-Z High-Z High-Z Active Active Standby1 Standby2 Program Low High 17V 0.5V Data-In Programming Read Tristate Notes: 1) VIN for don't care (X) inputs = VIL or VIH. 2) High: VIN 2.2 V for TTL inputs. VIN 3.5 V for CMOS inputs. Low: VIN 0.8 V for TTL inputs. VIN 1.5 V for CMOS inputs. 3) Minimum IDD is drawn when standby mode is implemented with CE = VDD (standby1 power). 2 Absolute Maximum Ratings Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Minimum -65C Maximum +150C -55C -0.5 V +125C +7.0 V -0.5 V VDD+ 0.5 V VDD+ 0.5 V -0.5 V Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4) 1.5 W +250C (Class I) Notes: 1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015. Recommended Operating Conditions Symbol VDD VPP Parameters(1) Supply Voltage Programming Voltage Minimum +4.5 VDD (2) Maximum +5.5 VDD (2) Units Volt Volt GND TC Supply Voltage Reference Case Temperature 0.0 -55 0.0 +125 Volt Celsius Input Logic "Low" - CMOS 0.0 +1.5 Input Logic "Low" - TTL 0.0 Input Logic "High" - CMOS +3.5 +0.8 VDD Input Logic "High" - TTL +2.2 VDD VIL VIH Notes: 1) All voltages referenced to GND. 2) VPP = VDD during non-programming mode. Power Sequencing Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: * Power-Up Sequence: GND, VDD, Inputs * Power-Down Sequence: Inputs, VDD, GND 3 Volt Volt DC Electrical Characteristics Symbol Test Conditions(1) Group A Subgroups Device Type (2) Supply Current (Cycling Selected) IDD1 F = FMAX = 1/tAVAV(min) CMOS Input No Output Load 1, 2, 3 All 150 mA Supply Current (Standby) IDD2 F = FMAX = 1/tAVAV(min) CE = VPP = VIH = VDD 1, 2, 3 All 2.0 mA High Level Output Voltage VOH 1, 2, 3 All Low Level Output Voltage VOL 1, 2, 3 All High Level Input Voltage TTL Inputs VIH 1, 2, 3 xxxT Low Level Input Voltage TTL Inputs VIL 1, 2, 3 xxxT High Level Input Voltage CMOS Inputs VIH 1, 2, 3 xxxC Low Level Input Voltage CMOS Inputs VIL 1, 2, 3 xxxC Input Leakage IILK 0 V VIN 5.5 V 1, 2, 3 All Output Leakage IOLK 0 V VOUT 5.5 V 1, 2, 3 All Cin (3) 4 Cout (3) 4 Test IOH= -2 mA IOH = -200 A IOL= 4 mA IOL = 200 A Limits Minimum Maximum 4.2 VDD - 0.1 V Units V 0.4 0.1 2.2 V V 0.8 3.5 V V 1.5 V -5 5 A -10 10 A All 7 pF All 10 pF Note: 2) The delineation in this table is by input device type (TTL or CMOS). xxxT represents a device with TTL inputs; xxxC represents a device with CMOS inputs. 3) Measured during initial device characterization. 1) -55 C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. Test conditions for AC measurements: * Input Levels * Input Rise and Fall Time * Input and Output Timing Reference Levels (Except for Tristate Parameters) * Input and Output Timing Reference Levels or Tristate Parameters * Programmed Array Mix of `1's and `0's * Output Load * Read Cycle - 0 V to VDD - 2.0 ns/Volt - 2.5 V Output Load Circuit - VOL = 0.5 V; VOH = VDD - 0.5 V 300 10% - 50% 2.8V - See Output Load Circuit Diagram - See Read Cycle Timing 50 pF 10% 4 Read Cycle AC Timing Characteristics (1) Limits Minimum Maximum Symbol Device Type Read Cycle Time tAVAV X4XX X6XX Address Access Time tAVQV X4XX X6XX 45 60 ns Chip Enable Access Time tELQV X4XX X6XX 45 60 ns Output Enable Access Time tGLQV X4XX X6XX 45 60 ns Chip Enable to Output Active tELQX 0 ns Output Enable to Output Active tGLQX 0 ns Output Hold After Address Change tAXQX 0 ns Chip Enable to Output Disable tEHQZ 15 ns Output Enable to Output Disable tGHQZ 15 ns Test Units 45 60 ns Note: 1) Test Conditions: -55C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. Read Cycle Timing Diagram tAVAV Valid Address Address tAXQX tAVQV tELQV CE tELQX tEHQZ tGLQV OE tGHQZ tGLQX Data Out Valid Data High Impedance 5 Dynamic Electrical Characteristics The PROM is asynchronous in operation, allowing the read cycle to be controlled by address or chip enable (CE) (refer to Read Cycle Timing diagram). To perform a valid read operation, both chip enable (CE) and output enable (OE) must be low. The output drivers can be controlled independently by the OE signal. Consecutive read cycles can be executed with CE held continuously low, and with OE held continuously low, and toggling the addresses. To control a read cycle with CE, all addresses and OE must be valid prior to or coincident with the enabling CE edge transition. Address or OE edge transitions can occur later than the specified setup times to CE, however, the valid data access time will be delayed. Any address edge transition that occurs during the time when CE is low will initiate a new read access, and data outputs will not become valid until tAVQV time following the address edge transition. Data outputs will enter a high impedance state tEHQZ time following a disabling CE edge transition. For an address-activated read cycle, CE and OE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid tAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is tAVAV. When the PROM is operated at the minimum addressactivated read cycle time, the data outputs will remain valid on the PROM I/O until tAXQX time following the next sequential address transition. To control a read cycle with OE, all addresses and CE must be valid prior to or coincident with the enabling OE edge transition. Address or CE edge transitions can occur later than the specified setup times to OE; however, the valid data access time will be delayed. Any address edge transition that occurs during the time when OE is high will initiate a new read access, and data outputs will not become valid until tAVQV time following the address edge transition. Data outputs will enter a high impedance state tGHQZ time following a disabling OE edge transition. Read Cycle Radiation Characteristics Total Ionizing Radiation Dose The PROM will meet all stated functional and electrical specifications over the entire operating temperature range after a total ionizing radiation dose of 2x105 rad(Si). All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T = 125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and PROM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(Si)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Single Event Effects The PROM has demonstrated no data upset when exposed to ion LETs 124 MeV/mg/cm2. Given that the design uses an anti-fuse for data storage and programmability, Single Event Device Rupture (SEDR) testing was also performed. No SEDR was detected to an effective LET of 88 MeV/mg/cm2. Latchup The PROM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Neutron Radiation The PROM will meet any functional or timing specification after a total neutron fluence of up to 1x1012 cm2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. 6 Radiation Hardness Ratings (1),(2), (3) Symbol Conditions Characteristics Minimum Units Maximum rad(Si) RTD Total Dose 200K SEL Single Event Latchup -55C Tcase 125C Immune Fails/Device-Day SEDR (4) Single Event Dielectric Rupture (anti-fuse) -55C Tcase 125C 0 Upsets/Fuse-Day RNF Neutron Fluence SEU (1) Single Event Upset N/cm 2 1E + 12 -55C Tcase 125C 0 Upsets/Bit-Day Notes: 1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan. 2) Device electrical characteristics are guaranteed for post irradiation levels at 25C, per MIL-STD-883, Test Method 1019.5, Condition A. 3) There are no storage elements on this device. 4) Tested with ions having perpendicular incidence at LET of 60 MeV/mg/cm2, 90% worst case particle environment, geosynchronous orbit, 0.025" of aluminum shielding. Tester AC Timing Characteristics TTL I/O Configuration Input Levels* CMOS I/O Configuration 3V . . . . . . . . . . . . . . . 1.5 V 0V........ VDD- 0.5 V . . . . . . . . . . . . . V /2 DD 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Sense Levels . . . . . . . . . . . . . V /2 DD . . . . . VDD- 0.4 V High Z . . . . . 0.4 V . . . . . VDD- 0.4 V High Z . . . . . 0.4 V High Z 3.4 V . . . . 2.4 V . . . . High Z 3.4 V . . . . 2.4 V . . . . High Z = 2.9 V High Z = 2.9 V *Input rise and fall times <5 ns 7 Radiation Hardness Assurance Reliability BAE SYSTEMS provides a superior quality level of radiation hardness assurance for our products. The excellent product quality is sustained via the use of our qualified QML operation which requires process control with statistical process control, radiation hardness assurance procedures and a rigid computer controlled manufacturing operation monitoring and tracking system. BAE SYSTEMS' reliability starts with an overall product assurance system that utilizes a quality system involving all employees including operators, process engineers and product assurance personnel. An extensive wafer lot acceptance methodology, using in-line electrical data as well as physical data, assures product quality prior to assembly. A continuous reliability monitoring program evaluates every lot at the wafer level, utilizing test structures as well as product testing. Test structures are placed on every wafer, allowing correlation and checks within-wafer, wafer-to-wafer, and from lot-to-lot. The BAE SYSTEMS technology is built with resistance to radiation effects. Our product is designed to exhibit < 1e -11 fails/bit-day in a 90% worst case geosynchronous orbit under worst case operating conditions. Total dose hardness is assured by irradiating test structures on every lot and total dose exposure with Cobalt 60 testing performed quarterly on TCI lots to assure the product is meeting the QML radiation hardness requirements. Reliability attributes of the CMOS process are characterized by testing both irradiated and non-irradiated test structures. The evaluations allow design model and process changes to be incorporated for specific failure mechanisms, i.e., hot carriers, electromigration, and time dependent dielectric breakdown. These enhancements to the operation create a more reliable product. Screening Levels The process reliability is further enhanced by accelerated dynamic life tests of both irradiated and non-irradiated test structures. Screening and testing procedures from the customer are followed to qualify the product. BAE SYSTEMS has two QML screen levels (Q and V) to meet full compliant space applications. For limited performance and evaluation situations, BAE SYSTEMS offers an engineering screen level. A final periodic verification of the quality and reliability of the product is validated by a TCI (Technology Conformance Inspection). Standard Screening Procedure Flow Wafer Lot Acceptance Serialization Destructive Bond Pull QML Level Q V X X X X Sample X Sample Internal Visual Temperature Cycle X X Constant Acceleration X X PIND Radiography Electrical Test Blank Array Dynamic Burn-In Electrical Test Test Row Dynamic Burn-In Final Electrical PDA Fine and Gross Leak External Visual Comments Alternate Method Used Die Traceability MIL-STD-883, TM 2010 X X X X X X X X X X X X X X X 8 X X X Meets Group A < 5% Fallout X X MIL-STD-883, TM 2009 Fuse Stress Methodology There are two main areas of fuse-related failure concerns in programmable devices. The first area of concern is unprogrammed fuses becoming mistakenly programmed over time. The second concern is programmed fuses becoming unprogrammed. With the ONO anti-fuse technology, it has been shown that the programmed anti-fuse actually becomes more reliable over time - that the repeated flow of current strengthens the programmed electrical connection and that the anti-fuse lifetime is greater than other forms of standard CMOS electromigration failure mechanisms. In addition to the normal burn-in cycles, an electrical stress methodology has been implemented that allows screening at wafer test for unprogrammed anti-fuse infant mortality failures and weaker anti-fuses that could diminish programming yield. This is accomplished by applying a higher than normal voltage across all unprogrammed anti-fuses. Specifically, there are two levels of high voltage (9V) stresses applied to unprogrammed anti-fuses at wafer test prior to burnin, and a third cycle of unprogrammed fuse stress applied during the final programmer box personalization. Parts that fail any of these tests are rejected. After personalization, the PROM is operated at 4.5 - 5.5 V, and will not experience subsequent stressing, and does not require additional postprogrammed electrical or temperature stressing. Because antifuse infant mortality failures can be detected and effectively screened, the PROM has as high a level of reliability as standard CMOS processed products. Additional justification for not performing post-programming burn-in will be provided on request. Burn-In Methodology There are two methods of burn-in defined: Blank Array Wordline burn-in and Test Row "Raster" Bitline burn-in. The Blank Array Wordline burn-in is designed to exercise the array cells in a sequence which will activate any latent defects in the array area. This sequence also creates alternate biasing of adjacent lines to detect defects in the wiring levels of the chip. The Test Row "Raster' Bitline burn-in is designed to exercise the device through a series of logic level shifts which simulate the active mode of operation of the device, i.e., exercises decode, sense amps, datapath, and peripheral circuitry. This mode is used to detect defects at the device level of the chip. Through the use of these two burn-in modes, the chip is subjected to an equivalent Q/V level burn-in. Blank Array Wordline Burn-In Pin Listing (1) All I/O pins specified in the burn-in pin lists are driven through individual series resistors (1.6K 10%). Burn-in voltages are defined using the following notation: Voltage Levels * V1: +5.5V (-0% /+10%) - VDD pin is tied to this level. * Vin(0): 0.0 V to +0.4 V - Low level for all programmed signals. * Vin(1): +5.5 V (-0% /+10%) - High level for all programmed signals. * GND Pins: - All module GND pins shall be tied to ground. Test Row "Raster" Burn-In Pin Listing (1) Input Signal Input Signal F/16 F/32 Input A0 Signal A9 High F/2 A10 High A1 F/4 A11 High A2 F/8 A12 F/64 A3 F/16 A13 F/128 Input A0 Signal A9 F A10 A1 F/2 A11 A2 F/4 A12 A3 F/8 A13 A4 F/16 A14 F/64 F/128 F/256 F/512 A4 F/32 A14 F/256 A5 F DQ0-7 F/1024 A5 F DQ0-7 F/512 A6 F/2 CE High CE Low F/4 OE Low Low A6 A7 A7 High OE Low VPP VDD VPP GND A8 F/8 A8 Note: 1) F = square wave, 100 KHz to 1.0 MHz. 9 High Burn-In Circuit V1 C1 = 0.1 F (10%) R = 1.6K (10%) C1 CE R R OE R * * * * * R 32K x 8 PROM A0 R A14 * * * R DQ0 DIN DQ7 Device Programming PROM programming is accomplished using the UnisiteTM Universal Programmer made by Data I/O corporation. Unisite is a tool for programming device technologies and packaging. The Data I/O family of universal programs and corresponding software releases and updates are available direct from Data I/O Corporation (800) 3-DATAIO, Technical Support). A PPI adapter #1007 must also be purchased from Data I/O to interface the PROM flatpack to the Data I/O Programmer Box Unit. The PROM device ID number and programming algorithm information is contained in an internal silicon signature which is read by the programmer box and is transparent to the user. Minimum System Requirements for Device Programming Hardware Unisite Definition Data I/O Programmer Box Function Program the PROMs PPI Adapter #1007 Host or PC Adapter Card for the BAE SYSTEMS 32K x 8 PROM Host * A Minicomputer, i.e., Sun, DEC or Apollo Workstation PC * A DOS-Based Personal Computer i.e., IBM PC or Compatible A Stand-Alone Terminal, i.e., DEC VT 200, Qume VT-101, and the Wyse WY-30/40/70 Family of Terminals Interface with the Unisite Programmer Control the Programmer and Remote Storage of Data Files Terminal Programming Programming Hints Post Programming Hints The PROM array is built with all "1's" and an anti-fuse technology is implemented to program "0's." All unused locations should remain unprogrammed as "1's" to save programming time and allow for additional program locations. The Data I/O Programmer uses slow I/O timings to both program and verify programming of PROM devices. After programming, it is recommended that users test devices at speed over application temperature range to ensure that programmed devices meet the application requirements. 10 Packaging The 32K x 8 PROM is offered in a custom 28-lead FP. The package is constructed of multilayer ceramic (AI2O3) and feature internal power and ground planes. It also features a non-conductive ceramic tie bar on the lead frame. The purpose of the tie bar is to allow electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. All NC pins must be connected to either VDD, GND or an active driver to prevent charge build up in the radiation environment. (NC = no connect.) Optional capacitors can be mounted to the package to 28-Lead Flat Pack Pinout A14 1 28 VDD A12 2 A7 A6 3 4 27 26 VPP A13 25 A8 A5 5 A4 A3 6 7 24 23 A9 A11 A2 8 22 21 OE A10 A1 A0 9 10 20 19 CE DQ7 DQ0 11 18 DQ6 DQ1 DQ2 12 13 17 16 DQ5 DQ4 GND 14 15 DQ3 Top View 28-Lead Flat Pack H G (1) QML (USA) Date Code A (Width) F J A=.017 .002 B=.050 .003 C=.035 .014 D=.400 .020 E=.175 .010 F=.760 .008 G=.500 .008 H=1.650 J=.650 K=.109 (2) Notes: B (Pitch) E D 1) Part mark per device specification. 2) "QML" may not be required per device specification. 3) Dimensions are in inches. K 4) Lead width: .008 .002. C 5) Lead height: .006 .002. 6) Unless otherwise specified, all tolerances are .005". No. 1 Index Index Marks 11 Ordering Information 32K x 8 PROM Memory Device *Part Number 197A807-WXYZ W W Package Type X Speed Designation 1 = 28 Pin Flatpack 4 = 45 ns 6 = 60 ns Y Screen Designation X Y Z Z Input Type 1=QML VV C = CMOS 3=Engineering T = TTL 4=QML VQ 5=QML QQ 7=Customer Specific BAE SYSTEMS reserves the right to make changes to any products herein to improve reliability, function or design. BAE SYSTEMS does not assume liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. BAE SYSTEMS An ISO 9001, AS9000, ISO 14001, and SEI CMM Level 4 Company 9300 Wellington Road, Manassas, VA 20110-4122 866-530-8104 http://www.baesystems-iews.com/space/ 0040_32K_8_PROM.ppt Cleared for Public Domain Release (c)2001 BAE SYSTEMS, All Rights Reserved BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122