6
Dynamic Electrical Characteristics
Radiation Characteristics
Total Ionizing Radiation Dose
The PROM will meet all stated functional and electrical
specifications over the entire operating temperature range
after a total ionizing radiation dose of 2x105 rad(Si). All
electrical and timing performance parameters will remain
within specifications after rebound at VDD = 5.5 V and T =
125°C extrapolated to ten years of operation. Total dose
hardness is assured by wafer level testing of process monitor
transistors and PROM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations
have been made between 10 keV X-rays applied at a dose
rate of 1x105 rad(Si)/min at T = 25°C and gamma rays (Cobalt
60 source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test environments.
Neutron Radiation
The PROM will meet any functional or timing specification after
a total neutron fluence of up to 1x1012 cm2 applied under
recommended operating or storage conditions. This assumes
an equivalent neutron energy of 1 MeV.
Single Event Effects
The PROM has demonstrated no data upset when exposed
to ion LETs ≤124 MeV/mg/cm2. Given that the design uses
an anti-fuse for data storage and programmability, Single
Event Device Rupture (SEDR) testing was also performed.
No SEDR was detected to an effective LET of 88
MeV/mg/cm2.
Latchup
The PROM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions.
Read Cycle
The PROM is asynchronous in operation, allowing the read
cycle to be controlled by address or chip enable (CE) (refer to
Read Cycle Timing diagram). To perform a valid read operation,
both chip enable (CE) and output enable (OE) must be low. The
output drivers can be controlled independently by the OE
signal. Consecutive read cycles can be executed with CE held
continuously low, and with OE held continuously low, and
toggling the addresses.
For an address-activated read cycle, CE and OE must be valid
prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between address
edge transitions is permissible; however, data outputs will
become valid tAVQV time following the latest occurring address
edge transition. The minimum address activated read cycle time
is tAVAV. When the PROM is operated at the minimum address-
activated read cycle time, the data outputs will remain valid on
the PROM I/O until tAXQX time following the next sequential
address transition.
To control a read cycle with CE, all addresses and OE
must be valid prior to or coincident with the enabling CE
edge transition. Address or OE edge transitions can occur
later than the specified setup times to CE, however, the
valid data access time will be delayed. Any address edge
transition that occurs during the time when CE is low will
initiate a new read access, and data outputs will not
become valid until tAVQV time following the address edge
transition. Data outputs will enter a high impedance state
tEHQZ time following a disabling CE edge transition.
To control a read cycle with OE, all addresses and CE
must be valid prior to or coincident with the enabling OE
edge transition. Address or CE edge transitions can occur
later than the specified setup times to OE; however, the
valid data access time will be delayed. Any address edge
transition that occurs during the time when OE is high will
initiate a new read access, and data outputs will not
become valid until tAVQV time following the address edge
transition. Data outputs will enter a high impedance state
tGHQZ time following a disabling OE edge transition.