DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 1 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
NOTE 2 The timing specification of high speed bin is backward compatible with low speed bin.
NOTE 3 Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
NOTE 4 SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
NOTE 5 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
NOTE 6 Violating tRFC specification will induce malfunction.
NOTE 7 Only Support prime DQ’s feedback for each byte lane.
Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Programmable Functions
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Features
Organization
512Mb x 8
256Mb x 16
Bank Address
BA0 – BA2
BA0 – BA2
Auto precharge
A10 / AP
A10 / AP
BL switch on the fly
A12 / 
A12 / 
Row Address
A0 – A15
A0 – A14
Column Address
A0 – A9
A0 – A9
Page Size
1KB
2KB
tREFI(us) 5
Tc<=85℃:7.8, Tc>85℃:3.9
tRFC(ns) 6
260ns
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
4Gb
(Org. / Package)
Length x Width
(mm)
Ball pitch
(mm)
512Mbx8
78-ball
TFBGA
9.00 x 10.50
0.80
256Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 11-11-11
Options
Nanya Technology Corp.
NT5CB(C)512M8CN / NT5CB(C)256M16CP
NTC has the rights to change any specifications or product without notification.
Temperature Range (Tc) 5
- Commercial Grade = 0℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 2 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Core Timing
DDR3-2133, DDR3(L)-1866, DDR3(L)-1600 and DDR3(L)-1333
Speed Bins
DDR3-2133
DDR3(L)-1866
DDR3(L)-1600
DDR3(L)-1333
Unit
14-14-14
13-13-13
11-11-11
9-9-9
10-10-10
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tAA
13.09
20
13.91
20
13.75
20
13.5
20
15
20
ns
tRCD
13.09
-
13.91
-
13.75
-
13.5
-
15
-
ns
tRP
13.09
-
13.91
-
13.75
-
13.5
-
15
-
ns
tRC
46.09
-
47.91
-
48.75
-
49.5
-
51
-
ns
tRAS
33
9*tREFI
34
9*tREFI
35
9*tREFI
36
9*tREFI
36
9*tREFI
ns
DDR3(L)-1066 and DDR3(L)-800
Speed Bins
DDR3(L)-1066
DDR3(L)-800
Unit
7-7-7
8-8-8
5-5-5
6-6-6
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tAA
13.125
20
15
20
12.5
20
15
20
ns
tRCD
13.125
-
15
-
12.5
-
15
-
ns
tRP
13.125
-
15
-
12.5
-
15
-
ns
tRC
50.625
-
52.5
-
50
-
52.5
-
ns
tRAS
37.5
9*tREFI
37.5
9*tREFI
37.5
9*tREFI
37.5
9*tREFI
ns
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 3 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Descriptions
The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits.
It is internally configured as an octal-bank DRAM.
The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous
devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or
differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in
BGA packages.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 4 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Ordering Information
Organization
Part Number
Package
Speed3
Clock
(MHz)
Data Rate
(Mb/s)
CL-TRCD-TRP
DDR3 Commercial Grade
512M x 8
NT5CB512M8CN-DI
78-Ball
800
DDR3-1600
11-11-11
NT5CB512M8CN-EK
933
DDR3-1866
13-13-13
NT5CB512M8CN-FL
1066
DDR3-2133
14-14-14
256M x 16
NT5CB256M16CP-DI
96-Ball
800
DDR3-1600
11-11-11
NT5CB256M16CP-EK
933
DDR3-1866
13-13-13
NT5CB256M16CP-FL
1066
DDR3-2133
14-14-14
DDR3L Commercial Grade
Organization
Part Number
Package
Speed3
Clock
(MHz)
Data Rate
(Mb/s)
CL-TRCD-TRP
512M x 8
NT5CC512M8CN-DI
78-Ball
800
DDR3L-1600 4
11-11-11
NT5CC512M8CN-DIB1
800
DDR3L RS-1600
11-11-11
NT5CC512M8CN-EK
933
DDR3L-1866 4
13-13-13
256M x 16
NT5CC256M16CP-DI
96-Ball
800
DDR3L-1600 4
11-11-11
NT5CC256M16CP-DIB1
800
DDR3L RS-1600
11-11-11
NT5CC256M16CP-EK
933
DDR3L-1866 4
13-13-13
DDR3(L) Industrial Grade
512M x 8
NT5CB512M8CN-DII
78-Ball
800
DDR3-1600
11-11-11
NT5CC512M8CN-DII
800
DDR3L-1600 4
11-11-11
256M x 16
NT5CB256M16CP-DII
96-Ball
800
DDR3-1600
11-11-11
NT5CC256M16CP-DII
800
DDR3L-1600 4
11-11-11
DDR3 Automotive Grade 2 2
256M x 16
NT5CB256M16CP-DIH
96-Ball
800
DDR3-1600
11-11-11
DDR3 Automotive Grade 3 2
256M x 16
NT5CB256M16CP-DIA
96-Ball
800
DDR3-1600
11-11-11
NOTE 1 Reduced Standby
NOTE 2 Please confirm with NTC for the available schedule.
NOTE 3 The timing specification of high speed bin is backward compatible with low speed bin.
NOTE 4 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional and
unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 5 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
NT
NANYA
Technology
5C
Product Family
5S = SDRAM
5D = DDR SDRAM
5T = DDR2 SDRAM
5C = DDR3 SDRAM
B512M8 C N DI
NANYA Component Part Numbering Guide
Organization (Depth , Width)
4M 16 = 8M8 = 64Mb
8M 16 = 16M8 = 128Mb
16M 16 = 32M8 = 64M4 = 256Mb
32M 16 = 64M8 = 128M4 = 512Mb
64M 16 = 128M8 = 256M4 = 1Gb
128M 16 = 256M8 = 512M4 = 2Gb
256M 16 = 512M8 =1024M4 = 4Gb
Note: M=Mono
Device Version
A = 1st Version B = 2nd Version
C = 3rd Version D = 4th Version
E = 5th Version F = 6th Version
G = 7th Version H = 8th Version
Speed
SDRAM
75B = PC-133 3-3-3
6K = PC-166 3-3-3
DDR SDRAM
6K = DDR - 333 2.5-3-3
5T = DDR - 400 3-3-3
DDR2 SDRAM
5A = DDR2 - 400 3-3-3
37B = DDR2 - 533 4-4-4
3C = DDR2 - 667 5-5-5
25C/AC = DDR2 - 800 5-5-5
25D/AD = DDR2 - 800 6-6-6
BE = DDR2-1066 7-7-7
BD = DDR2-1066 6-6-6
DDR3 SDRAM
AC = DDR3 - 800 5-5-5
AD = DDR3 - 800 6-6-6
BE = DDR3 - 1066 7-7-7
BF = DDR3 - 1066 8-8-8
CF = DDR3 - 1333 8-8-8
CG = DDR3 - 1333 9-9-9
DH = DDR3 - 1600 10-10-10
DI = DDR3 - 1600 11-11-11
EJ = DDR3 - 1866 12-12-12
EK = DDR3 - 1866 13-13-13
Special Type Option
Package Code
RoHS + Halogen Free
S= TSOP (II)
N=78-Ball BGA
P=96-Ball BGA
E=60-Ball BGA
J=68-Ball BGA
M=92-Ball BGA
U=71-Ball BGA
Y=63-Ball BGA
G=DDR1 BGA / DDR2 84-Ball BGA
8=136-Ball BGA
FK = DDR3 - 2133 13-13-13
Interface & Power ( VDD & VDDQ )
V = LVTTL (3.3V, 3.3V)
E = LVTTL (2.5V, 2.5V)
S = (2.5V, 2.5V)
M = LVTTL (1.8V, 1.8V)
U = SSTL_ 18 (1.8V, 1.8V)
B = SSTL_ 15 (1.5V, 1.5V)
A = SSTL_ 18 (2.0V, 2.0V)
C = SSTL_135 (1.35V, 1.35V)
SSTL_2
F= SSTL 125 (1.25V , .1.25V
_ )
DG = DDR3- 1600 9-9-9
FL = DDR3- 2133 14-14-14
I = Industrial Grade
B = Reduced Standby
H = Automotive Grade 2
A = Automotive Grade 3
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 6 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Ball Configuration – 78 Ball BGA Package (X8)
<TOP View>
See the balls through the package
1 2 3 4 5 6 7 8 9
AVSS VDD NC
NU,T VSS VDD A
BVSS VSSQ DQ0 DM,TDQS VSSQ VDDQ B
CVDDQ DQ2 DQS DQ1 DQ3 VSSQ C
DVSSQ DQ6 VDD VSS VSSQ D
EVREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E
FNC VSS RA CK VSS NC F
GODT VDD A  VDD CKE G
HNC  WE A10/AP ZQ NC H
JVSS BA0 BA2 A15 VREFCA VSS J
KVDD A3 A0
A12/ BA1 VDD K
LVSS A5 A2 A1 A4 VSS L
MVDD A7 A9 A11 A6 VDD M
NVSS REET A13 A14 A8 VSS N
1 2 3 4 5 6 7 8 9
Unit: mm
* BSC (Basic Spacing between Center)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 7 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Ball Configuration – 96 Ball BGA Package (X16)
<TOP View>
See the balls through the package
1 2 3 4 5 6 7 8 9
AVDDQ DQU5 DQU7 DQU4 VDDQ VSS A
BVSSQ VDD VSS U DQU6 VSSQ B
CVDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
DVSSQ VDDQ DMU DQU0 VSSQ VDD D
EVSS VSSQ DQL0 DML VSSQ VDDQ E
FVDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
GVSSQ DQL6 L VDD VSS VSSQ G
HVREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
JNC VSS RA CK VSS NC J
KODT VDD A  VDD CKE K
LNC  WE A10/AP ZQ NC L
MVSS BA0 BA2 NC VREFCA VSS M
NVDD A3 A0
A12/ BA1 VDD N
PVSS A5 A2 A1 A4 VSS P
RVDD A7 A9 A11 A6 VDD R
TVSS REET A13 A14 A8 VSS T
1 2 3 4 5 6 7 8 9
Unit: mm
* BSC (Basic Spacing between Center)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 8 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Ball Descriptions
Symbol
Type
Function

Input
Clock: CK and  are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of .
CKE
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence,
it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.

Input
Chip Select: All commands are masked when  is registered high.  provides for external
rank selection on systems with multiple memory ranks.  is considered part of the command
code.
RA, A, WE
Input
Command Inputs: RA, A and WE (along with ) define the command being entered.
For x8,
DM
For x16,
DMU, DML
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/T is enabled by Mode Register
A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
A10 / AP
Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only
one bank is to be precharged, the bank is selected by bank addresses.
For x8,
A0 – A15
For x16,
A0 – A14
Input
Address Inputs: Provide the row address for Activate commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/ have additional function as below.) The address inputs also provide the
op-code during Mode Register Set commands.
A12/
Input
Burst Chop: A12/is sampled during Read and Write commands to determine if burst chop
(on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, and DM/TDQS, NU/T
(when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 9 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Symbol
Type
Function
REET
Input
Active Low Asynchronous Reset: Reset is active when REET is LOW, and inactive when
REET is HIGH. REET must be HIGH during normal operation. REET is a CMOS rail to rail
signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V.
DQ
Input/output
Data Inputs/Output: Bi-directional data bus. DQ0 is the prime DQ in a low byte lane of
x4/x8/x16 configuration and DQ8 is the prime DQ in a high byte lane of x16 configuration for write
leveling.
For x8,
DQS, ()
For x16,
DQSL,(L),
DQSU,(U)
Input/output
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered
with write data. The data strobes DQS, DQSL, DQSU are paired with differential signals ,
L, U, respectively, to provide differential pair signaling to the system during both reads
and writes. DDR3 SDRAM supports differential data strobe only and does not support
single-ended.
For x8,
TDQS, (T)
Output
Termination Data Strobe: TDQS/T is applicable for X8 DRAMs only. When enabled via
Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on
TDQS/T that is applied to DQS/. When disabled via mode register A11=0 in MR1,
DM/T will provide the data mask function and T is not used. x16 DRAMs must disable the
TDQS function via mode register A11=0 in MR1.
NC
-
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V
VDD
Supply
Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V
VSSQ
Supply
DQ Ground
VSS
Supply
Ground
VREFCA
Supply
Reference voltage for CA
VREFDQ
Supply
Reference voltage for DQ
ZQ
Supply
Reference pin for ZQ calibration.
Notes:
1. Input only pins (BA0-BA2, A0-A15, RA, A, WE, , CKE, ODT, and REET) do not supply termination.
2. The signal may show up in a different symbol but it indicates the same thing. e.g., /CK = CK# =  = CKb, /DQS = DQS# =
 = DQSb, /CS = CS# =  = CSb.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 10 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Simplified State Diagram
Power
ON
Power
Applied Reset
Procedure
From any
State RESET
Initialization
ZQ Calibration Idle
MRS, MPR,
Write
Levelizing Self Refresh
Refreshing
SRE
SRX
REF
Activating
ACT
Precharge
Power
Down
PDE
PDX
Active
Power
Down
Bank
Active
Writing
Writing
Precharging
Reading
Write
Write A Read A
Write Read
Write A Read A
Write
Read
PRE,
PREA PRE,
PREA
Write A Read A
PRE,
PREA
PDX
PDE
Reading
Read
Automatic
Sequence
Command
Sequence
MRSZQCL
ZQCL
ZQCS
State Diagram Command Definitions
Abbr.
Function
Abbr.
Function
Abbr.
Function
ACT
Active
Read
RD, RDS4, RDS8
PDE
Enter Power-down
PRE
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Exit Power-down
PREA
Precharge All
Write
WR, WRS4, WRS8
SRE
Self-Refresh entry
MRS
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Self-Refresh exit
REF
Refresh
RESET
Start RESET Procedure
MPR
Multi-Purpose Register
ZQCL
ZQ Calibration Long
ZQCS
ZQ Calibration Short
-
-
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 11 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Basic Functionality
The DDR3(L) SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM.
The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is
combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst
length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A15 select the row). The
address bit registered coincident with the Read or Write command are used to select the starting column location for the
burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the
fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
RESET and Initialization Procedure
Power-up Initialization sequence
The Following sequence is required for POWER UP and Initialization
1. Apply power (REET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). REET
needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before REETbeing
de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms;
and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once
power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one
side and must be larger than or equal to VSSQ and VSS on the other side.
2. After REETis de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start
internal state initialization; this will be done independently of external clocks.
3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or
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Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
4. The DDR3(L) DRAM will keep its on-die termination in high impedance state as long as REETis asserted. Further,
the DRAM keeps its on-die termination in high impedance state after REET de-assertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the
ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [TXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 (L) SDRAM is now ready for normal operation.
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Reset and Initialization Sequence at Power- on Ramping (Cont’d)
CK
CK
tCKSRX
RESET
CKE
tIS
ODT
Command
BA0-BA2
T=200us T=500us tXPR tMRD tMRD tMRD tMOD tZQinit.
Do Not
Care Time break
10ns
MRSMRS MRS MRS ZQCL
MR2 MR3 MR1 MR0
VDD,
VDDQ
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Te Tk
NOP* NOP* Valid
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
TdTcTa Tb Tf Tg Th Ti Tj
tDLLK
Valid
Valid
Reset Procedure at Stable Power (Cont’d)
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be
maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3 (L) SDRAM is ready for normal operation.
Reset Procedure at Power Stable Condition
CK
CK
tCKSRX
RESET
CKE
tIS
ODT
Command
BA0-BA2
T=100ns T=500us tXPR tMRD tMRD tMRD tMOD tZQinit.
Do Not
Care Time break
10ns
MRSMRS MRS MRS ZQCL
MR2 MR3 MR1 MR0
VDD,
VDDQ
* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.
Te Tk
NOP* NOP* Valid
Valid
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
TdTcTa Tb Tf Tg Th Ti Tj
tDLLK
Valid
Valid
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VDDQ/VDDQ Voltage Switch Between DDR3L and DDR3
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Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the
DDR3 (L) SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As
the default values of the Mode Registers (R) are not defined, contents of Mode Registers must be fully initialized and/or
re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be
altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the
user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be
redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean
these commands can be executed any time after power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the
minimum time required between two MRS commands shown as below.
tMRD Timing
CK
CK
CKE
Do not
Care Time break
MRS NOP NOP NOP NOPCMD
VAL VALADDR
tMRD
MRS
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset,
and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the
following figure.
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tMOD Timing
CK
CK
CKE
MRS NOP NOP NOP NOPCMD
ADDR
tMOD
Non
MRS
VAL
Old Setting Updating Setting New Setting
VAL
VAL
Programming the Mode Registers (Cont’d)
The mode register contents can be changed using the same command and timing requirements during normal operation as
long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed
and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the
functionality and/or modes.
Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include
various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by
asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
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MR0 Definition
BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
0 0 PPD DLL TM RBT CL
A12 A8 A3
0 0 0
1 1 1
BA1 BA0 MR select A7
0 0 MR0 0
0 1 MR1 1 A1 A0
1 0 MR2 0 0
1 1 MR3 0 1
1 0
A11 A10 A9 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A6 A5 A4 A2
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
WR
CAS Latency
BL
MR select
Slow exit(DLL off)
PPD
Fast exit(DLL on)
WR
DLL Reset
No
Yes
mode
Normal
Test
Reserved
Read Burst Type
Nibble Sequential
Interleave
5
6
7
8
12
14
16
10
11
10
12
Reserved
Reserved
BC4(Fixed)
BL
8(Fixed)
BC4 or 8 (on the fly)
Reserved
CAS Latency
5
Reserved
Reserved
6
7
8
9
13
14
Reserved
*1: BA2 and A13~A15 are RFU and must be programmed to 0 during MRS.
*2: WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next
integer: WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than
WRmin. The programmed WR value is used with tRP to determine tDAL.
*3: The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each frequency
*4: The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timingtable.
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Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,
burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,
fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write
command via A12/.
Burst Type and Burst Order
Burst
Length
Read
Write
Starting
Column
Address
(A2,A1,A0)
Burst type:
Sequential
(decimal)
A3 = 0
Burst type:
Interleaved
(decimal)
A3 = 1
Note
4
Chop
Read
0,0,0
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1,2,3
0,0,1
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
0,1,0
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
0,1,1
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1,0,0
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1,0,1
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1,1,0
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1,1,1
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
Write
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1,2,4,5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
8
Read
0,0,0
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
0,0,1
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
0,1,0
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
0,1,1
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
1,0,0
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
1,0,1
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
1,1,0
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
1,1,1
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
Write
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2,4
Note:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8
mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected
on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that
during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Do not Care.
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CAS Latency
The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in
clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does
not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency
(CL); RL = AL + CL.
Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0
definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM
manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.
DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.
Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK
must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous
operations.)
Write Recovery
The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to
determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)
and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be
equal or larger than tWR (min).
Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,
the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be
met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge
power-down and upon exiting power-down requires tXP to be met prior to the next valid command.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive
latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , RA, A, WE high on
BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure.
MR1 Definition
BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
0 0 Qoff
TDQS
0Rtt_Nom 0 Level Rtt_Nom D.I.C Rtt_Nom D.I.C DLL
A11 TDQS A9 A6 A2 A4 A3
0 Disabled 0 0 0 0 0
1 Enabled 0 0 1 0 1
0 1 0 1 0
BA1 BA0 MR select 0 1 1 1 1
0 0 MR0 1 0 0
0 1 MR1 1 0 1 A0
1 0 MR2 1 1 0 0
1 1 MR3 1 1 1 1
A7 A5 A1
0 0 0
1 0 1
1 0
1 1
A12
0
1
Output buffer disabled
RZQ/12
RZQ/8
Reserved
Reserved
AL
Disabled
CL-1
CL-2
Reserved
AL
DLL Enable
Enable
Disable
RZQ/6
Reserved
Qoff
Output buffer enabled
Output Driver Impedance
RZQ/7
Reserved
Write Leveling enable
Disabled
RZQ/4
Disabled
Enabled
MR select
Rtt_Nom
RZQ/2
RZQ/6
* 1 : BA2 and A8, A10, and A13 ~ A15 are RFU and must be programmed to 0 during MRS.
*2: Outputs disabled - DQs, DQSs, s.
*3: RZQ = 240
*4: In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] = 1) with
MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
*5: If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
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DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to
normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is
automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh
operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or
synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.
Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During
tDLLK, CKE must continuously be registered high. DDR3(L) SDRAM does not require DLL for any Write operation, expect
when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable
operation in DLL-off Mode.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-
ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register
set command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9}
= {0, 0}, to disable Dynamic ODT externally.
Output Driver Impedance Control
The output driver impedance of the DDR3(L) SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1 definition
figure.
ODT Rtt Values
DDR3(L) SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination
value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt
value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
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Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L)
SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to
be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is
issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings.
Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL
register options are shown as the following table.
Additive Latency (AL) Settings
A4
A3
AL
0
0
0, (AL Disable)
0
1
CL-1
1
0
CL-2
1
1
Reserved
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Write leveling
For better signal integrity, DDR3(L) memory module adopted fly by topology for the commands, addresses, control signals,
and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes
flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS,
tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’ in DDR3(L) SDRAM to compensate
for skew.
Output Disable
The DDR3(L) SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is
enabled (A12=1) all output pins (DQs, DQS, , etc.) are disconnected from the device removing any loading of the
output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should
be set to ‘0’.
TDQS, T
TDQS (Termination Data Strobe) is a feature of x8 DDR3(L) SDRAM that provides additional termination resistance outputs
that may be useful in some system configurations.
When enabled via the mode register, the same termination resistance function is applied to be TDQS/T pins that are
applied to the DQS/ pins.
In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data
strobe function of RDQS is not provided by TDQS.
The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM
function is not supported. When the TDQS function is disabled, the DM function is provided and the T pin is not used.
The TDQS function is available in x8 DDR3(L) SDRAM only and must be disabled via the mode register A11=0 in MR1 for
x16 configurations.
TDQS, T Function Matrix
MR1 (A11)
DM / TDQS
NU / TDQS
0 (TDQS Disabled)
DM
Hi-Z
1 (TDQS Enabled)
TDQS
T
Note:
1. If TDQS is enabled, the DM function is disabled.
2. When not used, TDQS function can be disabled to save termination power.
3. TDQS function is only available for x8 DRAM and must be disabled for x16.
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Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency.
The Mode Register 2 is written by asserting low on , RA, A, WE high on BA1 and low on BA0 and BA2, while
controlling the states of address pins according to the table below.
MR2 Definition
BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
0 0 SRT ASR
A6 A2 A1 A0
0 0 0 0
1 0 0 1
0 1 0
0 1 1
1 0 0
A10 A9 1 0 1
0 0 1 1 0
0 1 1 1 1
1 0
1 1
A5 A4 A3
0 0 0
A7 0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
BA1 BA0 1 1 1
0 0
0 1
1 0
1 1
Quarter Array (BA[2:0]=110, &111)
1/8th Array (BA[2:0]=111)
PASR
Full Array
HalfArray (BA[2:0]=000,001,010, &011)
Quarter Array (BA[2:0]=000, & 001)
1/8th Array (BA[2:0] = 000)
3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)
HalfArray (BA[2:0] = 100, 101, 110, &111)
MR select
0
Rtt_WR
CWL
PASR
RFU
CWL
7 (1.875ns>=tCK(avg)>=1.5ns)
8 (1.5ns>=tCK(avg)>=1.25ns)
9 (1.25ns>=tCK(avg)>=1.07ns)
ASR
Manual SR Reference (SRT)
ASR enable
Rtt_WR
Dynamic ODT off
RZQ/4
RZQ/2
Reserved
6 (2.5ns>=tCK(avg)>=1.875ns)
SRT
MR select
MR0
10 (1.07ns>=tCK(avg)>=0.935ns)
RFU
5 (tCK(avg)>=2.5ns)
MR1
MR2
MR3
Normal operating
temperature range
Extended operating
temperature range
0
1
* 1 : Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
* 2 : BA2, A5, A8, A11 ~ A15 are RFU and must be programmed to 0 during MRS.
* 3 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.
DDR3(L) 4Gb SDRAM
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CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles,
between the internal Write command and the availability of the first bit of input data. DDR3(L) DRAM does not support any
half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL);
WL=AL+CWL.
Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)
DDR3(L) SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh
operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately.
Optional in DDR3(L) SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if
DDR3(L) SDRAM devices support the following options or requirements referred to in this material. For more details refer to
“Extended Temperature Usage”. DDR3(L) SDRAMs must support Self-Refresh operation at all supported temperatures.
Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional ASR function or
program the SRT bit appropriately.
Dynamic ODT (Rtt_WR)
DDR3(L) SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without
issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling
mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
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Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , RA, A,
WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below.
MR3 Definition
BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
0 MPR
A2 A1 A0
0 0 0
1 0 1
1 0
BA1 BA0 MR select 1 1
0 0 MR0
0 1 MR1
1 0 MR2
1 1 MR3
Normal operation
Dataflow from MPR
MPR Loc
0
Predefined pattern
Reserved
Reserved
Reserved
MPR Loc
MPR
MR select
* 1 : BA2, A3 - A15 are RFU and must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
DDR3(L) 4Gb SDRAM
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Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To
enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or
RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power
down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET
function is supported during MPR enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence.
Fig. 1: MPR Block Diagram
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, prior to issuing
the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or
RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown. When the MPR is enabled,
only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 =
0). Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of
RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable
mode. The RESET function is supported during MPR enable mode.
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MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
don't care (0b or 1b)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
1b
See MR3 Table
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
• One bit wide logical interface via all DQ pins during READ operation.
• Register Read on x8:
• DQ[0] drives information from MPR.
• DQ[7:1] either drive the same information as DQ [0], or they drive 0b.
• Register Read on x16:
• DQL[0] and DQU[0] drive information from MPR.
• DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
• Addressing during for Multi Purpose Register reads for all MPR agents:
• BA [2:0]: don’t care
• A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
• A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst
order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *)
• A[9:3]: don’t care
• A10/AP: don’t care
• A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
• A11, A13... (if available): don’t care
• Regular interface functionality during register reads:
• Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
• Support of read burst chop (MRS and on-the-fly via A12/BC)
• All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3(L)
SDRAM.
• Regular read latencies and AC timings apply.
• DLL must be locked prior to MPR Reads.
NOTE: *Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
DDR3(L) 4Gb SDRAM
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MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
Burst Length
Read Address
A[2:0]
Burst Order
and Data Pattern
1b
00b
Read Predefined
Pattern for System
Calibration
BL8
000b
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
1b
01b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
10b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
11b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
DDR3(L) 4Gb SDRAM
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DDR3(L) SDRAM Command Description and Operation
Command Truth Table
Function
Abbr.
CKE

RA
A
WE
BA0-
BA2
A13-
A15
A12-

A10-
AP
A0-
A9,
A11
NOTES
Previous
Cycle
Current
Cycle
Mode Register Set
MRS
H
H
L
L
L
L
BA
OP Code
Refresh
REF
H
H
L
L
L
H
V
V
V
V
V
Self Refresh Entry
SRE
H
L
L
L
L
H
V
V
V
V
V
7,9,12
Self Refresh Exit
SRX
L
H
H
X
X
X
X
X
X
X
X
7,8,9,12
L
H
H
H
V
V
V
V
V
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Row Address (RA)
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
Write with Auto Precharge (Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
Write with Auto Precharge (BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
RFU
L
H
CA
Write with Auto Precharge (BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
RFU
H
H
CA
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
Read (BC4, on the Fly
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
Read with Auto Precharge (Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
Read with Auto Precharge (BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
Read with Auto Precharge (BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
Power Down Exit
PDX
L
H
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
X
L
X
DDR3(L) 4Gb SDRAM
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DDR3(L) SDRAM Command Description and Operation
Command Truth Table (Conti.)
NOTE1. All DDR3(L) SDRAM commands are defined by states of , RA, A, WEand CKE at the rising edge of the clock. The MSB of
BA, RA and CA are device density and configuration dependant.
NOTE2. REET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
NOTE6. The Power-Down Mode does not perform any refresh operation.
NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
NOTE8. Self Refresh Exit is asynchronous.
NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.
NOTE10. The No Operation command should be used in cases when the DDR3(L) SDRAM is in an idle or wait state. The purpose of the
No Operation command (NOP) is to prevent the DDR3(L) SDRAM from registering any unwanted commands between operations.
A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle.
NOTE11. The Deselect command performs the same function as No Operation command.
NOTE12. Refer to the CKE Truth Table for more detail with CKE transition.
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CKE Truth Table
Current State
CKE
Command (N)
RA, A,WE, 
Action (N)
Notes
Previous Cycle
(N-1)
Current Cycle
(N)
Power-Down
L
L
X
Maintain Power-Down
14,15
L
H
DESELECT or NOP
Power-Down Exit
11,14
Self-Refresh
L
L
X
Maintain Self-Refresh
15,16
L
H
DESELECT or NOP
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power-Down Entry
11
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down Entry
11,13,14,18
H
L
REFRESH
Self-Refresh
9,13,18
NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
NOTE 2 Current state is defined as the state of the DDR3(L) SDRAM immediately prior to clock edge N.
NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition, CKE may
not transition from its valid level during the time period of tIS + tCKEmin + tIH.
NOTE 7 DESELECT and NOP are defined in the Command Truth Table.
NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period.
Read or ODT commands may be issued only after tXSDLL is satisfied.
NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state.
NOTE 10 Must be a legal command as defined in the Command Truth Table.
NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only.
NOTE 13 Self-Refresh cannot be entered during Read or Write operations.
NOTE 14 The Power-Down does not perform any refresh operations.
NOTE 15 “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.
NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.
NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered,
otherwise Active Power-Down is entered.
NOTE 18 ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all
Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3(L) SDRAM to perform a NOP (low and RA,
A, and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
Deselect Command
The Deselect function (HIGH) prevents new commands from being executed by the DDR3(L) SDRAM. The DDR3(L)
SDRAM is effectively deselected. Operations already in progress are not affected.
DLL- Off Mode
DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0
bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3(L). The maximum clock frequency for DLL-off
Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the
refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)
in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data
relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,
the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be
small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is
significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
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DLL-off mode READ Timing Operation
Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same
way and the skew between all DQ, DQS, and signals will still be tDQSQ.
CK
CK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
READ
CMD
Bank, Col b
Address
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
DQSdiff_DLL_on
DQ_DLL_on
DQSdiff_DLL_off
DQ_DLL_off
DQSdiff_DLL_off
DQ_DLL_off
RL = AL+CL = 6 (CL=6, AL=0)
RL(DLL_off) = AL+(CL-1) = 5 tDQSCKDLL_diff_min
tDQSCKDLL_diff_max
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
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DLL on/off switching procedure
DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit
set back to “0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following
procedure:
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must
be in high impedance state before MRS to MR1 to disable the DLL).
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any
MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh
mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS
command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered,
ODT signal can be registered LOW or HIGH.
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, and then DRAM is ready for next command.
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DLL Switch Sequence from DLL-on to DLL-off
CK
CK
T0 T1 T
a0T
a1T
b0T
c0T
d0T
d1T
e0T
e1
MRS 2)
1)
CMD
CKE
ODT
tMOD
T
f0
tCKSRE 4) tCKSRX 5) tXS tMOD
NOP SRE 3) NOP SRX 6) NOP MRS 7) NOP Vali
d 8)
tCKESR
Vali
d 8)
Vali
d 8)
Tim
e
break
Do
not
Car
e
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting with Idle State, RTT in Hi-Z State.
2) Disable DLL by setting MR1 Bit A0 to 1.
3) Enter SR.
4) Change Frequency.
5) Clock must be stable at least tCKSRX.
6) Exit SR.
7) Update Mode registers with DLL off parameters setting.
8) Any valid command.
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DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must
be in high impedance state before Self-Refresh mode is entered).
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with “Input clock frequency change” section.
4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subse-
quent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self
Refresh mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent
DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or
after tDLLK).
9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 38 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DLL Switch Sequence from DLL-on to DLL-off
CK
CK
T0 Ta0Ta1Tb0Tc0Tc1Td0Te0Tf1Tg0
1)
CMD
CKE
ODT
Th0
tCKSRE tCKSRX 4) tXS tMRD tDLLK
NOP SRE2) SRX5) MRS 6) MRS 7) MRS8) Valid
ODTLoff
+ 1tck 3) tMRD
Valid
tCKESR
Time
break Do not
Care
NOP
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting from Idle State.
2) Enter SR.
3) Change Frequency.
4) Clock must be stable at least tCKSRX.
5) Exit SR.
6) Set DLL-on by MR1 A0="0"
7) Start DLL Reset
8) Any valid command
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 39 Nanya Technology Cooperation ©
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Input Clock frequency change
Once the DDR3(L) SDRAM is initialized, the DDR3(L) SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is
not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1)
Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock
frequency.
For the first condition, once the DDR3(L) SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has
been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible,
provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole
purpose of changing the clock frequency. The DDR3(L) SDRAM input clock frequency is allowed to change only within the
minimum and maximum operating frequency specified for the particular speed grade.
The second condition is when the DDR3(L) SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit
mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the
mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock
frequency may change. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and
maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and
CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to
the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has
expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to
be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period,
ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock
frequency.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 40 Nanya Technology Cooperation ©
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Change Frequency during Precharge Power-down
NOTES:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering
Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
CK
CK
T0 T1 T2 Ta0Tb0Tc0Tc1Td0Td1Te0
CKE
Command
DQS,
DQS
tCH tCL
tCK
Te1
tIH tIS tIH tIS
tCKSRE
tCKE
tCKSRX
tCHb tCLb
tCKb
NOP NOP NOP NOP NOP MRS NOP Valid
DLL
Reset Valid
tIH tIS
Address
ODT
DQ
DM
High-Z
High-Z
tAOFPD/tAOF
tCPDED
tXP
tDLLK
Previous Clock Frequency New Clock Frequency
Frequency
Change
Enter Precharge
Power-Down mode Exit Precharge
Power-Down mode
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 41 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Write Leveling
For better signal integrity, DDR3(L) memory adopted fly by topology for the commands, addresses, control signals, and
clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight
time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS,
tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3(L) SDRAM to compensate
the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3(L) SDRAM to adjust the DQS -
 to CK -  relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS -
 to align the rising edge of DQS -  with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK -
, sampled with the rising edge of DQS - , through the DQ bus. The controller repeatedly delays DQS - until a
transition from 0 to 1 is detected. The DQS -  delay established though this exercise would ensure tDQSS specification.
Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual
tDQSS in the application with an appropriate duty cycle and jitter on the DQS- signals. Depending on the actual
tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in
“AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is
show as below figure.
Write Leveling Concept
0or 1 0 0
Diff _CK
Diff _DQS
Source
Diff _CK
Diff _ DQS
Destination
DQ
DQ
Push DQS to capture
0 -1 transition
0or 1 1 1
DQS/ driven by the controller during leveling mode must be determined by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
A separated feedback mechanism should be able for each byte lane. The low byte lane’s prime DQ, DQ0, carries the
leveling feedback to the controller across the DRAM configurations x4/x8 whereas DQ0 indicates the lower diff_DQS
(diff_LDQS) to clock relationship. The high byte lane’s prime DQ, DQ8, provides the feedback of the upper diff_DQS
(diff_UDQS) to clock relationship.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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DRAM setting for write leveling and DRAM termination unction in that mode
DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling
mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/ terminations are activated and deactivated
via ODT pin not like normal operation.
MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
DRAM termination function in the leveling mode
ODT pin at DRAM
DQS/ termination
DQs termination
De-asserted
off
off
Asserted
on
off
Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write
Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are
allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the
DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well
as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank
must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to
accept the ODT signal.
Controller may drive DQS low and  high after a delay of tWLDQSEN, at which time DRAM has applied on-die
termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, edge which is used by the
DRAM to sample CK –  driven from controller. tWLMRD (max) timing is controller dependent.
DRAM samples CK -  status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after
tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes
(DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS – 
delay setting and launches the next DQS/ pulse after some time, which is controller dependent. Once a 0 to 1
transition is detected, the controller locks DQS – delay setting and write leveling is achieved for the device. The
following figure describes the timing diagram and parameters for the overall Write leveling procedure.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 43 Nanya Technology Cooperation ©
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Timing details of Write leveling sequence (For Information. Only Support prime DQ)
DQS -  is capturing CK -  low at T1 and CK -  high at T2
NOP NOP NOP NOP NOP NOP NOP NOP NOP
CK
CK
CMD
ODT
Diff_DQS
Prime DQ
Late
Remaining
DQs
tMOD
tWLMRD tWLO
tWLS tWLH
tWLOE
tWLS tWLH
tWLO
NOPMRS
tDQSHtDQSLtDQSHtDQSL
T1 T2
Time
break Do not
Care
One Prime DQ:
Early
Remaining
DQs
tWLO
tWLO
Undefined
Driving Mode
tWLOEtWLO
tWLO
All DQs are Prime:
Late
Remaining
DQs
Early
Remaining
DQs
tWLMRD tWLO
tWLO
tWLOE
tWLDQSEN
NOP
Note:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on
one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state
through out the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode
3. NOP: NOP or deselect
4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS
is shown with solid line,  is shown with dotted line.
6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for
regular Writes; the max pulse width is system dependent.
Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in
undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1).
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 44 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Timing detail of Write Leveling exit
Extended Temperature Usage
Nanya’s DDR3(L) SDRAM supports the optional extended temperature range of 0°C to +95°C, TC. Thus, the SRT and ASR
options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double
refresh) anytime the case temperature is above +85°C (in supporting temperature range). The external refreshing
requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either
ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85°C or
self refresh cannot be used until the case temperature is at or below +85°C.
Mode Register Description
Field
Bits
Description
ASR
MR2(A6)
Auto Self-Refresh (ASR)
When enabled, DDR3(L) SDRAM automatically provides Self-Refresh power management functions for all
supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER
during subsequent Self-Refresh operation.
0 = Manual SR Reference (SRT)
1 = ASR enable
SRT
MR2(A7)
Self-Refresh Temperature (SRT) Range
If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation. If
ASR = 1, SRT bit must be set to 0.
0 = Normal operating temperature range
1 = Extended operating temperature range
CK
CK
T0 T1 Ta0Tc0Tc1Tc2Td1Te1
CMD
BA
tIS
tMOD
tMRD
ODT
RTT_DQS_DQS
DQS_DQS
Result = 1
tWLO
DQ
RTT_Nom
Td0Te0T2 Tb0
tAOFmin
tAOFmax
TransitioningTime Break Do not Care Undefined
Driving Mode
NOP NOP NOP NOP NOP NOP NOP MRS NOP Valid NOP Valid
MR1 Valid Valid
tODTLoff
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 45 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Auto Self-Refresh mode - ASR mode
DDR3(L) SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit
A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges.
In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature
changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit
A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed
with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not
automatically imply support of the Extended Temperature Range.
Self-Refresh Temperature Range - SRT
SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT)
Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an
appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an
appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature
Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details.
Self-Refresh mode summary
MR2
A[6]
MR2
A[7]
Self-Refresh operation
Allowed Operating
Temperature Range for
Self-Refresh mode
0
0
Self-Refresh rate appropriate for the Normal Temperature Range
Normal 1
0
1
Self-Refresh appropriate for either the Normal or Extended Temperature Ranges.
The DRAM must support Extended Temperature Range. The value of the SRT bit can
effect self-refresh power consumption, please refer to the IDD table for details.
Normal and Extended 2
1
0
ASR enabled (for devices supporting ASR and Normal Temperature Range).
Self-Refresh power consumption is temperature dependent.
Normal 1
1
0
ASR enabled (for devices supporting ASR and Extended Temperature Range).
Self-Refresh power consumption is temperature dependent.
Normal and Extended 2
1
1
Illegal
NOTES:
1. The Normal range depends on product’s grade.
- Commercial Grade = 0℃~85℃
- Industrial Grade (-I) = -40℃~85℃
- Automotive Grade 2 (-H) = -40℃~85℃
- Automotive Grade 3 (-A) = -40℃~85℃
2. The Normal and Extended range depends on product’s grade.
- Commercial Grade = 0℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 46 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
0
don't care
(0 or 1)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Writes will go to DRAM array.
1
See the following table
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read on x8:
DQ [0] drives information from MPR.
DQ [7:1] either drive the same information as DQ [0], or they drive 0.
Addressing during for Multi Purpose Register reads for all MPR agents:
BA [2:0]: don’t care.
A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.
A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is
switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)
A [9:3]: don’t care.
A10/AP: don’t care.
A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0
A11, A13: don’t care.
Regular interface functionality during register reads:
Support two Burst Ordering which are switched with A2 and A[1:0]=00.
Support of read burst chop (MRS and on-the-fly via A12/BC).
All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the
DDR3(L) SDRAM.
Regular read latencies and AC timings apply.
DLL must be locked prior to MPR READs.
Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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MPR Register Address Definition
The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS
to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
Burst
Length
Read Address
A[2:0]
Burst Order and Data Pattern
1
00
Read
Predefined
Pattern for
System
Calibration
BL8
000
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4
000
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
1
01
RFU
BL8
000
Burst order 0,1,2,3,4,5,6,7
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
1
10
RFU
BL8
000
Burst order 0,1,2,3,4,5,6,7
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
1
11
RFU
BL8
000
Burst order 0,1,2,3,4,5,6,7
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the
BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A15 selects the row. These rows remain active
(or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued,
except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row
is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
DDR3(L) 4Gb SDRAM
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READ Operation
Read Burst Operation
During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Read Burst Operation RL=5 (AL=0, CL=5, BL=8)
READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)
CK
CK
T0 T1 T3 T5 T6 T7 T9
CL=5
DQS, DQS
T2 T4 T8 T10
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
nDout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5 Dout
n +6 Dout
n +7
DQ
RL = AL + CL
tRPRE tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
CL=5
DQS, DQS
T2 T4 T8 T10
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
nDout
n +1 Dout
n +2 Dout
n +3
DQ RL = AL + CL
tRPREAL = 4
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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READ Timing Definitions
Read timing is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
• tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, .
• tDQSCK is the actual position of a rising strobe edge relative to CK, .
• tQSH describes the DQS,  differential output high time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
• tQSL describes the DQS,  differential output low time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
DDR3(L) 4Gb SDRAM
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Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
• tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and .
• tDQSCK is the actual position of a rising strobe edge relative to CK and .
• tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
• tQSL describes the data strobe low pulse width.
Clock to Data Strobe Relationship
NOTES:
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe edge
can vary between tDQSCK(min) and tDQSCK(max).
2. The DQS,  differential output high time is defined by tQSH and the DQS,  differential output low time is defined by tQSL.
3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are not
tied to tDQSCKmax (late strobe case).
4. The minimum pulse width of read preamble is defined by tRPRE(min).
5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
6. The minimum pulse width of read postamble is defined by tRPST(min).
7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
CK
CK
RL Measured
to this point
DQS, DQS
Early Strobe
DQS, DQS
Late Strobe
tLZ(DQS)min
tLZ(DQS)max
tRPRE
tRPRE
tDQSCKmin
tDQSCKmax
tQSH tQSL tRPST
tRPST
tHZ(DQS)min
tHZ(DQS)max
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 52 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Read Timing; Data Strobe to Data Relationship
The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked.
Rising data strobe edge parameters:
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins.
• tDQSQ; both rising/falling edges of DQS, no tAC defined
Data Strobe to Data Relationship
Dout
n +6 Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
DQS, DQS
T2 T4 T8
READ NOPCMD NOP NOP NOP NOP NOP NOP NOP NOP
Bank
Col n
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
DQ (Last data valid) RL = AL + CL
tRPRE
Dout
n +6 Dout
n +7
Dout
nDout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
tLZ(DQ)min
Valid data
tHZ(DQ)min
tDQSQmax
Valid data
tQH
tQH
Dout
n
tDQSQmin
DQ (First data no
longer valid)
All DQ collectively
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 53 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Read to Read (CL=5, AL=0)
T11T10
NOP NOP
Dout
n +6 Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP READ NOP NOP NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
tCCD tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
Bank
Col b
READ
Dout
b +6 Dout
b +7
Dout
b +1 Dout
b +2 Dout
b +3 Dout
b +4 Dout
b +5
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL8) to READ (BL8)
NOP NOP
tRPST
NOPCMD NOP NOP READ NOP NOP NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
RL = 5
Bank
Col b
READ
Dout
b +1 Dout
b +2 Dout
b +3
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL4) to READ (BL4)
tRPRE
tRPST
READ
Bank
Col n
READ
Bank
Col n
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 54 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
T11T10
NOP
Dout
n +6 Dout
n +7
tWPST
CK
CK
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
NOPCMD NOP NOP WRITE
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
READ to Write Command delay = RL +tCCD + 2tCK -WL
tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
Bank
Col b
Dout
b +7
Dout
b +1 Dout
b +2 Dout
b +3 Dout
b +4 Dout
b +5
WL = 5
DQS, DQS
DQ
READ (BL8) to WRITE (BL8)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL tRPRE
Dout
n
NOP NOP
RL = 5
READ
Dout
b +1 Dout
b +2 Dout
b +3
WL = 5
DQS, DQS
READ (BL4) to WRITE (BL4)
tWPRE
tRPST
T14 T15
NOP NOP
tWRPRE
tRPST
Bank
Col n
READ NOP NOP NOP
NOPNOPNOP
DQ
NOP NOP
tBL = 4 clocks
tWR
tWTR
READ
Bank
Col n
WRITE
Bank
Col b
NOP
Dout
b
NOPNOPNOP NOP
Dout
bDout
b +6
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 55 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
READ to READ (CL=5, AL=0)
T11T10
NOP NOP
Dout
n +6 Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP NOP NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
tCCD tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
READ
Dout
b +1 Dout
b +2 Dout
b +3
Dout
b
RL = 5
DQS, DQS
DQ
READ (BL8) to READ (BC4)
NOP NOP
tRPST
NOPCMD NOP NOP NOP NOP NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
RL = 5
READ
RL = 5
DQS, DQS
READ (BC4) to READ (BL8)
tRPRE
tRPST
DQ
READ
Bank
Col n
READ
Bank
Col n
READ
Bank
Col b
READ
Bank
Col b
Dout
b +6 Dout
b +7
Dout
b +1 Dout
b +2 Dout
b +3 Dout
b +4 Dout
b +5
Dout
b
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 56 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
READ to WRITE (CL=5, AL=0; CWL=5, AL=0)
T11T10
NOP NOP
Dout
n +6 Dout
n +7
tRPST
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP WRITE
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +4 Dout
n +5
tRPRE
Dout
n
T12
NOP
T13
NOP
RL = 5
READ
Dout
b +1 Dout
b +2 Dout
b +3
WL = 5
DQS, DQS
DQ
NOP NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
READ to WRITE Command delay = RL + tCCD/2 +2tCK - WL tRPRE
Dout
n
NOP NOP
RL = 5
READ
WL = 5
DQS, DQS
READ (BL4) to WRITE (BL8)
tWPRE
tRPST
DQ
READ
Bank
Col n
READ
Bank
Col n
NOP
Bank
Col b
WRITE
Bank
Col b
Dout
b +6 Dout
b +7
Dout
b +1 Dout
b +2 Dout
b +3 Dout
b +4 Dout
b +5
Dout
b
NOPNOPNOPNOP
READ (BL8) to WRITE (BC4)
NOP NOP NOPNOP
tWPST
tWPRE
Dout
b
READ to WRITE Command delay = RL + tCCD +2tCK - WL
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 57 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Write Operation
DDR3(L) Burst Operation
During a READ or WRITE command, DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (Auto Precharge can be enabled or disabled).
A12=0, BC4 (BC4 = Burst Chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
WRITE Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the
DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up”
and errors be limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including
ODT, etc.) and that it does satisfy all timing requirements not mentioned below.
Data Setup and Hold Violations
Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then
wrong data might be written to the memory location addressed with the offending WRITE command.
Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly
otherwise.
Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS,
tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to
the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in
unpredictable read data, however the DRAM will work properly otherwise.
Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations
are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge -
as shown).
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 58 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Write Timing Definition
Note:
1. BL=8, WL=5 (AL=0, CWL=5).
2. Din n = data in from column n.
3. NOP commands are shown for ease of illustration; other command may be valid at these times.
4. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
Tn
CK
CK
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
NOPCMD NOP NOP
Address
DQ
NOP
WL = AL + CWL
NOP NOP
Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDQSS tDSH
tDQSL
tDSS
tWPST(min)
tDQSL(min)
tDSS
tDSS tDSS
tDSS
DQ
tDSH
tDQSH tDQSL
tDSS
tDQSH
tWPRE(min)
tDSS
tDSH
tDQSH
tDSH
tDSH
tDSS tDSS
tDSS
DQ Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDSH
tDQSH tDQSH
tDSH
tDQSH
tDSHtDSH
NOP
tDQSH
tWPRE(min)
Write
Bank
Col n
tWPRE(min)
tDQSH
NOP
tDSS
tDQSL tDSS tDSS
NOP
tDSH
tDSH
Din
n +6 Din
n +7
Din
n +1 Din
n +2 Din
n +3 Din
n +4 Din
n +5
Din
n
tDQSH
tDSH
NOP
tDSS
tDSS
tDQSL(min)
tWPST(min)
tDQSL(min)
tWPST(min)
tDQSS
DQS, DQS
(tDQSS min)
DQS, DQS
(tDQSS nominal)
DQS, DQS
(tDQSS max)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 59 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
WRITE to WRITE (WL=5; CWL=5, AL=0)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +5
tCCD tWPRE
T12
NOP
T13
NOP
WL = 5
Dout
b +6 Dout
b +7
Dout
b +1 Dout
b +2 Dout
b +3 Dout
b +5
WL = 5
DQS, DQS
DQ
WRITE (BL8) to WRITE (BL8)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
tCCD tRPRE
NOP NOP
WL = 5
READ
Dout
b +1 Dout
b +2 Dout
b +3
WL = 5
DQS, DQS
WRITE (BC4) to WRITE (BC4)
tWPRE
tWPST
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPWRITE
DQ
WRITE
Bank
Col n
WRITE
Bank
Col b
NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4 Dout
n +6 Dout
bDout
b +4
tBL=4
tWR
tWTR
tBL=4
tWR
tWTR
Dout
nDout
b
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 60 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +5
tWPRE
T12
NOP
T13
READ
WL = 5
DQS, DQS
DQ
WRITE (BL8) to READ (BC4/BL8)
NOP
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
tRPRE
Dout
n
NOP READ
WL = 5
DQS, DQS
WRITE (BC4) to READ (BC4/BL8)
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPNOP
DQ
WRITE
Bank
Col n
NOP NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4 Dout
n +6
tWTR
RL=5
tBL=4
tWPST
Bank
Col b
tWTR
RL=5
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 61 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
WRITE to WRITE (WL=5, CWL=5, AL=0)
T11T10
NOP
Dout
n +7
CK
CK
T0 T1 T3 T5 T6 T7 T9
T2 T4 T8
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3 Dout
n +5
tCCD tWPRE
T12
NOP
T13
NOP
WL = 5
Dout
b +1 Dout
b +2
WL = 5
DQS, DQS
DQ
WRITE (BL8) to WRITE (BC4)
NOP
tWPST
NOPCMD NOP NOP NOP
Address
Dout
n +1 Dout
n +2 Dout
n +3
tCCD tRPRE
Dout
n
NOP NOP
WL = 5
READ
Dout
b +1 Dout
b +2 Dout
b +3
WL = 5
DQS, DQS
WRITE (BC4) to WRITE (BL8)
tWPRE
tWPST
tWPST
Bank
Col n
WRITE NOP NOP NOP
NOPNOPWRITE
DQ
WRITE
Bank
Col n
WRITE
Bank
Col b
NOP
Bank
Col b
Dout
n
NOP NOP NOP NOP
Dout
n +4 Dout
n +6 Dout
b
tBL=4
tWR
tWTR
tBL=4
tWR
tWTR
Dout
b +3
Dout
b +6 Dout
b +7
Dout
b +3 Dout
b +5
Dout
b +4
Dout
b
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 62 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3(L) SDRAMs. This command is not persistent,
so it must be issued each time a refresh is required. The DDR3(L) SDRAM requires Refresh cycles at an average periodic
interval of tREFI. When , RA, and A are held Low and WE High at the rising edge of the clock, the chip enters a
Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before
the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes
the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the
refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has
completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the
next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as
shown in the following figure.
In general, a Refresh command needs to be issued to the DDR3(L) SDRAM regularly every tREFI interval. To allow for
improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
A maximum of 8 Refresh commands can be postponed during operation of the DDR3(L) SDRAM, meaning that at no point
in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are
postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A
maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of
regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not
further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two
surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh
commands must be executed.
Self-Refresh Entry/Exit Timing
Postponing Refresh Commands (Example)
CK
CK
T0 T1 Ta0Tb0Tb1Tb3Ta1Tb2
NOPCMD NOP REF Valid
NOPREF NOP Valid ValidValid Valid REF
Tc0Tc1
Valid
tRFC tRFC(min)
tREFI (max, 9 x tREFI)
DRAM must be idle
DRAM must be idle
Time Break
9 x tREFI
tREFI
tREFI
8 REF-Command postponed
t
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 63 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Pulled-in Refresh Commands (Example)
Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3(L) SDRAM, even if the reset of the system is powered
down. When in the Self-Refresh mode, the DDR3(L) SDRAM retains data without external clocking. The DDR3(L) SDRAM
device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by
having , RA, A, and E held low with WE high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3(L) SDRAM must be idle with all bank precharge state with
tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering
ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the
Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal
operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically
enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3(L) SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and REET,
are “don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ,
VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within
tCKE period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3(L) SDRAM
must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock
tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device
can exit Self-Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going
back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on
command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL
can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL
can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements must be satisfied.
9 x tREFI
tREFI
t
tREFI
8 REF-Commands pulled-in
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 64 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on
the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to
compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration
commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.
Upon exit from Self-Refresh, the DDR3(L) SDRAM can be put back into Self-Refresh mode after waiting at least tXS period
and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each
positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is
raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3(L) SDRAM requires a minimum of one extra
refresh command before it is put back into Self-Refresh mode.
Self-Refresh Entry/Exit Timing
CK, CK
T1 T2 Ta0Tb0Tc0Tc1Te0Tf
ODTL
tCKSRE
tCKSRX
tCPDED
tRF
SRE NOP Valid 2)
tCKESR
tXSDLL
tXS
CMD
ODT
Note:
1. Only NOP or DES commands
2. Valid commands not requiring a locked DLL
3. Valid commands requiring a locked DLL
T0 Td0
Valid
CKE
NOP SRX NOP 1) Valid 3)
Valid Valid
Valid
Valid
Enter Self Refresh Exit Self Refresh
Do Not
Care Time
Break
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 65 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Power-Down Modes
Power-Down Entry and Exit
Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not
allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write
operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto
precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not
locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and
synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL
operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge
Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active
Power-Down mode.
Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, E, and REET. To protect
DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the
CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of
command and address receivers after tCPDED has expired.
Power-Down Entry Definitions
Status of DRAM
MRS bit A12
DLL
PD Exit
Relevant Parameters
Active
(A Bank or more open)
Don't Care
On
Fast
tXP to any valid command.
Precharged
(All Banks Precharged)
0
Off
Slow
tXP to any valid command. Since it is in precharge state,
commands here will be ACT, AR, MRS/EMRS, PR, or PRA.
tXPDLL to commands who need DLL to operate, such as RD,
RDA, or ODT control line.
Precharged
(All Banks Precharged)
1
On
Fast
tXP to any valid command.
Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during
precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, REET high, and a stable
clock signal must be maintained at the inputs of the DDR3(L) SDRAM, and ODT should be in a valid state but all other input
signals are “Don’t care” (If REET goes low during Power-Down, the DRAM will be out of PD mode and into reset state).
CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down
exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.
Active Power-Down Entry and Exit timing diagram
T0 T1 T2 Ta0Ta1Tb0Tb1Tc0
CK
CK
Valid NOP NOP NOP NOP NOP NOPCMD
CKE Valid Valid
tIS
tIH
tPD tIH
tIS tCKE
Address Valid Valid
tCPDED
Enter
Power-Down Exit
Power-Down
tXP
Do not
care Time
Break
Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate,
Precharge, Refresh, MRS:
Power-Down Entry after Read and Read with Auto Precharge
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Address Bank,
Col n
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Tb0 Tb1 Tb2
NOP NOP NOP NOP NOP NOP
tIS tCPDED
DQS
WL=AL+CWL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tWRAPDEN
BL8
BC4
WR (1)
Tb3
NOP
Tc0
Valid
tPD
Start Internal
Precharge
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Power-Down Entry after Write with Auto Precharge
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
RD or
RDA NOP NOP NOP NOP NOP NOPCMD
CKE
Address Valid Valid
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Ta8 Tb0 Tb1
NOP NOP NOP NOP NOP Valid
Valid
tIS tCPDED
DQS
RL = AL + CL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tRDPDEN
BL8
BC4
tPD
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Power-Down Entry after Write
Precharge Power-Down (Fast Exit Mode) Entry and Exit
Precharge Power-Down (Slow Exit Mode) Entry and Exit
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Address Bank,
Col n
Power-Down
Entry Do not
care Time
Break
Ta6 Ta7 Tb0 Tb1 Tb2
NOP NOP NOP NOP NOP NOP
tIS tCPDED
DQS
WL=AL+CWL
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
Din
bDin
b+1 Din
b+2 Din
b+3
tWRPDEN
BL8
BC4
Tc0
NOP
tPDWR
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0
CK
CK
WRITE NOP NOP NOP NOP NOP NOPCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED tIH tCKE
tIS
tXP
NOP Valid
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0
CK
CK
WRITE NOP NOP NOP NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED tIH tCKE
tIS tXP
NOP Valid
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Td0
Valid
tXPDLL
Valid
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Refresh Command to Power-Down Entry
T0 T1 T2 T3 Ta0 Ta1
CK
CK
REF NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid Valid
tREFPDEN
Address
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Active Command to Power-Down Entry
Precharge/Precharge all Command to Power-Down Entry
MRS Command to Power-Down Entry
T0 T1 T2 T3 Ta0Ta1
CK
CK
Active NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid Valid
tACTPDEN
Address
T0 T1 T2 T3 Ta0Ta1
CK
CK
PRE
PREA NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid Valid
tPREPDEN
Address
T0 T1 Ta0Ta1Tb0Tb1
CK
CK
NOP NOP ValidCMD
CKE
Do not
care Time
Break
NOP
tIS tCPDED
Valid
tPD
Valid
tMRSPDEN
Address
MRS
Valid
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3(L) SDRAM that allows the DRAM to turn on/off termination resistance
for each DQ, DQS, , and DM for x8 configuration and TDQS, T for x8 configuration, when enabled via A11=1 in
MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing
the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown as below.
Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The
value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1
and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is
determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Termination Truth Table
ODT pin
DRAM Termination State
0
OFF
1
ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general)
To other
circuitry
like
RCV, ...
VDDQ
/ 2
RTT
Switch DQ , DQS, DM, TDQS
ODT
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these
modes are:
Any bank active with CKE high
Refresh with CKE high
Idle mode with CKE high
Active power down mode (regardless of MR0 bit A12)
Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-
ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register
set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge
and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write
latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2.
ODT Latency and Posted ODT
In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT
signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative
to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3(L) SDRAM
latency definitions.
ODT Latency
Symbol
Parameter
DDR3-1600
Unit
ODTLon
ODT turn on Latency
WL - 2 = CWL + AL - 2
tCK
ODTLoff
ODT turn off Latency
WL - 2 = CWL + AL - 2
tCK
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance
begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are
measured from ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum
RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are
measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until
ODT is registered low.
Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6;
ODTLoff=AL+CWL-2=6
Synchronous ODT example with BL=4, WL=7
ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after
Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of
Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6
ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.
CK
CK
AL=3
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12
ODT
ODTH4, min
ODTLon = CWL + AL -2 ODTLoff = CWL + AL -2
T13 T14 T15
CWL - 2
DRAM_RTT
tAONmin
tAONmax tAONmin
tAONmax
RTT_NOM
AL=3
Transitioning Do not care
CKE
CK
CK
ODTH4
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12
ODT
ODTLon = CWL -2
T13 T14 T15
ODTLoff = WL - 2
DRAM_RTT
tAONmin tAONmax
tAOFmax
RTT_NOM
T16 T17 T18
ODTH4min
ODTH4
ODTLoff = CWL -2
ODTLon = CWL -2
tAOFmin
tAOFmax tAONmax
tAONmin tAOFmin
NOP NOP NOP NOP NOP NOP NOP WRS4NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Transitioning Do not care
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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ODT during Reads:
As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle
before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble
as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM
stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM
complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read
than shown in this example.
ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6;
AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14 T15 T16
CMD
Address
RL = AL + CL
RTT_NOMRTT
ODTLoff = CWL + AL - 2
tAOFmax
tAOFmin
ODTLon = CWL + AL - 2
RTT_NOM
tAONmax
ODT
DRAM
ODT
DQSdiff
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
DQ
Read NOP NOP NOP NOP NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 75 Nanya Technology Cooperation ©
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Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. This requirement is supported by the
“Dynamic ODT” feature as described as follows:
Functional Description
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows:
Two RTT values are available: RTT_Nom and RTT_WR.
The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.
The value for RTT_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
Nominal termination strength RTT_Nom is selected.
Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the
termination is controlled as follows:
A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the
write command, termination strength RTT_Nom is selected.
Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic
ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9
= [0,0], to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with
ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and
ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT
is register low.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Latencies and timing parameters relevant for Dynamic ODT
Name and Description
Abbr.
Defined from
Defined to
Definition for all
DDR3(L) speed pin
Unit
ODT turn-on Latency
ODTLon
registering external
ODT signal high
turning termination on
ODTLon=WL-2
tCK
ODT turn-off Latency
ODTLoff
registering external
ODT signal low
turning termination off
ODTLoff=WL-2
tCK
ODT Latency for changing from
RTT_Nom to RTT_WR
ODTLcnw
registering external
write command
change RTT strength from
RTT_Nom to RTT_WR
ODTLcnw=WL-2
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=4)
ODTLcwn4
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
ODTLcwn4=4+ODTLoff
tCK
ODT Latency for change from
RTT_WR to RTT_Nom (BL=8)
ODTLcwn8
registering external
write command
change RTT strength from
RTT_WR to RTT_Nom
ODTLcwn8=6+ODTLoff
tCK(avg)
Minimum ODT high time
after ODT assertion
ODTH4
registering ODT high
ODT registered low
ODTH4=4
tCK(avg)
Minimum ODT high time
after Write (BL=4)
ODTH4
registering write with
ODT high
ODT registered low
ODTH4=4
tCK(avg)
Minimum ODT high time
after Write (BL=8)
ODTH8
registering write with
ODT high
ODT register low
ODTH8=6
tCK(avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK(avg)
Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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ODT Timing Diagrams
Dynamic ODT: Behavior with ODT being asserted before and after the write
Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write
command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command).
Dynamic ODT: Behavior without write command, AL=0, CWL=5
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5
would also be legal.
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14 T15 T16
CMD
ODT
RTT
DQS/DQS
DQ
ODTLon
ODTLcwn4
T17
ODTLcnw
tAONmin
tAONmax
tADCmin
tADCmax
WL
tADCmin
tADCmax
tAOFmin
tAOFmax
Address
RTT_WR
Din
nDin
n+1 Din
n+2 Din
n+3
ODTH4ODTLoff
NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
ODTH4
RTT_Nom
Do not
care Transitioning
RTT_Nom
tADCmax
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
CMD
ODT
RTT
DQS/DQS
DQ
ODTLon
ODTLoff
tAONmin
tAONmax
tADCmin
RTT_Nom
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Address
ODTH4 ODTLoff
Do not
care Transitioning
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Dynamic ODT: Behavior with ODT pin being asserted together with write command
for the duration of 6 clock cycles.
Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.
Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF),
AL=0, CWL=5.
tAOFmax
tAOFmin
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
CMD
ODT
RTT
DQS/DQS
DQ
ODTH8
ODTLon
ODTLcnw
tAONmin
tAONmax
ODTLoff
WL
RTT_WR
NOP WRS8 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Din
hDin
h+1 Din
h+2 Din
h+3 Din
h+4 Din
h+5 Din
h+6 Din
h+7
ODTLcwn8
Do not
care Transitioning
Address
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
DQS/DQS
DQ
ODTLon
RTT_WR RTT_Nom
ODTLcnw
tAONmin tADCmin
tADCmax
tAOFmin
tAOFmax
tAONmax
ODTLoff
WL
ODTH4
ODTLcwn4
CMD NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Address
Din
nDin
n+1 Din
n+2 Din
n+3
Do not
care Transitioning
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
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Dynamic ODT: Behavior with ODT pin being asserted together with write command
for the duration of 4 clock cycles.
CK
CK#
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
DQS/DQS
DQ
ODTLon
RTT_WR
ODTLcnw
tAONmin tAOFmin
tAOFmax
tAONmax
ODTLoff
WL
ODTH4
ODTLcwn4
CMD NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Valid
Address
Din
nDin
n+1 Din
n+2 Din
n+3
Do not
care Transitioning
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 80 Nanya Technology Cooperation ©
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Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in
precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power
down mode if DLL is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state
and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in time when the ODT
resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT
resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has reached high
impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low.
Asynchronous ODT Timings on DDR3(L) SDRAM with fast ODT transition: AL is
ignored.
In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the
respective ADD/CMD receivers may be disabled.
Asynchronous ODT Timing Parameters for all Speed Bins
Symbol
Description
Min.
Max.
Unit
tAONPD
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
2
8.5
ns
tAOFPD
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
2
8.5
ns
CK
CK#
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8
ODT
RTT
tAONPDmin
CKE
tIH
tIS
T12 T13 T14 T15
tAONPDmax tAOFPDmin
tAOFPDmax
tIH
tIS
Do not
care Transitioning
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 81 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ODT timing parameters for Power Down (with DLL frozen) entry and exit transition
period
Description
Min.
Max.
ODT to RTT turn-on delay
min{ ODTLon * tCK + tAONmin; tAONPDmin }
min{ (WL - 2) * tCK + tAONmin; tAONPDmin }
max{ ODTLon * tCK + tAONmax; tAONPDmax }
max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
ODT to RTT turn-off delay
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin }
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD
WL-1
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition
period around power down entry, where the DDR3(L) SDRAM may show either synchronous or asynchronous ODT
behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted
backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where
CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of
tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later
one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point
at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are
included in the transition period.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and
(ODTLon*tCK + tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK + tAONmax). ODT de-assertion
during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK +
tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK + tAOFmax). Note that, if AL has a large value, the
range where RTT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_A, synchronous
behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the
transition period.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 82 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Synchronous to asynchronous transition during Precharge Power Down (with DLL
frozen) entry (AL=0; CWL=5; tANPD=WL-1=4)
CK
CK
CKE
CMD
Last sync.
ODT
tANPD
RTT
Sync. Or
async. ODT
ODTLoff tAOFmax
tAOFmin
tAOFPDmin
tAOFPDmax
ODTLoff+tAOFPDmin
ODTLoff+tAOFPDmax
RTT
tAOFPDmin
First async.
ODT
RTT
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
PD entry transition period
Do not
care Time
Break
Transitioning
tCPDEDmin
tCPDED
NOP
RTT
RTT
RTT
tAOFPDmax
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 83 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Asynchronous to Synchronous ODT Mode transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a
transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must
be expected from the DDR3(L) SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high.
tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODT-
Lon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the tran-
sition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as
the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain
becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD;
ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition
period with synchronous response.
Asynchronous to synchronous transition during Precharge Power Down (with DLL
frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9)
CK
CK
ODT_C
_sync
DRAM
_RTT_
C_sync
ODT_B
_tran
tAOFPDmax
tAOFPDmin
DRAM
_RTT_
B_tran
ODT_A
_async
DRAM_
RTT_A_
async
T0 T1 T2 Ta0Ta1Ta2Ta3Ta4Ta5Ta6Tb0Tb1Tb2Tc0Tc1Tc2Td0
Do not
care Time
Break
Transitioning
Td1
CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
CKE
NOP
tXPDLL
PD exit transition period
RTT
RTT
tAOFPDmin
ODTLoff + tAOFmax
ODTLoff + tAOFmin
tAOFPDmax
tANPD
NOP
tAOFmax
RTT
ODTLoff
tAOFmin
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 84 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit
may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be
synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period
(even if the entry ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the
response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from
the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is
assumed that there was no Refresh command in progress when Idle state was entered.
Transition period for short CKE cycles with entry and exit period overlapping
(AL=0; WL=5; tANPD=WL-1=4)
CK
CK
T11T10
T0 T1 T3 T5 T6 T7 T9T2 T4 T8 T12 T13 T14
tANPD
Do not
care Transitioning
CKE
CMD REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
PD exit transition period
tANPD tXPDLL
PD entry transition period
tRFC(min)
CKE
Short CKE high transition period tXPDLL
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 85 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ZQ Calibration Commands
ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3(L) SDRAM needs longer time to calibrate
output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be
issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine
inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO
which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the
transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing
period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing
window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS.
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or
tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM
calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh
exit, DDR3(L) SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible
time for ZQ Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or
tZQCS between ranks.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 86 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ZQ Calibration Timing
Note:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ calibration function, a 240 ohm +/- 1% tolerance external resistor connected between the ZQ pin and
ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ
calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited.
CK
CK
Tc2
T0 T1 Ta1Ta3Tb0Tb1Tc1Ta0Ta2Tc0
Address
CMD ZQCL NOP NOP NOP Valid Valid ZQCS NOP NOP NOP Valid
ODT
tZQCS
Valid Valid
Valid Valid Valid
A10
CKE Valid Valid Valid
Valid Valid Valid
(1)
(2)
(1)
(2)
DQ Bus Hi-Z Activities Hi-Z Activities
tZQCS
(3) (3)
Do not
care Time
Break
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 87 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Unit
Note
VDD
Voltage on VDD pin relative to Vss
-0.4 V ~ 1.80 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.4 V ~ 1.80 V
V
1,3
Vin, Vout
Voltage on any pin relative to Vss
-0.4 V ~ 1.80 V
V
1
Tstg
Storage Temperature
-55 ~ 100
C
1,2
Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and
VDDQ are less than 500Mv; Vref may be equal to or less than 300mV.
Refresh parameters by device density
Parameter
Symbol
1Gb
2Gb
4Gb
8Gb
Unit
REF command to ACT or REF command time
tRFC
110
160
260
350
ns
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 88 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Temperature Range
Symbol
Condition
Parameter
Value
Unit
Notes
Toper
Commercial
Normal Operating Temperature Range
0 to 85
C
1,2
Extended Temperature Range
85 to 95
C
1,3
Industrial
Operating Temperature Range
-40 to 95
C
1.4
Automotive Grade 2
Operating Temperature Range
-40 to 105
C
1
Automotive Grade 3
Operating Temperature Range
-40 to 95
C
1.4
Note:
1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specification will be supported. During operation,
the DRAM case temperature must be maintained between 0-85C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85C and 95C case temperature.
Full specifications are guaranteed in this range, but the following additional apply.
a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also possible to
specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual
Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto
Self-Refresh mode (MR2 A6=1 and MR2 A7=0).
4. During Temperature Operation Range, the DRAM case temperature must be maintained between -40°C~95°C under all operating
Conditions.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 89 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
AC & DC Operating Conditions
Recommended DC Operating Conditions
Symbol
Parameter
Rating
Unit
Note
Min.
Typ.
Max.
VDD
Supply Voltage
DDR3
1.425
1.5
1.575
V
1,2
DDR3L
1.283
1.35
1.45
3,4,5,6
VDDQ
Supply Voltage for Output
DDR3
1.425
1.5
1.575
V
1,2
DDR3L
1.283
1.35
1.45
3,4,5,6
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time
(e.g., 1 sec).
4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
5. Under these supply voltages, the device operates to this DDR3L specification.
6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed
for DDR3L operation.
7. VDD= VDDQ= 1.35V (1.283–1.45V )
Backward compatible to VDD= VDDQ= 1.5V ±0.075V
Supports DDR3L devices to be backward com-patible in 1.5V applications
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 90 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
AC & DC Input Measurement Levels
DDR3 AC and DC Logic Input Levels for Command and Address
Symbol
Parameter
DDR3
Unit
Notes
800,1066,1333,1600
1866,2133
Min
Max
Min
Max
VIH.CA(DC100)
DC input logic high
Vref + 0.1
VDD
Vref + 0.1
VDD
V
1, 5
VIL.CA(DC100)
DC input logic low
VSS
Vref - 0.1
VSS
Vref - 0.1
V
1, 6
VIH.CA(AC175)
AC input logic high
Vref + 0.175
Note 2
-
-
V
1, 2, 7
VIL.CA(AC175)
AC input logic low
Note 2
Vref - 0.175
-
-
V
1, 2, 8
VIH.CA(AC150)
AC input logic high
Vref + 0.150
Note 2
-
-
V
1, 2, 7
VIL.CA(AC150)
AC input logic low
Note 2
Vref - 0.150
-
-
V
1, 2, 8
VIH.CA(AC135)
AC input logic high
-
-
Vref + 0.135
Note 2
V
1, 2, 7
VIL.CA(AC135)
AC input logic low
-
-
Note 2
Vref - 0.135
V
1, 2, 8
VIH.CA(AC125)
AC input logic high
-
-
-
Note 2
V
1, 2, 7
VIL.CA(AC125)
AC input logic low
-
-
Note 2
Vref - 0.125
V
1, 2, 8
VRefCA(DC)
Reference Voltage for ADD,
CMD inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3, 4, 9
NOTE 1. For input only pins except REET. Vref = VrefCA(DC).
NOTE 2. See “Overshoot and Undershoot Specifications” .
NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
NOTE 4. For reference: approx. VDD/2 +/- 15 mV.
NOTE 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
NOTE 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
NOTE 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175)
value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value
is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.
NOTE 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value
is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used
when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced.
NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 91 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3L AC and DC Logic Input Levels for Command and Address
Symbol
Parameter
DDR3L
Unit
Notes
800,1066
1333,1600
1866
Min
Max
Min
Max
Min
Max
VIH.CA(DC90)
DC input logic high
Vref + 0.09
VDD
Vref + 0.09
VDD
Vref + 0.09
VDD
V
1
VIL.CA(DC90)
DC input logic low
VSS
Vref - 0.09
VSS
Vref - 0.09
VSS
Vref - 0.09
V
1
VIH.CA(AC160)
AC input logic high
Vref + 0.16
Note 2
Vref + 0.16
Note 2
-
-
V
1,2
VIL.CA(AC160)
AC input logic low
Note 2
Vref - 0.16
Note 2
Vref - 0.16
-
-
V
1,2
VIH.CA(AC135)
AC input logic high
Vref + 0.135
Note 2
Vref + 0.135
Note 2
Vref + 0.135
Note 2
V
1,2
VIL.CA(AC135)
AC input logic low
Note 2
Vref - 0.135
Note 2
Vref - 0.135
Note 2
Vref - 0.135
V
1,2
VIH.CA(AC125)
AC input logic high
-
-
-
-
Vref + 0.125
Note 2
V
1,2
VIL.CA(AC125)
AC input logic low
-
-
-
-
Note 2
Vref - 0.125
V
1,2
VRefCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3,4
NOTE 1 For input only pins except REET. Vref = VrefCA(DC).
NOTE 2 See “Overshoot and Undershoot Specifications”
NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 92 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3 AC and DC Logic Input Levels for DQ and DM
Symbol
Parameter
DDR3
Unit
Notes
800,1066
1333,1600
1866,2133
Min
Max
Min
Max
Min
Max
VIH.DQ(DC100)
DC input logic high
Vref + 0.1
VDD
Vref + 0.1
VDD
Vref + 0.1
VDD
V
1, 5
VIL.DQ(DC100)
DC input logic low
VSS
Vref - 0.1
VSS
Vref - 0.1
VSS
Vref - 0.1
V
1, 6
VIH.DQ(AC175)
AC input logic high
Vref + 0.175
Note 2
-
-
-
-
V
1, 2, 7
VIL.DQ(AC175)
AC input logic low
Note 2
Vref - 0.175
-
-
-
-
V
1, 2, 8
VIH.DQ(AC150)
AC input logic high
Vref + 0.150
Note 2
Vref + 0.150
Note 2
-
-
V
1, 2, 7
VIL.DQ(AC150)
AC input logic low
Note 2
Vref - 0.150
Note 2
Vref - 0.150
-
-
V
1, 2, 8
VIH.DQ(AC135)
AC input logic high
Vref + 0.135
Note 2
Vref + 0.135
Note 2
Vref + 0.135
Note 2
V
1, 2, 7
VIL.DQ(AC135)
AC input logic low
Note 2
Vref - 0.135
Note 2
Vref - 0.135
Note 2
Vref - 0.135
V
1, 2, 8
VRefDQ(DC)
Reference Voltage
for DQ, DM inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3, 4, 9
NOTE 1. Vref = VrefDQ(DC).
NOTE 2. See “Overshoot and Undershoot Specifications” .
NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:approx. +/- 15 mV).
NOTE 4. For reference: approx. VDD/2 +/- 15 mV.
NOTE 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
NOTE 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
NOTE 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);VIH.DQ(AC175) value is used when
Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when
Vref + 0.135V is referenced.
NOTE 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);VIL.DQ(AC175) value is used when
Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -0.150V is referenced, and VIL.DQ(AC135) value is used when
Vref - 0.135V is referenced.
NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 93 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3L AC and DC Logic Input Levels for DQ and DM
Symbol
Parameter
DDR3L
Unit
Notes
800,1066
1333,1600
1866
Min
Max
Min
Max
Min
Max
VIH.DQ(DC90)
DC input logic high
Vref + 0.09
VDD
Vref + 0.09
VDD
Vref + 0.09
VDD
V
1
VIL.DQ(DC90)
DC input logic low
VSS
Vref - 0.09
VSS
Vref - 0.09
VSS
Vref - 0.09
V
1
VIH.DQ(AC160)
AC input logic high
Vref + 0.16
Note 2
Vref + 0.16
Note 2
-
-
V
1,2
VIL.DQ(AC160)
AC input logic low
Note 2
Vref - 0.16
Note 2
Vref - 0.16
-
-
V
1,2
VIH.DQ(AC135)
AC input logic high
Vref + 0.135
Note 2
Vref + 0.135
Note 2
Vref + 0.135
Note 2
V
1,2
VIL.DQ(AC135)
AC input logic low
Note 2
Vref - 0.135
Note 2
Vref - 0.135
Note 2
Vref - 0.135
V
1,2
VIH.DQ(AC130)
AC input logic high
-
-
-
-
Vref + 0.13
Note 2
V
1,2
VIL.DQ(AC130)
AC input logic low
-
-
-
-
Note 2
Vref - 0.13
V
1,2
VRefDQ(DC)
Reference Voltage
for DQ, DM inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3,4
NOTE 1 For input only pins except REET. Vref = VrefDQ(DC).
NOTE 2 See “Overshoot and Undershoot Specifications”.
NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 94 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Vref Tolerances
The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following
figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).
Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max
requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref.
“Vref” shall be understood as Vref(DC).
The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level
and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for
Vref(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated
with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in
DRAM timing and their associated de-ratings.
Illustration of Vref(DC) tolerance and Vrefac-noise limits
Vref(DC)Vref(DC)max
Vref(DC)min
VDD/2
Vref ac-noise
Voltage
time
VDD
VSS
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 95 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3 Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )
Symbol
Parameter
DDR3-800, 1066, 1333, & 1600
Unit
Notes
Min
Max
VIHdiff
Differential input high
+ 0.200
Note 3
V
1
VILdiff
Differential input logic low
Note 3
- 0.200
V
1
VIHdiff(ac)
Differential input high ac
2 x (VIH(ac) - Vref)
Note 3
V
2
VILdiff(ac)
Differential input low ac
Note 3
2 x (VIL(ac) - Vref)
V
2
NOTE 1. Used to define a differential signal slew-rate.
NOTE 2. For CK -  use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU ,U use VIH/VIL(ac) of
DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,then the reduced level applies also here.
NOTE 3. These values are not defined; however, the single-ended signals CK, , DQS, , DQSL, L, DQSU,
U need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for
overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications”
DDR3L Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )
Symbol
Parameter
DDR3L-800, 1066, 1333, 1600 & 1866
Unit
Notes
Min
Max
VIHdiff
Differential input high
+ 0.180
Note 3
V
1
VILdiff
Differential input logic low
Note 3
- 0.180
V
1
VIHdiff(ac)
Differential input high ac
2 x (VIH(ac) - Vref)
Note 3
V
2
VILdiff(ac)
Differential input low ac
Note 3
2 x (VIL(ac) - Vref)
V
2
NOTE 1 Used to define a differential signal slew-rate.
NOTE 2 For CK -  use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU , U use VIH/VIL(AC) of
DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
NOTE 3 These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be
within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to “Overshoot and Undershoot Specifications”.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 96 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Definition of differential ac-swing and “time above ac-level”
Time
Differential Input Voltage (i.e. DQS –DQS, CK –CK)
tDVAC
tDVAC
Half cycle
VIH.Diff.AC.min
VIH.Diff. DC min
VIL.Diff.AC.max
0
VIL. Diff. DC max
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 97 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3 Allowed time before ringback (tDVAC) for CK -  and DQS - 
Slew Rate
[V/ns]
DDR3-800 / 1066 / 1333 / 1600
DDR3-1866 / 2133
tDVAC [ps]
@ |VIH/Ldiff(AC)| =
350mV
tDVAC [ ps ]
@ |VIH/Ldiff(AC)| =
300mV
tDVAC [ ps ]
@ |VIH/Ldiff(AC)| =
(DQS - ) only
tDVAC [ ps ]
@ |VIH/Ldiff(AC)| =
300mV
tDVAC [ ps ]
@ |VIH/Ldiff(AC)| =
(CK - ) only
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
> 4.0
75
-
175
-
214
-
134
-
139
-
4.0
57
-
170
-
214
-
134
-
139
-
3.0
50
-
167
-
191
-
112
-
118
-
2.0
38
-
119
-
146
-
67
-
77
-
1.8
34
-
102
-
131
-
52
-
63
-
1.6
29
-
81
-
113
-
33
-
45
-
1.4
22
-
54
-
88
-
9
-
23
-
1.2
note
-
19
-
56
-
note
-
note
-
1.0
note
-
note
-
11
-
note
-
note
-
< 1.0
note
-
note
-
note
-
note
-
note
-
NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become
equal to or less than VILdiff(ac) level.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 98 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3L Allowed time before ringback (tDVAC) for CK -  and DQS - 
Slew Rate
[V/ns]
DDR3L-800/1066/1333/1600
DDR3L-1866
tDVAC [ps]
@|VIH/Ldiff(AC)| =
320 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
270 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
270 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
250 mV
tDVAC [ps]
@|VIH/Ldiff(AC)| =
260 mV
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
> 4.0
189
-
201
-
163
-
168
-
176
-
4.0
189
-
201
-
163
-
168
-
176
-
3.0
162
-
179
-
140
-
147
-
154
-
2.0
109
-
134
-
95
-
105
-
111
-
1.8
91
-
119
-
80
-
91
-
97
-
1.6
69
-
100
-
62
-
74
-
78
-
1.4
40
-
76
-
37
-
52
-
56
-
1.2
note
-
44
-
5
-
22
-
24
-
1.0
note
-
note
-
note
-
note
-
note
-
< 1.0
note
-
note
-
note
-
note
-
note
-
NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become
equal to or less than VILdiff(ac) level.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 99 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, , ,L, or U) has also to comply
with certain requirements for single-ended signals.
CK and have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for
ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, , L have to reach VSEHmin / VSELmax (approxi-
mately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH150
(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and 
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 100 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Single-ended levels for CK, DQS, DQSL, DQSU, , , L, or U
Symbol
Parameter
DDR3(L)-800, 1066, 1333, & 1600
Unit
Notes
Min.
Max.
VSEH
Single-ended high-level for strobes
(VDDQ/2) + 0.175
note3
V
1, 2
Single-ended high-level for CK, 
(VDDQ/2) + 0.175
note3
V
1, 2
VSEL
Single-ended low-level for strobes
note3
(VDDQ/2) - 0.175
V
1, 2
Single-ended Low-level for CK, 
note3
(VDDQ/2) - 0.175
V
1, 2
Note:
1. For CK,  use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, , L, or U) use VIH/VIL(ac) of DQs.
2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low
level is used for a signal group, then the reduced level applies also there.
3. These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within
the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 101 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross
point voltage of differential input signals (CK,  and DQS, ) must meet the requirements in the following table. The
differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel
between of VDD and VSS.
Vix Definition
VDD
VSS
VDD/2
,
CK,DQS
VIX
VIX
VIX
VSEH
VSEL
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3
DDR3L
Unit
Notes
800/1066/1333/1600/
1866/2133
800/1066/1333/1600/
1866
Min
Max
Min
Max
VIX(CK)
Differential Input Cross Point
Voltage relative to
VDD/2 for CK, 
- 150
+ 150
- 150
+ 150
mV
1
- 175
- 175
mV
2
VIX(DQS)
Differential Input Cross Point
Voltage relative to
VDD/2 for DQS, 
- 150
+ 150
- 150
+ 150
mV
1
Note 1 The relation between Vix Min/Max and VSEL/VSEH should satisfy following:
(VDD/2) + VIX (min) - VSEL >= 25 mV ;
VSEH - ((VDD/2) + VIX (max)) >= 25 mV;
Note 2 Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and  are monotonic with a
single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -  is larger
than 3 V/ns.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 102 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK,  and DQS, ) are defined and measured as shown below.
Differential Input Slew Rate Definition
Description
Measured
Defined by
From
To
Differential input slew rate for rising edge
(CK-& DQS-)
VILdiffmax
VIHdiffmin
[VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK- & DQS-)
VIHdiffmin
VILdiffmax
[VIHdiffmin-VILdiffmax] / DeltaTFdiff
The differential signal (i.e., CK-& DQS-) must be linear between these thresholds.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 103 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Input Nominal Slew Rate Definition for single ended signals
Delta
TFdiff
Delta
TRdiff
VIHdiffMin
VILdiffMax
0
AC and DC Output Measurement Levels
Single Ended AC and DC Output Levels
Symbol
Parameter
DDR3(L)
Unit
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8xVDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5xVDDQ
V
VOL(DC)
DC output low measurement level (fro IV curve linearity)
0.2xVDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT+0.1xVDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT-0.1xVDDQ
V
1
Note:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver
impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Differential AC and DC Output Levels
Symbol
Parameter
DDR3(L)
Unit
Notes
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note:
1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver
impedance of 40 Ω and an effective test load of 25 Ω to VTT=VDDQ/2 at each of the differential outputs.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 104 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Single Ended Output Slew Rate
Description
Measured
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output Slew Rate Definition
Delta TFse
Delta TFse
VOH (AC)
VOL (AC)
VTT
Single Ended Output Voltage (i.e. DQ)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 105 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Output Slew Rate (Single-ended)
Parameter
Symbol
-
800
1066
1333
1600
1866
2133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Single-ended
Output Slew
Rate
SRQse
DDR3
2.5
5
2.5
5
2.5
5
2.5
5
2.5
5
2.5
5
V/ns
DDR3L
1.75
5
1.75
5
1.75
5
1.75
5
1.75
5
1.75
5
V/ns
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high)
while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high)
while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low
respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 106 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Differential Output Slew Rate
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Slew Rate Definition
Delta TFse
Delta TFse
VOh diff (AC)
VOL diff (AC)
0
Differential Output Voltage (i.e. DQS-DQS)
Output Slew Rate (Differential)
Parameter
Symbol
-
800
1066
1333
1600
1866
2133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Differential
Output Slew
Rate
SRQdiff
DDR3
5
10
5
10
5
10
5
10
5
10
5
10
V/ns
DDR3L
3.5
12
3.5
12
3.5
12
3.5
12
3.5
12
3.5
12
V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 107 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Reference Load for AC Timing and Output Slew Rate
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters
of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load
presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more
coaxial transmission lines terminated at the tester electronics.
Vtt = VDDQ/2
25 Ohm
CK , 
VDDQ
DUT DQ
DQS

Timing Reference Points
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 108 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
-
800
1066
1333
1600
1866
2133
Unit
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area.
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.67
0.5
0.4
0.33
0.28
0.25
V-ns
Maximum undershoot area below VSS
0.67
0.5
0.4
0.33
0.28
0.25
V-ns
NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
VDD
VSS
Overshoot Area
Undershoot Area
Maximum Amplitude
Maximum Amplitude
Time (ns)
Volts (V)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 109 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
800
1066
1333
1600
1866
2133
Unit
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area.
0.4
0.4
0.4
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.25
0.19
0.15
0.13
0.11
0.10
V-ns
Maximum undershoot area below VSS
0.25
0.19
0.15
0.13
0.11
0.10
V-ns
NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings
NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings
VDDQ
VSSQ
Overshoot Area
Undershoot Area
Maximum Amplitude
Maximum Amplitude
Time (ns)
Volts (V)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 110 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
34 Ohm Output Driver DC Electrical Characteristics
A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of
the external reference resistor RZQ as follows:
RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
under the condition that RONPd is turned off (1)
under the condition that RONPu is turned off (2)
Output Driver: Definition of Voltages and Currents
| IOut |
VDDQ – VOut
RONPu =
| IOut |
VOut
RONPd =
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 111 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Output Driver DC Electrical Characteristics, assuming RZQ = 240ohms; entire
operating temperature range; after proper ZQ calibration
RONNom
Resistor
Vout
Min.
Nom.
Max.
Unit
Notes
DDR3L
34 ohms
RON34Pd
VOLdc = 0.2 x VDDQ
0.6
1.0
1.15
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.15
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.9
1.0
1.45
RZQ / 7
1,2,3
RON34Pu
VOLdc = 0.2 x VDDQ
0.9
1.0
1.45
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.15
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.6
1.0
1.15
RZQ / 7
1,2,3
40 ohms
RON40Pd
VOLdc = 0.2 × VDDQ
0.6
1.0
1.15
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.15
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.9
1.0
1.45
RZQ / 6
1,2,3
RON40Pu
VOLdc = 0.2 × VDDQ
0.9
1.0
1.45
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.15
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.6
1.0
1.15
RZQ / 6
1,2,3
Mismatch between pull-up and pull-down,
MMPuPd
VOMdc = 0.5 x VDDQ
-10
+10
%
1,2,4
DDR3
34 ohms
RON34Pd
VOLdc = 0.2 x VDDQ
0.6
1.0
1.1
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.9
1.0
1.4
RZQ / 7
1,2,3
RON34Pu
VOLdc = 0.2 x VDDQ
0.9
1.0
1.4
RZQ / 7
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
RZQ / 7
1,2,3
VOHdc = 0.8 x VDDQ
0.6
1.0
1.1
RZQ / 7
1,2,3
40 ohms
RON40Pd
VOLdc = 0.2 × VDDQ
0.6
1.0
1.1
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.1
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.9
1.0
1.4
RZQ / 6
1,2,3
RON40Pu
VOLdc = 0.2 × VDDQ
0.9
1.0
1.4
RZQ / 6
1,2,3
VOMdc = 0.5 × VDDQ
0.9
1.0
1.1
RZQ / 6
1,2,3
VOHdc = 0.8 × VDDQ
0.6
1.0
1.1
RZQ / 6
1,2,3
Mismatch between pull-up and pull-down,
MMPuPd
VOMdc = 0.5 x VDDQ
-10
+10
%
1,2,4
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 112 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
NOTE 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration
schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.
NOTE 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 * VDDQ:
RonNom
RonPu – RonPd
MMPuPd =
X 100
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 113 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Output Driver Sensitivity Definition
Items
Min.
Max.
Unit
RONPU@VOHdc
0.6 - dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl
RZQ/7
RON@VOMdc
0.9 - dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl
RZQ/7
RONPD@VOLdc
0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl
RZQ/7
Output Driver Voltage and Temperature Sensitivity
Speed Bin
DDR3(L)-800/1066/1333
DDR3(L)-1600
Unit
Items
Min.
Max.
Min.
Max.
dRONdTM
0
1.5
0
1.5
%/C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/C
dRONdVH
0
0.15
0
0.13
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 114 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.
ODT is applied to the DQ, DM, DQS/, and TDQS/T (x8 devices only) pins.
A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down
resistors (RTTPu and RTTPd) are defined as follows:
under the condition that RTTPd is turned off (3)
under the condition that RTTPu is turned off (4)
On-Die Termination: Definition of Voltages and Currents
| IOut |
VDDQ – VOut
RTTPu =
| IOut |
VOut
RTTPd =
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 115 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ODT DC Electrical Characteristics
The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120, RTT60Pu120,
RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification
requirements, but can be used as design guide lines:
ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating
temperature range; after proper ZQ calibration(DDR3L)
MR1 A9,A6,A2
RTT
Resistor
Vout
Min.
Nom.
Max.
Unit
Notes
DDR3L
0,1,0
120Ω
RTT120Pd240
VOLdc = 0.2 x VDDQ
0.6
1
1.15
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.45
RZQ
1,2,3,4
RTT120Pu240
VOLdc = 0.2 x VDDQ
0.9
1
1.45
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.15
RZQ
1,2,3,4
RTT120
VIL(ac) to VIH(ac)
0.9
1
1.65
RZQ /2
1,2,5
0, 0, 1
60Ω
RTT60Pd120
VOLdc = 0.2 x VDDQ
0.6
1
1.15
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.45
RZQ/2
1,2,3,4
RTT60Pu120
VOLdc = 0.2 x VDDQ
0.9
1
1.45
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.15
RZQ/2
1,2,3,4
RTT60
VIL(ac) to VIH(ac)
0.9
1
1.65
RZQ/4
1,2,5
0, 1, 1
40Ω
RTT40Pd80
VOLdc = 0.2 x VDDQ
0.6
1
1.15
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.45
RZQ/3
1,2,3,4
RTT40Pu80
VOLdc = 0.2 x VDDQ
0.9
1
1.45
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.15
RZQ/3
1,2,3,4
RTT40
VIL(ac) to VIH(ac)
0.9
1
1.65
RZQ/6
1,2,5
1, 0, 1
30Ω
RTT30Pd60
VOLdc = 0.2 x VDDQ
0.6
1
1.15
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.45
RZQ/4
1,2,3,4
RTT30Pu60
VOLdc = 0.2 x VDDQ
0.9
1
1.45
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.15
RZQ/4
1,2,3,4
RTT30
VIL(ac) to VIH(ac)
0.9
1
1.65
RZQ/8
1,2,5
1, 0, 0
20Ω
RTT20Pd40
VOLdc = 0.2 x VDDQ
0.6
1
1.15
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.45
RZQ/6
1,2,3,4
RTT20Pu40
VOLdc = 0.2 x VDDQ
0.9
1
1.45
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.15
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.15
RZQ/6
1,2,3,4
RTT20
VIL(ac) to VIH(ac)
0.9
1
1.65
RZQ/12
1,2,5
Deviation of VM w.r.t. VDDQ/2, DVM
-5
+5
%
1,2,5,6
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 116 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating
temperature range; after proper ZQ calibration (DDR3)
MR1 A9,A6,A2
RTT
Resistor
Vout
Min.
Nom.
Max.
Unit
Notes
DDR3
0,1,0
120Ω
RTT120Pd240
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
RTT120Pu240
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ
1,2,3,4
0.5 x VDDQ
0.9
1
1,1
RZQ
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ
1,2,3,4
RTT120
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ /2
1,2,5
0, 0, 1
60Ω
RTT60Pd120
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
RTT60Pu120
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/2
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/2
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/2
1,2,3,4
RTT60
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/4
1,2,5
0, 1, 1
40Ω
RTT40Pd80
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
RTT40Pu80
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/3
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/3
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/3
1,2,3,4
RTT40
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/6
1,2,5
1, 0, 1
30Ω
RTT30Pd60
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
RTT30Pu60
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/4
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/4
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/4
1,2,3,4
RTT30
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/8
1,2,5
1, 0, 0
20Ω
RTT20Pd40
VOLdc = 0.2 x VDDQ
0.6
1
1.1
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.9
1
1.4
RZQ/6
1,2,3,4
RTT20Pu40
VOLdc = 0.2 x VDDQ
0.9
1
1.4
RZQ/6
1,2,3,4
0.5 x VDDQ
0.9
1
1.1
RZQ/6
1,2,3,4
VOHdc = 0.8 x VDDQ
0.6
1
1.1
RZQ/6
1,2,3,4
RTT20
VIL(ac) to VIH(ac)
0.9
1
1.6
RZQ/12
1,2,5
Deviation of VM w.r.t. VDDQ/2, DVM
-5
+5
%
1,2,5,6
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 117 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits
if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
NOTE 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.
NOTE 4. Not a specification requirement, but a design guide line.
NOTE 5. Measurement definition for RTT:
Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current
I(VIL(ac)) respectively.
NOTE 6. Measurement definition for VM and DVM:
Measure voltage (VM) at test pin (midpoint) with no load:
RTT =
I(VIH(ac)) – I(VIL(ac))
VIH(ac) – VIL(ac)
△
VM = ( – 1) x 100
VDDQ
2 x VM
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 118 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ODT Temperature and Voltage sensitivity
If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.
Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ
ODT Sensitivity Definition
Min.
Max.
Unit
RTT
0.9 – dRTTdT * l△Tl – dRTTdV * l△Vl
1.6 + dRTTdT * l△Tl + dRTTdV * l△Vl
RZQ/2,4,6,8,12
ODT Voltage and Temperature Sensitivity
Min.
Max.
Unit
dRTTdT
0
1.5
%/C
dRTTdV
0
0.15
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in the following figure.
Vtt =
25 Ohm
CK ,
VDDQ
DUT
Timing Reference Points
VSSQ
RTT=
DQ , DM
DQS , 
TDQS , T
VSSQ

ODT Timing Reference Load
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 119 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures.
Symbol
Begin Point Definition
End Point Definition
tAON
Rising edge of CK - CK defined by the end point of ODTLon
Extrapolated point at VSSQ
tAONPD
Rising edge of CK - CK with ODT being first registered high
Extrapolated point at VSSQ
tAOF
Rising edge of CK - CK defined by the end point of ODTLoff
End point: Extrapolated point at VRTT_Nom
tAOFPD
Rising edge of CK - CK with ODT being first registered low
End point: Extrapolated point at VRTT_Nom
tADC
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4, or ODTLcwn8
End point: Extrapolated point at VRTT_Wr and
VRTT_Nom respectively
Reference Settings for ODT Timing Measurements
Parameter
RTT_Nom
RTT_Wr
DDR3
DDR3L
VSW1[V]
VSW2[V]
VSW1[V]
VSW2[V]
tAON
RZQ/4
NA
0.05
0.10
0.05
0.10
RZQ/12
NA
0.10
0.20
0.10
0.20
tAONPD
RZQ/4
NA
0.05
0.10
0.05
0.10
RZQ/12
NA
0.10
0.20
0.10
0.20
tAOF
RZQ/4
NA
0.05
0.10
0.05
0.10
RZQ/12
NA
0.10
0.20
0.10
0.20
tAOFPD
RZQ/4
NA
0.05
0.10
0.05
0.10
RZQ/12
NA
0.10
0.20
0.10
0.20
tADC
RZQ/12
RZQ/2
0.20
0.30
0.20
0.25
Definition of tAON
tAON
Tsw2
Tsw1
Vsw1 Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VSSQ
CK
CK#
Begin point: Rising edge of CK – CK#
Defined by the end point of ODTLon
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 120 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Definition of tAONPD
tAONPD
Tsw2
Tsw1
Vsw1 Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VSSQ
CK
CK#
Begin point: Rising edge of CK – CK#
with ODT being first register high
Definition of tAOF
tAOF
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_Nom
CK
CK#
Begin point: Rising edge of CK – CK#
defined by the end point of ODTLoff
VRTT_Nom
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 121 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Definition of tAOFPD
tAOFPD
Tsw2
Tsw1
Vsw1
Vsw2
VSSQ
VTT
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_Nom
CK
CK#
Begin point: Rising edge of CK – CK#
with ODT being first registered low
VRTT_Nom
Definition of tADC
tADC
Tsw21
Tsw11
Vsw1
Vsw2
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point: Extrapolated point at VRTT_Nom
CK
CK#
Begin point: Rising edge of CK – CK#
defined by the end of ODTLcnw
VRTT_Nom
tADC
Tsw22
Tsw12
VSSQ
VTT
End point: Extrapolated point at VRTT_Wr
CK
CK#
Begin point: Rising edge of CK – CK# defined
by the end of ODTLcwn4 or ODTLcwn8
VRTT_Wr
VRTT_Nom
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 122 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Input/Output Capacitance
Parameter
Symbol
800
1066
1333
1600
1866
2133
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, ,
TDQS,T)
CIO
(DDR3)
1.4
3.0
1.4
2.7
1.4
2.5
1.4
2.3
1.4
2.2
1.4
2.1
pF
1,2,3
CIO
(DDR3L)
1.4
2.5
1.4
2.5
1.4
2.3
1.4
2.2
1.4
2.1
-
-
pF
1,2,3
Input capacitance, CK and 
CCK
0.8
1.6
0.8
1.6
0.8
1.4
0.8
1.4
0.8
1.3
0.8
1.3
pF
2,3
Input capacitance delta, CK and 
CDCK
0
0.15
0
0.15
0
0.15
0
0.15
0
0.15
0
0.15
pF
2,3,4
Input/output capacitance delta
DQS and 
CDDQS
0
0.15
0
0.15
0
0.15
0
0.15
0
0.15
0
0.15
pF
2,3,5
Input capacitance,
(CTRL, ADD,CMD input-only pins)
CI
(DDR3)
0.75
1.4
0.75
1.35
0.75
1.3
0.75
1.3
0.75
1.2
0.75
1.2
pF
2,3,6
CI
(DDR3L)
0.75
1.3
0.75
1.3
0.75
1.3
0.75
1.2
0.75
1.2
-
-
pF
2,3,6
Input capacitance delta,
(All CTRL input-only pins
CDI_CTRL
-0.5
0.3
-0.5
0.3
-0.4
0.2
-0.4
0.2
-0.4
0.2
-0.4
0.2
pF
2,3,7,8
Input capacitance delta,
(All ADD/CMD input-only pins)
CDI_ADD_
CMD
-0.5
0.5
-0.5
0.5
-0.4
0.4
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF
2,3,9,
10
Input/output capacitance delta, DQ,
DM, DQS, , TDQS, T
CDIO
-0.5
0.3
-0.5
0.3
-0.5
0.3
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2,3,11
Input/output capacitance of ZQ pin
CZQ
-
3
-
3
-
3
-
3
-
3
-
3
pF
2,3,12
NOTE 1. Although the DM, TDQS and T pins have different functions, the loading matches DQ and DQS
NOTE 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured
according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”)
with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, REET and ODT as necessary).
VDD=VDDQ=1.5V, VBIAS=VDD/2 and ondie termination off.
NOTE 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
NOTE 4. Absolute value of CCK-
NOTE 5. Absolute value of CIO(DQS)-CIO()
NOTE 6. CI applies to ODT, , CKE, A0-A15, BA0-BA2, RA, A, WE.
NOTE 7. CDI_CTRL applies to ODT,  and CKE
NOTE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(L))
NOTE 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RA, A and WE
NOTE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(L))
NOTE 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO())
NOTE 12. Maximum external load capacitance on ZQ pin: 5 pF.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 123 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3L IDD Currents
Symbol
Parameter/Condition
DDR3L-1600
(-DI/DII) (11-11-11)
DDR3L-1866
(13-13-13)
Unit
X8
X16
X8
X16
IDD0
Operating Current 0
One Bank Activate-> Precharge
50
60
56
66
mA
IDD1
Operating Current 1
One Bank Activate-> Read-> Precharge
56
80
61
84
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
16
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
24
29
mA
IDD2Q
Precharge Quiet Standby Current
24
27
mA
IDD2N
Precharge Standby Current
24
27
mA
IDD2NT
Precharge Standby ODT Current
30
34
33
37
mA
IDD3P
Active Power-Down Current
Always Fast Exit
30
33
mA
IDD3N
Active Standby Current
32
40
35
42
mA
IDD4R
Operating Current Burst Read
132
210
150
230
mA
IDD4W
Operating Current Burst Write
108
150
123
170
mA
IDD5B
Burst Refresh Current
175
185
mA
IDD6TC 1
(RS -DIB)
Self-Refresh Current:
Room Temperature Range
3.7
mA
IDD6 2
Self-Refresh Current
Normal
20
mA
IDD6ET 3
Self-Refresh Current:
Extended
22
mA
IDD7
All Bank Interleave Read Current
170
210
190
240
mA
IDD8
Reset Low Current
18
18
mA
NOTE 1 IDD6TC (RS-DIB):TC ≤ Room Temperature; SRT is disabled, ASR is enabled. Value is maximum.
NOTE 2 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum.
- Commercial Grade = 0℃~85℃
- Industrial Grade (-I) = -40℃~85℃
- Automotive Grade 2 (-H) = -40℃~85℃
- Automotive Grade 3 (-A) = -40℃~85℃
NOTE 3 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum.
- Commercial Grade = 0℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 124 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
DDR3 IDD Currents
Symbol
Parameter/Condition
DDR3-1600
(11-11-11)
DDR3-1866
(13-13-13)
DDR3-2133
(14-14-14)
Unit
X8
X16
X8
X16
X8
X16
IDD0
Operating Current 0
One Bank Activate -> Precharge
52
63
58
70
67
79
mA
IDD1
Operating Current 1
One Bank Activate-> Read-> Precharge
60
83
64
87
69
92
mA
IDD2P0
Precharge Power-Down Current
Slow Exit - MR0 bit A12 = 0
18
18
18
mA
IDD2P1
Precharge Power-Down Current
Fast Exit - MR0 bit A12 = 1
27
32
38
mA
IDD2Q
Precharge Quiet Standby Current
27
30
32
mA
IDD2N
Precharge Standby Current
27
30
32
mA
IDD2NT
Precharge Standby ODT Current
35
38
38
41
42
45
mA
IDD3P
Active Power-Down Current
Always Fast Exit
35
38
41
mA
IDD3N
Active Standby Current
35
43
38
45
41
48
mA
IDD4R
Operating Current Burst Read
140
220
155
240
173
270
mA
IDD4W
Operating Current Burst Write
115
160
130
180
150
190
mA
IDD5B
Burst Refresh Current
180
190
200
mA
IDD6 1
Self-Refresh Current
Normal
22
mA
IDD6ET 2
Self-Refresh Current
Extended
26
mA
IDD7
All Bank Interleave Read Current
175
220
200
250
235
280
mA
IDD8
Reset Low Current
20
mA
NOTE 1 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum.
- Commercial Grade = 0℃~85℃
- Industrial Grade (-I) = -40℃~85℃
- Automotive Grade 2 (-H) = -40℃~85℃
- Automotive Grade 3 (-A) = -40℃~85℃
NOTE 2 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum.
- Commercial Grade = 0℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 125 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD Measurement Conditions
Symbol
Parameter/Condition
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On;
tCK, nRC, nRAS, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
:High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On;
tCK, nRC, nRAS, nRCD, CL: see see the table of Timings used for IDD and IDDQ;
BL: 8(1,7); AL:0;
: High between ACT, RD and PRE;
Command, Address, Bank Address Inputs, Data IO: partially toggling;
Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD2N
Precharge Standby Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0; : stable at 1;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD2P(0)
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 126 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Command, Address, Bank Address Inputs: stable at 0;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
Pecharge Power Down Mode: Slow Exit(3)
IDD2P(1)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
Command, Address, Bank Address Inputs: stable at 0;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
Pecharge Power Down Mode: Fast Exit(3)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
Command, Address, Bank Address Inputs: stable at 0;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: MID-LEVEL;
DM:stable at 0;
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 127 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD3P
Active Power-Down Current
CKE: Low; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: stable at 1;
Command, Address, Bank Address Inputs: stable at 0;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: all banks open;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0
IDD4R
Operating Burst Read Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1,7); AL: 0;
: High between RD;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: seamless read data burst with different data between one burst and the next one;
DM:stable at 0;
Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD4W
Operating Burst Write Current
CKE: High; External clock: On;
tCK, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: High between WR;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: seamless write data burst with different data between one burst and the next one ;
DM: stable at 0;
Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at HIGH;
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 128 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD5B
Burst Refresh Current
CKE: High; External clock: On;
tCK, CL, nRFC: see the table of Timings used for IDD and IDDQ;
BL: 8(1); AL: 0;
: High between REF;
Command, Address, Bank Address Inputs: partially toggling;
Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity: REF command every nRFC;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C;
Auto Self-Refresh (ASR): Disabled(4);
Self-Refresh Temperature Range (SRT):Normal(5);
CKE: Low; External clock: Off;
CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1);AL: 0;
, Command, Address, Bank Address, Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity:Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: MID-LEVEL
IDD6ET
Self-Refresh Current: Extended Temperature Range (optional)(6)
TCASE: 0 - 95°C;
Auto Self-Refresh (ASR): Disabled(4);
Self-Refresh Temperature Range (SRT):Extended(5);
CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1);AL: 0;
, Command, Address, Bank Address, Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity:Extended Temperature Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: MID-LEVEL
IDD6TC
Auto Self-Refresh Current (optional)(6)
TCASE: 0 - 95°C;
Auto Self-Refresh (ASR): Enabled(4);
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 129 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Self-Refresh Temperature Range (SRT):Normal(5);
CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1);AL: 0;
, Command, Address, Bank Address, Data IO: MID-LEVEL;
DM:stable at 0;
Bank Activity:Auto Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: MIDLEVEL
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On;
tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the table of Timings used for IDD and IDDQ;
BL: 8(1,7); AL: CL-1;
: High between ACT and RDA;
Command, Address, Bank Address Inputs:partially toggling;
Data IO: read data bursts with different data between one burst and the next one;
DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing;
Output Buffer and RTT: Enabled in Mode Registers(2);
ODT Signal: stable at 0;
IDD8
RESET Low Current
RESET: LOW; External clock: Off;
CK and : LOW; CKE: FLOATING;
, Command, Address,Bank Address, Data IO: FLOATING;
ODT Signal: FLOATING
RESET Low current reading is valid once power is stable and RESET has been LOW for at least 1ms.
NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr
enable: set MR2 A[10,9] = 10B
NOTE 3. Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by
DDR3 SDRAM device
NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 130 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD0 Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 131 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD1 Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 132 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD2N and IDD3N Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 133 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD4R and IDDQ4R Measurement-Loop Pattern
IDD4W Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 134 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD5B Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 135 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
IDD7 Measurement-Loop Pattern
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 136 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Operating Frequency
DDR3-2133
Speed Bins
DDR3-2133
14-14-14
Unit
Parameter
Min
Max
tCK
(Avg)
CL5
CWL5
Reserved
ns
CWL6/7/8/9/10
Reserved
ns
CL6
CWL5
2.5
3.3
ns
CWL6
Reserved
ns
CWL7/8/9/10
Reserved
ns
CL7
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7
Reserved
ns
CWL8/9/10
Reserved
ns
CL8
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7
Reserved
ns
CWL8/9/10
Reserved
ns
CL9
CWL5/6
Reserved
ns
CWL7
1.5
< 1.875
ns
CWL8
Reserved
ns
CWL9/10
Reserved
ns
CL10
CWL5/6
Reserved
ns
CWL7
1.5
< 1.875
ns
CWL8
Reserved
ns
CWL9
Reserved
ns
CWL10
Reserved
ns
CL11
CWL5/6/7
Reserved
ns
CWL8
1.25
< 1.5
ns
CWL9
Reserved
ns
CWL10
Reserved
ns
tCK
(Avg)
CL12
CWL5/6/7/8
Reserved
ns
CWL9
Reserved
ns
CWL10
Reserved
ns
CL13
CWL5/6/7/8
Reserved
ns
CWL9
1.07
< 1.25
ns
CWL10
Reserved
ns
CL14
CWL5/6/7/8/9
Reserved
ns
CWL10
0.938
< 1.07
ns
Supported CL
5,6,7,8,9,10,11,12,13,14
nCK
Supported CWL
5,6,7,8,9,10
nCK
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 137 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Operating Frequency
DDR3-1866 and DDR3L-1866
Speed Bins
DDR3(L)-1866
13-13-13
Unit
Parameter
Min
Max
tCK
(Avg)
CL5
CWL5
Reserved
ns
CWL6/7/8/9
Reserved
ns
CL6
CWL5
2.5
3.3
ns
CWL6
Reserved
ns
CWL7/8/9
Reserved
ns
CL7
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7/8/9
Reserved
ns
CL8
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7
Reserved
ns
CWL8/9
Reserved
ns
CL9
CWL5/6
Reserved
ns
CWL7
1.5
< 1.875
ns
CWL8
Reserved
ns
CWL9
Reserved
ns
CL10
CWL5/6
Reserved
ns
CWL7
1.5
< 1.875
ns
CWL8
Reserved
ns
CL11
CWL5/6/7
Reserved
ns
CWL8
1.25
< 1.5
ns
CWL9
Reserved
ns
CL12
CWL5/6/7/8
Reserved
ns
CWL9
Reserved
ns
CL13
CWL5/6/7/8
Reserved
ns
CWL9
1.07
< 1.25
ns
Supported CL
6,7,8,9,10,11,13
nCK
Supported CWL
5, 6, 7, 8, 9
nCK
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 138 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Operating Frequency
DDR3-1600 and DDR3L-1600
Speed Bins
DDR3(L)-1600
11-11-11
Unit
Parameter
Min
Max
tCK
(Avg)
CL5
CWL5
3.0
3.3
ns
CWL6/7/8
Reserved
ns
CL6
CWL5
2.5
3.3
ns
CWL6
Reserved
ns
CWL7/8
Reserved
ns
CL7
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7
Reserved
ns
CWL8
Reserved
ns
CL8
CWL5
Reserved
ns
CWL6
1.875
< 2.5
ns
CWL7
Reserved
ns
CWL8
Reserved
ns
CL9
CWL5/6
Reserved
ns
CWL7
1.5
<1.875
ns
CWL8
Reserved
ns
CL10
CWL5/6
Reserved
ns
CWL7
1.5
< 1.875
ns
CWL8
Reserved
ns
CL11
CWL5/6/7
Reserved
ns
CWL8
1.25
<1.5
ns
Supported CL
5, 6, 7, 8, 9, 10, 11
nCK
Supported CWL
5, 6, 7, 8
nCK
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 139 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Operating Frequency
DDR3-1333 and DDR3L-1333
Speed Bins
DDR3(L)-1333
9-9-9
DDR3(L)-1333
10-10-10
Unit
Parameter
Min
Max
Min
Max
tCK
(Avg)
CL5
CWL5
3.0
3.3
3.0
3.3
ns
CWL6/7
Reserved
Reserved
ns
CL6
CWL5
2.5
3.3
2.5
3.3
ns
CWL6
Reserved
Reserved
ns
CWL7
Reserved
Reserved
ns
CL7
CWL5
Reserved
Reserved
ns
CWL6
1.875
< 2.5
Reserved
ns
CWL7
Reserved
Reserved
ns
CL8
CWL5
Reserved
Reserved
ns
CWL6
1.875
< 2.5
1.875
< 2.5
ns
CWL7
Reserved
Reserved
ns
CL9
CWL5/6
Reserved
Reserved
ns
CWL7
1.5
< 1.875
Reserved
ns
CL10
CWL5/6
Reserved
Reserved
ns
CWL7
1.5
< 1.875
1.5
< 1.875
ns
Supported CL
5, 6, 7, 8, 9, 10
5, 6, 8, 10
nCK
Supported CWL
5, 6, 7
5, 6, 7
nCK
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 140 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Fundamental AC Specifications – Operating Frequency
DDR3-1066 and DDR3L-1066
Speed Bins
DDR3(L)-1066
7-7-7
DDR3(L)-1066
8-8-8
Unit
Parameter
Min
Max
Min
Max
tCK
(Avg)
CL5
CWL5
3.0
3.3
3.0
3.3
ns
CWL6
Reserved
Reserved
ns
CL6
CWL5
2.5
3.3
2.5
3.3
ns
CWL6
Reserved
Reserved
ns
CL7
CWL5
Reserved
Reserved
ns
CWL6
1.875
< 2.5
Reserved
ns
CL8
CWL5
Reserved
Reserved
ns
CWL6
1.875
< 2.5
1.875
< 2.5
ns
Supported CL
5, 6, 7, 8
5, 6, 8
nCK
Supported CWL
5, 6
5, 6
nCK
DDR3-800 and DDR3L-800
Speed Bins
DDR3(L)-800
5-5-5
DDR3(L)-800
6-6-6
Unit
Parameter
Min
Max
Min
Max
tCK
(Avg)
CL5
CWL5
2.5
3.3
3.0
3.3
ns
CL6
CWL5
2.5
3.3
2.5
3.3
ns
Supported CL
5, 6
5, 6
nCK
Supported CWL
5
5
nCK
Fundamental AC Specifications Notes
NOTE 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of
tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
NOTE 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
tCK(AVG) value (3.0, 2.5, 1.875, 1.5, 1.25, 1.07, or 0.938 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding
up to the next ‘Supported CL’, where tCK(AVG) = 3.0 ns should only be used for CL = 5 calculation.
NOTE 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next
valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.5 ns or 1.25 ns or 1.07 ns or 0.938 ns). This result is tCK(AVG).MAX
corresponding to CL SELECTED.
NOTE 4. ‘Reserved’ settings are not allowed. User must program a different value.
NOTE 5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 141 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
supplier’s data sheet and/or the DIMM SPD information if and how this setting is supported.
NOTE 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject
to Production Tests but verified by Design/Characterization.
NOTE 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject
to Production Tests but verified by Design/Characterization.
NOTE 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject
to Production Tests but verified by Design/Characterization.
NOTE 9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject
to Production Tests but verified by Design/Characterization.
NOTE 10.Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject
to Production Tests but verified by Design/Characterization.
NOTE 11.For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRPmin must be 13.125 ns. SPD settings must be
programmed to match. For example, DDR3-1333(9-9-9) devices supporting down binning to DDR3-1066(7-7-7) should
program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(11-11-11)
devices supporting down binning to DDR3-1333(9-9-9) or DDR3-1066(7-7-7) should program 13.125 ns in SPD bytes for
tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte
21,23) also should be programmed accodingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for
DDR3-1333(9-9-9) and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600(11-11-11).
NOTE 12.DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
NOTE 13.For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.
NOTE 14.For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting
must be programed to match. For example, DDR3-1866(13-13-13) devices supporting down binning to DDR3-1600(11-11-11)
or DDR3-1333(9-9-9) or 1066(7-7-7) should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and
tRPmin (byte20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed
accordingly. For example, 47.125ns (tRASmin + tRPmin = 34 ns+ 13.125 ns)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 142 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Electrical Characteristics & AC Timing
Timing Parameters for DDR3(L)-800, DDR3(L)-1066, and DDR3(L)-1333
Parameter
Symbol
DDR3(L)-800
DDR3(L)-1066
DDR3(L)-1333
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_off)
8
-
8
-
8
-
ns
Average Clock Period
tCK(avg)
Refer to “Fundamental AC Specifications”
ps
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT (per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-100
100
-90
90
-80
80
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-90
90
-80
80
-70
70
ps
Cycle to Cycle Period Jitter
tJIT(cc)
200
180
160
ps
Cycle to Cycle Period Jitter during DLL
locking period
JIT(cc, lck)
180
160
140
ps
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
-
-
ps
Cumulative error across n = 2, 14 . . . 49, 50
cycles
tERR(nper)
tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min
tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max
ps
Data Timing
DQS,  to DQ skew, per group, per
access
tDQSQ
-
200
-
150
-
125
ps
DQ output hold time from DQS, 
tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, 
tLZ(DQ)
-800
400
-600
300
-500
250
ps
DQ high impedance time from CK, 
tHZ(DQ)
-
400
-
300
-
250
ps
Data setup time to DQS,  referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
DDR3-AC175
75
-
25
-
-
-
ps
tDS(base)
DDR3-AC150
125
-
75
-
30
-
ps
tDS(base)
DDR3L-AC160
90
-
40
-
-
-
ps
tDS(base)
DDR3L-AC135
140
-
90
-
45
-
ps
Data hold time from DQS,  referenced
to
Vih(dc) / Vil(dc) levels
tDH(base)
DDR3-DC100
150
-
100
-
65
-
ps
tDH(base)
DDR3L-DC90
160
-
110
-
75
-
ps
DQ and DM Input pulse width for each input
tDIPW
600
-
490
-
400
-
ps
Data Strobe Timing
DQS, differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
tCK(avg)
DQS,  differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
tCK(avg)
DQS,  differential output high time
tQSH
0.38
-
0.38
-
0.4
-
tCK(avg)
DQS,  differential output low time
tQSL
0.38
-
0.38
-
0.4
-
tCK(avg)
DQS,  differential WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK(avg)
DQS,  differential WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK(avg)
DQS,  rising edge output access time
from rising CK, 
tDQSCK
-400
400
-300
300
-255
255
ps
DQS and  low-impedance time
(Referenced from RL – 1)
tLZ(DQS)
-800
400
-600
300
-500
250
ps
DQS and  high-impedance time
(Referenced from RL + BL/2)
tHZ(DQS)
-
400
-
300
-
250
ps
DQS,  differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,  differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,  rising edge to CK,  rising edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,  falling edge setup time to
CK,  rising edge
tDSS
0.2
-
0.2
-
0.2
-
tCK(avg)
DQS,  falling edge hold time from
CK,  rising edge
tDSH
0.2
-
0.2
-
0.2
-
tCK(avg)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 143 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
nCK
Internal READ Command to
PRECHARGE Command delay
tRTP
tRTPmin.: max(4tCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
tWTR
tWTRmin.: max(4tCK, 7.5ns)
tWTRmax.: -
WRITE recovery time
tWR
15
-
15
-
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12tCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
Refer to “Fundamental AC Specifications”
PRE command period
tRP
ACT to ACT or REF command period
tRC
ACTIVE to PRECHARGE command period
tRAS
A to A command delay
tCCD
4
-
4
-
4
-
nCK
Auto precharge write recovery + precharge
time
tDAL(MIN)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
1
-
nCK
ACTIVE to ACTIVE command period (1KB
page size)
tRRD
max(4tCK,1
0ns)
-
max(4t
CK,7.5n
s)
-
max(4tCK
,6ns)
-
ACTIVE to ACTIVE command period (2KB
page size)
tRRD
max(4tCK,1
0ns)
-
max(4t
CK,10n
s)
-
max(4tCK
,7.5ns)
-
Four activate window (1KB page size)
tFAW
40
-
37.5
-
30
-
ns
Four activate window (2KB page size)
tFAW
50
-
50
-
45
-
ns
Command and Address setup time to CK,
 referenced to Vih(ac) / Vil(ac) levels
tIS(BASE)
DDR3-AC175
200
-
125
-
65
-
ps
tIS(BASE)
DDR3-AC150
350
-
275
-
190
-
ps
tIS(BASE)
DDR3L-AC160
215
-
140
-
80
-
ps
tIS(BASE)
DDR3L-AC135
365
-
290
-
205
-
ps
Command and Address hold time from CK,
 referenced to Vih(dc) / Vil(dc) levels
tIH(BASE)
DDR3-DC100
275
-
200
-
140
-
ps
tIH(BASE)
DDR3L-DC90
285
-
210
-
150
-
ps
Control and Address Input pulse width for
each input
tIPW
900
-
780
-
620
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQINIT
tZQINITmin: max(512tCK, 640ns)
tZQINITmax: -
Normal operation Full calibration time
tZQOPER
tZQOPERmin: max(256tCK, 320ns)
tZQOPERmax: -
Normal operation Short calibration time
tZQCS
tZQCSmin: max(64 tCK, 80ns)
tZQCSmax: -
Reset Timing
Exit Reset from CKE HIGH to a valid
command
tXPR
tXPRmin.: max(5 tCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring
a locked DLL
tXS
tXSmin.: max(5 tCK, tRFC (min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
Minimum CKE low width for Self Refresh
entry to
exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 tCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh
Entry (SRE) or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 tCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self
Refresh Exit (SRX) or Power-Down Exit
(PDX) or Reset Exit
tCKSRX
tCKSRXmin.: max(5 tCK, 10 ns)
tCKSRXmax.: -
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 144 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Power Down Timings
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
tXP
max(3tCK,7.
5ns)
-
max(3t
CK,7.5n
s)
-
max(3tCK
,6ns)
-
CKE minimum pulse width
tCKE
max(3tCK7.
5ns)
-
max(3t
CK,5.62
5ns)
-
max(3tCK
,5.625ns)
-
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10tCK, 24ns)
tXPDLLmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmin.: -
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tACTPDENmin.: 1
tACTPDENmax.: -
nCK
Timing of PRE or PREA command to Power
Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power
Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down
entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down
entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down
entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down
entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT turn on Latency
ODTLon
WL-2=CWL+AL-2
nCK
ODT turn off Latency
ODTLoff
WL-2=CWL+AL-2
nCK
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
RTT turn-on
tAON
-400
400
-300
300
-250
250
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/ rising edge after
write leveling mode is programmed
tWLMRD
40
-
40
-
40
-
nCK
DQS/ delay after write leveling mode is
programmed
tWLDQSEN
25
-
25
-
25
-
nCK
Write leveling setup time from rising CK, 
crossing to rising DQS,  crossing
tWLS
325
-
245
-
195
-
ps
Write leveling hold time from rising DQS,
 crossing to rising CK,  crossing
tWLH
325
-
245
-
195
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 145 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Timing Parameters for DDR3(L)-1600, DDR3(L)-1866, and DDR3(L)-2133
Parameter
Symbol
DDR3(L)-1600
DDR3(L)-1866
DDR3(L)-2133
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK (DLL_off)
8
-
8
-
8
-
ns
Average Clock Period
tCK(avg)
Refer to “Fundamental AC Specifications”
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Absolute Clock Period
tCK(abs)
Min.: Tck(avg)min + Tjit(per)min
Max.: Tck(avg)max + Tjit(per)max
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Clock Period Jitter
JIT(per)
-70
70
-60
60
-50
50
ps
Clock Period Jitter during DLL locking period
JIT(per, lck)
-60
60
-50
50
-40
40
ps
Cycle to Cycle Period Jitter
tJIT(cc)
140
120
100
Cycle to Cycle Period Jitter during DLL
locking period
JIT(cc, lck)
120
100
80
Duty Cycle Jitter
tJIT(duty)
-
-
-
-
-
-
ps
Cumulative error across n = 2, 14 . . . 49, 50
cycles
tERR(nper)
tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min
tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max
ps
Data Timing
DQS,  to DQ skew, per group, per
access
tDQSQ
-
100
-
85
-
75
ps
DQ output hold time from DQS, 
tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, 
tLZ(DQ)
-450
225
-390
195
-360
180
ps
DQ high impedance time from CK, 
tHZ(DQ)
-
225
-
195
-
180
ps
Data setup time to DQS,  referenced to
Vih(ac) / Vil(ac) levels
tDS(base)
DDR3-1600(AC
175)
DDR3-1866/21
33(AC150)
-
-
-
-
-
-
ps
tDS(base)
DDR3-1600(AC
150)
DDR3-1866/21
33(AC135)
10
-
68
-
53
-
ps
tDS(base)
DDR3L-1600(AC1
35) ,SR=1V/ns
DDR3L-1866(AC1
30),SR=2V/ns
25
-
70
-
-
-
ps
Data hold time from DQS,  referenced
to
Vih(dc) / Vil(dc) levels
tDH(base)
DC100
45
-
-
-
-
-
ps
tDH(base)
DC90
DDR3L-1600(SR
=1V/ns)
DDR3L-1866(SR
=2V/ns)
55
-
75
-
-
-
ps
DQ and DM Input pulse width for each input
tDIPW
360
-
320
-
280
-
ps
Data Strobe Timing
DQS, differential READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
tCK(avg)
DQS,  differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
tCK(avg)
DQS,  differential output high time
tQSH
0.4
-
0.4
-
0.4
-
tCK(avg)
DQS,  differential output low time
tQSL
0.4
-
0.4
-
0.4
-
tCK(avg)
DQS,  differential WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK(avg)
DQS,  differential WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK(avg)
DQS,  rising edge output access time
from rising CK, 
tDQSCK
-225
225
-195
195
-180
180
ps
DQS and  low-impedance time
(Referenced from RL – 1)
tLZ(DQS)
-450
225
-390
195
-360
180
ps
DQS and  high-impedance time
tHZ(DQS)
-
225
-
195
-
180
ps
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 146 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
(Referenced from RL + BL/2)
DQS,  differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,  differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK(avg)
DQS,  rising edge to CK,  rising edge
tDQSS
-0.27
0.27
-0.27
0.27
-0.27
0.27
tCK(avg)
DQS,  falling edge setup time to
CK,  rising edge
tDSS
0.18
-
0.18
-
0.18
-
tCK(avg)
DQS,  falling edge hold time from
CK,  rising edge
tDSH
0.18
-
0.18
-
0.18
-
tCK(avg)
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
nCK
Internal READ Command to
PRECHARGE Command delay
tRTP
tRTPmin.: max(4tCK, 7.5ns)
tRTPmax.: -
Delay from start of internal write
transaction to internal read command
tWTR
tWTRmin.: max(4tCK, 7.5ns)
tWTRmax.: -
WRITE recovery time
tWR
15
-
15
-
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
tMODmin.: max(12tCK, 15ns)
tMODmax.:
ACT to internal read or write delay time
tRCD
Refer to “Fundamental AC Specifications”
PRE command period
tRP
ACT to ACT or REF command period
tRC
ACTIVE to PRECHARGE command period
tRAS
A to A command delay
tCCD
4
-
4
-
4
-
nCK
Auto precharge write recovery + precharge
time
tDAL(MIN)
WR + roundup(tRP / tCK(avg))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
1
-
nCK
ACTIVE to ACTIVE command period (1KB
page size)
tRRD
max(4tCK,
6ns)
-
max(4tCK
,5ns)
-
max(4tCK
,5ns)
-
ACTIVE to ACTIVE command period (2KB
page size)
tRRD
max(4tCK,
7.5ns)
-
max(4tCK
,6ns)
-
max(4tCK
,6ns)
-
Four activate window (1KB page size)
tFAW
30
-
27
-
25
-
ns
Four activate window (2KB page size)
tFAW
40
-
35
-
35
-
ns
Command and Address setup time to CK,
 referenced to Vih(ac) / Vil(ac) levels
tIS(BASE)
DDR3-1600(AC
175)
DDR3-1866/21
33(AC150)
45
-
-
-
-
-
ps
tIS(BASE)
DDR3-1600(AC
150)
DDR3-1866/21
33(AC125)
170
-
150
-
135
-
ps
tIS(BASE)
DDR3L
(AC160)
60
-
-
-
-
ps
tIS(BASE)
DDR3L
(AC135)
185
-
65
-
-
-
ps
tIS(BASE)
DDR3L
(AC125)
-
-
150
-
-
-
ps
Command and Address hold time from CK,
 referenced to Vih(dc) / Vil(dc) levels
tIH(BASE)
DDR3
DC100
120
-
100
-
95
-
ps
tIH(BASE)
DDR3L
DC90
130
-
110
-
-
-
ps
Control and Address Input pulse width for
each input
tIPW
560
-
535
-
470
-
ps
Calibration Timing
Power-up and RESET calibration time
tZQINIT
tZQINITmin: max(512tCK, 640ns)
tZQINITmax: -
Normal operation Full calibration time
tZQOPER
tZQOPERmin: max(256tCK, 320ns)
tZQOPERmax: -
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 147 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Normal operation Short calibration time
tZQCS
tZQCSmin: max(64 tCK, 80ns)
tZQCSmax: -
Reset Timing
Exit Reset from CKE HIGH to a valid
command
tXPR
tXPRmin.: max(5 tCK, tRFC(min) + 10ns)
tXPRmax.: -
Self Refresh Timings
Exit Self Refresh to commands not requiring
a locked DLL
tXS
tXSmin.: max(5 tCK, tRFC (min) + 10ns)
tXSmax.: -
Exit Self Refresh to commands requiring a
locked DLL
tXSDLL
tXSDLLmin.: tDLLK(min)
tXSDLLmax.: -
nCK
Minimum CKE low width for Self Refresh
entry to
exit timing
tCKESR
tCKESRmin.: tCKE(min) + 1 tCK
tCKESRmax.: -
Valid Clock Requirement after Self Refresh
Entry (SRE) or Power-Down Entry (PDE)
tCKSRE
tCKSREmin.: max(5 tCK, 10 ns)
tCKSREmax.: -
Valid Clock Requirement before Self
Refresh Exit (SRX) or Power-Down Exit
(PDX) or Reset Exit
tCKSRX
tCKSRXmin.: max(5 tCK, 10 ns)
tCKSRXmax.: -
Power Down Timings
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with
DLL frozen to commands not requiring a
locked DLL
tXP
max(3tCK,
6ns)
-
max(3tCK
,6ns)
-
max(3tCK
,6ns)
-
CKE minimum pulse width
tCKE
max(3tCK
5ns)
-
max(3tCK
,5ns)
-
max(3tCK
,5ns)
-
Exit Precharge Power Down with DLL frozen
to commands requiring a locked DLL
tXPDLL
tXPDLLmin.: max(10tCK, 24ns)
tXPDLLmax.: -
Command pass disable delay
tCPDED
tCPDEDmin.: 1
tCPDEDmin.: -
nCK
Power Down Entry to Exit Timing
tPD
tPDmin.: tCKE(min)
tPDmax.: 9*tREFI
Timing of ACT command to Power Down
entry
tACTPDEN
tACTPDENmin.: 1
tACTPDENmax.: -
nCK
Timing of PRE or PREA command to Power
Down entry
tPRPDEN
tPRPDENmin.: 1
tPRPDENmax.: -
nCK
Timing of RD/RDA command to Power
Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down
entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down
entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR /tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down
entry (BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down
entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down
entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT turn on Latency
ODTLon
WL-2=CWL+AL-2
nCK
ODT turn off Latency
ODTLoff
WL-2=CWL+AL-2
nCK
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
RTT turn-on
tAON
-225
225
-195
195
-180
180
ps
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 148 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/ rising edge after
write leveling mode is programmed
tWLMRD
40
-
40
-
40
-
nCK
DQS/ delay after write leveling mode is
programmed
tWLDQSEN
25
-
25
-
25
-
nCK
Write leveling setup time from rising CK, 
crossing to rising DQS,  crossing
tWLS
165
-
140
-
125
-
ps
Write leveling hold time from rising DQS,
 crossing to rising CK,  crossing
tWLH
165
-
140
-
125
-
ps
Write leveling output delay
tWLO
0
7.5
0
7.5
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
Jitter Notes
Note 1
Unit “Tck(avg)” represents the actual Tck(avg) of the input clock under operation. Unit “Nck” represents one clock cycle of
the input clock, counting the actual clock edges. Ex) Tmrd=4 [Nck] means; if one Mode Register Set command is regis-
tered at Tm, anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x Tck(avg) +
Terr(4per), min.
Note 2
These parameters are measured from a command/address signal (CKE, , RA, A, WE, ODT, BA0, A0, A1, etc)
transition edge to its respective clock signal (CK/) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. Tjit(per), Tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
Note 3
These parameters are measured from a data strobe signal (DQS(L/U), LU)) crossing to its respective clock signal
(CK, ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. Tjit(per), Tjit(cc), etc), as
these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or
not.
Note 4
These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective
data strobe signal (DQS(L/U), LU) crossing.
Note 5
For these parameters, the DDR3(L) SDRAM device supports tnPARAM [Nck] = RU{Tparam[ns] / tCK(avg)[ns]}, which is
in clock cycles, assuming all input clock jitter specifications are satisfied.
Note 6
When the device is operated with input clock jitter, this parameter needs to be derated by the actual Terr(mper), act of
the input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.)
Note 7
When the device is operated with input clock jitter, this parameter needs to be derated by the actual Tjit(per),act of the
input clock. (Output deratings are relative to the SDRAM input clock.)
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 149 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Timing Parameter Notes
1. Actual value dependent upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rouned-up to next higher integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFi.
7. For definition of RTT-on time tAON See “Timing Parameters”.
8. For definition of RTT-off time tAOF See “Timing Parameters”.
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.
10. WR in clock cycles are programmed in MR0.
11. The maximum read postamble is bounded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this
parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter.
15. tREFi depends on TOPER.
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate. Note for
DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET, Vref(DC)=VrefCA(DC).
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for
DQ and DM signals, VREF(DC)=VrefDQ(DC). For input only pins except RESET, Vref(DC)=VrefCA(DC).
18. Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
19. The maximum preamble is bound by tLZ (DQS) max on the left side and tDQSCK(max) on the right side.
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in
progress, but power-down IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases
where additional time such as tXPDLL(min) is also required.
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 150 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64
Nck for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and Temperature Sensitivity”
and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between ZQCS commands can be determined
from these tables and other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate)
drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection / [(Tsens x Tdriftrate) + (Vsens x Vdriftrate)] where Tsens = max(dRTTdT, dRONdTM) and Vsens =
max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if Tsens = 1.5%/C, Vsens = 0.15%/Mv, Tdriftrate = 1 C/sec and Vdriftrate = 15Mv/sec, then the interval between
ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to
accommodate for the lower altemate threshold of 150Mv and another 25ps to account for the earlier reference point [(175Mv –
150Mv) / 1V/ns].
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 151 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Address / Command Setup, Hold, and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)
and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal
from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal
from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain
above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid
input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach VIH/IL(ac).
ADD/CMD Setup and Hold Base-Values for 1V/ns
Grade
Symbol
Reference
800
1066
1333
1600
1866
2133
Unit
Notes
DDR3
tIS(base) AC175
VIH/L(ac)
200
125
65
45
-
-
ps
1
tIS(base) AC150
VIH/L(ac)
350
275
190
170
-
-
ps
1
tIS(base) AC135
VIH/L(ac)
-
-
-
-
65
60
ps
1
tIS(base) AC125
VIH/L(ac)
-
-
-
-
150
135
ps
1
tIH(base) DC100
VIH/L(dc)
275
200
140
120
100
95
ps
1
DDR3L
tIS(base) AC160
VIH/L(ac)
215
140
80
60
-
-
ps
1
tIS(base) AC135
VIH/L(ac)
365
290
205
185
65
-
ps
1,2
tIS(base) AC125
VIH/L(ac)
-
-
-
-
150
-
ps
1,3
tIH(base) DC90
VIH/L(ac)
285
210
150
130
110
-
ps
1
NOTE 1 (AC/DC referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK- slew rate)
NOTE 2 The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for
DDR3L-800/1066 or 100 ps for DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to
account for the earlier reference point [(160 mV - 135 mV) / 1 V/ns].
NOTE 3 The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866
of derating to accommodate for the lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point [(135 mV -
125 mV) / 1 V/ns].
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 152 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based AC160 Threshold
DDR3L AC160 Threshold -> VIH(ACAC)=VREF(DC)+160 mV, VIL(AC)=VREF(DC)-160 mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
80
45
80
45
80
45
88
53
96
61
104
69
112
79
120
95
1.5
53
30
53
30
53
30
61
38
69
46
77
54
85
64
93
80
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-1
-3
-1
-3
-1
-3
7
5
15
13
23
21
31
31
39
47
0.8
-3
-8
-3
-8
-3
-8
5
1
13
9
21
17
29
27
37
43
0.7
-5
-13
-5
-13
-5
-13
3
-5
11
3
19
11
27
21
35
37
0.6
-8
-20
-8
-20
-8
-20
0
-12
8
-4
16
4
24
14
32
30
0.5
-20
-30
-20
-30
-20
-30
-12
-22
-4
-14
4
-6
12
4
20
20
0.4
-40
-45
-40
-45
-40
-45
-32
-37
-24
-29
-16
-21
-8
-11
0
5
Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based AC135 Threshold
DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135 mV, VIL(AC)=VREF(DC)-135 mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
68
45
68
45
68
45
76
53
84
61
92
69
100
79
108
95
1.5
45
30
45
30
45
30
53
38
61
46
69
54
77
64
85
80
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
-3
2
-3
2
-3
10
5
18
13
26
21
34
31
42
47
0.8
3
-8
3
-8
3
-8
11
1
19
9
27
17
35
27
43
43
0.7
6
-13
6
-13
6
-13
14
-5
22
3
30
11
38
21
46
37
0.6
9
-20
9
-20
9
-20
17
-12
25
-4
33
4
41
14
49
30
0.5
5
-30
5
-30
5
-30
13
-22
21
-14
29
-6
37
4
45
20
0.4
-3
-45
-3
-45
-3
-45
6
-37
14
-29
22
-21
30
-11
38
5
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 153 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3L-1866 tIS/tIH - AC/DC based AC125 Threshold
DDR3L Alternate AC125 Threshold -> VIH(AC)=VREF(DC)+125 mV, VIL(AC)=VREF(DC)-125 mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
63
45
63
45
63
45
71
53
79
61
87
69
95
79
103
95
1.5
42
30
42
30
42
30
50
38
58
46
66
54
74
64
82
80
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
3
-3
3
-3
3
-3
11
5
19
13
27
21
35
31
43
47
0.8
6
-8
6
-8
6
-8
14
1
22
9
30
17
38
27
46
43
0.7
10
-13
10
-13
10
-13
18
-5
26
3
34
11
42
21
50
37
0.6
16
-20
16
-20
16
-20
24
-12
32
4
40
-4
48
14
56
30
0.5
15
-30
15
-30
15
-30
23
-22
31
-14
39
-6
47
4
55
20
0.4
13
-45
13
-45
13
-45
21
-37
29
-29
37
-21
45
-11
53
5
Derating values DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC175 Threshold
DDR3 AC175 Threshold -> VIH(ac)=VREF(dc)+175mV, VIL(ac)=VREF(dc)-175mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
88
50
88
50
88
50
96
58
104
66
112
74
120
84
128
100
1.5
59
34
59
34
59
34
67
42
75
50
83
58
91
68
99
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-2
-4
-2
-4
-2
-4
6
4
14
12
22
20
30
30
38
46
0.8
-6
-10
-6
-10
-6
-10
2
-2
10
6
18
14
26
24
34
40
0.7
-11
-16
-11
-16
-11
-16
-3
-8
5
0
13
8
21
18
29
34
0.6
-17
-26
-17
-26
-17
-26
-9
-18
-1
-10
7
-2
15
8
23
24
0.5
-35
-40
-35
-40
-35
-40
-27
-32
-19
-24
-11
-16
-2
-6
5
10
0.4
-62
-60
-62
-60
-62
-60
-54
-52
-46
-44
-38
-36
-30
-26
-22
-10
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 154 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC150 Threshold
DDR3 Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
0
-4
0
-4
0
-4
8
4
16
12
24
20
32
30
40
46
0.8
0
-10
0
-10
0
-10
8
-2
16
6
24
14
32
24
40
40
0.7
0
-16
0
-16
0
-16
8
-8
16
0
24
8
32
18
40
34
0.6
-1
-26
-1
-26
-1
-26
7
-18
15
-10
23
-2
31
8
39
24
0.5
-10
-40
-10
-40
-10
-40
-2
-32
6
-24
14
-16
22
-6
30
10
0.4
-25
-60
-25
-60
-25
-60
-17
-52
-9
-44
-1
-36
7
-26
15
-10
Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC135 Threshold
DDR3 Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
68
50
68
50
68
50
76
58
84
66
92
74
100
84
108
100
1.5
45
34
45
34
45
34
53
42
61
50
69
58
77
68
85
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
-4
2
-4
2
-4
10
4
18
12
26
20
34
30
42
46
0.8
3
-10
3
-10
3
-10
11
-2
19
6
27
14
35
24
43
40
0.7
6
-16
6
-16
6
-16
14
-8
22
0
30
8
38
18
46
34
0.6
9
-26
9
-26
9
-26
17
-18
25
-10
33
-2
41
8
49
24
0.5
5
-40
5
-40
5
-40
13
-32
21
-24
29
-16
37
-6
45
10
0.4
-3
-60
-3
-60
-3
-60
6
-52
14
-44
22
-36
30
-26
38
-10
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 155 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC125 Threshold
DDR3 Alternate AC125 Threshold -> VIH(ac)=VREF(dc)+125mV, VIL(ac)=VREF(dc)-125mV
CK,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/ADD
Slew rate
V/ns
2
63
50
63
50
63
50
71
58
79
66
87
74
95
84
103
100
1.5
42
34
42
34
42
34
50
42
58
50
66
58
74
68
82
84
1
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
4
-4
4
-4
4
-4
12
4
20
12
28
20
36
30
44
46
0.8
6
-10
6
-10
6
-10
14
-2
22
6
30
14
38
24
46
40
0.7
11
-16
11
-16
11
-16
19
-8
27
0
35
8
43
18
51
34
0.6
16
-26
16
-26
16
-26
24
-18
32
-10
40
-2
48
8
56
24
0.5
15
-40
15
-40
15
-40
23
-32
31
-24
39
-16
47
-6
55
10
0.4
13
-60
13
-60
13
-60
21
-52
29
-44
37
-36
45
-26
53
-10
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 156 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Required time tVAC above VIH(AC) {below VIL(AC)} for ADD/CMD transition
Slew
Rate
[V/ns]
DDR3
DDR3L
Unit
800/1066/1333/1600
1866/2133
800/1066/1333/1600
1866
175mV [ps]
150mV[ps]
135mV [ps]
125mV [ps]
160 mV [ps]
135 mV [ps]
135 mV [ps]
125 mV [ps]
> 2.0
75
175
168
173
200
213
200
205
ps
2.0
57
170
168
173
200
213
200
205
ps
1.5
50
167
145
152
173
190
178
184
ps
1.0
38
130
100
110
120
145
133
143
ps
0.9
34
113
85
96
102
130
118
129
ps
0.8
29
93
66
79
80
111
99
111
ps
0.7
22
66
42
56
51
87
75
89
ps
0.6
note
30
10
27
13
55
43
59
ps
0.5
note
note
note
note
Note
10
Note
18
ps
<0.5
note
note
note
note
Note
10
Note
18
ps
NOTE Rising input signal shall become equal to or greater than VIH(ac) level and falling input signal shall become equal to or less
than VIL(ac) level.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 157 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base)
and tDH(base) value to the delta tDS and delta tDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + delta tDS
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the
first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal
from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line
between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal
from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)
at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation. These values are typically not subject to production test. They are verified by design and characterization.
Derating values DDR3L-800/1066 tDS/tDH - AC/DC based AC160 Threshold
DDR3L AC160 Threshold -> VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV
DQS,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew rate
V/ns
2
80
45
80
45
80
45
-
-
-
-
-
-
-
-
-
-
1.5
53
30
53
30
53
30
61
38
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
-1
-3
-1
-3
7
5
15
13
23
21
-
-
-
-
0.8
-
-
-
-
-3
-8
5
1
13
9
21
17
29
27
-
-
0.7
-
-
-
-
-
-
3
-5
11
3
19
11
27
21
35
37
0.6
-
-
-
-
-
-
-
-
8
-4
16
4
24
14
32
30
0.5
-
-
-
-
-
-
-
-
-
-
4
-6
12
4
20
20
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-8
-11
0
5
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 158 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3L- 800/1066/1333/1600 tDS/tDH - AC/DC based AC135/ Threshold
DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
DQS,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew rate
V/ns
2
45
68
45
68
45
-
-
-
-
-
-
-
-
-
-
1.5
45
30
45
30
45
30
53
38
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
2
-3
2
-3
10
5
18
13
26
21
-
-
-
-
0.8
-
-
-
-
3
-8
11
1
19
9
27
17
35
27
-
-
0.7
-
-
-
-
-
-
14
-5
22
3
30
11
38
21
46
37
0.6
-
-
-
-
-
-
-
-
25
-4
33
4
41
14
49
30
0.5
-
-
-
-
-
-
-
-
-
-
29
-6
37
4
45
20
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30
-11
38
5
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
Derating values DDR3L- 1866 tDS/tDH - AC/DC based AC130 Threshold
DDR3L Alternate AC130 Threshold -> VIH(AC)=VREF(DC)+130mV, VIL(AC)=VREF(DC)-130mV
DQS,  Differential Slew Rate
8.0 V/ns
7.0 V/ns
6.0 V/ns
5.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew
rate
V/ns
4
33
23
33
23
33
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.5
28
19
28
19
28
19
28
19
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
22
15
22
15
22
15
22
15
22
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
-
-
13
9
13
9
13
9
13
9
13
9
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-22
-15
-22
-15
-22
-15
-22
-15
-14
-7
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
-65
-45
-65
-45
-65
-45
-57
-37
-49
-29
-
-
-
-
-
-
0.9
-
-
-
-
-
-
-
-
-
-
-62
-48
-62
-48
-54
-40
-46
-32
-38
-24
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-61
-53
-53
-45
-45
-37
-37
-29
-29
-19
-
-
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-49
-50
-41
-42
-33
-34
-25
-24
-17
-8
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-37
-49
-29
-41
-21
-31
-13
-15
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-31
-51
-23
-41
-15
-25
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-28
-56
-20
-40
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 159 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3- 800/1066 tDS/tDH - AC/DC based AC175 Threshold
DDR3 AC175 Threshold
DQS,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew rate
V/ns
2
50
88
50
88
50
-
-
-
-
-
-
-
-
-
-
1.5
59
34
59
34
59
34
67
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
-2
-4
-2
-4
6
4
14
12
22
20
-
-
-
-
0.8
-
-
-
-
-6
-10
2
-2
10
6
18
14
26
24
-
-
0.7
-
-
-
-
-
-
-3
-8
5
0
13
8
21
18
29
34
0.6
-
-
-
-
-
-
-
-
-1
-10
7
-2
15
8
23
24
0.5
-
-
-
-
-
-
-
-
-
-
-11
-16
-2
-6
5
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-30
-26
-22
-10
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC150 Threshold
DDR3 AC150 Threshold
DQS,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew rate
V/ns
2
50
75
50
75
50
-
-
-
-
-
-
-
-
-
-
1.5
50
34
50
34
50
34
58
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
0
-4
0
-4
8
4
16
12
24
20
-
-
-
-
0.8
-
-
-
-
0
-10
8
-2
16
6
24
14
32
24
-
-
0.7
-
-
-
-
-
-
8
-8
16
0
24
8
32
18
40
34
0.6
-
-
-
-
-
-
-
-
15
-10
23
-2
31
8
39
24
0.5
-
-
-
-
-
-
-
-
-
-
14
-16
22
-6
30
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
7
-26
15
-10
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 160 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Derating values DDR3- 1866/2133 tDS/tDH - AC/DC based AC135 Threshold
DDR3
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,  Differential Slew Rate
8.0 V/ns
7.0 V/ns
6.0 V/ns
5.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew
rate
V/ns
4
34
25
34
25
34
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.5
29
21
29
21
29
21
29
21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
23
17
23
17
23
17
23
17
23
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
-
-
14
10
14
10
14
10
14
10
14
10
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-23
-17
-23
-17
-23
-17
-23
-17
-15
-9
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
-68
-50
-68
-50
-68
-50
-60
-42
-52
-34
-
-
-
-
-
-
0.9
-
-
-
-
-
-
-
-
-
-
-66
-54
-66
-54
-58
-46
-50
-38
-42
-30
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-64
-60
-56
-52
-48
-44
-40
-36
-32
-26
-
-
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-53
-59
-45
-51
-37
-43
-29
-33
-21
-17
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-43
-61
-35
-53
-27
-43
-19
-27
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-39
-66
-31
-56
-23
-40
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-38
-76
-30
-60
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC135 Threshold
DDR3
Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV
DQS,  Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew rate
V/ns
2
68
50
68
50
68
50
-
-
-
-
-
-
-
-
-
-
1.5
45
34
45
34
45
34
53
42
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
2
-4
2
-4
10
4
18
12
26
20
-
-
-
-
0.8
-
-
-
-
3
-10
11
-2
19
6
27
14
35
24
-
-
0.7
-
-
-
-
-
-
14
-8
22
0
30
8
38
18
46
34
0.6
-
-
-
-
-
-
-
-
25
-10
33
-2
41
8
49
24
0.5
-
-
-
-
-
-
-
-
-
-
29
-16
37
-6
45
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30
-26
38
-10
NOTE1: Cell contents shaded in gray are defined as ‘not supported’.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 161 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Required time tVAC above VIH(AC) {below VIL(AC)} for DQ transition
Slew
Rate
[V/ns]
DDR3
DDR3L
Unit
800/1066
800/1066/
1333/1600
800/1066/
1333/1600
1866
2133
800/1066
800/1066/
1333/1600
1866
175mV [ps]
150mV[ps]
135mV [ps]
135mV [ps]
135 mV [ps]
160 mV [ps]
135 mV [ps]
130 mV [ps]
> 2.0
75
105
113
93
73
165
113
95
ps
2.0
57
105
113
93
73
165
113
95
ps
1.5
50
80
90
70
50
138
90
73
ps
1.0
38
30
45
25
5
85
45
30
ps
0.9
34
13
30
Note
Note
67
30
16
ps
0.8
29
Note
11
Note
Note
45
11
Note
ps
0.7
Note
Note
Note
-
-
16
Note
-
ps
0.6
Note
Note
Note
-
-
Note
Note
-
ps
0.5
Note
Note
Note
-
-
Note
Note
-
ps
<0.5
Note
Note
Note
-
-
Note
Note
-
ps
NOTE Rising input signal shall become equal to or greater than VIH(ac) level and falling input signal shall become equal to or less than
VIL(ac) level.
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 162 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
Revision History
Version
Page
Modified
Description
Released
1.0
-
-
Preliminary Revision
03/2012
1.0
-
-
Official Revision
07/2012
1.0
-
-
Add IT grade parts (Industry Temperature) IDDs.
10/2012
1.0
-
-
Re-move speed 1066 and 1333 Spec
12/2012
1.0
-
-
Voltage SPEC modified
01/2013
1.0
-
-
Modified MR2 Function
02/2013
1.0
-
-
Add RS (Reduced Standaby) Part Numbers
02/2013
1.0
-
-
Modified Part Numbers
03/2013
1.0
-
-
Add tRFC SPEC and Automobile Part Numbers
05/2013
1.1
P1
-
Renew the first page
06/2013
All
-
1. Remove ‘on page xxx’
2. Follow NTC’s data center to change the Revision Rule
P3
Ordering Information
Add Part Number ‘NT5CB256M16CP-DIH’.
P4
Part Number Naming
Rule
Special Type Option
1. Add H = Automotive Grade 2
2. Modify A = Automotive 3 (was: A = Automotive)
P5-11
Fundamental AC
Specifications
1. Make all options follow JEDEC standards.
2. Add 800, 1066 and 1333 specifications.
P13-14
Package Outline
Drawing
1. Add side view of package to POD
2. Redraw the ballout
P24,27,30,32
MR0,1,2,3
Redraw the MR functions
P89
Absolute Maximum DC
Ratings
1. Follow JEDEC specifications
VDD: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)
VDDQ: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)
Vin,Vout: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)
P90
Temperature Spec
1. Automatic Grade 3: -40 to 85 (was: -40 to 95)
P92-123
All
1. Make all specifications follow JEDEC specifications
2. Add DDR3(L) 800, 1066 and 1333 specifications
P124-136
IDD specifications
1. Add IDD test conditions
P137-143
Timing specifications
1. Make all specifications follow JEDEC specifications
2. Add DDR3(L) 800, 1066 and 1333 specifications
P146-156
Derating table
1. Make all specifications follow JEDEC specifications
2. Add DDR3(L) 800, 1066 and 1333 specifications
1.2
P14
96 ballout
1. Update POD spec to 12mm (was: 11.2mm caused by typo)
06/2013
P24,27,30,32
MR
1. Add notes below the MR tables
P1,P90
Temperature spec
1. Automotive Grade 3: -40 ~ 95 (was: -40~85)
2. Add Automotive Grade 2 Spec on page 90.
P147-150,
152-155
tIS/tIH/tDS/tDH Derating
table
1. Add DC conditions
P152
Data Setup,Hold
1. Correct the typo in 1st paragraph: tDS(base) and tDH(base), was: tDH(base) and
tDH(base)
1.3
P1
-
1. Renew.
08/2013
P2.133-138
Fundamental AC Spec.
1. Divide the table. Put Core Timing on page 2 and Operating Frequency on
P130-135
P4
Ordering Info
1. Package: TFBGA (was: WBGA)
P6-7
Package Outline
Drawing
1. Ball descriptions (was: Pin descriptions)
2. Add seating plane, wiring bonding molding height and top view
P8-9
Ball descriptions
1. Ball descriptions (was: Pin descriptions)
2. Add Note 2 to the table.
All
-
1. Format adjustment
P44
Extended Temperature
Usage
1. in supporting temperature range(was: and does not exceed +95°C)
2. removed: Table 14 summarizes the two extended temperature options and Table
15 summarizes how the two extended temperature options relate to one another.
P62
Self Refresh Operation
1. ZQCALfunction requirements [TBD]
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 163 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
P117
tAON
1. Add tAON diagram.
1.4
P1
-
1. Write Leveling :Add Note 7
2. Density and Addressing: Add tREFI
09/2013
P9
DQ Description
Add: DQ0 is the prime DQ in a low byte lane of x4/x8/x16 configuration and DQ8 is
the prime DQ in a high byte lane of x16 configuration for write leveling.
P41-P43
Write Leveling
Emphasize Write Leveling only supports prime DQ’s feedback.
1. A separated feedback mechanism should be able for each byte lane. The low byte
lane’s prime DQ, DQ0, carries the leveling feedback to the controller across the
DRAM configurations x4/x8 whereas DQ0 indicates the lower diff_DQS
(diff_LDQS) to clock relationship..The high byte lane’s prime DQ, DQ8, provides
the feedback of the upper diff_DQS (diff_UDQS) to clock relationship.
2. Timing details of Write leveling sequence: Add (For Information. Only Support prime
DQ)
P124
IDD specifications
Add 2133 IDD specs.
All
-
Format adjusted and realigned.
1.5
P2,4,123,124,137
DDR3L-1866
1. Add DDR3L-1866 part number and specifications.
2. Update IDD specification.
12/2013
1.6
P1,4
Voltage backward
compatible
1. Temperature Range: Add part number’s code
2. NOTE 4: Enhance the statement of voltage backward compatible.
04/2014
P19
CAS Latency
Correct the description: bit A2, A4~A6 (was: bit A9~A11)
P45, P123, 124
Self refresh
Emphasize the difference among the grades about Self refresh temperature range
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Version 1.6 164 Nanya Technology Cooperation ©
04/2014 All Rights Reserved.
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