ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844001 is a Fibre Channel Clock Generator ICS and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS844001 uses an 18pF parallel resonant crystal over the range of 20.4MHz - 28.3MHz. For Fibre Channel applications, a 26.5625MHz crystal is used. The frequency select pin allows the device to generate either 106.25MHz or 212.5MHz from a 26.5625MHz crystal. To generate 187.5MHz for 12Gb Ether net, a 23.4375MHz cr ystal is used. The ICS844001 uses IDT's 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Fibre Channel and Ethernet jitter requirements. The ICS844001 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * One Differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (20.4MHz - 28.3MHz) * Output frequency range: 81.66MHz - 226.66MHz * VCO range: 490MHz - 680MHz * RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.74ps (typical) * 3.3V or 2.5V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages COMMON CONFIGURATION TABLE - FIBRE CHANNEL, 12Gb ETHERNET Inputs Output Frequency (MHz) 26.5625 1 24 6 Multiplication Value M/N 4 26.5625 0 24 3 8 212.5 23.4375 0 24 3 8 187.5 Crystal Frequency (MHz) FREQ_SEL M N 106.25 BLOCK DIAGRAM PIN ASSIGNMENT FREQ_SEL Pullup /3 XTAL_IN OSC XTAL_OUT Phase Detector 0 Q nQ VCO 490MHz - 680MHz /6 1 1 2 3 4 8 7 6 5 VDD Q nQ FREQ_SEL ICS844001 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = /24 (fixed) IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR VDDA GND XTAL_OUT XTAL_IN 1 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Analog supply pin. 2 Power 5 GND XTAL_OUT, XTAL_IN FREQ_SEL Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. 6, 7 nQ, Q Output Differential clock outputs. LVDS interface levels. 8 VDD Power Core supply pin. 3, 4 Type Description Input Input Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR Test Conditions Minimum 2 Typical Maximum Units ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the -0.5V to VDD + 0.5 V device. These ratings are stress specifications only. Functional op- Outputs, IO (LVDS) Continuous Current Surge Current eration of product at these conditions or any conditions beyond 10mA 15mA those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG tended periods may affect product reliability. -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter V DD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD - 0.12 3.3 VDDA Analog Supply Voltage VDD V IDD Power Supply Current 115 mA IDDA Analog Supply Current 12 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VDD - 0.12 2.5 VDDA Analog Supply Voltage VDD V IDD Power Supply Current 110 mA IDDA Analog Supply Current 12 mA Maximum Units V TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical VDD = 3.3V 2 VDD + 0.3 VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 A VIL Input Low Voltage IIH Input High Current FREQ_SEL VDD = VIN = 3.465V or 2.625V IIL Input Low Current FREQ_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 A TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 350 415 480 mV 50 mV 1.225 1.325 1.425 V 50 mV NOTE: Please refer to Parameter Measurement Information for output information. IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 3 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 300 390 480 mV 50 mV 1.325 V 50 mV Maximum Units 28.3 MHz 1.0 1.2 NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 20.4 Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 226.66 MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency tjit(O) tR / tF RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 187.5MHz @ Integration Range: 637kHz - 10MHz 212.5MHz @ Integration Range: 637kHz - 10MHz 20% to 80% FREQ_SEL = 1 o dc Output Duty Cycle FREQ_SEL = 0 NOTE 1: Please refer to the Phase Noise Plots following this section. 0.74 ps 0.48 ps 0.70 ps 175 500 ps 48 45 52 55 % % Maximum Units 226.66 MHz TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency tjit(O) tR / tF RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 187.5MHz @ Integration Range: 637kHz - 10MHz 212.5MHz @ Integration Range: 637kHz - 10MHz 20% to 80% FREQ_SEL = 1 o dc Output Duty Cycle FREQ_SEL = 0 NOTE 1: Please refer to the Phase Noise Plots following this section. IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 4 0.97 ps 0.58 ps 0.95 ps 175 500 ps 48 45 52 55 % % ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR TYPICAL PHASE NOISE AT 106.25MHZ @3.3V 0 -10 Fibre Channel Filter 106.25MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.74ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 NOISE POWER dBc Hz -20 -30 -40 -50 -120 -130 -140 -150 -160 -170 Phase Noise Result by adding Fibre Channel Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 212.5MHZ @3.3V 0 -10 Fibre Channel Filter 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.70ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 NOISE POWER dBc Hz -20 -30 -40 -50 -110 -120 -130 -140 -150 -160 -170 Phase Noise Result by adding Fibre Channel Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 5 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION SCOPE VDD 3.3V5% POWER SUPPLY + Float GND - SCOPE VDD Qx 2.5V5% POWER SUPPLY + Float GND - VDDA LVDS Qx VDDA LVDS nQx nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQ Q t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VVDD DD out 80% DC Input VSW I N G Clock Outputs LVDS 80% 20% 20% tR out tF VOS/ VOS OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD V DD LVDS 100 VOD/ VOD out DC Input out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 6 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844001 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V or 2.5V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS844001 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p Figure 2. CRYSTAL INPUt INTERFACE IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 7 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 8 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844001. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844001 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (115mA + 12mA) = 440mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.440W *90.5C/W = 109.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 9 0 1 2.5 101.7C/W 90.5C/W 89.8C/W ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W NOTE: An airflow of 1 meter per second is strongly recommended. TRANSISTOR COUNT The transistor count for ICS844001 is: 2533 IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 10 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 11 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844001AG 4001A 8 lead TSSOP tube 0C to 70C ICS844001AGT 4001A 8 lead TSSOP 2500 tape & reel 0C to 70C ICS844001AGLF 001AL 8 lead "Lead-Free" TSSOP tube 0C to 70C ICS844001AGLFT 001AL 8 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM FEMTOCLOCKSTM CLOCK GENERATOR 12 ICS844001 REV A AUGUST 31, 2006 ICS844001 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA