ATICE50MEM - Atmel - Datasheet.Live

ICE50

..............................................................................................

User Guide

ICE50 User Guide i

2523A–AVR–11/02

Table of Contents

Section 1

Preface .................................................................................................1-1

1.1 About this Manual .....................................................................................1-1

1.1.1 Warnings ............................................................................................1-1

1.1.2 Tips.....................................................................................................1-1

1.1.3 Workaround........................................................................................1-1

1.1.4 Checklists ...........................................................................................1-1

1.1.5 Related Documentation......................................................................1-2

1.2 ICE50 Firmware History............................................................................1-2

1.2.1 Version 1.0 ............... ..... ................... ..... .... ..... ....................................1-2

1.2.2 Version 1.1 ............... ..... ................... ..... .... ..... ....................................1-2

1.2.3 Version 1.2 ............... ..... ................... ..... .... ..... ....................................1-2

1.3 ICE50 Known Issues.................................................................................1-2

1.3.1 User Break in Sleep Mode..................................................................1-2

1.3.2 ADC Latch-up.....................................................................................1-2

1.3.3 User Break..........................................................................................1-2

1.4 Reporting Problems ..................................................................................1-3

Section 2

Introduction...........................................................................................2-1

2.1 ICE50 Contents.........................................................................................2-1

2.2 ICE50 Features.........................................................................................2-2

2.3 System Requirements........................ ..... ..... ...................................... ..... ..2-3

2.3.1 Hardware Requiremen ts........................ .... ..... ..... ...............................2-3

2.3.2 Software Requirements......................................................................2-3

2.3.3 Target Hardware Requirements .........................................................2-3

2.3.4 Operating Conditions..........................................................................2-3

2.3.5 Host Interface.....................................................................................2-3

Section 3

General Description..............................................................................3-1

3.1 General Hardware Description..................................................................3-1

3.1.1 What is an In-Circuit Emulator?........ ..... .... ..... ....................................3-1

3.2 Main Emulator Unit....................................................................................3-2

3.2.1 Emulator Unit......................................................................................3-2

3.2.2 Status LEDs........................................................................................3-2

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ii ICE50 User Guide

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3.3 POD Bay...................................................................................................3-4

3.3.1 Removing POD from POD Bay ..........................................................3-4

3.3.2 Inserting POD Into POD Bay..............................................................3-4

3.3.3 Expansion Bay....................................................................................3-5

3.3.4 USB Connector...................................................................................3-5

3.3.5 RS-232C Connector...........................................................................3-5

3.3.6 Reset Button........ ..... ......................................................... ..... ..... ..... ..3 - 5

3.3.7 Power Switch......................................................................................3-5

3.3.8 Power Connector................................................................................3-6

3.4 Personality Adapter Description................................................................3-6

3.4.1 Personality Adapter Description.........................................................3-6

3.4.2 t26 Personality Adapter......................................................................3-7

3.4.3 t28 and t29 Personality Adapter.........................................................3-8

3.4.4 m8 Personality Adapter......................................................................3-8

3.4.5 m32 Personality Adap ter ..................................... ..... .... ..... .................3- 9

3.4.6 m162 Personality Adapter..................................................................3-9

3.4.7 m128 Personality Adapter................................................................3-10

3.4.8 m169 Personality Adapter................................................................3-10

3.5 POD Description .....................................................................................3-11

3.5.1 POD Description...............................................................................3-11

3.5.2 Digital I/O..........................................................................................3-12

3.5.3 Analog Comparator ..........................................................................3-14

3.5.4 A/D Converter...................................................................................3-14

3.6 Power System Description......................................................................3-15

3.6.1 Power Supply ...................................................................................3-15

3.6.2 ICE50 Power System .......................................................................3-15

3.6.3 Target Application Power Requirements..........................................3-16

3.7 Probe Description ...................................................................................3-17

3.7.1 Probe Description.............................................................................3-17

3.7.2 External Clock Signal .................. ..... ..... .... ................... ..... ..... ..... .....3-18

3.7.3 Internal Clock Signal Provided by AVR Studio.................................3-18

3.7.4 External 32 kHz RTC Crystal............ ..... ................... .... ..... ..... ..........3-19

3.7.5 Internal RC Oscillator .................. ..... ..... ...........................................3-19

3.7.6 External Crystal and External Reso na tor ............ ..... .... ....................3-19

3.7.7 External RC Oscillator........ .... ..... .....................................................3-19

3.8 Test Adapter ...........................................................................................3-19

3.8.1 Using the Test Adapter.....................................................................3-20

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ICE50 User Guide iii

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Section 4

Connecting ICE50.................................................................................4-1

4.1 Connecting ICE50 for Emulation...............................................................4-1

4.2 Connecting ICE50 to host PC...................................................................4-1

4.3 Connecting the Probe to the Target Board ...............................................4-1

4.3.1 Connecting PDIP Adapters.................................................................4-1

4.3.2 Connecting TQFP Adapters ...............................................................4-3

4.4 ICE50 Power-up Sequence.......................................................................4-4

Section 5

Configuring AVR Studio........................................................................5-1

5.1 ICE50 Emulator Options ...........................................................................5-1

5.2 AVR Studio Configuration Quick Start Guide............................................5-2

5.3 Device Selection .......................................................................................5-3

5.4 Fuses and Lock Bits..................................................................................5-5

5.5 Lock Bits ...................................................................................................5-8

5.6 ICE Status......... ........................................................................................5-9

5.7 Boot Block Options ................... .... ................... ..... ..... ..... ................... .....5-11

5.8 Special ....................................................................................................5-12

5.9 Downloading New Parts for ICE50..........................................................5-12

5.10 Upgrading the ICE50 Firmware...............................................................5-13

Section 6

Special Considerations.........................................................................6-1

6.1 Electrical Compatibility..............................................................................6-1

6.1.1 Power .................................................................................................6-1

6.1.2 I/O Lines..... ..... .... ...............................................................................6-1

6.2 Sleep Mode...............................................................................................6-2

6.3 Target Hardware Requirements................................................................6-2

6.4 Clock Options............................................................................................6-2

6.5 Differences Between Emu lat or and Part.................... ..... .... ..... .................6-2

Section 7

Trace.....................................................................................................7-1

7.1 Enabling Trace in AVR Studio...................................................................7-1

7.2 The Trace Window....................................................................................7-2

7.3 Contents of Trace Window Based on Instruction (ICE50).........................7-4

7.4 Accessing External Data Memory (ICE50 Trace) ...................................7-14

7.5 Interrupt Handlin g (ICE5 0 Trace)..................... ................... ..... ..... ..... .....7- 14

7.6 Reset (ICE50 Trace)...............................................................................7-15

7.7 Save Trace Buffer to File (ICE50)...........................................................7-15

7.8 Sleep (ICE50 Trace) ...............................................................................7-15

Table of Contents

iv ICE50 User Guide

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Section 8

Troubleshooting....................................................................................8-1

8.1 Troubleshooting Guide..............................................................................8-1

ICE50 User Guide 1-1

Rev. 2523A–AVR–11/0 2

Section 1

Preface

1.1 About this

Manual This manual is using th e nomenclat ure descri bed in thi s section to show warning s, tips,

workarounds etc.

1.1.1 Warnings This manual contains important warnings to prevent damage to your system and the

ICE50. All the warnings are emphasized as shown in the example below.

 WARNING!

This is a warning...

Please read all warnings carefully.

1.1.2 Tips Some sections contain useful tips for using the ICE50. All the tips are emphasized as

shown in the example below.

Tip!

This is a tip...

1.1.3 Workaround Workaround!

This is a workaround...

1.1.4 Checklists Once comfortable with the configurtion and use of the ICE50, the checklists at the end of

these sections can be used for fast setup of a new project.

The checklists are of great help for getting the debugging system on-line without prob-

lems. However, novice users sho uld also check that the operating condi tions of the

target system are c ompli ant to the require ments of ICE50 . This is described in the Co n-

necting ICE50 section.

Preface

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1.1.5 Related

Documentation The following electronic documents from Atmel® are related to th e use of the AVR®

microcontrollers, and of the debugging tools. All documents can be found on the Atmel

Products CD-ROM enclosed in the ICE50 kit. For more information and document

updates, please visit our web site: www.atmel.com.

AVR Studio® user's guide.

Descr ibes in detail how to use the AVR Studio debugging environment.

Describes in detail how to use the AVR Assembler.

Data sheets for the different AVR devices.

Errata sheets for the different AVR devices.

Applicatio n note s des cribing different applicati on examples for the AVR

microcontrollers.

Descr ibes in detail how to use the AVR Studio debugging environment.

Note: AVR Studio 4.0 or later is required for ICE50 support. AVR Studio 3.x versions

will not work with ICE50!

1.2 ICE50 Firmware

History There has been several releases of the ICE50 firmware.

1.2.1 Versio n 1.0 First released version.

1.2.2 Versio n 1.1 Errors in trace module fixed.

Version table readout in main module fixed.

1.2.3 Versio n 1.2 All parts with ADC: ADC bit 3 and 4 where interchanged. This is now fixed on all parts

with ADC.

Trace of Program Counter is now correct in single step.

Brown-out Detection (BOD): Selection of Brown-out Voltage is now enabled f or all

parts.

Mega8: Reset Disable Fuse added to ICE50 options.

1.3 ICE50 Known

Issues There are some kn own issue s in the ICE50 tha t use rs need s to be aware of.

1.3.1 User Break in Sleep

Mode

User break in sleep mode is not supported. Use an interrupt to wake up the part or a

reset to Reset the emulator.

User break in sleep mode is not supported. Workaround: A Reset will break and

reset the emulator .

1.3.2 ADC Latch-up The ADC may latch-up if the target is powered before the ICE. Also make sure that

no residual voltage is present on the ADC input pins if the ICE is not powered.

1.3.3 User Break User break in sleep mode is not supported. Use an interrupt to wake up the part or a

reset to reset the emulator.

Preface

ICE50 User Guide 1-3

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1.4 Reporting

Problems Problems with AVR Studio can be reported to avr@atmel.com. Problems with beta

releases can be reported to avrbeta@atmel.com.

Preface

1-4 ICE50 User Guide

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ICE50 User Guide 2-1

Rev. 2523A–AVR–11/0 2

Section 2

Introduction

ATICE50 is an advanced In-Circuit Emulator that covers a wide range of the eight b its

AVR microcontrollers from Atmel. This section gives a brief introduction to it’s features.

2.1 ICE50 Contents Figure 2-1.

The ATICE50 contains the following items:

ICE50 Main Unit/Pod/Two FPC (Flexible Printed Circuit) Cables & Probe

Personality Adapters for:

– ATmega8

– ATmega16

– ATmega162

– ATmega32

– ATmega128

–ATtiny26

Introduction

2-2 ICE50 User Guide

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9-pin RS-232C Cable

USB Cable

Power Supply

European Power Supply Cable

US Power Supply Cable

AVR Technical Library CD-ROM

– AVR Data Sheets

– Application Notes

– AVR Studio 4.00 or Later

ICE50 Quick Start Guide

2.2 ICE50 Features The ICE50 In-circuit Emulator is a High-end Emulator from Atmel designed to emulate a

wide range of AVR devices. The ICE50 is controlled by AVR Studio 4.0 or later. Present,

the following devices are supported:

–ATtiny26

– ATmega8

– ATmega16

– ATmega162

– ATmega32

– ATmega128

– ATmega169

– ATmega8515

– ATmega8535

The ICE50 supports the following features:

Emulates All Digital and Analog Peripherals

Target Voltage Range 2.2V - 5.5V

Full Target Frequency Range for All Supported Devices

Watches

Trace Buffer

Unlimited Number of Break Points

Symbolic De bugging Suppo rt

Full Visibility of and Access to Register File, SP, PC , and Memories

Access to all I/O Registers

I/O Configurable to Run or Halt in Stopped Mode

Cycle Counter

Introduction

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2.3 System

Requirements The following minimum requirements apply for the ICE50.

2.3.1 Hardware

Requirements For using the ICE5 0 with AVR Studio, a Pentium 233 MHz (or more) class personal

computer with following specifications is recommended:

64 MByte RAM, or more

20 MByte of f ree hard disk (HD) space

CD-ROM or Internet access

Recommended Screen Resolution 1024x768

16650 Compatible Serial Port (COM port)

AVR Studio v4.0 or later ins tal le d

Acrobat Reader v4.0 or later installed (optional).

2.3.2 Software

Requirements The following operating systems are currently supported by AVR Studio:

Windows NT® Version 3.51(1)

Windows NT Version 4.0(1)

Windows® 95

Windows 98 (ME)

Windo ws 2000

Windows XP

AVR Studio is always updated to fit new operating systems and versions. See AVR

Studio User's Guide for latest information.

Note: 1. Windows NT 3.51 an d Windows NT 4.0 does not support USB communic at ion.

2.3.3 Target Hardware

Requirements

The target must be able to supply 2.2 - 5.5V @150mA. See Table 3-6 for further

information.

2.3.4 Operating

Conditions

Operation Temperature: 0°C - 70°C

Operating Humidity: 10 - 90 % RH (non-condensing)

Supply Voltage: +9.0V to +12.0V DC

WARNING!

Violating the recommended operating conditions for the ICE50 might cause incor-

rect operation and damage the emulator.

2.3.5 Host Interface RS-232C @ 115200 bps, 1 start-, 8 dat a-, and 1 stop-bi t, no parity with hardwa re hand-

shaking. 9-p in female connector with RTS and CTS connected to sup port hardware

handshaking.

Introduction

2-4 ICE50 User Guide

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ICE50 User Guide 3-1

Rev. 2523A–AVR–11/0 2

Section 3

General Description

This setion describes the different components of the ATICE50 in detail.

3.1 General

Hardware

Description

In this section a brief description of emulation is given, and a closer look at the parts that

make up the ICE50.

3.1.1 What is an In-Circuit

Emulator? The ICE50 is an In-Circuit Emulator. An emulator is a dedicated piece of hardware

designed to “emulat e” the behaviour of another piece of hardware. In th e case of the

ICE50, it is designed to behave as a wide range of AVR devices. Exact emulation is the

goal for all emulators and the ICE50 offers the highest possible level of compatibility.

The ICE50 emulator system consists of the following five modules:

Main Emulator Unit

POD

Probe

Personality adapters

Test adapter

General Description

3-2 ICE50 User Guide

2523A–AVR–11/02

3.2 Main Emulator

Unit The main emulator unit contains the “brain” of the ICE50.

3.2.1 Emulato r Unit The main emul ator unit is sh own in Figure 3-1 . The main unit contai ns the cont rol logic,

and general hardware necessary to emulate an AVR device.

Figure 3-1. ICE50 Main Emulator

Status LEDs

POD Bay

Expansion Bay

USB Connector

RS-232C Connector

Reset Button

Power Switch

Power Connector

3.2.2 Status LEDs There are three LEDs on the front of the ICE50 cabinet. One red, one red/green duo

LED and one green LED. All these LEDs give important status information on the ICE50

and which mode it is operating in. The picture below shows a close-up of the LEDs.

When turning on power on the ICE50 the normal LED sequence will be as follows:

1. Red Power LED turns ON.

2. Mode LED turns ON and is first red and next orange.

3. Green status LED turns ON (after approx 15 seconds).

This indicate that the unit is operating and ready for use.

Figure 3-2. Emulator LEDs

Expansion Bay

POD Bay

LEDs

Power Connector/

Power Switch

Reset

Button

RS-232C/

USB

General Description

ICE50 User Guide 3-3

2523A–AVR–11/02

3.2.2.1 Red Power LED The red LED is the power indicator LED. This will be lit if power on the ICE50 is turned

on and the power s ys tem is working correctly. If t he L ED st ays off after power on, m ake

sure the p ower supp ly meet s the requirem ents of t he ICE50. If us ing anot her powe r sup-

ply than the one supplied with the ICE50 make sure that the power polarity is correct.

See the Power System section for more details on power requirements.

3.2.2.2 Multi Color Mode

LED The Multicolor LED displays information about which mode the ICE50 is working in. Dur-

ing the startup seque nce this LED is first red, next o range. Orange indicates t hat the

Emulator is in stopped mode. A green light indicates that the ICE is in run mode. If the

LED turns red it indicate s an emulator error. If th is happens cons ult the troubles hooting

guide.

3.2.2.3 G re en Status LED The green LED will be turned on when the ICE50 is ready for emulation. Once the green

LED is on, the ICE50 is ready for emulati on. The LED will fla sh during upgradi ng of the

ICE50. The LED will be turned off during loading of a new part, and lit when the part is

finished loading. If the LED does not turn on after a power up sequence please consult

the troubleshooting guide for possible solutions.

Figure 3-3. Mul t i Co lor Mode

Table 3-1. LED Color Definitions

LED Meaning State Description

Red Power Off Power not connected, or ICE50 Turned off.

On Power connected, ICE50 on and voltages OK.

Multi Mode

Green Run mode

Red Error condition, if permanently lit.

Orange Stopped mode

Green Status

Off ICE50 is initializing.

On ICE50 Ready for emulation.

Blinking The LED will flash when doing an upgrade.

General Description

3-4 ICE50 User Guide

2523A–AVR–11/02

3.3 POD Bay The ICE50 has a very flexible architecture that will ensure a long product life. The differ-

ent AVR devices are characterised through their number of I/O pins and analog

features. Both the I/O pins and the analog features are implemented on the POD board.

If new AVR device s ar e made av ail able to the m arket that co nta in I/O o r anal og feat ures

that cannot be emulated by the current POD, Atmel is dedicated to create new POD

modules that support the functionality of the new devices.

3.3.1 Removing POD from

POD Bay If for some reason the POD must be removed from the POD Bay, the recommended

procedure is as described below. See also Figure 3-4.

1. Lift the POD on the front edge until a click is heard. The POD is now ready to be

pulled up from the bay.

2. Lift the POD out of the Bay.

Figure 3-4. Removing POD from POD Bay

Without the POD connecte d, the ICE50 will still be able to em ulate core fu nction s of the

AVR (e.g., timers). This feature can be useful in some debugging sessions. If the POD is

inserted and there is no target power appli ed, the ICE will be held in Reset until target

power is turned on. By disabling POR an d BOD Reset in ICE50 other options dial og,

ICE50 will emulate correctly even if target power is not connected.

3.3.2 Inserting POD Into

POD Bay Only original ICE50 Pods should be used with ICE50 and care should be taken when

placing or removing the POD. During norm al use there is no need to remove the POD

from the bay. If for some reason the POD is disconnected, the recommended procedure

to re-insert the POD is as follows. See also Figure 3-5.

1. Place the POD in the ICE50 POD connector. Make sure that the connector male

and female guides align.

2. Use both hands and apply press ure on the upper half of the POD (on top of the

connector).

3. After pressing the connector firmly in place, use one hand to apply pressure on

the lower half of the POD. You will hear a click when the POD locks into position.

General Description

ICE50 User Guide 3-5

2523A–AVR–11/02

Figure 3-5. Inserti ng POD Into POD Bay

3.3.3 Expansion Bay The expansion connector is in tended for f uture use, and n ot used in th e current ve rsion

of ICE50. The POD pl aced in this socket is an empty POD enclosur e and serves the

purpose of protecting the Expansion Connector.

3.3.4 USB Connector USB communicatio n is sup ported in AVR St udio 4, Bui ld 181 and higher ve rsions. USB

Drivers are found on the AVR Technical Library CD-Rom. The USB port is shown in Fig-

ure 3-6

Figure 3-6. USB-, RS-232C-communication, and Reset Button

3.3.5 RS-232C Connector Present, all communic at ion betwe en th e ICE50 and AVR Studio is done thro ugh a stan-

dard RS-232C interf ace. This is the communi cation protocol used by COM ports on

PCs. The communi cation runs at 1 15200 bit/s, no parit y, 8 data bits, 1 stop bit, (N81).

For information on how to connect the ICE50 to a PC see the Connecting ICE50 to PC

section. See Figure 3-6.

3.3.6 Reset Button By pressing the reset button on the ICE50, a Warm Reset of the Emulator is preformed.

After approximately 15 seconds the configuration is completed, and the green status

LED will turn on indicating that the emulator is ready for use. See Figure 3-6.

3.3.7 Power Switch The Power Switch is the main on/off switch for the ICE50 Emulator. Switching this off

will turn of f p ower on t he ICE5 0. Th e ICE50 wil l howe ve r re main grounded to the p ower

supply. See Figure 3-7.

General Description

3-6 ICE50 User Guide

2523A–AVR–11/02

Figure 3-7. Power Swi tch and Connector

3.3.8 Power Connector The Power Connector on the ICE50 system is a standard type with 2.1 mm center tap.

Ground should be connected to the center tap. For more information about power

requirements and operating conditions see the Power System Description. See Figure

3-7.

3.4 Personality

Adapter

Description

The personality adapters of the ICE50 provides the physical adaption between the

ICE50 and the target device.

3.4.1 Personality Adapter

Description ICE50 is supplied with a range of personality adapters. These adapters map the pinout

from the ICE50 POD to each of the microcontrollers it supports. Each adapter includes

an identification code that the ICE50 and AVR Studio use for automatic device detec-

tion. The ICE50 package contains the following Personality Adapters:

Each adapter corres pon ds t o on e pin ou t type and sup po rts on e or mo re AVR mic roco n-

trollers. Table 3-2 shows which devices are supported by the different Personality

Adapters.

Table 3-2. Personality Adapters

Device Use Personality Adapter Named Seral Number

ATmega16 m32 A9902.3.1310.A

ATmega128 m128 W10635SDF

ATmega32 m32 A9902.3.1310.B

ATtiny28/29 t28/t29 A9902.3.1350.B

ATtiny26 t26 A9902.3.1370.A

ATmega162 m162 A9902.3.1300.B

ATmega8 m8 A9902.3.1390.C

ATmega169 m169 W10634SDF

General Description

ICE50 User Guide 3-7

2523A–AVR–11/02

3.4.1.1 Connecting the

Personality Adapter

to the Probe

When connec ting the Pers onality Adap ter and the Probe , make sure that the Probe i s

connected with the correct orientation. The connectors will only fit when the boards have

the correct orientation. On the Personality Adapters a circle indicates pin 1. Make sure

that the circle on the Probe matches the circle on the Personality Adapter as shown in

Figure 3-8.

Figure 3-8. Connecting Personality Adapter to Probe

3.4.2 t26 Personality

Adapter The t26 Pers onality adapt er is a PDIP adapter fo r t26 devices. The footprint is a stan-

dard 20-lead 0.300" wide, PDIP package. If the target uses another package type, an

additional adapter has to be pu rchased from a third party vendor . When connecti ng the

Personality Adapter to the Probe, make sure to align the circles on the Probe and Per-

sonality Adapter as shown above.

Figure 3-9. t26 Personality Adapter(1)

Note: 1. SNR: A9902.3.1370.A

3.4.2.1 Supported Devices ATtiny26

General Description

3-8 ICE50 User Guide

2523A–AVR–11/02

3.4.3 t28 and t29

Personality Adapter The t28 Personality adapter is a PDIP a dapter for t28 devi ces. The footp rint is a stan-

dard 28-lead 0.300" wide, PDIP package. If the target uses another package type, an

additional adapter has to be pu rchased from a third party vendor . When connecti ng the

Personality Adapter to the Probe, make sure to align the circles on the Probe and Per-

sonality Adapter as shown above.

Figure 3-10. t28 and t29 Personality Adapter(1)

Note: 1. SNR: A9902.3.1350.B

3.4.3.1 Supported Devices ATtiny28

3.4.4 m8 Personality

Adapter The m8 Person ality adapter is a PDIP adapter for m8 devices. The f ootprint is a sta n-

dard 28-lead 0.300" wide, PDIP package. If the target uses another package type, an

additional adapter has to be pu rchased from a third party vendor . When connecti ng the

Personality Adapter to the Probe, make sure to align the circles on the Probe and Per-

sonality Adapter as shown above.

Figure 3-11. m8 Personality Adapter(1)

Note: 1. SNR: A9902.3.1390.C

3.4.4.1 Supported Devices ATmega8

General Description

ICE50 User Guide 3-9

2523A–AVR–11/02

3.4.5 m32 Personal ity

Adapter The m32 Person ality adapt er i s a PDIP ada pter fo r m32/m 16 de vice s. The footp rint is a

standard 40-lead 0.600" wide, PDIP package. If the target uses another package type,

an additional adapter has to be purchased from a third party vendor. When connecting

the Personality Adapter to the Probe, make sure to align the circles on the Probe and

Personality Adapter as shown above.

Figure 3-12. m3 2 Pers ona lity Adapter(1)

Note: 1. SNR: A9902.3.1310.B

3.4.5.1 Supported Devices ATmega32/ATmega16

3.4.6 m162 Personalit y

Adapter The m162 Personality adapter is a PDIP adapter for m162 devices. The footprint is a

standard 40-lead 0.600" wide, PDIP package. If the target uses another package type,

an additional adapter has to be purchased from a third party vendor. When connecting

the Personality Adapter to the Probe, make sure to align the circles on the Probe and

Personality Adapter as shown above.

Figure 3-13. m162 Personality Adapter(1)

Note: 1. SNR: A9902.3.1300.B

3.4.6.1 Supported Devices ATmega162

General Description

3-10 ICE50 User Guide

2523A–AVR–11/02

3.4.7 m128 Personalit y

Adapter The m128 Pers onality Adapter is a T QFP64 adapter, an d it consists of two m odules.

The bottom mod ule has the TQFP footprin t, and sh ould be soldere d on the ta rget app li-

cation. Make s ure to s older it with the corr ect ori entati on. Pin 1 is in dicated with a prin ted

“1” as shown here. Once the bottom module is soldered into the application, connect the

top module. Ma ke sure that pin 1 on the top module matches the pin 1 on the botto m

module.

Once the Personality Adapter is securely mounted, place the Probe on the Personality

adapter. The circle marked on the Probe should align with pin 1 on the m128 adapter.

Figure 3-14. m128 Personality Adapter(1)

Note: 1. SNR: W10635SDF

3.4.7.1 Supported Devices ATmega128

3.4.8 m169 Personalit y

Adapter Figure 3-15. m169 Personality AdapterFigure 1

Note: 1. SNR: W10634SDF

3.4.8.1 Supported Devices ATmega169

General Description

ICE50 User Guide 3-11

2523A–AVR–11/02

3.5 POD Description The ICE50 POD implements al l digital I /O and analog functionalit y of the cu rrent AVR

family of devices. If new AVR devices are made available to the market that contain I/O

or analog featu res that cannot be emulated by th e current POD, Atmel is dedicated to

create new POD modules that support the functionality of the new devices.

3.5.1 POD Description The ICE50 POD is shown in Figure 3-16. It connec ts to the mai n unit thro ugh two doc k-

ing connectors . When c onne cting or disconn ectin g the POD do n ot use ex cess ive forc e

as this might damage the POD.

Figure 3-16. ICE50 POD

The POD contains all analog and digital logic necessary to emulate the target AVR

device. The circuitry is designed to give as close as possible electrical characteristics as

the real device. The POD emulates the following functions:

Digital I/O

Analog Comp arator

A/D Converter

The ICE50 is a jumperless design. All configuration of the POD is done through AVR

Studio. No manual configuration of jumpers is necessary.

General Description

3-12 ICE50 User Guide

2523A–AVR–11/02

3.5.2 Digital I/O The Digital IO ports of the ICE50 are realized as shown in Figure 3-17 using CMOS buff-

ers and voltage converters.

Figure 3-17. Digital I/O

The propagation delay of the IO ports are larger for the ICE50 than for the actual emu-

lated part. The diagram below shows the timing data for driving out and reading in a

signal on th e IO ports of the Emula tor. The data di rection regis ter is assume d set to “1”

in Figure 3-18. Table 3-3 shows typical data.

Figure 3-18. Data Direction Register

PULLUP (DDRxy & PORTxy)

DDRxy

PORTxy

PINxy

PINKEEPx

VCC

330K

36K

Pxy

VCC Emulator VCC Target

LEVEL CONVERTER

DIGITAL I/O

tILH

PORTxy

Pxy

tOHL

tIHL

tOLH

PINxy

General Description

ICE50 User Guide 3-13

2523A–AVR–11/02

Notes: 1. tOHL = Time from clearing the PORT register to the output changes

2. tOLH = Time fr om settin g the PORT register to the output changes

3. tIHL = Time from changing the input level to the PIN signal changes (high to low)

4. tILH = Time from changing the input level to the PIN signal changes (low to high)

Figure 3-19 shows the timing data for tristating/driving the IO pins. Table 3-4 shows

related typical data.

Figure 3-19. Timing Data

Notes: 1. tDZL = time from setting the DDR register to the output is driven low.

2. tDLZ = time from clearing the DDR register to the output is tristated.

3. tDZH = time from setting the DDR register to the output is driven high.

4. tDHZ = time from clearing the DDR register to the output is driven low.

The drive capability of the output buffers are ± 24 mA at 3V VCC. This slightly exceeds

the driving capability of the actual parts. The operating voltage range of the IO circuits

are 2 VCC to 5.5 VCC. At 2V V CC the buffers are able to sink 25 mA with a maximal output

low voltage (VOLmax) of 1V.

The hysteresis voltage for the input buffers are typically 0.8V at 3V VCC and 1.2 V at 5.5 V

VCC.

Table 3-3. Data Direction

Delay Typical Value (2 V Target) Typical Value (5V Target)

tOHL(1) 13 ns 10 ns

tOLH(2) 13 ns 10 ns

tIHL(3) 13 ns 10 ns

tILH(4) 13 ns 10 ns

Table 3-4. Timing Data

Delay Typical Value (2V target) Typical Value (5V target)

tDZL(1) 15 ns 15 ns

tDLZ(2) 15 ns 15 ns

tDZH(3) 15 ns 15 ns

tDHZ(4) 15 ns 15 ns

DDRxy

PORTxy

Pxy

tDZL tDLZ

tDZH tDHZ

High Z High Z High Z

General Description

3-14 ICE50 User Guide

2523A–AVR–11/02

3.5.3 Analog Comparator The Analog Comparator is built around a high speed comparator and a CMOS output

buffer/volta ge c on ve rter. Fi gure 3-20 shows the Analog Comparator bloc k diagram. The

total propagation delay from the AIN0 and AIN1 pins to the internal ACO signal is typi-

cally 90ns , max 210ns. For parts, t he total propag ation delay from the AIN0 and AIN1

pins to the internal ACO signal is typically 500 ns, max 750 ns.

The comparator features an internal hysteresis of typical 1 mV, max 4 mV @ 25°C to

ensure clean switching.

Figure 3-20. Analog Comparator Block Diagram

3.5.4 A/D Converter The block diagram of the ICE50 AD converter is shown in Figure 3-21.

Figure 3-21. ICE50 AD Converter

ACME

ADEN

AIN1

ADC Multiplexer

Output

ACBG

1.2V

AIN0

ACD

100R

ACO

ANALOG COMPARATOR

330Ω

Pos

Input

Mux

Neg

Input

Mux

ADMUX Decoder

1.2V

VCC

-10K

10K +

-ref

ref

1x/10x/100x

1x/2x

ADC Multiplexer Output 10-bit ADC

Vin

Vref

330Ω

Voltage

Reference

Selection

Aref Out

-10K

10K +

-Vref

Q[0..9]

A/D Converter

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

AVCC

Aref

2.5V

General Description

ICE50 User Guide 3-15

2523A–AVR–11/02

The ADC is bui lt us ing a nalog multi plexe rs, pro gramma ble gain ins trument ati on am plifi-

ers and a 10-bit successive approximation A/D converter. This construction should have

the same performance as the actual part, but since the ADC is located on the POD as

an external construction the analog components will be more susceptible to ambient

noise and noise from switching IO lines.

Note: Internal analog reference voltage is set to 2.5 volt when using the emulator. This

differs from part which uses 2.56 V. Due to this fact ADC conversions done by

the emulator using the internal analog reference voltage differ from the conver-

sions done in part.

All inputs to the ADC hav e se ria l c urre nt li miting resisto rs of 330Ω. This is to prote ct th e

inputs of the ADC circuit when the emulator is switched off and the target power is

present. The outputs of the input multiplexers are clamped to VCC and GND and thus

when target VCC is present and th e emulator po we r i s turn ed off there will fl ow a current

of approximately (Vinput - 0.3V)/330Ω through each ADC inp ut pin .

3.6 Power System

Description The ICE50 needs extern al power in order to function. A switc hi ng po wer ada pter is sup-

plied with the unit . The po wer ada pte r will ac ce pt input voltages in the rang e of 10 0VAC

to 240VAC and frequencies from 50Hz to 60Hz. This will cover most situations.

3.6.1 Power Supply Figure 3-22. Power Supply

The power supply delivered with ICE50 is dimensione d to meet t he requ irements of the

Emulator. If a nother powe r supp ly is use d, it sho uld supply a voltag e between 9 and 15

VDC, and a minimum of 20W. It connects to the main unit through a standard connector

with 2.1 mm center tap. Ground is connected to the center tap.

3.6.2 ICE50 Power System The ICE50 has an internal power regulator designed to deliver regulated voltages for

use by the ICE itself. The power system is not designed to provide external power to the

target application.

General Description

3-16 ICE50 User Guide

2523A–AVR–11/02

3.6.3 Target Application

Power

Requirements

The Probe and pa rts of the POD are powe red by the target app lication power syste m.

The dynamic power requirements of the Probe/POD will not differ significantly from the

power requirements of t he actual dev ice. See below for power req uirements. The s tatic

power requirement for th e POD is listed in Table 3-6. The targ et power syst em must be

dimensioned to tolerate this current consumption.

Note: The Digital I/O drive capabilities of the ICE50 POD differ slightly from what can

be expected in the actual device. For details on the Digital I/O drive capabilities

compared to the actual device, please see the Digital I/O section of the POD

description.

Table 3-5. Power Requirements

Power Requirements

Power Voltage Requirements 9 - 15 VDC

Power Consu m ption < 20 W

Target Application Voltage Range 2.7 - 5.5 V

Table 3-6. Target Voltage

Target Voltage

ICE50 (POD/P robe) curre nt co nsumption from Target Applica tio n,

Normal (Typical) Worst Case

2.5V 5 mA 7 mA

3.3V 20 mA 30 mA

5.0V 85 mA 125 mA

5.5V 110 mA 165 mA

General Description

ICE50 User Guide 3-17

2523A–AVR–11/02

3.7 Probe

Description The ICE50 probe is the link between the flex cable going out from the POD and the Per-

sonaliy Adapter that fits into the target application. The main purpose of the probe is to

route all the signals from the flex cable to the appropriate pins of the personality adapter.

In addition the Probe imp lements current lim itation o n all the I/O pins in ord er to prote ct

both the target and the POD. The probe also implements proper line termination in order

to avoid ringing on high freuency signals.

3.7.1 Probe Description The Probe con tains cloc k driv er circ uitry for th e ICE 50, v oltage pola rity a nd s hort ci rcuit

protection. Figure 3-23 sho w a picture of the probe and a simplified block d iagram of

how the clock driver ci rcuitry is implemente d is shown in Figure 3-24 and Figure 3-25.

By putting the clock driver circuitry on the Probe (as close as possible to the target

board) the best possible emulation of the AVR clock options are achieved.

Figure 3-23. Probe

Figure 3-24. Tim er Os ci llator

Timer

Oscillator

Drive

Enable

Output

General Description

3-18 ICE50 User Guide

2523A–AVR–11/02

Figure 3-25. Ex tern al Clock

3.7.1.1 Available Clock

Options The current version of the Probe has some restrictions with regards to clock options

support. The unsupported clock modes are quite easy to emulate with simple

workarounds as described in Section 3.7.6 and Section 3.7.7. The Probe version can be

found on top of the back side of the Probe (left side of the right picture above).

3.7.1.2 ICE50 Probe version

A9902.3.1200.E Version A9902.3.1200.E of the Probe supports the following clock options:

External Clock Signal

Internal Clock Signal provided by AVR Studio

External 32 kHz RTC Crystal

Internal Calibrated RC Oscillator

The following clock options are not supported by Probe version A9902.3.1200.C. A

description for workarounds for the unsupported clock modes can be found in section

“External Crystal and External Re sonator” on page 19 and “Externa l RC Oscillator” on

page 19.

3.7.2 External Clock

Signal An external clock signal can be applied to the XTAL1 pin on the emulator probe. The

Emulator can th en be set up to u se th is sig nal as the s yst em cloc k. See dev ice sel ecti on

for a description of how to set up AVR Studio for this option. The clock signal must meet

the cond itions as shown in Table 3-7.

3.7.3 Internal Clock Signal

Provided by AVR

Studio

The Emulator may be set up to run on an internal programmable clock. The frequency

range of this programmable clock is 5 kHz to 20 MHz. However, the maximum fre-

quency cannot be set higher than the speed limit of the actual part. Only certain output

frequencies are po ssible to gene rate with highest accu racy. However the clock genera-

tor generally produces an output frequency within 0.1% of the desired output frequency.

If the target application should run on the same clock as the AVR chip/emulator, the

internal programmable clock may be driven out on the XTAL2 pin. See section device

selection for a description of how to set up the internal program mable clock.

Enable

XTAL2

Enable

XTAL1

Table 3-7. Clock Signal Conditions

Value

Frequency 5KHz to 20MHz

Duty cycle 50%

Absolute maximum input voltage 1.8 - 7.0V

Recommended input voltage 1.8 - 5.5V

Minimum high leve l input v oltage 1.7V

Maximum low le vel input voltage 0.5V

General Description

ICE50 User Guide 3-19

2523A–AVR–11/02

3.7.4 External 32 kHz RTC

Crystal The Asynchronous Timers in the emul ated part may be clocked by an external 32 kHz

crystal. Thi s crysta l sho uld be connec ted to the T OSC1 an d TOSC2 pins of the perso n-

ality adapter. To ensure proper operation the crystal should be connected as close to

the personality adapter as p ossible. The Oscillator driver on the probe is design ed to

work with most parallel mode 32 kHz crystals.

3.7.5 Internal RC

Oscillator In AVR Stud io th e Emulator may b e se t to ru n on a n Internal RC Os ci lla tor. See s ec tio n

device selection for a description of how to set up the Internal RC Oscillator.

3.7.6 External Crystal a nd

External Resonator External crystal/res onator is not suppo rted on the ICE50 probe. I nstead, configure the

Emulator to use t he inte rnal programm able cloc k. The XTAL 1 pin will th en be tri-st ated.

XTAL2 pin will be enabled and the intern al programmable clock is driven out on the

XTAL2 pin. See special section for a description of how to set up the XTAL2 clock.

3.7.7 External RC

Oscillator External RC Oscillator is not supported on the ICE50 probe. Instead, configure the emu-

lator to use th e internal progra mmable clock. Th e XTAL1 and XTAL2 pins will then be

tristated.

3.8 Test Adapter ICE50 is supplied with a Test Adapter. See Figure 3-26.

Figure 3-26. Te st Adap te r(1)

Note: 1. SNR: A9902.3.1400.A

The adapter includes an identification code that the ICE50 and AVR Studio uses for

detection. The ICE50 Test Adapter is used for the following tests:

Analog Comp arator

Analog Digital Converter

I/O pins

General Description

3-20 ICE50 User Guide

2523A–AVR–11/02

3.8.1 Using the Test

Adapter The test adapter must be connected to the probe.

To start the test program open AVR Studio and select from the drop down menu: Tools-

>ICE50 Selftest. The window showing in Figure 3-27 will appear:

Figure 3-27. Start Test Program in AVR Studio

The tests that require a Test Adapter connected to the probe are the ones marked on

the list above. Se lect th e test th at sho uld be run, and pres s the “Run ” button to start th e

test. Finally, the test program will show the status of the test.

Note: AVR Studio 4.0 or later is required for ICE50 support. AVR Studio 3.x versions

will not work with ICE50!

Tip!

AVR Studio is constantly being updated. Check for upgrades at www.atmel.com.

ICE50 User Guide 4-1

Rev. 2523A–AVR–11/0 2

Section 4

Connecting ICE50

ICE50 connects to both the PC where t he firmware develo pm en t is be ing ma de an d th e

target application. This section describes the connection procedure.

4.1 Connecting

ICE50 for

Emulation

This section wi ll descri be how to con nect an d configu re the ICE50 for correc t operatio n.

This task can be divided in the following tasks:

1. Selecting correct Personality Adapter

2. Connecting the Probe to the Target Board

3. Connecting ICE50 to PC

4. Correct Power-Up Sequence

5. Configuring AVR Studio

Please follow the above description to make sure that the ICE50 is configured properly!

4.2 Connecting

ICE50 to host PC The ICE50 connects to the host PC through a sta ndard COM port. Make sure that t he

ICE50 is powered down before connecting the cable between the ICE50 and the host

PC. Use the 9-pin RS-232C cable that is shipped with the ICE50. Connect the male

cable connector to the ICE50 and the female connector to the host PC. The communica-

tion runs at 115200 bit/s, no parity, 8 data bits, 1 stop bit, (N81), and with hardware

handshake.

AVR Studio can not force control over a COM port. If other equipment or software driv-

ers have control of the COM port (eg. IrDA, PDA, Scanner.. ) communication with the

ICE50 will fail. Make sure that no other software has control of the COM port that ICE50

is connected to.

Note: The USB interface is not supported in the current version of the ICE50. Once

the ICE50 is connected to the host PC, continue with connecting the probe to

the target board.

4.3 Connecting the

Probe to the

Target Board

The Probe is connected to the targ et board through one o f the supplied Personalit y

Adapters. To ensure correct operat ion make sure that the correct Personality Adapter is

used.

4.3.1 Connecting PDIP

Adapters Before connecting the ICE50 to the target application, make sure that the ICE50 and the

target application are not powered. This also applies when removing the ICE50. When

Connectin g ICE 5 0

4-2 ICE50 User Guide

2523A–AVR–11/02

connecting o r disconnecting the ICE50 f rom the host PC, make su re that the ICE50 is

not powered.

1. Inserting the personality adapter . Make sure that pin 1 on the personality adapter

correspon ds with pin 1 on the target socket/footprint.

2. Mount the Probe onto the personality adapter. Do not use excessive force; the

Probe only fits one way into the personality adapter. Use the circles on the Per-

sonality Adapters and the Probe to safely determine correct orientation. Make

sure that the probe is connected to the pod connector on the ICE50.

Figure 4-1. Connecting PDIP Adapters (Part One of Two)

Note: 1. Place the Pe rsonality Adap ter in the target applicatio n socket. Make sure tha t the dot

on the Personality Adapter m atch pin 1 in the target socket.

Figure 4-2. Connecting PDIP Adapters (Part Two of Two)

Note: 1. Place the Probe on the Personality Adapter. The circle on the probe should face in

the same direction as the dot on the Personality Adapter.

Connecting ICE50

ICE50 User Guide 4-3

2523A–AVR–11/02

4.3.2 Connecting TQFP

Adapters The m128 TQFP adapter consists of two parts:

The bottom p art that sho uld be solde red into th e target applic ation , and th e top p art

that interface with the ICE50 Probe . When moun ting the TQFP ad apter, make sure

that the adapter is soldered into the application with the correct orientation.

1. Start soldering the bottom part of the Personality Adapter on the target applica-

tion. Make sure that pin 1 on the adapter matches pin 1 in the target application.

2. Place the TQFP top module on top of the soldered bottom module. Again take

care to place it with the correct orientation.

3. Place the Probe on the Personality Adapter.

Use low temperature solder and soldering iron when soldering the bottom part to the tar-

get. This will ensure that the solder on the adapter is not removed during soldering.

Figure 4-3. Connecting TQFP Adapters (Part One of Three)

Note: 1. Place and solder the bottom module. Take care to place it with correct orientation.

Connectin g ICE 5 0

4-4 ICE50 User Guide

2523A–AVR–11/02

Warning!

Every design precaution is ta ken so that the p robe and ICE50 POD s hould not be

damaged if incorrectly placed. However, selecting wrong adapter, or placing the

adapter with wrong orientation may damage the ICE50 POD.

Connecting or disconnecting the POD or Personality Adapter while the target application

is powered might damage the Probe and/or the POD.

Once the Probe and Personality Adapter are connected, continue by correct Power-up

sequence.

4.4 ICE50 Power-up

Sequence When the ICE50 is properly connected to the target and the host PC, the power can be

turned on. The following procedure is recommended to ensure proper communication

between the ICE50 and AVR Studio.

Power up ICE50, wait for yellow LED to be lit.

Power up target board.

Start AVR Studio.

Note: The equip ment will not be harmed in any way if a different power up sequ ence

is used, but since AVR Studio tries to detect peripherals when started, the

ICE50 will not be detected if not powered.

Once the power-up sequence is done, the ne xt step is to start up and configure AVR

Studio. For more information on Power Supply requirements follow this link.

ICE50 User Guide 5-1

Rev. 2523A–AVR–11/0 2

Section 5

Configuring AVR Studio

When the ICE50 is properly connecte d to the target application, the ne xt step is to set

up the correct device configuration in AVR Studio. This is required when an application

project i s opened for the first time, and can later b e changed in the emulator options

menu. The configuration is stored in a sepa rate file, and will automatically b e loaded

when starting the project later.

This section is div id ed in two sub se cti ons :

1. One Quick Start Guide describing the procedure to get the AVR Studio

configured.

2. One subsection describing all emulator options in detail.

5.1 ICE50 Emulator

Options

Device Selection Options

Fuses

ICE Module/Revision list

Special

Note: AVR Studio 4.0 or later is required for ICE50 support. AVR Studio 3.x versions

will not work with ICE50!

Configuring AVR Studio

5-2 ICE50 User Guide

2523A–AVR–11/02

5.2 AVR Studio

Configuration

Quick Start

Guide

Follow the procedure described below to configure the ICE50:

1. Connect the ICE50 and start AVR Studio. See Connecting ICE50 for a more

detailed description.

2. Select between creating a new or opening an existing AVR Assembler project.

See picture below.

3. If you have already made an object file you can open this directly. See Figure 5-

Figure 5-1. Welc om e to AVR Stud io 4

4. If a new project is chosen, type in the project name. Chec k create initialfile if you

would like an assembler file with the same name as the project. If you would like

a folder created with the same name check this option. Browse to select location

for the project. See Figure 5-2.

Figure 5-2. New Project Window

Configuring AVR Studi o

ICE50 User Guide 5-3

2523A–AVR–11/02

5. Press the next button. Now select ICE50 as target and then chose the part to

emulate. Press finish to complete the wizard. AVR Studio will now be ready for

use. See Figure 5-3. Parts that are downloaded and available in ICE50 are

shown highlighted. If a part in grey colour is selected the tool for downloading

new parts is launched. See download new parts for ICE50.

Figure 5-3. AVR Studio 4 Screenshot

5.3 Device Selection 1. In AVR Studio go to Debug->ICE50 Options. De vice Selection is highlighted and

it is possible to choose from different parts in the pulldown menu. Note the icon

to the left for each part name. Click this icon if this part is to be loaded into the

ICE50. A total of four part files can be contained in the ICE50 at the same time.

Some part files contain two AVR emulator parts. The status bar at the right side

indicates how many part files ICE50 contains.

For ATmega128 it is also possible to choose ATmega103 compatibility mode.

2. Select between the following clock sources:(This wi ll affect the fuse settings for

the actual part).

– Internal XTAL Oscillator

– Internal RC Oscillator

– External Clock

3. Different start-up times can be selected from the Start-up time pulldown menu.

(This will affect the fuse settings for the actual part.)

4. Part frequency can be selected from the frequency pulldown menu as shown in

Figure 5-4 or the frequency can be typed in the editor box.

Configuring AVR Studio

5-4 ICE50 User Guide

2523A–AVR–11/02

Figure 5-4. Device Selection

In addition two buttons called ICE Reset and Set Default are located in the lower left cor-

ner. See Figure 5-4. The ICE Reset button res ets the ICE while the s et Default button

loads the default settin gs. ICE rese t perform s the sa me rese t as th e rese t butto n on the

back of the ICE50.

Configuring AVR Studi o

ICE50 User Guide 5-5

2523A–AVR–11/02

5.4 Fuses and Lock

Bits The Fuse- and Lock bit settings in the part can be viewed and configured from AVR Stu-

dio. The Fus e settings can only be viewed and no t edited in the “Fuse and Lock bit”

view. Configuration is performed in the other views.

In AVR Studio go to Debug->ICE50 options. Highlight Fuses and Lock bits. It is now

possible to view 4 different settings. Note that Fuses marked with “!” do not affect

emulation.

Figure 5-5. Fuse and Lock Bits Settings

1. By pressing “Extended” Fuse the tree expands and it is possible to see the set-

tings for this fuse. “0” indicates on or Fuse programmed, “1” indicates off. It is not

possible to edit the Fuse setting here. The Extended Fuses are available fo r

selected parts. See the datasheet f or the part when configuring the Fuses. In this

case the ATmega128. The Extended Fuse is used to support special features.

See Figure 5-6.

Configuring AVR Studio

5-6 ICE50 User Guide

2523A–AVR–11/02

Figure 5-6. Exte nd ed Fus e Setti ng s

2. By pressing “Low Fuse” the tree expands and it is possible to see the settings for

this Fuse. “0” indicates on, “1” indicates off. The Fuse settings can not be edited

here. See the dat asheet for the part when configuring th e Fuses . See Figu re 5-7.

Figure 5-7. Low Fuse Settings

3. By pressing “High Fuse” the tree expands and it is possible to see the settings

for this Fuse. “0” indicates on, “1” indicates off. The Fuse settings can not be

edited here. See the datasheet for the part when configuring the Fuses. Note

that Fuses marked with “!” do not affect emulation. See Figure 5-8.

Configuring AVR Studi o

ICE50 User Guide 5-7

2523A–AVR–11/02

Figure 5-8. High Fuse Settings

Tip!

Not all fuse settings are supported by the ICE50. The following fuses are ignored:

– OCDEN. On Chip debug is not available in ICE50.

– SPIEN. Serial Programming not available.

– EESAVE. Not available in ICE50.

– JTAGEN. Not available in ICE50.

Configuring AVR Studio

5-8 ICE50 User Guide

2523A–AVR–11/02

5.5 Lock Bits By pressing Lock bits the tree expands and it is possible to see the Lock bit settings. “0”

indicates on, “1” indicates off. The fuse settings can not be edited here. See the

datasheet for the part when configuring the Lock bits. See Figure 5-9.

Figure 5-9. Loc k Bits Settin gs

Configuring AVR Studi o

ICE50 User Guide 5-9

2523A–AVR–11/02

5.6 ICE Status In AVR Studio go to Debug->ICE50 Options. Highlight ICE Status. The report which

appear describes the different modules with respect to software version and firmware

version. See Figure 5-10. In addition two buttons called ICE Reset and Set Default are

located in th e lower left corner. See figu re below. The ICE Reset button pe rforms a

warm emulator reset and can be used instead of the reset button on the back of the

ICE50 while the Set Default button loads the default setting for the actual part.

Figure 5-10. ICE Status

Reports for the different FPGA configuration files and the hardware revisions in the dif-

ferent PCB's are also shown. See Figure 5-11.

Configuring AVR Studio

5-10 ICE50 User Guide

2523A–AVR–11/02

Figure 5-11. ICE Staus Window

Configuring AVR Studi o

ICE50 User Guide 5-11

2523A–AVR–11/02

5.7 Boot Block

Options In AVR Studio go to Debug->ICE50 options. Highlight Boot Block Options. Four different

pulldown menus will appear. See Figure 5-12. The four menus are:

1. Boot Size. Select between the available Boot Sizes in the pulldown menu.

2. Reset Vector. Select application or Boot Reset Vector.

3. Boot Lock Protection mode0, Application section. Select between four different

types. See datasheet f or the actual part for more information.

4. Boot Lock Protection mode1, Boot section. Select between four different types.

See datash eet for the actual part for more information.

Note: This menu is only available for AVR parts wit h Boot Block.

Figure 5-12. Boot Block Options

Note: AVR Studio 4.0 or later is required for ICE50 support. AVR Studio 3.x versions

will not work with ICE50!

Configuring AVR Studio

5-12 ICE50 User Guide

2523A–AVR–11/02

5.8 Special Special settings c an be confi gured from AVR Studio.

In AVR Studio go to De bug->ICE5 0 Option s. Hi ghlig ht Other Opt ions. It is n ow poss ible

to configure XRAM, Reset sources and Timer oscillator. See Figure 5-13.

XRAM: Choose between emulate XRAM memory internally in ICE50, or enable the

AVR external XRAM interface for using RAM in the target application.

Reset Sources: enable/disable POR (P ower-on Reset), BOD (Brown-o ut Detector), or

External Reset.

Timer Oscillator: Choose between internal or external.

The two checkboxes in the upper right corner makes it possible to:

Disable sourcing of XTAL2 clock .

Enable Watchdog Timer always on. Watchdog ca be configured to break on

Watchdog overflow or reset on Watchdog ov erflow.

Figure 5-13. Speci al Sett ings

In addition two buttons called ICE Reset and Set Default are located in the lower left cor-

ner. The ICE Reset button resets the ICE while th e Set Default button loads the default

setting. ICE reset performs the same reset as the reset button on the back of the ICE50.

5.9 Downloading

New Parts for

ICE50

AVR Studio will check if newer files are avai lable in the ICE50 dat file, and prompt the

user whether an upgrade should be performed.

AVR Studio is continously updated. Check the Atmel web site, www.atmel.com, for

upgrades.

Configuring AVR Studi o

ICE50 User Guide 5-13

2523A–AVR–11/02

5.10 Upgrading the

ICE50 Firmware The ICE50 firmware can be upgraded from AVR Studio.

In AVR Studio go to Tools ->ICE50 Upgrade. The window as shown in Figure 5-14 will

appear.

Figure 5-14. ICE50 Upgrade Window

From this window it is possi ble to select two buttons. The Sta rt Upgrade butt on will per-

form an upgrade of the ICE50.

Note: If the skip Version check checkbox is marked all modules and part files will be

upgraded. If the Allow Downgrade checkbox is marked the ICE 50 firmware can

be downgraded.

The ICE50 Info button shows th e current firmware ver sion in all modules and part f iles.

See Figure 5-15.

Configuring AVR Studio

5-14 ICE50 User Guide

2523A–AVR–11/02

Figure 5-15. Version Information

ICE50 User Guide 6-1

Rev. 2523A–AVR–11/0 2

Section 6

Special Considerations

The ICE50 accurately emulates most AVR features. However, there are some differ-

ences worth noting.

Clock Options

A/D Converter Accu racy

Differences from actual part

Electrical Compatibility

Sleep mode

Target hardware requirements

If you expe ri ence pro bl ems not desc ri be d in t his sec tio n, p leas e s ee th e tr ou ble sh oot i ng

section for more information.

6.1 Electrical

Compatibility ICE50 is creat ed to emu late an a ctual AVR de vice in detail. When it comes to elec trical

compatibility some issues must be considered. They are described in this section.

6.1.1 Power The POD is protected ag ain st wron g po lari ty from the targe t power. In addition the POD

will not be powered when ICE50 power is disabled. See Figure 6-1.

Figure 6-1. Power

6.1.2 I/O Lines The I/O lines are current limited by a thermis tor. Ove r vol tag e is s upp res se d by a schot-

tky diode. This circuit can be seen in Figure 6-2.

ICE on

POD Polarity

Protection POD

Target Power

Special Considerations

6-2 ICE50 User Guide

2523A–AVR–11/02

Figure 6-2. I/O Lines

6.2 Sleep Mode When in sleep mode th ere will be no power reduction as ca n be seen in an actual part.

6.3 Target Hardware

Requirements The target must be able to supply 2.5 - 5.5V @ 200 mA.

6.4 Clock Options The Current version of the ICE50 Probe has limited support for Clock options. See

Available Clock Options for an overview of the supported modes.

Other modes can however easily be emulated using the modes above.

6.5 Differences

Between

Emulator and

Part

The ATmega8 personality adapter (SNR: A9902.3.1390.A) does not support External

Timer Oscillator.

ADC internal voltage reference is 2.5V, and not 2.56V as in part.

Resetable

Fuse POD I/O

Probe I/O

Table 6-1. Target Voltage

Target Voltage

ICE50 (POD/Probe) current consumption from Target Application

Normal Worst Case

2.5V 5 mA 7 mA

3.3V 20 mA 30 mA

5.0V 85 mA 125 mA

5.5V 110 mA 165 mA

ICE50 User Guide 7-1

Rev. 2523A–AVR–11/0 2

Section 7

Trace

The ICE50 contains a 144-bit wide, 128K levels deep Trace Buffer. This document

describes the contents of the AVR Studio Trace Buffer view.

7.1 Enabling Trace

in AVR Studio 1. To enable Trace in AVR Studio select “Trace Normal” from the trace toolbar pull-

down menu. See Figure 7- 1.

Figure 7-1. Enable Trace

2. In th e active source wind o w select Trace st art and st op b y pre ssing F 8. Press F8

once for Trace to start at this line. Press F8 twice for Trace to end at this line.

Press F8 three times to remove Trace. Alternatively the icons on the Trace tool-

bar menu can be used instead of F8. The hand is equal to Trace start and stop.

The hands with red marks will rem ove all Trace points . Trace on is m arked with a

“1” while trace off is marked by a “1” with a red line across. See Figure 7-2.

Figure 7-2. Start and Stop Trace

3. It is possible to have several start and stop points. Each pair of start and stop

points will ha ve an unique number (Function ID). In Figure 7-3 two Trace

start/stop pair are shown (number 1 and 2).

Trace

7-2 ICE50 User Guide

2523A–AVR–11/02

Figure 7-3. Multiple Start and Stop Trace

The Function ID numbers can be select ed fro m the trace toolbar. In Figure 7-4 Func tio n

ID “2” is selected from a drop down menu.

Figure 7-4. Fun cti on ID Selection

4. Open Trace Window.

7.2 The Trace

Window To view the Trace output, select “Trace Output” from the view menu or press the trace

window icon in the trace toolbar. The trace window icon is located as number three from

the right in Figure 7-5.

Figure 7-5. Trace Output

A window like illustrated in Figure 7-6 will appear on the screen. The contents of the

trace buffer will of course vary with the actual project.

Figure 7-6. Trace Buffer

The Trace f unction of th e ICE50 traces th e program exe cution every c lock cycle t race

every single cycle in the execution.

The Trace view c ontains the colu mns describe d below. A more deta iled description of

the contents of each column for the individual AVR instruction is found in the section:

Contents of Trace Window based on Instruction.

Timestamp Column: This column contains the value of the Cycle Counter at the time

when the information was logged. Note that the Cycle Counter has 41 bits so it will

wrap at a value of 0x20000000000 or 2199023255552d .

If executing with a clock frequency of 20 MHz, this means that the Cycle Counter will

wrap every 30 hours.

Progr am Mem ory Address col umn (Ins Ad dr): T his c olu mn con tai ns th e curren t value

Trace

ICE50 User Guide 7-3

2523A–AVR–11/02

of the Program Counter, i.e., it is the address in the Program Memory of the

instruction currently being executed. For m ulticycle instructions, the contents of this

column may contain other values. See the descripti on of the various instruction.

Valid Instruction (VI): This is a status flag which tells if the instruction is fetched and

ready for e xecution. For m ulticycle instructions this bit will only be “1” in the first cycle.

Instruction Column (Ins): This column contains the instruction word and the

disassembled mnemonic representation of all instructions being executed. For

multicycle instructions, this column will only contain information in the first cycle of the

instruction. For the remaining cycles of the instructions, the column is left blank.

Data Addres s Column (Dat.Add r): This column co ntains the ac tive ad dress in the data

memory space, and only contains information during some cycles in instructions

reading from or writing to the data memory. See the description of the instructions to

see what this field means for each instructi on.

Register File Low/High Value column (RL &RH): For some of the instructions, the

result being fed back to the Register File is also sent to the Trace Buffer. For other

instructions, this field does not contain any information. See the description of the

instructions to see what this means in the various cases.

Register File Valid Signal (VR): This status bit indicates if the values on column RL

and RH is valid in this cycle..

Spare Signals (S): Fo r future use.

Status Register Column (SR): Contains the AVR Status Register.

Function ID (PS): This column contains the Function ID number .

Interrupt Acknowledge Column: If an interrupt routine is invoked this column will

contain a “1” else a “0”.

Trace

7-4 ICE50 User Guide

2523A–AVR–11/02

7.3 Contents of

Trace Window

Based on

Instruction

(ICE50)

As can be seen from Enabling Trace, the contents of the different colum ns varies with

which instruction is being executed. This section describes how to interpret the contents

of the Trace buffer based on which instruction is being executed.

Some of the explanations are tagged with a number. This number indicates the cycle

number in the instruction execution (important for multi-cycle instructions only). The

term N/A is used when a field does not contain any valuable information.

Table 7-1. Arithmetic and Logic Instructions

Instruction

INSTA[0..15] PMem Addr

[PC[A0..22] Reg.Val

RegFileL[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

ADD Rd,Rr Address of instruction Result of additi on N/A N/ A Z,C,N,V,S,H

ADC Rd, Rr Address of instruction Result of addition N/A N/A Z,C,N,V,S, H

ADIW Rdl,K 1. Address of instruction 1. Result of addit ion, low byte 1. N/A 1. N/A Z,C,N,V,S

2. Address of next instruction 2. Result of addition, high byte 2. N/A 2. N/A

SUB Rd, Rr Address of instruction Result of subtraction N/A N/A Z,C,N,V,S,H

SUBI Rd, K Address of instruction Result of subtraction N/A N/A Z,C,N,V,S,H

SBC Rd, Rr Address of instruction Result of subtraction N/A N/A Z,C,N,V,S,H

SBCI Rd, K Address of instruction Result of subtraction N/A N/A Z,C,N,V,S,H

SBIW Rdl,K 1. Address of instruction 1. Result of subtraction, low byte 1. N/A 1. N/A Z,C,N,V,S,H

2. Address of next instruction 2. Result of subtraction, high byte 2. N/A 2. N/A

AND Rd, Rr Address of instruction Result of logical AND N/A N/A Z,N,V,S

ANDI Rd, K Address of instruction Result of logical AND N/A N/A Z,N,V,S

OR Rd,Rr Address of instruction Result of logical OR N/A N/A Z,N,V,S

ORI Rd, K Address of instruction Result of logical OR N/A N/A Z,N,V,S

EOR Rd, Rr Address of instruction Result of logical EOR N/A N/A Z,N,V,S

COM Rd Address of instruction Result of complement N/A N/A Z,C,N,V,S

NEG Rd Address of in struction Result of negation N/A N/A Z,C,N,V,S,H

SBR Rd,K Will nev er appear (is

disassembled to ORI

instruction) N/A N/A N/A Z,N,V,S

CBR Rd,K Will never appear (is

disassembled to ANDI

instruction) N/A N/A N/A Z,N,V,S

INC Rd Address of instruction Result of incrementation N/A N/A Z,N,V,S

DEC Rd Address of instruction Result of decrement ation N/A N/A Z,N,V,S

TST Rd Will never appear (is

disassembled to AND

instruction) N/A N/A N/A Z,N,V,S

CLR Rd Address of instruction Result (always 0x00) N/A N/A Z,N,V,S

SER Rd Will never appear (is

disassembled to LDI

instruction) N/A N/A N/A N/A

Trace

ICE50 User Guide 7-5

2523A–AVR–11/02

MUL Rd, Rr 1. Address of instruction 2.

Address of next instruction 1. N/A 2. Result of multiplication 1. N/A 2. N/A 1. N/A 2.

N/A Z,C

MULS Rd, Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A Z,C

2. Address of next instruction 2. Result of multiplication 2. N/A 2. N/A

MULSU Rd , Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A Z,C

2. Address of ne x t instruction 2. Result of multiplication 2. N/A 2. N/A

FMUL Rd, Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A Z,C

2. Address of ne x t instruction 2. Result of multiplication 2. N/A 2. N/A

FMULS Rd , Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A Z,C

2. Address of ne x t instruction 2. Result of multiplication 2. N/A 2. N/A

FMULSU Rd, Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A Z,C

2. Address of ne x t instruction 2. Result of multiplication 2. N/A 2. N/A

Table 7-1. Arithmetic and Logic Instructions (Conti nued)

Instruction

INSTA[0..15] PMem Addr

[PC[A0..22] Reg.Val

RegFileL[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

7-6 ICE50 User Guide

2523A–AVR–11/02

Table 7-2. Data Transfer Instructions

Instruction

INSTA[0..15] PMem Addr [PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

MOV Rd, Rr(1) Address of instruction Value loaded into

MOVW Rd, Rr(1) Addres s of instruction Value loaded into

Rd+1 N/A N/A N/A

LDI Rd, K(1) Address of inst ruction Value loaded into

LD Rd, X(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (X) 2. Address of next

instruction

LD Rd, X+(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (X) 2. Value read

LD Rd, - X(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (X) 2. Value read

LD Rd, Y(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Y) 2. Value read

LD Rd, Y+(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Y) 2. Value read

LD Rd, - Y(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Y) 2. Value read

LDD Rd,Y+q(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Y+q) 2. Value read

LD Rd, Z(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Z) 2. Value read

LD Rd, Z+(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Z) 2. Value read

LD Rd, -Z(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Z) 2. Value read

LDD Rd, Z+q(1) 1. Address of instruction 1. N/A 1. N/A) 1. N/A N/A

2. Address of next instruction 2. Value read 2. Address read

from (Z+q 2. Value read

Trace

ICE50 User Guide 7-7

2523A–AVR–11/02

LDS Rd, k(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of address-part of

instruction 2. Value read 2. Address read

from (k) 2. Value read

ST X, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (X) 2. Value written

ST X+, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Address written

to (X) 2. Value written

ST - X, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1 . N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (X) 2. Value written

ST Y, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Y) 2. Value written

ST Y+, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Y) 2. Value written

ST - Y, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Y) 2. Value written

STD Y+q,Rr 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Y+q) 2. Value written

ST Z, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Z) 2. Value written

ST Z+, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Z) 2. Value written

ST -Z, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Z) 2. Value written

STD Z+q,Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. N/A 2. Address written

to (Z+q) 2. Value written

STS k, Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of address-part of

instruction 2. N/A 2. Address written

to (k) 2. Value written

Table 7-2. Data Transfer Instructions (Continued)

Instruction

INSTA[0..15] PMem Addr [PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

7-8 ICE50 User Guide

2523A–AVR–11/02

Note: 1. Internal Memory

LPM

1. Address of instruction 1. NA 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

LPM Rd, Z

1. Address of instruction 1. N/A 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

LPM Rd, Z+

1. Address of instruction 1. N/A 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

ELPM

1. Address of instruction 1. NA 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

ELPM Rd, Z

1. Address of instruction 1. NA 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

ELPM Rd, Z+

1. Address of instruction 1. NA 1. N/A 1. N/A

N/A 2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. W or d addres s of da ta rea d 3. Data read 3. N/A 3. N/A

SPM

1. Address of instruction 1. N/A 1. N/A 1. N/A

N/A

2. Address of next instruction 2. N/A 2. N/A 2. N/A

3. Word address of data

write 3. Data write 3. N/A 3. N/A

IN Rd, P Address of instruction Value read from port 6 LSB give I/O

address (A) Value read from port N/A

OUT P, Rr Address of instruction Value written to port 6 LSB give I/O

address (A) Value written to port N/A

PUSH Rr(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Address of next instruction 2. Value pushed 2. Stack Pointer 2. Value pushed

POP Rd(1) 1. Address of instruction 1. N/A 1. N/A 1. N/A N/A

2. Ad dress of next instruction 2. Value popped 2. Stack Pointer 2. Value popped

Table 7-2. Data Transfer Instructions (Continued)

Instruction

INSTA[0..15] PMem Addr [PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

ICE50 User Guide 7-9

2523A–AVR–11/02

Table 7-3. Branch Instructions

Instruction

INSTA

[0..15] PMem Add r

[PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

RJMP 1. Address of instruction

2. N/A 1. N/A

2. N/A N/A

IJMP 1. Addres s of instruction

2. N/A 1. N/A

2. Destination address 1. N/A

2. N/A N/A

JMP

1. Address o f ins truction

2. Address of address-part

of instruct ion

3. N/A

1. N/A

2. N/A

3. N/A

1. N/A

2. N/A

3. N/A

1. N/A

2. N/A

3. N/A

N/A

RCALL(1)

1. Address o f ins truction

2. N/A

3. Address of RCALL

destination

1. N/A

2. N/A

3. N/A

1. N/A

2. Stack Pointer

3. Stack Pointer

1. N/A

2. Return address, low byte

3. Return address, high byte

N/A

ICALL(1)

1. Address o f ins truction

2. N/A

3. Address of ICALL

destination

1. N/A

2. N/A

3. N/A

1. N/A

2. Stack Pointer

3. Stack Pointer

1. N/A

2. Return address, low byte

3. Return address, high byte

N/A

CALL(1)

1. Address o f ins truction

2. Address of address-part

of instruct ion

3. N/A

4. Address of CALL

destination

1. N/A

2. N/A

3. N/A

4. N/A

1. N/A

2. N/A

3. Stack Pointer

4. Stack Pointer

1. N/A

2. N/A

3. Return address, low byte

4. Return address, high byte

N/A

RET(1)

1. Address o f ins truction

2. N/A

3. N/A

4. N/A

1. N/A

2. N/A

3. N/A

4. N/A

1. N/A

2. Stack Pointer

3. Stack Pointer

4. N/A

1. N/A

2. Return address, high byte

3. Return address, low byte

4. N/A

N/A

RETI(1)

1. Address o f ins truction

2. N/A

3. N/A

4. N/A

1. N/A

2. N/A

3. N/A

4. N/A

1. N/A

2. Stack Pointer

3. Stack Pointer

4. N/A

1. N/A

2.Return addr ess, high byte

3. Return address, low byte

4. N/A

N/A

CPSE

1. Address o f ins truction(2) 1. N/A(2) 1. N/A(2) 1. N/A(2) N/Aä

1. Address o f ins truction(3)

2. Address of skipped

instruction(3)

1. N/A(3)

2. N/A(3) 1. N/A(3)

2. N/A(3)

1. Address o f ins truction(4)

2. Address of skipped

instruction, first word(4)

3. Address of skipped

instruction, sec o nd wo rd(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

CP Address of instruction N/A N/A N/A N/A

CPC Address of instruction N/A N/A N/A N/A

CPI Address of instruction N/A N/A N/A N/A

Trace

7-10 ICE50 User Guide

2523A–AVR–11/02

SBRC

1. Address o f ins truction(2) 1. N/A(2) 1. N/A(2) 1. N/A(2) N/A

1. Address o f ins truction(3)

2. Address of skipped

instruction(3)

1. N/A(3)

2. N/A(3) 1. N/A(3)

2. N/A(3)

1. Address o f ins truction(4)

2. Address of skipped

instruction, first word(4)

3. Address of skipped

instruction, sec o nd wo rd(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

SBRS

1. Address o f ins truction(2) 1. N/A(2) 1. N/A(2) 1. N/A(2) N/A

1. Address o f ins truction(3)

2. Address of skipped

instruction(3)

1. N/A(3)

2. N/A(3) 1. N/A(3)

2. N/A(3)

1. Address o f ins truction(4)

2. Address of skipped

instruction, first word(4)

3. Address of skipped

instruction, sec o nd wo rd(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

SBIC

1. Address o f ins truction(2) 1. N/A(2) 1. 5 LSB give I/O address (A)(2) 1. N/A(2) N/A

1. Address o f ins truction(3)

2. Address of skipped

instruction(3)

1. N/A(3)

2. N/A(3) 1. 5 LSB give I/O address (A)(3)

2. N/A(3) 1. N/A(3)

2. N/A(3)

1. Address o f ins truction(4)

2. Address of skipped

instruction, first word(4)

3. Address of skipped

instruction, sec o nd wo rd(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. 5 LSB give I/O address (A)(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

SBIS

1. Address o f ins truction(2) 1. N/A(2) 1. 5 LSB give I/O address (A)(2) 1. N/A (2) N/A

1. Address o f ins truction(3)

2. Address of skipped

instruction(3)

1. N/A(3)

2. N/A(3) 1. 5 LSB give I/O address (A)(3)

2. N/A(3) 1. N/A(3)

2. N/A(3)

1. Address o f ins truction(4)

2. Address of skipped

instruction, first word(4)

3. Address of skipped

instruction, sec o nd wo rd(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

1. 5 LSB give I/O address (A)(4)

2. N/A(4)

3. N/A(4)

1. N/A(4)

2. N/A(4)

3. N/A(4)

BRBS 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRBC 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BREQ 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

Table 7-3. Branch Instructions (Continued)

Instruction

INSTA

[0..15] PMem Add r

[PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

ICE50 User Guide 7-11

2523A–AVR–11/02

BRNE 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRCS 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRCC 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRSH 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRLO 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRMI 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRPL 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRGE 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRLT 1. Address of inst ruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRHS 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRHC 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRTS 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRTC 1. Addres s of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

Table 7-3. Branch Instructions (Continued)

Instruction

INSTA

[0..15] PMem Add r

[PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

7-12 ICE50 User Guide

2523A–AVR–11/02

Notes: 1. Stack in internal memory

2. Condition not met (no skip)

3. Condition met, skippin g 1 word instruction

4. Condition met, skippin g 2 word instruction

5. Branch taken

6. Branch not t aken

BRVS 1. Address of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRVC 1. Address of instruction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRIE 1. Address o f ins truction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

BRID 1. Address o f ins truction(6) 1. N/A(6) 1. N/A(6) 1. N/A(6) N/A

1. Address o f ins truction(5)

2. N/A(5) 1. N/A(5)

2. N/A(5)

Table 7-3. Branch Instructions (Continued)

Instruction

INSTA

[0..15] PMem Add r

[PC[A0..22]

Reg.Val

RegFileL

[0..7]

Dat.Addr

RAM_EEADDR

[0..22] Dat.Val Status

Trace

ICE50 User Guide 7-13

2523A–AVR–11/02

Table 7-4. Bit and Bit-test Instructions

Instruction

INSTA [0..15] PMem Addr [PC [A0..22] Reg.Val RegFileL

[0..7] Dat.Addr

RAM_EEADDR[0..22] Dat.Val Status Register

LSL Address of inst ruction Y/N N/A N/A Z,C,N,V

LSR Address of instru cti on Y/N N/A N/A Z,C,N,V

ROL Address of inst ruction Y/N N/A N/A Z,C,N,V

ROR Address of instruction Y/N N/A N/A Z,C,N,V

ASR Address of instruction Y/N N/A N/A Z,C,N,V

SWAP Address of instruction Y/N N/A N/A N/A

BSET Address of instr u ction N/ A N/A N/A Z,C,N,V,H

BCLR Address of inst ruction N/A N/A N/A Z,C,N,V,H

SBI 1. Address of instruction

2. Address of next instruction 1. N/A

2. N/A 1. Y/N

2. Y/N 1. Y/N

2. Y/N N/A

CBI 1. Address of instruction

2. Address of next instruction 1. N/A

2. N/A 1. Y/N

2. Y/N 1. Y/N

2. Y/N N/A

BST Address of instruction N/A N/A N/A T

BLD Add re ss of ins t ruction Y/N N/A N/A N/ A

SEC Address of instruction N/A N/A N/A C

CLC Address of instructi on N/A N/A N/A C

SEN Address of instruction N/A N/A N/A N

CLN Address of instructi on N/A N/A N/A N

SEZ Address of instruction N/A N/A N/A Z

CLZ Address of instructi on N/A N/A N/A Z

SEI Address of instruction N/A N/A N/A I

CLI Add re ss of ins tructi on N/A N/A N/A I

SES Address of instruction N/A N/A N/A S

CLS Add re ss of ins tructi on N/A N/A N/A S

SEV Address of instruction N/A N/A N/A V

CLV Address of instructi on N/A N/A N/A V

SET Address of instruction N/A N/A N/A T

CLT Addre ss of instruction N/A N/A N/A T

SEH Address of instruction N/A N/A N/A H

CLH Address of instructi on N/A N/A N/A H

Trace

7-14 ICE50 User Guide

2523A–AVR–11/02

7.4 Accessing

External Data

Memory (ICE50

Trace)

Instructions that are accessing data memory have different timing based on whether the

memory is internal or external. For external memory accesses, the timing is again

dependen t on the number of wait states. Th is document do es not describe t he exact

timings of these instructions, but they are fairly similar to those described above. A full

description of the timing of these instructions can be found in Contents of Trace Window

based on Instru ction. It applies to the following instruc tions: LD (various forms), L DD

(various forms), ST (vario us forms), STD (various forms), LDS, STS, RCALL, ICAL L,

CALL, RET, RETI, PUSH, POP.

7.5 Interrupt

Handling (ICE50

Trace)

Interrupts are asynchronous events to the regular program flow. There is no instruction

associate d with the start of the processo r handling an interru pt. However, once the pro-

cessor has stored the return address to the stack, it will start to execute code from the

interrupt vector address. An example is shown in below (Figure 7-7 shows the code

being executed), where an interrupt occurs during the execution of the instruction RJMP

-0x0001. The Interrupt Ac knowledg e (IA) flag is set to “1” as c an be seen in Fi gure 7- 8.

When this instruction is completed (two cycle instruction), it can be observed that the

program counter is written to the stack at addresses 0x2F before it starts executing from

the interrupt vector (in this case, interrupt vector 0x000013). After the (in this case very

simple) in terrupt program has completed, e xecution resumes.

Figure 7-7. Example Code

Table 7-5. MCU Control Instructions

Instruction INSTA

[0..15] PMem Ad dr [PC

[A0..22] Reg.Val RegFileL

[0..7] Dat.Addr

RAM_EEADDR [0..22] Dat.Val Status Regis ter

NOP Address of instruction N/A N/A N/A N/A

SLEEP Address of instruction N/A N/A N/A N/A

WDR Address of instruction N/A N/A N/A N/A

BREAK Address of instruction N/A N/A N/A N/A

Trace

ICE50 User Guide 7-15

2523A–AVR–11/02

Figure 7-8. Trace Window Output

7.6 Reset (ICE50

Trace) An External Reset, BOD (Brown-out Detection) or a Watchdog Reset while Trace is

enabled will be traced in the trace window.

7.7 Save Trace

Buffer to File

(ICE50)

The Trace Buffer can be dumpe d to a file. Thi s functi on is avail abl e from the me nu File-

>Save as. Note that the trace window must be the active wi ndow.

7.8 Sleep (ICE50

Trace) If Trace is enabled when the microcontroller enters sleep mode, sleep will be logged into

the Trace Buffer. This applies to all s leep modes. Note, however, that the Time Stamp

still coun ts while the microc ontroller is asle ep, and this can be used to measu re how

long the micro controller has been asleep whe n it is woken up. Th e trace buffer wi ll be

filled with sleep instructions fo r each cycle as long as the microcontroller is in sle ep

mode.

Trace

7-16 ICE50 User Guide

2523A–AVR–11/02

ICE50 User Guide 8-1

Rev. 2523A–AVR–11/0 2

Section 8

Troubleshooting

The troubleshooting guide gives advise if errors occurs.

8.1 Troubleshooting

Guide LEDs

– Red Power LED does not turn on. See P ower Supply Trouble

– Multi color LED turns Red (error led lights up). See Configuration error

– Green LED does not light up. Start AVR Studio and try to change part.

Power Supply Trouble

– Check th at power supply is conn ected

– Check for wrong polarity

– Check that the power source is not too weak

– Pow er Switch do esn't work

Configuration Error

– Not all modules have signed on. See ICE Status. Check if a module is

missing. A module not signed on will report a zero in the version field.

Communication Errors

– Check that the serial cable is connected.

– Check that the POD is properly connected. See Inserting POD into POD Bay

– Can't establish communication. Check if other equipment has control over the

COM port, IrDA etc.

– Cycle power and restart AVR Studio

– Do no use serial port I/O card or USB to serial adapter

– USB communication is not yet supported

Troubleshooting

8-2 ICE50 User Guide

2523A–AVR–11/02

Printed on recycled paper.

2523A–AVR–11/02 /0M

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