MO SEL VITELIC
1
V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 2 56 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (4 04)
PRELIMINARY
V58C2256(804/404/164)S Rev.1.2 April 2002
67758
DDR333B DDR266A DDR266B DDR200
Clock Cycle Time (tCK2) 7.5 ns 7.5ns 10 ns 10 ns
Clock Cycle Time (tCK2.5) 6 ns 7ns 7.5 ns 8 ns
System Frequency (fCK max) 166 MHz 143 MHz 133 MHz 125 MHz
Features
■High speed data transfer rates with syste m
frequency up to 166 MHz
■Data Mask for Write Control
■Four Banks controlled by BA0 & BA1
■Program mable CA S Lat ency : 2, 2.5
■Program ma ble Wrap Sequence: Seq uential
or Interleave
■Program ma ble Burst Length:
2, 4, 8 f or Sequent ial Type
2, 4, 8 for Interleave Type
■Automa tic and Controlled Precharge Comma nd
■Power Down Mode
■Auto Refresh and Self Refresh
■Refresh In te rva l : 8 1 92 cycle s/6 4 ms
■Availab le in 66-pin 400 mil TSOP
■SSTL-2 Com patible I/Os
■Double Data Rate (DDR)
■Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
■On-Chip DLL aligns DQ and DQs transitions with
CK transitions
■Differential clock inputs CK and CK
■Power Supply 2.5V ± 0.2V
■QFC options f or FET cont rol. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timi ng
DDR 266A Support s PC2100 module with 2-3-3 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 S upports PC1 600 module wi th 2-2 -2 tim ing
Description
The V58C2256(804/404/164)S is a four bank
DDR DRA M or gan ized as 4 banks x 8M bi t x 8 (804 ),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed dat a transf er rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chron izes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
D RAMs . A sequential and gaple ss data rate is pos-
sible depending on burst length, CAS latency and
spe ed grade of the device.
De vice Usa g e C h ar t
Operating
Temperature
Range
Package Outline CK Cycle Time (ns) Power Temperature
MarkJEDEC 66 TSOP I I -6 -7 -75 -8 Std. L
0°C to 70° C • • • • • • • Blank
2
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
66 Pi n Pl astic T SOP -I I
PIN CONFIG URATIO N
Top View
Pin N ames
CK , C K Di ffe ren tia l C lo ck Inpu t
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
DQS (UDQS, LDQS) Data Strobe (Bidirectional)
A0–A12 Address Inputs
BA0, BA1 Bank Select
DQ’s Data Input/Output
DM (UDM, LDM) Data Mas k
VDD Power (+2.5V)
VSS Ground
VDDQ Power for I/O’s (+2.5V)
VSSQ Ground for I/O’s
NC Not connected
VREF Reference Voltage for Inputs
QFC FET Control
1
2
3
4
5
6
9
10
11
12
13
14
7
8
15
16
17
18
19
20
21
22
66
65
64
63
62
61
58
57
56
55
54
53
60
59
52
51
50
49
48
47
46
45
23
24
25
44
43
42
26
27 41
40
28
29
30
31
32
33
39
38
37
36
35
34
VDD
NC
V
DDQ
NC
DQ0
V
SSQ
VDDQ
NC
DQ1
VSSQ
NC
NC
NC
NC
VDDQ
NC
NC
VDD
NC
WE
CAS
RAS
CS
NC
BA0
BA1
VSS
NC
VSSQ
NC
DQ3
VDDQ
VSSQ
NC
DQ2
VDDQ
NC
NC
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
V
DDQ
NC
DQ1
V
SSQ
VDDQ
NC
DQ3
VSSQ
NC
NC
NC
DQ2
VDDQ
NC
NC
VDD
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
DQ3
DQ4
VDDQ
LDQS
NC
VDD
Q
FC/NC
NC
WE
QFC/NC QFC/NC
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
A8
A7
A6
A5
A4
VSS
A11
A9
A8
A7
A6
A5
A4
VSS
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ5
VDDQ
VSSQ
NC
DQ4
VDDQ
NC
NC
NC
DQ5
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
DQ12
DQ11
VSSQ
UDQ
S
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
66 PIN TSOP (II)
(400mil x 875 mil)
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
8Mb x 16
16Mb x 8
32Mb x 4
MO SEL VITELIC
V58C2256(804/404/164)S
3
V58C2256(804/404/164)S Rev. 1.2 April 2002
Block Diagram
Row de coder
Memory array
Bank 0
8192 x 1024
x 8
Column decoder
Sense amplifier & I(O) bus
Row d ec oder
Memory array
Bank 1
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 3
Column decoder
Sense amplifier & I(O) bus
Input buffer Output buffer
DQ0-DQ3
Column address
counter Colum n ad dress
buffer Row address
buffer Refresh Counter
A0 - A12, BA0, BA1A0 - A9, A11, AP, BA0, BA1
Control logic & timing generator
CK
CKE
CS
RAS
CAS
WE
DM
Row Addresses
Column Addresses
DLL
Strobe
Gen. Da ta Str obe
CK, CK
CK
DQS
QFC
8192 x 1024
x 8 8192 x 102 4
x 8 8192 x 1024
x 8
64M x 4
V 58 C 2 256(80/40/16) 4 S X T XX
DDRSDRAM
CMOS 2.5V
256Mb, 4K Refresh
4 Banks
COMPONENT
REV LEVEL A=0.17u, B=0.14u
COMPONENT
PACKAGE, T = TSOP
SSTL
SPEED
6 (166MHZ@CL2.5)
MOSEL VITELIC
MANUFACTURED
7 (143MHZ@CL2.5))
75(133MHZ@CL2.5)
x8, x4, x16
8 (125MHZ@CL2.5)
4
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Block Diagram
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Column decoder
Sense amplifier & I(O) bus
Row de coder
Memory array
Bank 2
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 3
Column dec oder
Sense amplifier & I(O) bus
Input buffer Outpu t buf fer
DQ0-DQ7
Column address
counter Column address
buffer Row address
buffer Refresh Counter
A0 - A12, BA0, BA1A0 - A9, AP, BA0, BA1
Co ntrol logi c & ti mi ng generato r
CK
CKE
CS
RAS
CAS
WE
DM
Row Add resses
Column Addresses
DLL
Strobe
Gen. Data Strobe
CK, CK
CK
DQS
QFC
32M x 8
8192 x 512
x 16 bit 8192 x 512
x 16bit 8192 x 512
x 16bit
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MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Block Diagram
Row decoder
Memory array
Bank 0
8192 x 256
x32 bit
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Column decoder
Sense amplifier & I(O) bus
Row de coder
Memory array
Bank 2
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 3
Column decoder
Sense amplifier & I(O) bus
Input buffer Outpu t buf fer
DQ0-DQ15
Column address
counter Column address
buffer Row address
buffer Refresh Counter
A0 - A11, BA0, BA1A0 - A8, AP, BA0, BA1
Co ntrol logi c & ti mi ng generato r
CK
CKE
CS
RAS
CAS
WE
DM
Row Add resses
Column Addresses
DLL
Strobe
Gen. Data Strobe
CK, CK
CK
DQS
QFC
8192 x 256
x 32 bit 8192 x 256
x 32 bit 8192 x 256
x 32 bit
16M x 16
Capacitance*
TA = 0 to 70°C, VCC = 2.5V ± 0.2V, f = 1 Mhz
*Note: Capacit ance is sampled and not 100% tested.
A bsol u te M aximum R atings*
Operating temperature range........ ....... ...0 to 70 °C
Storage te mpe rature range .............. ..-55 to 150 °C
VDDS upp ly Voltage Relative to VSS.....- 1 V to +3.6V
VDDQ Supply Voltage Relative to VSS
......................................................-1V to +3.6V
VREF and Inputs Voltage Relati ve to VSS
......................................................-1V to +3.6V
I/O Pins Voltage Rela tive to VSS
..........................................-0.5V to VDDQ+0.5V
Power di ssi pation .. ........................................1.6 W
Data out current (short circuit)...................... 50 mA
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended peri ods may affect device reliability .
Inpu t Capacitanc e Symbol Min Max Unit
BA0, BA1, CKE, CS, RAS, (CAS,
A0-A 1 1, WE)CINI 23.0pF
Input Capacitance (CK, CK)C
IN2 23.0pF
Data & DQS I/O Capacitance COUT 45pF
Input Capacitance (DM) CIN3 45.0pF
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Signal Pi n D escript i o n
Pin Type Signal Polarity Function
CK
CK Input Pulse Positive
Edge The syste m cloc k input. All inputs except DQs and D Ms are sampled on the rising edge
of CK.
CKE Input Level Active High Activates the CK signal when high and deactivates the CK signal when low, thereby ini-
tiates eithe r the P ower Down mode, or the Self Refr esh mo de.
CS Input Pulse Active Low CS enab les the command dec oder when low and disables th e command decoder when
hig h. Wh en th e co mma nd deco der i s dis ab le d, new com man ds are i gn ore d b ut pre vio us
operations continue.
RAS, CAS
WE Input Pulse Ac tive Low W hen sampled at the positive rising edge o f the clock, CAS, RA S, an d WE de fine the
command to be exec uted by the SDRAM.
DQS Input/
Output Pu lse Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
A0 - A12 Input Level — During a Bank Ac tivate command cycle, A0-A12 defines the row address (RA0-RA1 2)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column addres s (CA0- CAn)
when sampled at the rising clock edge.C An depends on the SDR AM organization:
64M x 4 DDR CAn = CA9, A11
32M x 8 DDR CAn = CA9
16M x 16 DDR CAn = CA8
In addition to the column address, A10(=AP) is used to invoke autoprecha rge operat ion
at the end of th e burst read or write cycle. If A10 is high, auto precharge is selecte d and
BA0, BA1 defines the bank to be precharg ed. If A10 is low, autoprecharge is disabled.
Duri ng a P re cha rge co mman d c ycl e, A 1 0(=A P) is us ed in co nj un ctio n wi t h BA 0 a nd BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regar dles s of state of BA0 and B A1.
BA0,
BA1 Input Level — Selec ts which bank is to be active.
DQx Input/
Output Level — Data Input/Output pins operate in the s ame manner as on conventi onal DRAMs.
DM,
LDM,
UDM
Input Pulse Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blo c ks the write operation if is high for x 16 LDM
corresp onds to d ata on D Q0-DQ7, UDM corresponds to data on DQ 8-DQ15.
QFC Output Level Active Low FET Control: Output during every read and write access. Can be used to control isolation
switches on modules.
V DD , VSS Su pp ly Po wer an d gr o un d for the inp ut buffe r s and the core log ic .
VDDQ
VSSQ Supply — — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VRE F In pu t Lev el — S STL Ref e renc e Vol t ag e for Inpu ts
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MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Mode Regis t er Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It pr ograms
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a vari ety of different applications. The default value of the mode regist er i s not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, W E and BA0 ( The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A 12 in the same cycle as CS, RAS, CA S, WE and B A0 low is writt en in the mode reg ister. Two cl ock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionalit y. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mos el Vitelic specific test
mode during production test. A8 is used for DLL reset. A7 mus t be set to low for normal MRS operation. Refer
to the table for specific cod es for various burst length, addressing modes and CAS lat e nc ie s .
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
Address Bus
CAS Latency
A
6
A
5
A
4
Latency
0 0 0 Reserve
0 0 1 Reserve
01 0 2
01 1 3
1 0 0 Reserve
Reserve
10 1
1 1 0 2.5
1 1 1 Reserve
Burst Length
A
2
A
1
A
0
Latency
Sequential Interleave
0 0 0 Reserve Reserve
001 2 2
010 4 4
011 8 8
1 0 0 Reserve Reserve
1 0 1 Reserve Reserve
1 1 0 Reserve Reserve
1 1 1 Reserve Reserve
A
7
mode
0Normal
1Test
A
3
Burst Type
0 Sequential
1 Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A
8
DLL Reset
0No
1 Yes
Mode Register Set
0RFU : Must be set "0"
Extended Mode Register
Mode Register
DLLI/OQFC
A
0
DLL Enable
0 Enable
1 Disable
A
2
QFC Contro
l
0 Disable
1 Enable
A
1
I/O Strength
0 Full
1 Half
BA
0
A
n
~ A
0
0 (Existing)MRS Cycle
1 Extended Funtions(EMRS)
Command
201 534 867
CK, CK
tCK
t
MRD
Precharge
All Banks Mode
Register Set
tRP
*2
*1 Any
Command
BA
1
BA
0
A
3
A
2
A
1
A
0
0TM
CAS Latency BT Burst LengthRFU DLL
MRS
MRS
A
12
to
8
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Mode Register Set Timing
Burst Mode Operation
Burst Mode Operation is used to pr ovide a const ant fl ow of data to memory l ocatio ns (Write cycle ), or fr om
memory locations ( Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable a nd are determined by a ddress bits A0—A3 during the
Mode Register Set command. Burst t ype d efines the sequence in which the burst data will be delive re d or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write c ommand. The burst length c an be program med to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.
Burst Length and Sequence
Burst Lengt h Starting Length (A2, A1, A0) Se quential Mode Inter leave Mode
2xx0 0, 1 0, 1
xx1 1, 0 1, 0
4
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
x11 3, 0, 1, 2 3, 2, 1, 0
8
000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
T5T0 T1 T2 T3 T4 T6 T7 T8
t
RP
t
MRD
t
CK
Pre- All MRS/EMRS ANY
M
ode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.
CK, CK
Command
I
f a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command
T9
t
o allow time for the DLL to lock onto the clock.
9
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Bank Activ ate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR S DRAM has four ind epende nt banks, so t wo Bank Select addresses (BA0 and
BA1) are supported. The Bank Activate comm and must be applied before any Read or Write operation can
be exe cuted. The delay f rom the B ank Activat e comm and to t he first Read or Write com ma nd mu st m eet or
exceed the minimum RAS to CAS delay time (tRCD min). On ce a bank has been a ctivated, i t must b e pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank t o Bank delay
time (tRRD min ) .
Bank Activat ion Timing
Re ad Operati o n
With the DLL enabled, al l devices operating at the sa me frequ ency within a s ys tem are e nsured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-
cess variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and da ta strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input di fferent ial clock (CK , CK) by the on-chip DLL. Therefore, when the DLL is enab led and the clock fre-
quency is within the specified range for proper DLL operation, t he data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally al igned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de-
layed and us ed to latch the output data into the receiving device. The to lerance for skew between DQS and
DQ (tDQSQ) is t ighter than that possible for CK to DQ (tAC) o r DQS to CK (tDQSCK).
T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5
(CAS Latency = 2; Burst Length = Any)
t
RRD
(min)t
RP
(min)
t
RC
t
RCD
(min)
Begin Precharge Bank A
CK, CK
B
A/Address
Command
Bank/Col
Read/A
Bank/Row
Activate/A Activate/B
Pre/A
Bank/Row
Activate/A
Bank Bank/Row
t
RAS
(min)
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Output Data (DQ) and Data St robe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
The minimum time during which the output data ( DQ) is valid is critical for t he receiving device (i.e., a mem-
ory con troller device). T his al so appl ies t o t he data strobe durin g t he read c ycle since it is tightly c ou pled to
the output data. The minimum data output valid time (tDV) and minimum data s trobe valid time (tDQSV) are de-
rived from the minimum clock high/l ow time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
(CAS Latency = 2.5; Burst Length = 4
)
T0 T1 T2 T3 T4
NOP NOPNOP
D0
CK, CK
C
ommand
DQS
DQ D2
tDQSCK(max)
tDQSCK(min)
D1
tAC(min) tAC(max)
D3
READ NOP
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MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Output Data and Data Strobe Va lid Window for DDR Read Cycles
Re ad Pream b l e an d Po sta mb l e Oper ation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe “read pr eam-
ble” (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of
valid dat a.
Once the burst of read data i s concluded and given that no subsequent burst read operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “read postamble” (tRPST). This transition happens nominally one-half clock period after the last edge of
valid dat a.
Consecutive or “gap less” burst read operatio ns are possible from the same DDR SDRAM device with no
requirem ent for a data strobe “read” preamble o r postamble in be tween the groups of burst data. T he data
strobe read pre amble is required before the DDR device drives the first output data off chip. Similarly, the
data str obe postam ble is i ni tiat ed when the d ev ice s tops dr ivi ng DQ data at the ter minat ion of rea d bur st c ycle s.
D0D1
(CAS Latency = 2; Burst Length = 2)
T0 T1 T2 T3 T4
READ NOP NOPNOP
C
ommand
DQS
DQ
tDV(min)
CK, CK
tDQSV(min)
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Data Strobe P reamble and Pos tamble Timings f or DDR Read Cycles
Consecutive Bur st Read Operation and Effect s on the Data Strobe Preamble and Posta mble
(CAS Latency = 2; Burst Length = 2)
T0 T1 T2 T3 T4
READ NOP NOPNOP
D0D1
CK, CK
C
ommand
DQS
DQ
tRPRE(max)
tRPST(min)
tRPRE(min)
tRPST(max)
tDQSQ(max)
tDQSQ(min)
NOP Read
B
NOP NOP NOP NOPRead
A
D0
A
D1
A
NOP
D2
A
D3
A
Command
DQS
DQ
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
D0
B
D1
B
D2
B
D3
B
NOP Read
B
NOP NOP NOP NOPRead
A
D0
A
D1
A
NOP
D2
A
D3
A
Command
DQS
DQ
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
NOP
D0
B
D1
B
D2
B
D3
B
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V58C2256(804/404/164)S Rev. 1.2 April 2002
Auto P r ech arg e Op erati o n
The Auto Precharge operation can be issued by having column address A 10 high when a Read or Write
command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst
operati on is execut ed and t he b ank rema ins active at the com pletion of the burst sequence. When the Au to
Precharge c om m and is act ivated, the ac tive bank autom at ically beg ins to p recharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with A uto P recharge comm and is i nitiated, the DDR SDRAM wi ll enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length =
4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
Begin Autoprecharge
BAACT R w/AP NOPNOP NOP NOP NOP NOP
CK, CK
C
ommand
DQS
DQ
tRAS(min) tP(min)
Earliest Bank A reactivate
T9
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V58C2256(804/404/164)S
Read w ith Autoprecharge Timing as a Func tion of CAS Lat ency
T0 T1 T2 T3 T4 T5 T6 T7 T8
NOPRAP NOPNOP NOP NOP BA NOP
CK, CK
C
ommand
DQS
DQ
t
RAS
(min)
t
RP
(min)
BA NOP
T9
D
0
D
1
D
2
D
3
DQS
DQ
CAS Latency=2
CAS Latency=2.5
(CAS Latency = 2, 2.5, Burst Length = 4)
D
0
D
1
D
2
D
3
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V58C2256(804/404/164)S Rev. 1.2 April 2002
Prec harg e Tim ing During Re ad Operati on
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be iss ued on the rising clock edge which is CAS late ncy (CL) clock cycles before the e nd of the Read
burst. A ne w Bank Activate (BA) c ommand m ay be issued to the sam e bank after the RAS precharge time
(tRP). A Precharge command can not be issued until tRAS(m in ) is satisf ie d.
Read w ith Precharge Tim ing as a Function of CAS Latency
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
NOPRead NOPNOP PreANOP BA NOP
CK, CK
C
ommand
DQS
DQ
tRAS(min) tRP(min)
BA NOP
T9
D0D1D2D3
DQS
DQ
CAS Latency=2
CAS Latency=2.5
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
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V58C2256(804/404/164)S
Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high wi th CS and WE l ow at the rising e dge o f the c lock. When the Burs t Stop command is issue d durin g a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(LBST) equal to the CAS laten cy programmed into t he device. If the Burst Stop command is i ssued during a
burst Writ e cycle, the command will be treated as a NOP command.
Read Termina ted by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length =
4)
T0 T1 T2 T3 T4 T5 T6
BST NOP NOP NOP NOPRead
D
0
D
1
CK, CK
Command
DQS
DQ
D
0
D
1
DQS
DQ
C
AS Latency = 2
C
AS Latency = 2.5
L
BST
L
BST
L
BST
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Read Interrupted by a Precharge
A Burst Read oper ation can be interrupted by a precharge of the same bank. The Precharge command to
Outp ut Disable latency is equivalent to the CAS latency.
Read Interrupted by a P recharge Tim ing
Bur st Write Op eration
The Burst Write command is issued by having CS, C AS , and WE low while holdi ng RAS high at the rising
edge of the clock . T he address inputs determine t he starting column address . The memory controller is re-
quired to provide an i nput dat a strobe (DQ S) to the DDR S DRAM to strob e or latch the input data (DQ) and
data mask (DM) into the device. During Wri te cyc les, the data strobe applied to the DDR S DRAM is required
to be no minally cent ered wi thin the data (DQ) and data mask (DM) val id wind ows. The dat a strob e mu st be
driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min)
and tDQSS(max) define the allowable window when the data strobe must be driven high.
Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is
registered into the dev ice (WL=1). The input data valid window is nominally centered around the midpoint of
the data strob e signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold
time ( tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst
length is c ompleted. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
W rite Preamb le and Postam b le Operati on
Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe
signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe “write preamble”.
This t rans it ion f rom H i-Z to logic low no minally ha ppens on the f alling edge of th e c lock af ter the wr ite co m-
mand has been registered by the device. The preamble is explicitly defined by a set up time (tWPRES(min)) and
hold time (tWPREH(min)) referenced to the first falling edge of CK after the write com mand.
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
NOPRead NOPNOP PreANOP BA NOP
CK, CK
C
ommand
DQS
DQ
tRAS(min) tRP(min)
BA NOP
T9
D0D1D2D3
DQS
DQ
CAS Latency=2
CAS Latency=2.5
(CAS Latency = 2, 2.5, 3; Burst Length =
8)
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Burst Write Timing
Once the burst of write data is concluded and given that no subsequent bur st write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
(CAS Latency = Any; Burst Length =
4)
T0 T1 T2 T3 T4
WRITE NOP NOPNOP
D
0
D
1
D
2
D
3
CK, CK
C
ommand
D
QS(nom)
DQ(nom)
t
WPRES
t
WPREH
t
DQSS
t
WPST
t
QDQSH
D
0
D
1
D
2
D
3
DQS(min)
DQ(min)
t
DQSS
(min)
D
0
D
1
D
2
D
3
D
QS(max)
DQ(max)
t
WPRES
(min)
t
DQSS
(max)
t
QDQSS
t
QDQSS
t
QDQSH
t
WPREH
(min)
t
WPREH
(max)
t
WPRES
(max)
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V58C2256(804/404/164)S Rev. 1.2 April 2002
W rite Interru pted by a Precharg e
A Burst Write can be interrupted before completion of the burst b y a Precharge command, with the only
restricti on being that the interval that separat es the commands be at l east one clock cycle.
Write Interrupted by a Precharge Timing
Write with Auto Precharge
If A10 is high when a Write com m and i s issued, the Wri te with auto P rec harge function is performed. An y
new command to the same bank should not be issued until the internal precharge is completed. The internal
precha rge begins after keeping tWR (mi n. ) .
Write with Auto Precharge Tim ing
(CAS Latency = 2; Burst Length = 8
)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Write
A
NOP Pre
A
NOP NOP NOP NOP NOP NOP NOP NOP
CK, CK
C
ommand
DQS
T12
DM
D
0
D
1
D
2
D
3
DQ
Data is masked
by Precharge Command
Data is masked
by DM input DQS input ignored
D
4
D
5
t
WR
D
6
(CAS Latency = Any; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
NOPWAP NOPNOP NOP NOP NOP NOP BA
CK, CK
C
ommand
DQS
DQ
tRAS(min)
tRP(min)
BA NOP
T9 T10
tWR(min)
Begin Autoprecharge
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V58C2256(804/404/164)S
Pr echarge T i mi n g D u r ing W r i te Oper ation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write r ecover y require-
ment. This i s the time requi red by a DRAM sense am p t o fully store the voltage level. For DDR SDRA M s, a
timing pa rameter (tWR) is used to indicate the requ ired amount of time bet ween the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe
in the Prec harge command.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3
NOPWrite NOPNOP NOP NOP PreA
NOP
CK, CK
C
ommand
DQS
DQ
tRAS(min) tRP(min)
BA NOP
T9 T1
0
tWR
D0D1D2D3
DQS
DQ
tWR
BA
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V58C2256(804/404/164)S Rev. 1.2 April 2002
Data Mask Func tion
The DDR SDRAM has a Data Mask function that i s used in con juncti on with the W rite cycle, but not the
Read cycle. When th e Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issue d, the Data Mask must be referenced to both the rising and fal ling edges of Data Strobe.
Data Mask Tim ing
Burst Interruption
Read Interru pted by a Read
A Burst Read can be interrupted before c ompletion of the bu rs t by issuing a new Read command t o any
bank. When the previous burst is inter rupted, the remaining addresses are overri dden with a f ull burst l ength
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupt ing Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is ille gal to int err upt a Read with autoprec harge co m man d with a Read comm and .
Read Interrupted by a Read Command Timing
(CAS Latency = Any; Burst Length = 8)
T0 T1 T2 T3 T4 T5 T6 T7 T8
D0D1D2D3D4D5D6D7
NOP NOP NOPNOP NOP NOP NOPWrite
CK, CK
C
ommand
DQS
DQ
DM
T9
tDMDQSS tDMDQSS
tDMDQSH tDMDQSH
(CAS Latency = 2; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
ReadBNOP NOP NOP NOP NOP NOP
DA0 DA1 DB0 DB1
ReadA
DB2 DB3
CK, CK
C
ommand
DQS
DQ
T9
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Read Int errupted by a Write
To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst
read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once
the Burst Stop command has be en issued, a W rite command can not be issued until a minimum delay or
latency (LBST) has b een sat isfied. This latency is m easured f rom the Burst S top c ommand and i s equivale nt
to the CAS latency programmed into the mode register. In instances where CAS latenc y is measured in half
clock cycles, the minimum delay (LBST) is roun ded up to the ne xt full clock cycle (i.e., if CL=2 then LBST=2, if
CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprec harge c om man d with a Write comm and.
Read Interrupted by Burst Stop Command Followe d by a Write Com mand Timing
W rite Interrupted by a Write
A Burst Write can be interrupted before com pletion by a new Write co mmand t o any bank . When the pre-
vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new
address. The data from the first Write command continues to be input into the device until the Write Latency
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-
mand is input into the device. Writ e com ma nds can be issued on each rising edge of the s ystem clock . It i s
illegal to interrupt a Write wi th autoprecharge comma nd with a Write command.
Write Interrupted by a Write Command Tim ing
(CAS Latency = 2; Burst Length = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
BST NOP Write NOP NOP NOP NOP
D0D1
Read
D0D1D2D3
CK, CK
C
ommand
DQS
DQ
T9
LBST
(CAS Latency = Any; Burst Length =
4)
T0 T1 T2 T3 T4 T5 T6 T7 T8
Write
A
NOP NOPWrite
B
NOP NOP NOP NOP
DA0 DA1 DB0 DB1 DB2 DB3
CK, CK
C
ommand
DQS
DQ
DM
T9
Write Latency
DM0 DM1 DM0 DM1 DM2 DM3
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V58C2256(804/404/164)S Rev. 1.2 April 2002
W rite Interrupted by a Read
A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted
prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must
be ma sked off with the dat a m ask (DM) input pin to p revent invalid d ata from being written into the m emo ry
array. Any data that is present on the DQ pins coincident with or foll owing t he Read command will be masked
off by the Read command and will not be written to the array. The memory controller must give up control of
both the D Q bus and t he DQS bus at least one clock cycle before the read dat a appears on the ou tputs in
order to avoid contention. In order to avoid data contention within the device, a delay is required (tCDLR) from
the last valid data input befo re a Read comm and can be iss ued to the device. It is illegal to interrupt a Write
with autoprecharge com ma nd with a Read comman d.
Write Interrupted by a Re ad Command Timing
Auto Refresh
The Aut o Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the
rising edge of the clock. All bank s must be prec harged and idle for a tRP(min) before the Aut o Refres h com-
mand is applied. No control of the address pins is required once this cycle has started because of the internal
address counter. When the Auto Refr esh cycle has completed, all banks will be in t he idle state. A delay be-
tween the Aut o Refresh com mand and the nex t Activa te command or sub sequent Aut o Refresh command
must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Au to
Refresh cycle has begun. CS input m us t rem ain h igh d uring the refresh period or NOP commands m ust be
registered on each rising edge of the CK input until the re fresh period is satisfied.
Auto Refresh Timing
(CAS Latency = 2; Burst Length = 8
)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
Write NOP ReadNOP NOP NOP NOP NOP NOP NOP NOP
CK, CK
C
ommand
DQS
T12
DM
D
2
D
3
D
4
D
5
D
0
D
2
D
3
D
4
D
5
D
6
D
1
D
7
DQ
Data is masked
by Read command
Data is masked
by DM input DQS input ignored
D
0
D
1
t
WTR
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
NOP NOP NOP
CK, CK
C
ommand
CKE
T11
Auto Ref ANY
High
Pre All
tRFC
tRP
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V58C2256(804/404/164)S
Self Refresh
A self refresh command is def ined by having CS, RAS, CA S and CKE held low with WE high at the rising
edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device
in self refresh mode. During the self ref res h operation, all inputs except CKE are ignored. The clock is inter-
nally disab led d uring sel f refres h ope ration t o reduce power consum pti on. The s elf refresh is exit ed by sup-
plying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting
CKE high for longer than tSREX for lock ing of DLL. The auto refresh is required before s elf refresh entry and
after self refresh exit.
Power Down Mode
The power down mode is entered when CK E is low and exited when CKE is high. Once the power down
mode is initiated, all of the receiver circuits e xcep t clock, CKE and DLL circuit are g ated off to reduce power
consum ption. All banks should be in idle st ate prior to entering the prec harge power d own mode and CK E
shou ld be set high a t least 1tck+tIS p rior to row ac tive c omm and. During power down mode, refr esh opera-
tions cannot be performed, therefore the device cannot remain in power down mode longer than the refresh
period (tREF) of the device.
Command
CKE
Stable Clock
tSREX
Auto
Refresh
NOP
Self
Refresh • •
• •
• •
• •
• •
• •
CK, CK • •
CKE
Precharge Active ReadNOP
Active
power downpower down Exit
Active
Entry
power
Exit
down
power
Entry
down
Precharge
• •
• •
• •
• •
• •
• •
precharge
Command
CK, CK
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V58C2256(804/404/164)S Rev. 1.2 April 2002
QFC function
QFC function
when driven low on reads coincident with the start of preamble, this DRAM out put signal says that one cy-
cle later there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is
also driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever t he dev ice is in s tandby, t he signal is HI-Z. D QS is intended to e nable an
external data switch. QFC can be enable d or disabled through EMRS control.
QFC timing on Read opera tion
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end
of DQS pos tamble
Figu re 26. QFC timing on read operation
C
ommand
201 534 867
Read
Dout 0 Dout 1
Hi-Z
DQS
DQ’S
QFC
t
QPRE
t
QPST
CL = 2, BL =
2
CK
CK
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QFC timing on Write operation
QFC on writes is enabled as soon as possible after the clock edge of write command and dis abled as soon
as possible after the last DQS-in low goi ng edge.
Figure 2 7. : QFC timing on write operation with tDQSS max
Figure 28. : QFC timing on write operation with tDQSSmin
1. The value of tQCK min. is 1. 25n s from the last low going data strobe edge to QFC HI-Z.
2. The value of tQCK max. is 0.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC HI- Z.
201 534 867
Hi-Z
DQS@tDQSSmax
QFC tQCK *1tQOHmin.
Dout0 Dout1
BL=2
Write
DQ’S@tDQSSmax
Command
CK
CK
*2tQOHmax.
DQS@tDQSSmin
DQ’S@tDQSSmin
201 534 867
Hi-Z
QFC tQCK *1tQOHmin.
Dout0 Dout1
BL=2
Write
Command
CK
CK
*2tQOHmax.
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V58C2256(804/404/164)S Rev. 1.2 April 2002
TRUTH TABLE 2 – CKE
(Notes: 1-4)
NOTE:
1. CKEn is t he logic state of CKE at clock edg e n; CKEn-1 was t he state of CKE at t he previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the comm and registered at clock edge n, and ACTIONn i s a result of COMMANDn.
4. All st ates and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period.
A minimum of 200 cl ock cy cles is needed before applying a read command, for the DLL to loc k.
CKEn-1 CKEn CURREN T STATE COMMANDn ACTIONn NOTES
LL
Power-Down X Maint ain Power-Down
Self Refresh X Maintain Self Refresh
LH
Power-Down DESELECT or NOP Exit Power-Down
Self Refresh DESELECT or NOP Exit Self Refresh 5
HL
All Banks Idle DESELECT or NOP Precharge Power-Down Entry
Bank(s) Active DESELECT or NOP Active Power-Down Entry
All Banks Idle AUTO REFRESH Self Refr es h Entry
H H See Tru th Table 3
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TRUTH TABLE 3 – Current State Ba nk n - Command to Ba nk n
(N otes: 1-6; notes appear below and on next page)
NOTE:
1. This table appli es when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR
ha s been me t (if the previous stat e wa s self refresh).
2. Thi s tabl e is bank -sp ecific, exc ept wher e noted, i.e. , the c urrent stat e is fo r a s pecif ic bank a nd the com mand s shown
are those allowed to be i ssued t o that bank when in that st ate. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been prec harged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled,
and has not yet t erminated or been terminated.
Write: A WRITE burst has been initiated, wi th AUTO PRECHARGE disabl ed,
and has not yet t erminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP com-
mands,
or allowable comman ds to the other bank should be issued on any clock edge occurring during these states.
All owable commands to the other bank are determined by it s current state an d Trut h T able 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. Once tRP is me t, the ba n k will be in the id le sta t e.
CURRENT STATE /CS /RAS /CAS /WE COMMAND/ACTION NOTES
Any H X X X DESEL ECT (NO P/c onti nu e previou s opera tion )
L H H H NO OPER ATION (NOP/c ontinue previous operation)
Idle
L L H H ACTIVE (select and activate row)
LLLHAUTO REFRESH 7
L L L L MODE REGISTER SET 7
Row Activ e L H L H READ (select column and start READ burst) 10
L H L L WRITE (select column and start WRITE burst) 10
L L H L PRECHARGE (deactivate row in bank or banks) 8
Read (Auto Prec harge
Disabled)
L H L H READ (select column and start new RE AD burst) 10
L L H L PRECHARGE (truncate READ burs t, start PRECHARGE) 8
L H H L BURST TERMINATE 9
Write (Auto Precharge
Disabled)
L H L H READ (select column and start READ burst) 10, 11
L H L L WRITE (select column and start new WRITE burst) 10
L L H L PRE CH AR GE (tr unc at e WRI TE bu rs t, st ar t PRE CH ARGE ) 8, 11
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V58C2256(804/404/164)S Rev. 1.2 April 2002
NOTE: (continued)
Row Activa ti ng: Starts with registration of an ACTIVE com mand and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row acti ve” stat e.
Read w/Auto-P rec harge Enabled: Starts with registration of a READ command with AUTO PRECHARGE
enabled and ends wh en tRP has been met. Once tRP is met, the ban k w ill
be in the idle state.
Writ e w/Auto-Precharge Enabled: Starts with regi stration of a WRITE command wi th AUTO PRECHARGE
enabled and ends wh en tRP has been met. Once tRP is met, the ban k w ill
be in the idle state.
5. The foll owing states must not be interrupt ed by any executabl e com mand; DESELECT or NOP commands must be
applied on each positive clock edge during these st ates.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRC is met. Once tRFC is met, the DDR SDRAM will be in the “all banks
idle” state.
Accessing Mo de Register: Starts with registrati on of a MODE REGISTER SET command and ends
when tMRD has been met. Once tMTC is m et, the DDR SDRAM will be in
the “all banks idle” state.
Precharging Al l: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. Once tRP is met, al l banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. May or may not be bank-specific; if multiple banks ar e to b e prec harged, each must be in a val id stat e for prechar ging.
9. Not bank-specific; BURST TERMI NATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs l ist ed in the Comm and/Action col um n include READs or WRITEs wit h AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
11. Requires appropriate DM m asking.
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V58C2256(804/404/164)S
TRUTH TABLE 4 – Current State Ba nk n - Command to Ba nk m
(N otes: 1-6; notes appear below and on next page)
NOTE:
1. Thi s table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and aft er tXSR has been me t
(if the previous state was self refresh).
2. This table descri bes alternate bank operation, except where note d, i .e. , the current state is for bank n and the
com ma nds shown are those al lowed to be issued to bank m (assu ming that bank m is in such a stat e that the given
com ma nd is all owable). Excep ti ons ar e covered in the notes below.
3. Curr ent s tate definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activat ed, and tRCD has been met. No data
bursts/acces ses and no registe r accesses are in progress.
Read: A READ burst has been initiated, wi th AUTO PRECHARGE disabl ed, and
has not yet terminated or been term inated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and
has not yet terminated or been term inated.
CURRENT STATE /CS /RAS /CAS /WE COMM AND/ACTION NOTES
Any H X X X DESELECT (NOP/continue previ ous op eration)
L H H H NO OPER ATION (N O P/ c on ti nu e pr e vi ou s op er a ti on)
Idle X X X X An y Comm an d Otherw ise Allowed to Bank m
Row Act ivating,
Active, or Prec h arg ing
L L H H ACTIV E (select and activate row)
L H L H READ (select column and start READ burst) 7
L H L L WR ITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read
(Auto-Precharge
Disabled)
L L H H ACTIV E (select and activate row)
L H L H READ (select column and start new READ burst) 7
L L H L PRECHARGE
Write
(Aut o- Pr ec h arge
Disabled)
L L H H ACTIV E (select and activate row)
L H L H READ (select column and start READ burst) 7, 8
L H L L WRI TE ( se le ct col um n and sta rt ne w WRITE burst ) 7
L L H L PRECHARGE
Read
(With Auto-P recha rge)
L L H H ACTIV E (select and activate row)
L H L H READ (select column and start new READ burst) 3a, 7
L H L L WR ITE (select column and start WRITE burst) 3a, 7, 9
L L H L PRECHARGE
Write
(With Auto-P recha rge)
L L H H ACTIV E (select and activate row)
L H L H READ (select column and start READ burst) 3a, 7
L H L L WRI TE ( se le ct col um n and sta rt ne w WRITE burst ) 3a, 7
L L H L PRECHARGE
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V58C2256(804/404/164)S Rev. 1.2 April 2002
NOTE: (continued)
Read with Auto Precharge Enabl ed: See followi ng text
Write with Auto Precharge Enabl ed: See following text
3a. The Read wi th Auto Precharge Enabled or Write with Auto Prec harge Enabled states can each be broken
into two parts: the access period and the precharge period. For Read with Auto Precharge, t he precharge
period is def ined as if the same burst wa s executed with Auto Prec harge disabled and then followed with the
earliest possib le PRECHARGE command that still accesses all of the dat a in t he burst. F or Write with Auto
Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Pr echarge was
disabl ed. The access period starts with regi stration of t he com m and and ends where the precharge period
(or tRP) begins.
During the precharge period of the Read with Auto Pr echarge Enabled or Write with Auto Precharge Enabled
states, ACTIVE, PRECHARGE, READ and WRITE com m ands to the ot her ba nk ma y be appl ied; during the
access per iod, only ACTIVE and PRECHARGE commands t o the other bank may be appli ed. In either case, al l
other related limitations apply (e.g. contention between READ data and WRITE data must be avoided).
4. AUTO REFRESH and MODE REGISTER SET commands ma y only b e issued when all banks are idl e.
5. A BURST TERMINATE comman d cannot be issued to another bank; it appli es to t he bank represent ed by the
current st ate only.
6. All states and sequences not shown are il legal or reserved.
7. READs or WRITEs listed in the Command/Action column inclu de READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
8. Requires appropri ate DM masking.
9. A WRITE command may be applied after the completion of data output.
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V58C2256(804/404/164)S
Simpl ified State Diagram
PREAL L = Precharge All Banks CKEL = Enter Power Down
MRS = Mode Register Set CKEH = Exit Power Down
EMRS = Extende d Mode Regi ster Set ACT = Active
REFS = Enter Self Refresh Write A = Write with Autoprec harge
REFSX = Exit Self Refresh Read A = Read with Autoprecharge
REFA = Auto Refresh PRE = Prech arge
Self
Auto
Idle
MRS
EMRS
Row
Precharge
Write
Write
Write
Read
Read
Power
ACT
Read A
Read
REFS
REFSX
REFA
CKEL
MRS
CKEH
CKEH
CKEL
Write
Power
Applied
Automatic Sequence
Command Sequence
Read A
Write A
Read
PRE PRE
PRE
PRE
Refresh
Refresh
Active
Active
Power
Down Precharge
Power
Down
On
A
Read
A
Read
A
Write A
Burst Stop
PREALL
Precharge
PREALL
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V58C2256(804/404/164)S Rev. 1.2 April 2002
DC Operating Conditions & Specifications
DC Operating Co nditions
Recommended operating c onditions(Voltage refe renced to VSS=0V, TA=0 to 7 0°C)
Notes: 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-
t o-p eak no is e on VREF may not exceed 2% of the DC value
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must tra ck variations in the DC level of V REF
3. VID is the magnitude of the difference betwee n the input level on CK and the input level on CK.
Table 11. DC operating condition
Parameter Symbol Min Max Unit Note
Supply voltage (for device with a nominal VDD of 2.5V) VDD 2.3 2.7
I/O Supply voltage VDDQ 2.3 2.7 V
I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1
I/O Termi nation voltage(system) VTT VREF-0.04 VREF+0.04 V 2
Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V
Input logic low voltage VIL(DC) -0.3 VREF-0.15 V
Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V
Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3
I np ut le akag e cu r ren t I I-2 2 uA
Output leakage current IOZ -5 5 uA
Output High Current (VOUT = 1.95V) IOH -16.8 mA
Output Low Current (VOUT = 0.35V) IOL 16.8 mA
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V58C2256(804/404/164)S
IDD Specifications and Conditions
(0°C < TA < 70°C, VDDQ=25V+ 0. 2V, VDD =2.5 +0.2V)
Conditions Version
Symbol -6 -7 -7.5 -8 Unit
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200,
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B; DQ,DM and DQS inputs changing
twi ce per clock cycle; address and control inputs changin g once per clock cycle IDD0 110 100 100 90 mA
Operating current - One bank operation; One bank ope n, BL =4 I DD 1 140 120 1 20 1 00 m A
Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P 25 20 20 15 mA
Precharge Fl oating s tandby cur rent; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK=100Mhz fo r DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; Vin = Vref for DQ,DQS and DM IDD2F 40 35 35 35 mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK =
100Mhz fo r DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable
with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM IDD2Q 45 40 40 35 mA
Act ive po wer - dow n st an dby c urr e nt; one ba nk act i ve; po w er- dow n mo de ; CKE =< V IL ( ma x);
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166MHZ for DDR333B; Vin =
Vref for DQ,DQS and DM IDD3P 25 20 20 15 mA
Ac t iv e standby cur re n t; CS# >= VI H(min); CKE >=VIH( min); one bank acti ve; active - pre-
charge; tRC=tRASmax; t CK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166Mhz
for DDR333B; DQ, DQS a nd DM inputs c hanging twice per clock cycle; a ddress and other control
inputs changing once per clock cycle
IDD3N 80 70 70 60 mA
Operating current - burst read; Burst length = 2; rea ds; continguous burst; One bank active;
address and control inputs changing o nce per c lock c ycle; C L=2 at tCK = 100Mhz fo r DDR200,
CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B, CL=2.5 at
tCK=166Mhz for DDR333B; 50% of data changing at every burst; lout = 0 m A
IDD4R 230 190 190 150 mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active ad-
dress and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2
at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs
changing twice per clock cycle, 50% of input data changing at every burst
IDD4W 210 170 170 130 mA
Auto refresh current; tRC = tRF C(min ) - 8*tCK for DDR200 at 100Mh z, 10*tCK for DDR266A
& DDR266B at 133Mhz, 12*tCK for DDR333B; distributed refr esh IDD5 200 190 190 180 mA
Self refresh cu rrent; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR 200,
133Mhz for DDR266A & DDR266B, 166Mhz for DDR333B.
Self refresh cu rrent; (Low Power)
IDD6
(normal) 3333mA
(L) 1.8 1.8 1.8 1.8 mA
Operating current - Four bank operation; Four bank i nterl eaving with B L=4 IDD7 350 300 300 250 mA
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V58C2256(804/404/164)S Rev. 1.2 April 2002
AC Operating Conditions & Tim m ing Specific ation
AC Operating Co nditions
Note:
1.Vih( max) = 4.2V. The overshoot voltage duratio n is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK a nd the input o n CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIM ING for P C333/PC266/PC200 -Absolute
Specifications
(Notes: 1-5, 14-17) ( 0° C < T A < 70°C; VDDQ = +2.5 V ±0.2V, +2.5V ±0.2V)
Parameter/Condition Symbol Min Max Unit Note
Input H igh (Logic 1) V oltage, D Q , DQ S and D M signals VIH(AC) VREF + 0.35 V 1
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.35 V 2
Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 3
Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 4
AC CHARACTERISTICS -6 -7 -75 -8
PARAMETER SYM-
BOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Access window of DQs from CK/CK tAC -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
CK h igh-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30
CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30
Clo ck cycle time CL = 2.5 tCK (2.5) 6 12 7 12 7.5 12 8 12 ns 52
CL = 2 tCK (2) 7.5 12 7.5 12 10 12 10 12 ns 52
DQ and DM input hold time relative to
DQS tDH 0.45 0.5 0.5 0.6 ns 26,31
DQ and DM input setup time relative to
DQS tDS 0.45 0.5 0.5 0.6 ns 26,31
DQ and DM input pulse width (for each in -
put) tDIPW 1.5 1.75 1.75 2 ns 31
Access window of DQS from CK/CK tDQSCK -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS input high pulse w idth tDQSH 0.35 0.35 0.35 0.35 tCK
DQS input low pulse width tDQSL 0.35 0.35 0.35 0.35 tCK
DQS-DQ skew, DQS to last DQ valid,
per group, per access tDQSQ 0.45 0.5 0.5 0.6 ns 25,26
Write command to first DQS latching tran-
sition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 0.2 tCK
DQS falling edge from CK rising - hold
time tDSH 0.2 0.2 0.2 0.2 tCK
Half clock period tHP tCH,
tCL
tCH,
tCL
tCH,
tCL
tCH,
tCL ns 34
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V58C2256(804/404/164)S
Dat a-out high-impedance window from
CK/CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 18
Dat a-o ut l ow- impe da nce win do w fr o m CK /
CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 18
Ad d r es s an d co ntrol inpu t ho l d tim e
(fast slew rate) tIHF.75 .90 .90 1.1 ns 14
Address and control input setup time
(fast slew rate) tISF.75 .90 .90 1.1 ns 14
Ad d r es s an d co ntrol inpu t ho l d tim e
(slow slew rate) tIHS0.80 1 1 1.1 ns 14
Address and control input setup time
(slow slew rate) tISS0.80 1 1 1.1 ns 14
LOAD MODE RE GISTER comm and c ycle
time tMRD 2 2 2 2 tCK
DQ-DQS hold, DQS to first DQ to go non-
valid,
per access
tQH tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS ns 25, 26
Data hold skew factor tQHS 0.60 0.75 0.75 1 ns
ACTIVE to PRECHARGE command tRAS 42 120,00
045 120,00
045 120,00
050 120,00
0ns 35
ACTIVE to READ with Auto precharge
command tRAP tRAS(MIN) - (burst length * tCK/2) ns 46
ACTIVE to ACTIVE/AUTO REFRESH
command period tRC 60 65 65 70 ns
AUTO REFRESH comman d period tRFC 72 75 75 80 ns 50
ACTIVE to READ or WRITE delay tRCD 18 20 20 20 ns
PRECHARGE command period tRP 18 20 20 20 ns
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 42
DQ S r ea d po stam bl e tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
ACTIVE bank a to ACTIVE bank b com-
mand tRRD 12 15 15 15 ns
DQS write pream ble tWPRE 0.25 0.25 0.25 0.25 tCK
DQS write preamble setup time tWPRES 0 0 0 0 ns 20, 21
DQS write postam ble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 19
Wri te recovery ti me tWR 15 15 15 15 ns
Internal WRITE to READ command delay tWTR 1 1 1 1 tCK
Data valid output window na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 25
Average periodic refresh interval tREFI 7.8 7.8 7.8 7.8 us
Terminating voltage delay to VDD tVTD 0 0 0 0 ns
AC CHARACTERISTICS -6 -7 -75 -8
PARAMETER SYM-
BOL MIN MAX MIN MAX MIN MAX MIN MAX UNITSNOTES
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V58C2256(804/404/164)S Rev. 1.2 April 2002
Exit SELF REFRESH to non-READ com-
mand tXSNR 75 75 75 80 ns
Exit SELF REFRESH to READ command tXSRD 200 200 200 200 tCK
AC CHARACTERISTICS -6 -7 -75 -8
PARAMETER SYM-
BOL MIN MAX MIN MAX MIN MAX MIN MAX UNITSNOTES
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V58C2256(804/404/164)S
SLEW RATE DERATING VALUES
(Notes: 14; notes appear on pages 50-53) 0°C TA +70°C; VDDQ= +2.5V ±0.2V, VDD = +2.5V ± 0.2V)
SLEW RATE DERATING VALUES
(Note: 31; notes appear on page s 50-53) (0°C TA +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
NOTES:
1. Al l vol tages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC c haracteristics may be conduc ted at nom inal
reference/supply volt age levels, but th e related specifications and device operat ion are guaranteed fo r the
full voltage ra nge specified.
3. Outputs measured with equivalent load:
ADDRESS / COMMAND
SPEED SLEW RATE tIS tIH UNITS NOTES
-6, -7, -75 0.500V / ns 1 1 n s 14
-6, -7, -75 0.400V / ns 1.05 1 ns 14
-6, -7, -75 0.300V / ns 1.10 1 ns 14
-6, -7, -75 0.200V / ns 1.15 1 ns 14
-8 0.50 0V / ns 1.1 1.1 ns 14
-8 0.40 0V / ns 1.15 1.1 ns 14
-8 0.30 0V / ns 1.20 1.1 ns 14
-8 0.20 0V / ns 1.25 1.1 ns 14
Date, DQS, DM
SPEED SLEW RATE tDS tDH UNITS NOTES
-7, -75 0.500V / ns 0.50 0.50 ns 31
-7, -75 0.400V / ns 0.55 0.55 ns 31
-7, -75 0.300V / ns 0.60 0.60 ns 31
-7, -75 0.200V / ns 0.65 0.65 ns 31
-8 0. 50 0V / ns 0. 60 0.60 ns 31
-8 0. 40 0V / ns 0. 65 0.65 ns 31
-8 0. 30 0V / ns 0. 70 0.70 ns 31
-8 0. 20 0V / ns 0. 75 0.75 ns 31
O
utput
(
VOUT)
VTT
50Ω
Referenc
e
Point
30pF
39
MO SEL VITELIC
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V58C2256(804/404/164)S Rev. 1.2 April 2002
NOTES: (continued)
4. AC ti ming and IDD tests m ay use a VIL-to-VIH swing of up to 1. 5V in t he test environment, but input
timi ng is sti ll referenc ed to VREF (or to th e crossing point f or CK/CK), and parameter specifications
are guaranteed for the specified AC input levels under nor ma l use conditions. The m ini mum slew r ate
for the inp ut si gnals used to test t he device is 1V/ns in the range be tween VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as def ined in the SSTL_2 Standard (i.e., the receiver wi ll
effectively switch as a result of the signal crossing the AC input level, an d wil l rema in in that state as long
as the si gnal does not ring back ab ove [below] the DC input LOW [HIGH] level).
6. VREF is expe cted to equal VDDQ/2 of the trans mit-ting devi ce and to track variati ons in the DC level
of the same . Peak-to-peak noise (non-com mo n mode) on VREF may not exceed ±2 percent of the DC value.
Thus, from VDDQ/2, VREF is al lowed ±25mV for DC error and an addi tional ±25mV for AC noise.
7. VTT is not appl ied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF and must tr ack variatio ns in t he DC level of VREF.
8. VID is the magnitude of the di fference between the input level on CK and the input level on CK.
9. The value of VIX is expected to equal VDDQ/2 of the tran sm it ting device and mu st track varia-tions in the
DC le vel of the sa me .
10. IDD is dependent on output lo ading and cycle ra tes. Specifie d values are obtained with minimu m cyc le
time at CL = 2 for -6, -7 and -8 , CL = 2.5 for -75 with the outputs open.
11. Enables on-chi p refresh and address counters.
12. IDD specifications are tested after the devic e is pr operly initialized, and is averaged at the defined cycle rate.
13. Thi s parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T A = 25°C,
VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they
are matched in loading.
14. Command/Address input slew rate = 0.5V/ns. For -6, -7 and -75 with slew rates 1V/ns a nd faster, tIS and tIH are
reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from the 500m V/ns. tIH has 0ps added, that is, it remai ns constant. If the slew rate
exceeds 4.5V/ns, f unctionality is uncertain.
1 5. The CK/C K i nput r eferen ce lev el ( for t iming r eferenc ed to CK/CK) is the point at which CK and CK cross; the input
reference l evel for signals other than CK/CK is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE •0. 3 x VDDQ is recognized as LOW .
17. The output timing reference level, as measured at the tim ing reference point indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time wi ndows as valid data transitions. These parameters
are not re ferenced to a specifi c voltage level, but specify when the devic e output is no lo nger driving (HZ) or begins
driving (LZ).
19. The maximum limit for thi s parameter is not a device limit. The device will operate w ith a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negati ve va lue, but system performance coul d be
degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or b efore the W RITE command. The case shown (DQS
going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRIT E was in prog ress, DQS could be HIGH during this ti me , depending on tDQSS.
22. MIN (tRC o r tRFC) for IDD m easurements i s the smallest mult iple of tCK that meets t he m inimum absolute va lue
for the respective parameter. tRAS (MAX) for IDD measurements is the largest mul ti ple of tCK that
meets the maximum absolut e value for tRAS.
40
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
NOTES: (continued)
23. The refresh period 64ms. This equates to an average refresh rate of 7.8µs.
24. The I/O capacitance p er DQS and DQ byte/ group will not differ by more than thi s maximum am ount for an y
given device.
25. The valid data window is der ived b y achi eving other specificati ons - tHP (tCK/2), tDQSQ, and tQH
(tQH = tHP - tQH S). The data val id wind ow dera tes direct ly porp orti onal wit h the cloc k duty cycl e and a pract ical data
vali d windo w can be d eri ved. T he cl ock i s a llowed a maxi mum dut y cycl e v ariat ion of 45 /55. F unct ional ity i s uncer t ain
when operat ing beyond a 45/55 rati o. The data valid window der ating cur ves are provid ed below for duty cycl es rang-
ing between 50/50 and 45/55.
26. Referenced to each output group: x4 = DQ S with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-
DQ7; and UDQS with DQ8-DQ15 .
27. Th is li mit is act ually a nomi nal val ue and does not resul t in a f ail va lue. CKE is HI GH during REFRESH co mmand
period (tRFC [MIN]) else CKE is LOW (i.e., during standby).
28. To maintain a valid level, the tran sit ioning edge of the i nput must:
a) Sustain a constant slew rate fr om the current AC level through to the target AC level, VIL(AC) or VIH(AC).
b) Reach at lea st the tar get A C level.
c) After the AC target level is reached, continue t o maintain at least th e tar get DC level, VIL (DC) or VIH( DC).
29. The Input capacitance per pin group will not differ by mo re than this maximum amou nt f or any given device..
30. CK and CK input slew rate must be •1V/ns.
31. DQ and DM i nput slew rates must not deviate f rom DQS by mor e than 10%. If the DQ/D M /DQS sl ew rate is less
than 0. 5V/ns, tim ing must be der ated: 50ps must be added to tDS and tDH for each 100mv /ns reduc ti on in sl ew rate.
If sl ew rate exceeds 4V/ ns, functionality is uncertain.
32. VDD must not vary mor e than 4% if CKE is not acti ve while a ny bank is active.
NOTES: (continued)
3.8
3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250
3.400
50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55
2.463
2.500 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125
3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.90
0
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
-7, -75 @tCK = 10ns
-8, @tCK = 10ns
-7, -75 @tCK = 7.5ns
-8, @tCK = 8ns
-7, @tCK = 7ns
ns
41
MO SEL VITELIC
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V58C2256(804/404/164)S Rev. 1.2 April 2002
33. The clock is allo wed up to ±150ps of ji tter. Each timi ng parameter is allowed to vary by the same amount.
34. tHP min is the lesser of tCL minimum and tCH mini mum actually applied to the device CK and CK/ inputs,
collectively during bank active.
35. READs and WR ITEs with auto precharge are not al lowed to be issued unti l tRAS(MIN) can be satisf ied prior
to the internal precharge com-mand being issued.
36. Appl ies to x16 only. Fi rst DQS (LDQS or UDQS) to transition to l ast DQ (DQ0- DQ1 5) to tra nsition vali d.
Initial JEDEC specif icat ions suggested this to be same as tDQSQ.
37. Nor ma l Out put Drive Curves:
a) The full variation in driver pull-d own current from minimu m to max imum process, te mperature and voltage
will li e wit hin the outer bounding lines of the V- I curve of Figure A.
b) The vari ati on in d ri ver p ull-down current wit hin nominal li mits of voltage and temp erature is expected, but no
guaranteed, to lie withi n the inner bounding lin es of the V-I c urve o f Fig ure A.
c) The full vari ation in driv er pull -up curren t from minimum to maxi mum process , temper at ure and volt age wil l lie
within the outer bounding lines of the V-I curve of Figure B.
d)The vari ation in driv er pul l-up current within nominal li m it s of vo lt age and temperature is expected, but not
guaranteed, to lie withi n the inner bounding lin es of the V-I c urve o f Fig ure B.
e) The full variation in the rat io of the max imum to minimum pull -up and pull-down current should be
between .71 and 1.4, for device dr ain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage
and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-t o-source voltages from 0.1V to 1.0 Volt.
g) On the x4, the QFC# output o nly h as the pull-down characteristics which apply.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-d own current from minimu m to max imum process, te m-perature and vo lt age
will li e wit hin the outer bounding lines of the V- I curve of Figure C.
b) The vari ati on in d ri ver p ull-down current wit hin nominal li mits of voltage and temp erature is expected, but not
guaranteed, to lie within the inner bounding lin es of t he V-I curve of Fig ure C.
c) The ful l variation in dr iver pull- up current from m inimum to maximum process, t em perature and volt age will lie
within the out er bo unding lines of the V-I cur ve of Figure D.
d)The vari ation in driv er pul l-up current within nominal li m it s of vo lt age and temperature is expected, but not
guaranteed, to lie within the inner bounding lin es of t he V-I curve of Fig ure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull -down c urrent should be between
.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-t o-source voltages f rom 0.1V to 1.0 V.
39. The voltage levels used are derived from t he referenced test load. In practi ce, the voltage levels obtain ed fr om
a properly terminat ed bus wi ll provide si gnificantly differe nt vol tage values.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width •3ns and the pulse width can not be great er than 1/3
of t he cycl e r ate. VIL un ders hoot: VIL(MIN) = -1.5 V for a pulse wi dth • 3ns and t he pu lse wi dth can n ot be gr eat er than
1/3 of the cycle rate.
41. VDD and VDDQ must tr ack each o ther.
42. Note 42 is not used.
NOTES: (continued)
42
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V58C2256(804/404/164)S
43. Note 43 is not used.
44. Duri ng initialization, VDDQ, VTT, and VREF must be equal t o or less than VDD + 0.3V. Alter natively, VTT may
be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-
sistance is used between the VTT supply and the input pin.
45. Note 45 is not used.
46. tRAP •t RCD.
47. Note 47 is not used.
48. Random addressi ng changing 50% of data changing at every transfer.
49. Random addressi ng changing 100% of data changing at every t ransfer.
50. CKE must be acti ve (hi gh) dur ing t he e ntire t ime a refr esh com mand is ex ecuted. That i s, f rom the tim e the AUTO
REFRESH command i s regi stered, CKE must be active at e ach ri sing clock edge, until tREF later.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q i s sim ilar to IDD2F
except IDD2Q specifies the address and control i nputs to remain stable. Although IDD2F, I DD2N, and I DD2Q are
similar, IDD2F is “worst case.”
52. W henever the operating frequency i s altered, not including jitt er, the DLL is required to be reset. This is followed
by 200 clock cycles.
M
a
x
i
m
u
m
Nom
inal
h
ig
h
Nominal low
Nominal low
Nominal high
Minimum
Minimum
Maximum
80
70
60
50
40
30
20
10
0
.0 0.5 1.0 1.5 2.0 2.5 0.0
-120
-100
-80
-60
-40
-20
0
0.5 1.0 1.5 2.0 2
.5
0
43
MO SEL VITELIC
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V58C2256(804/404/164)S Rev. 1.2 April 2002
IBIS: I/V Characteris tics for Input and Output Buffers
Normal strengt h driver
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltag e will lie within the outer
bounding lines the o f t he V-I curve of Fig ure a.
3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b.
4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure b.
5. The full variation in the ratio of the maximum to minimum pullup an d pulldown current will not exceed 1.7, for device drain to sour ce
voltage from 0 to VDDQ/2
6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages from
0 to VDDQ/2
Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down (below )
Pulldown Current (mA) Pullup Current (mA)
Voltage (V) Typical Low Typical H igh Mini mum Maximum Typi cal Low Typic al High Min imum Maximum
0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0
Minimum
TypicalLow
TypicalHigh
Maximum
0
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5 2.0 2.5
Iout(mA)
Vout(V)
Maximum
TypicalHigh
Minumum
Iout(mA)
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
0.0 0.5 1.0 1.5 2.0 2.5
TypicalLow
V
DDQ
—Vout(V)
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Table 17. Pull down and pull up current values
Temperature (Tambient)
Typical 25°C
Minimum 70°C
Maximum 0°C
Vdd/Vddq
Typical 2.5V
Minimum 2.3V
Maximum 2.7V
The above characteristics are specified under best, worst and normal process variation/conditions
0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0
0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8
0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8
0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8
0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4
0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8
0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5
0.9 47.5 55.2 39.6 69.9 -41.8 -59.4 -38.2 -77.3
1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2
1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0
1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6
1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1
1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5
1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0
1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4
1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7
1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2
1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5
2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9
2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2
2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6
2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0
2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3
2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6
2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9
2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
45
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Half strength driver
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltag e will lie within the outer
bounding lines the of the V-I curve of Figure a.
3. Thenominal p ullup V-I c urve for DDR S DRAM devices will be within the inner b ounding lines of the V-I curve of be low Fi gure b.
4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure b.
5. The ful l variation in t he ratio of the maxim um to minimum pullup and pulldow n current wil l not exceed 1 .7, for device drain to so urce
voltage from 0 to VDDQ/2
6. The Full variation in th e ratio of the nominal pullup to pulldown current shoul d be unity ±10%, for device drain to so urce voltages
from 0 to VDDQ/2
Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down (below )
Pulldo wn Current (mA) Pullup Current (mA)
Voltage (V) Typ ical Low Typical High Minimum Maximum Typical Low Typical High Minimum Maximum
0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0
Iout(mA)
Minimum
TypicalLow
TypicalHigh
Maximum
0
10
20
30
40
50
60
70
80
90
0.0 1.0 2.0
Iout(mA)
Vout(V)
Maximum
TypicalHigh
Minumum
Iout(mA)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.5 1.0 1.5 2.0 2.5
TypicalLow
V
DDQ
—Vout(V)
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Table 18. Pull down and pull up current values
Temperature (Tambient)
Typica l 25 °C
Minimum 70°C
Maximum 0°C
Vdd/Vddq
Ty pi ca l 2.5V
Minimum 2.3V
Maximum 2.7V
The above characteristics are specified under best, worst and normal process variation/conditions
0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9
0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6
0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2
0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6
0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0
0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2
0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8
0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5
1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2
1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7
1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0
1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1
1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1
1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7
1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4
1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63. 5
1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6
1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7
2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8
2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6
2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3
2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9
2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4
2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7
2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8
2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
Pulldo wn Current (mA) Pullup Current (mA)
Voltage (V) Typ ical Low Typical High Minimum Maximum Typical Low Typical High Minimum Maximum
47
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 36 - DATA INPUT (WRITE) TIMING
DI n = Data In for co lumn n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed
order following DI n
Figure 37 - DATA OUT PUT (READ) TIMING
1. tDQSQ ma x occurs when D Q S is the earliest among DQS and DQ signals to transition.
2. tDQ SQ min occurs when DQS is the latest among DQS and DQ signals to t ransition .
3. tDQSQ n om, show n for reference, occurs when DQS transiti ons in the center am ong DQ signal transitions.
DON'T CARE
DQ
DM
D
QS
DI
n
tDS
tDH
tDS
tDH
tDSL tDSH
t
min
DQSQ
t
max
DQSQ
DQ
D
QS
t
min
DQSQ
t
max
DQSQ t
nom
DQSQ
Burst Length = 4 in the case shown
tDV
D
QS, DQ
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V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Figure 38 - INITIALIZE AND MO DE REGISTER SETS
CKE LVCMOS LOW LEVEL
DQ
BA0, BA1
200 cycles of CLK**
Extended
Mode
Register
Set Load
Mode
Register,
Reset DLL
(with A8 = H)
Load
Mode
Register
(with A8 = L)
tMRD tMRD tMRD
tRP tRFC tRFC
tIS
Power-up:
VDD and
CLK stable
T = 200µs
()()
()()
()()
()()
High-Z
tIH
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
DM
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
DQS
High-Z
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
A0-A9, A11
()()
()()
()()
()()
A10
ALL BANKS
DON'T CARE
CK
/CK
tCK
tCH tCL
VTT
(system*)
tVTD
VREF
VDD
VDDQ
C
OMMAND
MRSNOP PREEMRS AR
()()
()()
()()
()()
()()
()()
()()
()()
AR
tIS tIH
BA0=H,
BA1=L
tIS tIH tIS tIH
BA0=L,
BA1=L
tIS tIH
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
CODE
tIS tIH
CODE
MRS
BA0=L,
BA1=L
CODE
CODE
()()
()()
()()
()()
PRE
ALL BANKS
tIS tIH
RA
RA
ACT
BA
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.
The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.
()()
()()
CODE
CODE
49
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 39 - POW ER-DOWN MODE
CK
/CK
C
OMMAND
VALID* NOP
ADDR
CKE
VALID VALID
DON'T CARE
No column accesses are allowed to be in progress at the time Power-Down is entered
* = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down
mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already
active) then the Power-Down mode shown is Active Power Down.
DQ
DM
DQS
VALID
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS tIH
tIH tIS
Enter
Power-Down
Mode
Exit
Power-Down
Mode
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
NOP
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V58C2256(804/404/164)S
Figure 40 - AUT O REFRESH MODE
CK
/CK
C
OMMAND
NOP
VALID VALID
NOP NOPPRE
A0-A8
CKE
RA
RA
A9, A11
A10
BA0, BA1
*Bank(s) BA
DON'T CARE
* = "Don't Care", if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e. must precharge all active banks)
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible at these times
DM, DQ and DQS signals are all "Don't Care"/High-Z for operations shown
AR NOP AR NOP ACTNOP
ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIH
tIS tIH
RA
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
DQ
DM
DQS
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
tRC
tRP tRC
51
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 41 - SE LF REFRES H MODE
CK
/CK
C
OMMAND
NOP AR
ADDR
CKE
VALID
DON'T CARE
DQ
DM
DQS
VALIDNOP
tCK clock must be stable before
exiting Self Refresh mode
tRP*
tCH tCL
tIS
tIS
tIH
tIS
tIS tIH
tIH tIS
Enter
Self Refresh
Mode Exit
Self Refresh
Mode
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
* = Device must be in the "All banks idle" state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CLK)
are required before a READ command can be applied.
tXSNR/
tXSRD**
52
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Figure 42 - READ - WITHOUT AUTO PRECHARGE
CK
/CK
COMMAND
NOPNOP PREREAD
CKE
Col
n
RA
RA
A10
BA0, BA1
Bank
x
*Bank
x
DON'T CARE
DO
n
= Data Out from column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO
n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
DQ
DM
DQS
C
ase 1:
t
AC/tDQSCK = min
C
ase 2:
t
AC/tDQSCK = max
DQ
DQS
NOP NOP ACT NOP NOPNOP
VALID VALIDVALID
DIS AP ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
tRPRE
tQPRE
tRPRE
tRP
t
t
RA
CL = 2
t
min
HZ
t
max
HZ
t
min
LZ
t
max
LZ
t
max
LZ
t
min
AC
t
max
t
min
t
max
AC
Bank
x
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
DO
n
DO
n
DQSCK
RPST
tQPST
/QFC
(optional)
DQSCK
RPST
tQPRE tQPST
/QFC
(optional)
t
min
LZ
StartAutoprecharge
53
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 43 - READ - WITH AUTO PRECHARGE
CK
/CK
COMMAND
NOPNOP PREREAD
CKE
Col
n
RA
RA
A10
BA0, BA1
Bank
x
*Bank
x
DON'T CARE
DO
n
= Data Out from column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO
n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
DQ
DM
DQS
C
ase 1:
t
AC/tDQSCK = min
C
ase 2:
t
AC/tDQSCK = max
DQ
DQS
NOP NOP ACT NOP NOPNOP
VALID VALIDVALID
DIS AP ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
tRPRE
tQPRE
tRPRE
tRP
t
t
RA
CL = 2
t
min
HZ
t
max
HZ
t
min
LZ
t
max
LZ
t
max
LZ
t
min
AC
t
max
t
min
t
max
AC
Bank
x
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
DO
n
DO
n
DQSCK
RPST
tQPST
/QFC
(optional)
DQSCK
RPST
tQPRE tQPST
/QFC
(optional)
t
min
LZ
54
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Figure 44 - BANK READ ACCESS
CK
/CK
COMMAND
NOP NOP NOPNOP READACT
CKE
RA RA
RA
RA
RA
A10
BA0, BA1
Bank
x
Bank
x
NOP NOP NOPPRE
DIS AP ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tIH
tIS tIH
RA
DO
n
= Data Out from column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO
n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
tRCD tRAS
tRC
*Bank
x
Bank
x
tRP
CL = 2
Col
n
ACT
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
DON'T CARE
DQ
DM
DQS
C
ase 1:
t
AC/tDQSCK = min
C
ase 2:
t
AC/tDQSCK = max
DQ
DQS
tRPRE
tQPRE
tRPRE
t
t
t
min
HZ
t
max
HZ
t
min
LZ
t
max
LZ
t
max
LZ
t
min
LZ t
min
AC
t
max
t
min
t
max
AC
DO
n
DO
n
DQSCK
RPST
tQPST
/QFC
(optional)
DQSCK
RPST
tQPRE tQPST
/QFC
(optional)
55
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 45 - WRITE - WITHOUT AUTO PRECHARGE
CK
/CK
COMMAND
NOPNOP NOPWRITE
CKE
Col
n
RA
RA
A10
BA0, BA1
Bank
x
*Bank
x
BA
DON'T CARE
DI
n
= Data In for column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order following DI
n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other valid commands may be possible at these times
NOP NOP PRE NOP
VALID
ACTNOP
DIS AP ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIH
tIS
tIS
tIH
tIH
tRP
tIH
tIS tIH
RA
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
DQ
DM
DQS
DI
n
t
tDQSS t
t
C
ase 1:
t
DQSS = min
C
ase 2:
t
DQSS = max
DQ
DM
DQS
DI
n
ttWR
tDQSS t
tt
t
WPST
DQSH
DQSL
tWPRES
WPST
DQSH
DQSL
WPRE
WPRES
tWPRE
tDSS tDSS
tDSH tDSH
tQOH MAX
tQCK
/QFC
(optional)
tQCK tQOH MIN
/QFC
(optional)
56
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Figure 46 - WRITE - WITH AUTO PRECHARGE
CK
/CK
COMMAND
NOPNOP NOPWRITE
CKE
Col
n
RA
RA
A10
BA0, BA1
Bank
x
BA
DON'T CARE
DI
n
= Data In for column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order following DI
n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other valid commands may be possible at these times
NOP NOP NOP NOP
VALID VALID
ACTNOP
EN AP
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tDAL
RA
VALID
tIH
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
DQ
DM
DQS
DI
n
t
tDQSS t
t
C
ase 1:
t
DQSS = min
C
ase 2:
t
DQSS = max
DQ
DM
DQS
DI
n
t
tDQSS t
tt
t
WPST
DQSH
DQSL
tWPRES
WPST
DQSH
DQSL
WPRE
WPRES
tWPRE
tDSS tDSS
tDSH tDSH
tQOH MAX
tQCK
/QFC
(optional)
tQCK tQOH MIN
/QFC
(optional)
57
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
Figure 47 - BAN K WRITE ACCESS
CK
/CK
COMMAND
NOP NOPNOP WRITEACT
CKE
RA
A10
BA0, BA1
Bank
x
Bank
x
DON'T CARE
DI
n
= Data In for column
n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order following DI
n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address
NOP commands are shown for ease of illustration; other valid commands may be possible at these times
NOP NOP NOP NOP PRE
DIS AP ONE BANK
ALL BANKS
tCK tCH tCL
tIS
tIS
tIH
tIS
tIS
tIH
tIH
tRCD
tRAS
tIH
tIS tIH
RA
x4:A0-A9
x8:A0-A8
x16:A0-A7
x4:A11
x8:A9, A11
x16:A8, A9, A11
Col
n
*Bank
x
RA
tWR
DQ
DM
DQS
DI
n
t
tDQSS t
t
C
ase 1:
t
DQSS = min
C
ase 2:
t
DQSS = max
DQ
DM
DQS
DI
n
t
tDQSS t
tt
t
WPST
DQSH
DQSL
tWPRES
WPST
DQSH
DQSL
WPRE
WPRES
tWPRE
tDSS tDSS
tDSH tDSH
tQOH MAX
tQCK
/QFC
(optional)
tQCK tQOH MIN
/QFC
(optional)
58
V58C2256(804/404/164)S Rev. 1.2 April 2002
MO SEL VITELIC
V58C2256(804/404/164)S
Package Diagram
66-Pin TSOP-II (400 mil)
Units : Millimeters
0.30 ± 0.08
1.00 ± 0.10
11.76 ± 0.20
0.65TYP(0.71)
22.22 ± 0.10
0.125
(0.80)
10.16 0.10
0~8
#1 #33
#66 #34
(1.50)
(1.50)
0.65 ± 0.08
1.20MAX
(0.50) (0.50)(10.76)
(10• )(10•)
+0.075
-0.035
(0.80)
0.10 MAX
0.075 MAX
[]
0.05 MIN
(10• )
(10•)
(R0.15)
0.210 0.05
0.665 0.05
(R0.15)
(4
•
)
(R0.25)
(R0.25)
0.45~0.75
0.25TYP
NOTE
1. ( ) IS REFERENCE
59
MO SEL VITELIC
V58C2256(804/404/164)S
V58C2256(804/404/164)S Rev. 1.2 April 2002
WORLDWIDE OFFICES
© Copyright , MOSEL VITELIC Corp. Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality contr
ol
sampling techniques which are intended to provide an assuranc
e
of high quality products suitable for usual commercial applic
a-
tions. MOSEL VITELIC does not do testing appropriate to provid
e
100% product quality assurance and does not assume any liab
il-
ity for consequential or incidental arising from any use of its pro
d-
ucts. If such products are to be used in applications in whic
h
personal injury might occur from failure, purchaser must do
its
own quality assurance testing appropriate to such applications
.
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