M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 200 pin Unbuffered DDR SO-DIMM Based on DDR333 512Mb bit B Die device Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Unbuffered DDR SO-DIMM based on 110nm 512M bit die B * Address and control signals are fully synchronous to positive device, organized as 64Mx8 and 32Mx16 DDR SDRAM clock edge * Performance: * Programmable Operation: - DIMM CAS Latency: 2, 2.5 PC2700 fCK tCK Speed Sort 6K DIMM CAS Latency 2.5 Clock Frequency 166 Clock Cycle fDQ DQ Burst Frequency - Burst Type: Sequential or Interleave Unit - Burst Length: 2, 4, 8 - Operation: Burst Read and Write MHz 6 ns 333 MHz * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 7.8 s Max. Average Periodic Refresh Interval * Intended for 166 MHz applications * Serial Presence Detect EEPROM * Inputs and outputs are SSTL-2 compatible * Gold contacts on module PCB * VDD = VDDQ = 2.5V 0.2V * Available in "Green" packaging (lead & halogen free) * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges Description M1N1G64DS8HB0F, M1N51264DSH8B1G, M1N25664DSH4B1G, M1S1G64DS8HB0F, M1S51264DSH8B1G and M1S25664DSH4B1G are un-buffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM). All devices on these modules are based on Nanya's 110nm die B generation of 512M bit devices. The M1N1G64DS8HB0F and M1S1G64DS8HB0F are organized as two ranks of 128Mx64 high-speed memory array and use sixteen 64Mx8 DDR SDRAMs BGA packages. The M1N51264DSH8B1G and M1S51264DSH8B1G are organized as two ranks of 64Mx64 high-speed memory array and use eight 32Mx16 DDR SDRAMs TSOP packages. The M1N25664DSH4B1G and M1S25664DSH4B1G are organized a single rank of 32Mx64 high-speed memory array and use four 32Mx16 DDR SDRAMs TSOP packages. The DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The SO-DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) data can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC. REV 1.2 June 3, 2005 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Ordering Information "Green"Part Number Size M1N1G64DS8HB0F-6K 128Mx64 M1N51264DSH8B1G-6K 64Mx64 M1N25664DSH4B1G -6K 32Mx64 Part Number Size M1S1G64DS8HB0F-6K 128Mx64 M1S51264DSH8B1G-6K 64Mx64 M1S25664DSH4B1G-6K 32Mx64 REV 1.2 June 3, 2005 Speed Power DDR333 PC2700 166MHz (6ns @ CL = 2.5) Devices 2.5-3-3 133MHz (7.5ns @ CL = 2) Speed Gold 2.5V PC2700 166MHz (6ns @ CL = 2.5) Devices 2.5-3-3 133MHz (7.5ns @ CL = 2) (lead and halogen free) Power DDR333 Leads 2.5V Leads Gold 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Pin Description CK0, CK1, CK2, Differential Clock Inputs. DQ0-DQ63 Data input/output Clock Enable DQS0-DQS7 Bidirectional data strobes RAS Row Address Strobe DM0-DM7 Input Data Mask CAS Column Address Strobe VDD Power WE Write Enable VDDQ Supply voltage for DQs CK0, CK1, CK2 CKE0, CKE1 S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 3 VSS 4 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 9 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 S0 122 S1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 DQS8 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.2 June 3, 2005 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Input/Output Functional Description Symbol CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Type (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the S0, S1 (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. RAS, CAS, WE (SSTL) VREF Supply VDDQ Supply BA0, BA1 (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, these lines define the row address when sampled at the rising clock edge. During a Read or Write command cycle, these lines defines the column address when A0 - A9 A10/AP A11 - A13 sampled at the rising clock edge. In addition to the column address, AP is used to invoke (SSTL) - auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS8 (SSTL) Active High CB0 - CB7 (SSTL) - DM0 - DM8 Input Active High VDD, VSS Supply SA0 - SA2 - SDA - SCL - VDDSPD REV 1.2 June 3, 2005 Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. DQS8 is used for ECC modules (CB0-CB7) and is not used on x64 modules. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pull-up. Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Functional Block Diagram 2 Ranks, 16 devices, 64Mx8 DDR SDRAMs S0 S1 DQS0 DM0 DQS4 DM4 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS D0 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQS1 DM1 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQS2 DM2 DQS D5 DQS D13 DQS6 DM6 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQS D6 DQS D14 DQS7 DM7 DQS3 DM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 BA0-BA1 : SDRAMs D0-D15 A0-A12 A0-A12 : SDRAMs D0-D15 RAS RAS : SDRAMs D0-D15 CAS CAS : SDRAMs D0-D15 CKE0 CKE : SDRAMs D0-D7 CKE1 CKE : SDRAMs D8-D15 WE : SDRAMs D0-D15 WE Notes : 1. 2. 3. 4. DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 June 3, 2005 D15 Strap: see Note 4 Serial PD SCL WP DQ-to-I/O wring may be changed within a byte. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.2 D7 DQS Clock Wiring Clock Input SDRAMs CK0/CK0 8 SDRAMs CK1/CK1 8 SDRAMs CK2/CK2 NC SPD D0-D15 D0-D15 D0-D15 VDDSPD VDD/VDDQ VREF VSS VDDID DQS A0 A1 A2 SA0 SA1 SA2 SDA * Clock Net Wiring R=120 Ohms CK0/CK1 CK0/CK1 Card Edge D0/D8 D1/D9 D2/D10 D3/D11 D4/D12 D5/D13 D6/D14 D7/D15 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Functional Block Diagram 2 Ranks, 8 devices, 32Mx16 DDR SDRAMs S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS A0-A12 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS UDQS D5 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CKE0 CKE : SDRAMs D0-D3 CKE1 CKE : SDRAMs D4-D7 WE : SDRAMs D0-D7 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS D2 UDQS D6 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D7 D0-D7 D0-D7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VDDSPD VDD/VDDQ VREF VSS VDDID BA0-BA1 : SDRAMs D0-D7 RAS : SDRAMs D0-D7 June 3, 2005 D4 A0-A12 : SDRAMs D0-D7 CAS : SDRAMs D0-D7 REV 1.2 UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 RAS Notes : 1. 2. 3. 4. CS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CAS WE LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 BA0-BA1 CS D7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 Clock Wiring Clock Input SDRAMs CK0/CK0 4 SDRAMs CK1/CK1 4 SDRAMs CK2/CK2 NC Serial PD SCL WP DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. A0 A1 A2 SA0 SA1 SA2 SDA * Clock Net Wiring R=120 Ohms CK0/CK1 CK0/CK1 Card Edge D0/D4 D1/D5 D2/D6 D3/D7 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Functional Block Diagram 1 Rank, 4 devices, 32Mx16 DDR SDRAMs S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS A0-A12 D0 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 BA0-BA1 CS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0-A12 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. WE Notes : 1. 2. 3. 4. REV 1.2 June 3, 2005 WE : SDRAMs D0-D3 LDQS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS VDDSPD VDD/VDDQ VREF VSS VDDID BA0-BA1 : SDRAMs D0-D3 RAS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D3 D0-D3 D0-D3 CK0 CK0 CK1 CK1 Serial PD SCL WP DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. CK2 A0 A1 A2 SA0 SA1 SA2 SDA CK2 2 loads 2 loads 0 loads 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Serial Presence Detect Byte 0 Description Number of Serial PD Bytes Written during Production Byte 27 Description Minimum Row Precharge Time (tRP) 1 Total Number of Bytes in Serial PD device 28 Minimum Row Active to Row Active delay (tRRD) 2 Fundamental Memory Type 29 Minimum RAS to CAS delay (tRCD) 3 Number of Row Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS) 4 Number of Column Addresses on Assembly 31 Module Bank Density 5 Number of DIMM Rank 32 Address and Command Setup Time Before Clock 6 Data Width of Assembly 33 Address and Command Hold Time After Clock 7 Data Width of Assembly (cont') 34 Data Input Setup Time Before Clock 8 Voltage Interface Level of this Assembly 35 Data Input Hold Time After Clock 9 10 DDR SDRAM Device Cycle Time 36-40 CL=2.5 DDR SDRAM Device Access Time from Clock 41 CL=2.5 Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period 11 DIMM Configuration Type 12 Refresh Rate/Type 43 Max Cycle Time (tCK max) 13 Primary DDR SDRAM Width 44 Maximum DQS-DQ Skew Time (tDQSQ) Error Checking DDR SDRAM Device Width 45 Maximum Read Data Hold Skew Factor (tQHS) 46 Reserved 47 Dimm Height 14 15 16 17 18 42 Reserved DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device 48-61 Banks DDR SDRAM Device Attributes: CAS Latencies Supported (tRFC) Reserved 62 SPD Revision Checksum Data 19 DDR SDRAM Device Attributes: CS Latency 63 20 DDR SDRAM Device Attributes: WE Latency 64-71 Manufacturer's JEDEC ID Code 21 DDR SDRAM Device Attributes: 72 Module Manufacturing Location 22 23 DDR SDRAM Device Attributes: General Minimum Clock Cycle CL=2.5 73-90 Module Part number 91-92 Module Revision Code Module Manufacturing Data 24 yy= Binary coded decimal year code, 0-99(Decimal), Maximum Data Access Time from Clock at 93-94 CL=2 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 25 Minimum Clock Cycle Time at CL=1 95-98 Module Serial Number 26 Maximum Data Access Time from Clock at CL=1 99-127 Reserved REV 1.2 June 3, 2005 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 SPD Values for M1N1G64DS8HB0F / M1S1G64DS8HB0F Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR400 -5T 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=3 DDR SDRAM Device Access Time from Clock at CL=3 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min Clk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2.5 Maximum Data Access Time (tAC) from Clock at CL=2.5 Minimum Clock Cycle Time at CL=2 Maximum Data Access Time (tAC) from Clock at CL=2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved Minimum Active/Auto-Refresh Time (tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto Refresh Command Period (tRFC) 43 SDRAM Device Maximum Cycle Time (tCK max) 44 SDRAM Device Maximum DQS-DQ Skew Time (tDQSQ) 45 SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) 46 Superset Information (may be used in future) 47 SDRAM device Attributes - DDR SDRAM DIMM Height 48-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum Data 64-71 Manufacturer's JEDED ID Code 72 Module Manufacturing Location 73-255 Reserved 1. please refer to BNDCJ-0082 2. byte 73-255 please refer to NDCJ-0969 REV 1.2 June 3, 2005 DDR333 DDR266 -6K -75B 128 256 DDR SDRAM 13 11 2 X64 X64 SSTL 2.5V 5ns 6ns 7.5ns 0.65ns 0.7ns 0.75ns Non-Parity SR/1x(7.8us), Self Refresh Flag X8 N/A 1 Clock 2,4,8 4 2.5/3 2/25 2/2.5 0 1 Differential Clock +/-0.2V Voltage Tolerance 6.0ns 7.5ns 10ns 0.7ns 0.75ns 0.75ns N/A N/A 15ns 18ns 20ns 10ns 12ns 15ns 15ns 18ns 20ns 40ns 42ns 45ns 512MB 0.6ns 0.75ns 0.9ns 0.6ns 0.75ns 0.9ns 0.4ns 0.45ns 0.5ns 0.4ns 0.45ns 0.5ns Undefined 55ns 60ns 65ns 70ns 72ns 75ns 0.4 0.5 12 0.45 0.55 Undefined 31.75mm Undefined 1.0 0B Hex bank 3 Undefined 0.5 0.75 DDR400 -5T 50 65 18 60 70 3C 28 3C 28 60 60 40 40 37 46 DDR333 -6K 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 75 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 Note DDR266 -75B 75 75 0C A0 75 50 3C 50 2D 90 90 50 50 41 4B 30 2D 32 55 75 00 01 00 10 C8 58 35 7F7F7F0B00000000 Note 1 Note 2 28 50 1 2 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 SPD Values for M1N51264DSH8B1G / M1S51264DSH8B1G Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR400 -5T 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=3 DDR SDRAM Device Access Time from Clock at CL=3 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min Clk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2.5 Maximum Data Access Time (tAC) from Clock at CL=2.5 Minimum Clock Cycle Time at CL=2 Maximum Data Access Time (tAC) from Clock at CL=2 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved Minimum Active/Auto-Refresh Time (tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto Refresh Command Period (tRFC) 43 SDRAM Device Maximum Cycle Time (tCK max) 44 SDRAM Device Maximum DQS-DQ Skew Time (tDQSQ) 45 SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) 46 Superset Information (may be used in future) 47 SDRAM device Attributes - DDR SDRAM DIMM Height 48-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum Data 64-71 Manufacturer's JEDED ID Code 72 Module Manufacturing Location 73-255 Reserved 1. please refer to BNDCJ-0082 2. byte 73-255 please refer to NDCJ-0969 REV 1.2 June 3, 2005 DDR333 DDR266 -6K -75B 128 256 DDR SDRAM 13 11 1 X64 X64 SSTL 2.5V 5ns 6ns 7.5ns 0.65ns 0.7ns 0.75ns Non-Parity SR/1x(7.8us), Self Refresh Flag X8 N/A 1 Clock 2,4,8 4 2.5/3 2/25 2/2.5 0 1 Differential Clock +/-0.2V Voltage Tolerance 6.0ns 7.5ns 10ns 0.7ns 0.75ns 0.75ns N/A N/A 15ns 18ns 20ns 10ns 12ns 15ns 15ns 18ns 20ns 40ns 42ns 45ns 512MB 0.6ns 0.75ns 0.9ns 0.6ns 0.75ns 0.9ns 0.4ns 0.45ns 0.5ns 0.4ns 0.45ns 0.5ns Undefined 55ns 60ns 65ns 70ns 72ns 75ns 0.4 0.5 12 0.45 0.55 Undefined 31.75mm Undefined 1.0 0B Hex bank 3 Undefined 0.5 0.75 DDR400 -5T 50 65 18 60 70 3C 28 3C 28 60 60 40 40 37 46 DDR333 -6K 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 75 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 Note DDR266 -75B 75 75 0C A0 75 50 3C 50 2D 90 90 50 50 41 4B 30 2D 32 55 75 00 01 00 10 C7 57 34 7F7F7F0B00000000 Note 1 Note 2 28 50 1 2 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 SPD Values for M1N25664DSH4B1G / M1S25664DSH4B1G Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR400 -5T 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=3/2.5/2.5 DDR SDRAM Device Access Time from Clock at CL=3/2.5/2.5 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min Clk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2.5/2/2 Maximum Data Access Time (tAC) from Clock at CL=2.5/2/2 Minimum Clock Cycle Time at CL=2/1/1.5 Maximum Data Access Time (tAC) from Clock at CL=2/1/1.5 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved Minimum Active/Auto-Refresh Time (tRC) SDRAM Device Minimum Auto-Refresh to Active/Auto Refresh Command Period (tRFC) 43 SDRAM Device Maximum Cycle Time (tCK max) 44 SDRAM Device Maximum DQS-DQ Skew Time (tDQSQ) 45 SDRAM Device Maximum Read Data Hold Skew Factor (tQHS) 46 Superset Information (may be used in future) 47 SDRAM device Attributes - DDR SDRAM DIMM Height 48-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum Data 64-71 Manufacturer's JEDED ID Code 72 Module Manufacturing Location 73-255 Reserved 1. please refer to BNDCJ-0082 2. byte 73-255 please refer to NDCJ-0969 REV 1.2 June 3, 2005 DDR333 DR266 -6K -75B 128 256 DDR SDRAM 13 10 1 X64 X64 SSTL 2.5V 5ns 6ns 7.5ns 0.65ns 0.7ns 0.75ns Non-Parity SR/1x(7.8us), Self Refresh Flag X16 N/A 1 Clock 2,4,8 4 2.5/3 2/2.5 2/2.5 0 1 Differential Clock +/-0.2V Voltage Tolerance 6.0ns 7.5ns 10ns 0.7ns 0.75ns 0.75ns N/A N/A 15ns 18ns 20ns 10ns 12ns 15ns 15ns 18ns 20ns 40ns 42ns 45ns 256MB 0.6ns 0.75ns 0.9ns 0.6ns 0.75ns 0.9ns 0.4ns 0.45ns 0.5ns 0.4ns 0.45ns 0.5ns Undefined 55ns 60ns 65ns 70ns 72ns 75ns 0.4 0.5 12 0.45 0.55 Undefined 31.75mm Undefined 1.0 0B Hex bank 3 Undefined 0.5 0.75 DDR400 -5T 50 65 18 60 70 3C 28 3C 28 60 60 40 40 37 46 DDR333 -6K 80 08 07 0D 0A 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 C0 75 75 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 Note DR266 -75B 75 75 0C A0 75 50 3C 50 2D 90 90 50 50 41 4B 30 2D 32 55 75 00 01 00 10 8E 1E FB 7F7F7F0B00000000 Note1 Note 2 28 50 1 2 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation (per device component) 1 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V Symbol Parameter Min Max Units Notes VDD Supply Voltage 2.3 2.7 V 1 VDDQ I/O Supply Voltage 2.3 2.7 V 1 0 0 V VSS, VSSQ Supply Voltage, I/O Supply Voltage VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIH (DC) VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 -10 10 A 1 -10 10 A 1 -16.8 - mA 1 16.8 - mA 1 II IOZ IOH IOL Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.2 June 3, 2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max VREF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 1.2 June 3, 2005 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W Parameter/Condition clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Notes Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level. Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 REV 1.2 June 3, 2005 M1N1G64DS8HB0F M1S1G64DS8HB0F PC2700 (6K) 1575 1634 57 420 195 767 1705 1910 3125 38 4961 M1N51264DSH8B1G M1S51264DSH8B1G PC2700 (6K) 810 839 30 222 103 406 875 977 1585 20 2503 M1N25664DSH4B1G M1S25664DSH4B1G PC2700 (6K) 382 397 13 99 46 180 415 466 770 9 1229 mA mA mA mA mA mA mA mA mA mA mA 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Package Dimensions Non-ECC, 16 BGA devices, M1N1G64DS8HB0F/ M1S1G64DS8HB0F FRONT 67.60 (2X) 1.80 2.15 1 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 1.80 2.45 BACK SIDE 3.80 MAX 1.00+/- 0.10 Detail A 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail B Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) Note: Devices are not to scale and are there as references only. REV 1.2 June 3, 2005 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Package Dimensions Non-ECC, 8 TSOP devices, M1N51264DSH8B1G / M1S51264DSH8B1G FRONT 67.60 (2X) 1.80 1 2.15 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 1.80 BACK SIDE 3.80 MAX 2 40 42 200 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.2 June 3, 2005 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Package Dimensions Non-ECC, 4 TSOP devices, M1N25664DSH4B1G / M1S25664DSH4B1G FRONT 67.60 (2X) 1.80 1 2.15 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 1.80 SIDE BACK 3.00 MAX 2 40 42 200 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.2 June 3, 2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64DS8HB0F / M1N51264DSH8B1G / M1N25664DSH4B1G M1S1G64DS8HB0F / M1S51264DSH8B1G / M1S25664DSH4B1G 1GB, 512MB and 256MB PC2700 Revision Log Rev Date 1.2 June 3, 2005 REV 1.2 June 3, 2005 Modification Updated Functional Block Diagram. 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.