Integrated Device Technology, Inc. VERY LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT) PRELIMINARY INFORMATION IDT713256SL FEATURES * Ideal for 16/32-bit notebook/sub-notebook cache at 20, 25, and 33MHz, and for other battery-operated equipment * Very low standby current (maximums): 3.0mA standby 500uA full standby + Fast access times: 20/25/30ns * Battery-backup operation: 2V data retention 300uA data retention current (max.) * Small package for space-efficient layouts: 28-pin 300 mil SOJ + Ideal configuration for large cache sizes, with minimum space and minimum power: 32K x8 * Produced with advanced high-performance CMOS technology * Input and output are TTL-compatible * Single 3.3V(+0.3V) power supply DESCRIPTION The !DT713256SL is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high- performance, high-reliability CMOS technology. The |DT713256SL has outstanding low power characteris- tics, as well as fast speeds. Address access times of 20, 25, and 30ns are ideal for 16 and 32-bit notebook and laptop cache designs running at 20, 25, and 33MHz, and operating from 3.3 volts. For instance, two of these SRAMs interface directly to many 386 notebook cache controllers to form a 64kB cache. Portable communica- tions and test equipment benefit from these fast speeds and low power too. When the power managementlogic puts the iDT713256SL in standby mode, its very low power characteristics contribute to extended battery life. When CS goes HIGH, the SRAM will automatically go to a low power standby mode and will remain in standby as long as CS remains HIGH. Furthermore, under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to always be less than 1.65mW and typically will be much smaller. This SRAM aiso offers battery-backup data retention atas little as 2 volts. Under this condition, power consumption is guaranteed not to exceed 1.0mW and typically will be much smaller. The package chosen for this device, 28-pin 300mil SOJ, helps the designer attain the stringent space goals typical of notebooks, sub-notebooks, and battery-operated portable equipment. FUNCTIONAL BLOCK DIAGRAM Ao e e ADDRESS e DECODER Ai4 Oo CIRCUIT O07 cs OE CONTROL __ | WE CIRCUIT The IDT logo ts a registered trademark of integrated Device Technology Inc 262,144 BIT MEMORY ARRAY VO CONTROL 3012 drw OF COMMERCIAL TEMPERATURE RANGES 1992 Integrated Devices Technology. inc 9.1 SEPTEMBER 1992 DSC-1100/- 1IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS Ai4 (]1 28 (1 Vcc Ai2 2 a7 1) We A7 (3 26 1 A13 Ac (4 25 [J As Ass 24 T] Ag ACH6 soog5 % AN A317 22 [1] OE A2 (8 21 Aso Ai Ole 2 CS Ao (] 10 19 [7 07 VOo G11 je 1 O06 vO1 C12 17 VO5 VO2 113 16 1 W/O4 GND (4 14 15 Lo VO3 3012 drw 02 sou TOP VIEW PIN DESCRIPTIONS VOo-/07 cs WE OE Data Select Write Enable Enable Ground Power 3012 tbl OF ABSOLUTE MAXIMUM RATINGS") Symbol Rating com. Unit Vterm) | Terminal Voltage with 0.5 to +4.6 Vv Respect to GND VteRM) | Terminal Voltage with -0.5 to VCC+0.5| V Respect to GND TA Operating Temperature 010 +70 C TBIAS Temperature Under Bias 55 to +125 C TsTG Storage Temperature 55 to +125 C PT Power Dissipation 1.0 Ww louT DC Output Current 50 mA NOTES: 3012 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Vcc terminals only Input, Output, and 1/O terminals; 4.6V maximum CAPACITANCE (Ta = +25C, f = 1.0MHz, SOJ package) Symbol Parameter'") Conditions Max. | Unit CIN Input Capacitance VIN = 3dV 5 pF Cout Output Capacitance VouT = 3dV 7 pF NOTE: 3012 tbl 04 1. This parameter is determined by device characterization, but is not production tested. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE TRUTH TABLE) Grade Temperature GND Vec Commercial 0C ta +70C ov 3.3V +0.3V WE cs Function 3012 tel 05 H Z Z Z Disable Dout_| Read RECOMMENDED DC OPERATING Din__| Write CONDITIONS NOTE: 3012 tbl 02 Symbol Parameter Min. | Typ. | Max. [Unit 1. H= Vin, L = Vil, X = Don't Care Vcc Supply Voltage 3.0 3.3 3.6 Vv GND Supply Voltage 0 0 0 Vv ViH input High Voltage 2.0 |Vec+0.3] V Vit Input Low Voltage [0.5 | 0.8 Vv NOTE: 3012 tol 06 1. Vit (min.) = -1.0V for pulse width less than 5ns, once per cycle. 9.1 2IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS" 2) (Voc = 3.3V + 0.3V, VLC = 0.2V, VHC = Vcc - 0.2V) 713256SL20 713256SL25 | 713256SL30 Symbol Parameter Power Com'l. Coml. Com'l. Unit icc Dynamic Operating Current CS < ViL, Outputs SL 95 90 85 mA Open, Vcc = Max., f = fax) IsB Standby Power Supply Current (TTL Level) SL 3 3 3 mA CS = Vin, Vcc = Max., Outputs Open, f = faax!2) IsBt Full Standby Power Supply Current (CMOS Level) SL 0.5 0.5 05 mA CS 2 Vic, Vcc = Max., f=0 NOTES: 3012 thi 07 1. All values are maximum guaranteed values. 2. fMax = 1/tRc, only address inputs cycling at fmax: f = 0 means that no inputs are cycling. AC TEST CONDITIONS Reference Levels 1.5V Reference Levels 1.5V AC Test Load land 2 3012 tol 08 3.3V 3.3V 3200, 3200 DATAoUT DATAOUT 350Q 30pF* 3500 5pF* 3012 drw 03 3012 drw 04 Figure 1. AC Test Load Figure 2. AC Test Load (for tcLz, toLz, tcHz, toHz, tow, twHz) Includes scope and jig capacitances DC ELECTRICAL CHARACTERISTICS Vec = 3.3V+0.3V Test Condition Vcc = Max., ViN = GND to Vcc Symbol Parameter tu Current loL = Vcc = Min. IDT713256SL Max. Unit 2 0.4 3012 tbl 09 9.1IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES Vic = 0.2V, VHC = Vcc - 0.2V Typ. Max. Vec @ Vec @ Symbol Parameter [fest Condition Min. 2.0v 2.0V Unit VDA VCC for Data Retention _ 2.0 _ Vv IccpR Data Retention Current _- _ 300 HA iCDR Chip Deselect to Data Retention Time CS = Vic 0 _ _ ns tal?) Operation Recovery Time tacl?} = = ns NOTES: 3012 thi 10 1. Ta= +25C. 2. thc = Read Cycle Time 3. This parameter is guaranteed, but is not production tested. LOW Vcc DATA RETENTION WAVEFORM DATA t* RETENTION -*4 TTT oT MODE Va Voc 3.0V% 7 3.0V tcDR VoR22V tr 3012 drw 05 9.1 4IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Vcc = 3.3V +0.3V, ALL TEMPERATURE RANGES) 713256SL20 713256SL25 713256SL30 Parameter Min. Max. Min. Max. Min. Max. Unit Read tRC Read Time 20 25 30 tAA Address Access Time TtACS Select Access Time tcLz Select to in Low-Z\! tOE Enable to toLz Enable to tCHZ Select to tOHZ Disable to in Zz! tOH Hold from Address Write two Write Time tcw Chip Select to End-of-Write Taw Address Valid to End-of-Write tas Address Set Time twe Write Pulse Width twR Write Time tow Data to Write Time ns 1DHi Data Hold from Write Time 0 0 ns tOH2 Data Hold from Write Time 0 0 ns tow Active from End-of-W! ns NOTE: 3012 tbl 11 1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested 9.1 5(DT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1) < tAC >| ADDRESS an touz tcnz DATAouT DATA VALID 3012 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2" 2: 4) j~ tRC ra ADDRESS y at ton | | tox DATAouT PREVIOUS DATA VALID DATA VALID 3012 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 31:3: 4) cs \ poud__tAcs tonz (5) at teiz{5) > DATAouT DATA VALID 3012 drw 08 NOTES: WE is HIGH for read cycie. . Device is continuously selected, CS = Vit. . Address valid prior to or coincident with CS transition low. OE = Vit. . Transition is measured +200mV from steady state Oh wn 9.1IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)": 2:3: 5: 7) a twe > ADDRESS x x toHz () p OE N taw - y~- cs \ / e tas rlee twe (7) p\twR r| WE f twuz () | tow ~ DATAout + (4) (4) A\ tow DH DATAIN DATA VALID 3012 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)" 2: 3: 5) two ADDRESS x x TAW > os x ke TAS tow (7) a tyes am = /_ Pe tOW epetDH2 DATAIN DATA VALID 3012 drw 10 NOTES: . WE or CS must be HIGH during all address transitions. . A write occurs during the overlap of a LOW CS and a LOW WE. . twr is measured from the earlier of CS or WE going HIGH to the end of the write cycle. During this period, I/O pins are in the output state so that the input signals must not be applied. . If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. . Transition is measured 200mV from steady state. . If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of twe or (twHz + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified twr NOOARONS 9.1 7IDT713256SL 3.3V CMOS STATIC RAM 256K (32K x 8-BIT) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT713256 XX XX X x Power Speed Package Process/ Temperature | Range | Blank Commercial (0C to +70C) 300 mil SOJ (SO28-5) 25 Speed in nanoseconds | 30 SL SL Low Power 3012 dew 11 9.1