SIMATIC S5
Order No.
6ES5 997-3UA22, Release 03
S5-135U/155U
CPU 922/CPU928/CPU 928B/CPU 948
List of Operations
C79000-H8576-C124-03
This publication is protected by copyright. Transmission and reproduction of this
do cument as wel l as use and noti fica tion of i ts c onten ts ar e not perm it ted w ithou t
expr e ss au th ority. Th is al so ap pl ie s to tra n sl at ion i nto ot he r lang ua ge s.
Offenders will be liable for damages. All rights, including rights created by patent
gr an t or r egi st rat ion of a ut il i ty mo de l or de si g n, ar e res er ve d.
Technical data subject to alteration.
Copyright © Siemens AG 1993 All Rights Reserved
Order No.: 6ES5 997-3UA22
Order from: Elektronikwerk Karlsruhe
Printed in the Federal Republic of Germany
Contents
Page
Explanatory Notes on the List of
Operations 1
Explanatory Notes on the Operands 3
Explanatory Notes on the Formal
Operands (Block Parameters) 7
Basic Operations 10
Boolean Logi c Operations 10
Set/Reset Operations/Binary 16
Load Operations 20
Transfer Operations 28
Timer Operations 34
Counter Operations 36
Arithmetic Operations 38
Comparison Operations 42
Block Call Operations 48
Block End Operations 52
Null Operations 54
Stop Operation 54
Display Construction Operations 54
Supplementary Operations 56
Logic Operations 56
Digital Operations 56
Bit Test Operations 58
Set/Reset Operations 62
Timer and Counter Operations 66
Load and Transfer Operations 70
Conversion Operations 74
Shi ft and Rotate Operations 76
Jump Operations 78
Other Operations 80
C79000-J8576-C124-03 I
Page
System Operations 86
Load and Transfer Operations 86
Arithmetic Operations 94
Jump Operations 96
Other Operations 96
Set Operations 100
Register to Register Transfer Operations 102
Load, Transfer and Arithmetic Operations
with the Base Address Register 102
Access to local, word-oriented memory 106
Test/set Busy location (global area) 106
Access to global, byte-oriented memory 108
Access to global, word-oriented memory 110
Open page 110
Test/set Busy location (page area) 110
Access to byte-oriented pages 112
Access to word-oriented pages 114
Machine Code Listing 116
Alphabetical Index of Operations
(with Machine Code) 131
Explanatory Notes on the
Condition Codes 144
List of Organization Blocks 146
OBs for Program Processi ng 146
OBs for Start-up Procedures 148
OBs for Handling Controller Errors
in the CPU 922/928/928B 150
OBs for Handling Controller Errors
in the CPU 948 154
OBs with Special Functions 156
II C79000-J8576-C124-03
Exp lan ato ry Notes on
the Lis t of Op era tions
Abbreviations Explanations
ACCU 1
ACCU 2
ACCU 3
ACCU 4
The four 32-bit accumulators
ACCU 1-H
ACCU 2-H
ACCU 3-H
ACCU 4-H
The high word of the four 32-bit accumulators
ACCU 1-L
ACCU 2-L
ACCU 3-L
ACCU 4-L
The low word of the four 32-bit accumulators
Condition codes
CC0/CC1
OV
OS
Y
1
0
N
Co nditi on codes 0/1 (see pa ges 119, 12 0)
Overfl ow; this conditio n code is set e.g. if the
number range is exceeded during arithmetic
operations.
Stored overflow; this condition code is set if
at least one arithmetic operation causes an
overflow (for detection of arithmetic errors).
The cond iti on code is set/ reset depe nd ing o n
the statement.
Condition code is set
Condition code is reset
Condition code is not affected
(see Explanatory Notes on the
Condition Codes)
Forma l ope ran d Sym bolic labe l with u p to 4 characte rs. The
f irst chara ct er m u st be a letter
(see page 7ff).
C79000-J8576-C124-03 1
Abbreviations Explanations
PI Process Image → memory areas for data
that are read from the I/Os and/or trans-
ferred to the I/Os. The I/O image remains in
these memory areas during one program
c ycle an d is upda ted p rior to the n ext. The
binary logic and set/reset operations always
us e the PI.
PII/PIQ Process Image of Inputs/Outputs
RLO Bi nar y Resu lt of Logic Operat ion (1 bi t)
RLO-dependent
command flo w?
Y
Y
Y
N
C om mand exe cution de pend s on the RL O
The statement is executed only if RLO = "1".
The statement is executed only on the
leading edge of the RLO
(RLO chan ge s from "0 " to "1" ).
The statement is executed only after the
RL O change s from "1 " to "0"
(falling edge).
The statement is always executed.
RLO reset?
Y
1
N
Command affects the RLO
RLO is set to "1" or "0".
Please refer to the function description of the
corresp on di ng statemen t for exp lanation on
how the new RLO is formed.
RLO is set to "1".
RLO does not change.
RLO reloaded? Y
N
The RLO does not change. The RLO cannot
be co mbin ed any furt he r. If a comm a nd
which reloads the RLO is followed by a
binary logic operation, the scan result is
reloaded and a new RLO is started.
The RLO can be combined further.
STL St ate m en t L ist m eth od of re pre se nta tion in
STEP 5.
2C79000-J8576-C124-03
Exp lan ato ry Notes on the
Operands
Abbr Description
Pe rmis sible Value
Range for
Operands Size
in
Bits
CPU Range
BN Byte constant
(fixed-point no.) all - 128 to +127 8
C Counter a ll 0 to 255 -
D Data bit all 0.0 to 255.15 1
DB Data block 922/
928/
928B
948
3 to 255
2 to 255
-
DD Data double word all 0 to 254 32
DH Double word constant
(hexadecimal) all1) 0 to FFFF FFFF 32
DL Data word (left-hand
byte) all 0 to 255 8
DR Data word (right-hand
byte) all 0 to 255 8
DW Data word (in a DB or
DX) all 0 to 255 16
DX Data block (extension) 922/
928
928B/
948
1 to 255
3 to 255
-
F Flag all 0.0 to 255.7 1
FB Functio n block all 0 to 255 -
FD Flag do uble word all 0 to 252 3 2
FW Flag word all 0 to 254 16
FX Functio n block
(extension) all 0 to 255 -
1) CPU 922 from ver sion 09
C79000-J8576-C124-03 3
Abbr Description
Pe rmis sible Value
Range for
Operands Size
in
Bits
CPU Range
FY Flag byte all 0 to 255 8
I Input (in PII) all 0.0 to 127 .0 1
I B Input by te ( in PII) all 0 to 127 8
ID Input double word
(in PII) all 0 to 124 32
IW Input word (in PII) all 0 to 126 16
KB Constant (1 byte) all 0 to 255 8
KC Constant (count) all 0 to 999 16
KF Constant
(fixed-point number) all -32768
to +32767 16
KG Constant
(floating-point number) all ±0,1701412.1039
to
±0,1469368.10-38
32
KH Constant
(hexadecimal code) all 0 to FFFF 16
KM Constant
(2-byte bit pattern) all Arbitrar y bit
pattern 16
KS Constant (2 characters) all ASCII characters 16
KT Constant (time) all 0.0 to 999.3 16
KY Constant (2 bytes) all 0 to 255
(per byte) 16
OB Organization block all 1 to 39 -
OB Operating system
special function 922/
928/
928B
948
110 to 255
121 to 255
-
OW Word of the extended
I/O area
(without PII/PIQ update)
all 0 to 254 16
OY Byte of the extended
I/O area
(without PII/PIQ update)
all 0 to 255 8
4C79000-J8576-C124-03
Abbr Description
Permissible Value
Ran ge for
Operands Size
in
Bits
CPU Range
PB Program block all 0 to 255 -
PW Peripheral word of
- digital inputs
(direct reading of the PII)
- an alo g inputs/d ig ital input s
(without PII update)
-digital ou tputs
(with PIQ update)
- analog outpu ts/di gital
ou tput s
(without PIQ update)
all
0 to 126
128 to 25 4
0 to 126
128 to 25 4
16
PY Peripheral byte of
- digital inputs
(direct reading of the PII)
- an alo g inputs/d ig ital input s
(without PII update)
- digital outputs
(with PIQ update)
- analog outpu ts/di gital
outputs
(without PIQ update
all
0 to 127
128 to 25 5
0 to 127
128 to 25 5
8
Q Output (with PIQ update) all 0.0 to 127.0 1
QB Output byte
(with PIQ update) all 0 to 12 7 8
QD Outp ut doub le word
(with PIQ update) all 0 to 12 4 32
QW Outp ut word
(with PIQ update) all 0 to 12 6 16
RI Interface data area all 0 to 255 16
RJ Extended interface data
area all 0 to 25 5 16
RS System data area all 0 to 255 16
RT Extended system data area all 0 to 255 16
C79000-J8576-C124-03 5
Abbr Description
Permissible Value
Range for
Operands Size
in
Bits
CPU Range
S Flag, additional (S flag) 922
928
928B
948
n/a
n/a
0.0 to 1023.7
0.0 to 4095.7
1
SB Sequence block all 0 to 255 -
SD Fl ag do uble word,
additional
(S fla g doub le word )
922
928
928B
948
n/a
n/a
0 to 1020
0 to 4092
32
SW Flag word, additional
(S flag word) 922
928
928B
948
n/a
n/a
0 to 1022
0 to 4094
16
SY Fla g byte, additio nal
(S flag byte) 922
928
928B
948
n/a
n/a
0 to 1023
0 to 4095
8
T Timer all 0 to 255 -
6C79000-J8576-C124-03
Exp lan ato ry Notes on the
Form al Op era nds
(Blo ck Parameters )
A maximum of 126 different formal operands (nos. 1 to 126) can be
programmed per FB/FX.
Parameter
Type Data Type Actual Operands
Permitted
I, Q BI for an op era nd with
bit address I, Q, F
BY for an opera nd with
byte addre ss IB, QB, FY, DL, DR,
PY, OY
W for an op era nd with
word address IW, QW, FW, DW,
PW, OW
D for an operand
with double word
address
ID, QD, FD, DD
D KM for a b inary patte rn
(16 bits) Constants
KY for 2-byte serial
absolute value
numbers from 0 to 255
KH for a 4 d igi t
hexa dec imal nu mber
KS for a characte r
(max. 2 alphanum.
characters)
KT for a t im e i n BCD
with time base
1 .0 t o 999.3
KC for a count valu e
in BCD
from 0 to 999
KF for a fi xed-p oi nt
numb er from
- 32768 to +32767
KG for a floa tin g-p oi nt
numb er from
±0,1701412 . 1039 to
±0,1469368 . 10-38
C79000-J8576-C124-03 7
Parameter
Type Data Type Actual Operands
Permitted
B Type specifica tion not
permitted DB D ata bloc ks:
statement C DB
is executed
FB Function blocks
(pe rm itte d with ou t
parameters only)
are called uncon-
ditionally:
JU FB
OB Organization blocks
are called uncon-
ditionally:
JU OB
PB Program blocks
are called uncon-
ditionally :
JU PB
SB Sequence block s
are called
unconditionally:
JU SB
T Type specificatio n n ot
permitted T
C Type specifica tion not
permitted C
8C79000-J8576-C124-03
Intentionally blank!
C79000-J8576-C124-03 9
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Ope rati on
with this
time s in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Boolean Logic Operations
All logic opera tio ns gen era te a re sult (RLO).
The first RLO in a string of logic operations generates the new RLO
fro m the signal status scan ne d. All sub sequ en t log ic opera tio ns
generate the new RLO from the signal status scanned, and gate it
with the old RLO. The string of logic opera tio ns is te rm inate d by
an ope ration that relo ad s the RLO (e.g ., se t/rese t ope rati on ).
A I 0.0 to 127.7 N N N N N Y N 20-25 0.9 0.57 0.18 S can inp ut for "1" and comb in e wi th RLO th rou gh
log ic AND
A Q 0.0 to 127.7 N N N N N Y N 20-25 0.9 0.57 0.18 Scan output for "1" and combine with RLO through
log ic AND
A F 0.0 to 255.7 N N N N N Y N 20-25 0.9 0.57 0.18 Scan flag for "1" and combine with RLO through
log ic AND
AS 0 .0 to 1023.7 N N N N N Y N 3.7 Scan S flag for "1" and combine with RLO through
log ic AND
S 0 .0 to 4095.7 N N N N N Y N 0 .39
A D 0.0 to 255.15 N N N N N Y N 37-3 8 29 3.4 0 .77 Scan a bit in the data block (DB/DX) for "1" and
combine with RLO through logic AND
A T 0 to 25 5 N N N N N Y N 20 -25 0.9 0.57 0.18 Scan a time for "1" and combine with RLO through
log ic AND
A C 0 to 255 N N N N N Y N 19 -23 0 .9 0.5 7 0.18 Scan a counter for "1" and combine with RLO with
RLO through logic AND
AN I 0.0 to 127.7 N N N N N Y N 20-2 5 0.9 0.57 0.18 S can inp ut for "0" and comb in e wi th RLO throu gh
log ic AND
AN Q 0.0 to 12 7.7 N N N N N Y N 20-25 0.9 0 .57 0. 18 Scan output for "0" and combine with RLO through
log ic AND
10 11
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
time s in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Boo lean L og ic Operati ons (co ntin ued )
AN F 0 .0 to 255.7 N N N N N Y N 20-25 0.9 0.57 0 .18 Scan flag for "0" and combine with RLO through
logic AND
AN S 0 .0 to 1023.7 N N N N N Y N 3 .7 Scan S flag for "0" and combine with RLO through
logic AND
S 0 .0 to 4095.7 N N N N N Y N 0.39
AN D 0.0 to 25 5.15 N N N N N Y N 36-41 29 3 .4 0.77 Scan a bit in the data block (DB/DX) for "0 " and
combine with RLO through logic AND
AN T 0 to 255 N N N N N Y N 22 0. 9 0 .57 0 .1 8 Scan a time for "0" and combine with RLO through
logic AND
AN C 0 to 255 N N N N N Y N 18-2 0 0. 9 0.57 0.18 Scan a counter for "0" and combine with RLO
th rou gh lo gic AN D
O I 0.0 to 127.7 N N N N N Y N 19-21 0.9 0.57 0.18 Scan input for "1" and combine with RLO through
logic OR
O Q 0.0 to 127.7 N N N N N Y N 19-21 0.9 0.57 0.18 Scan output for "1" and combine with RLO through
logic OR
O F 0.0 to 257.7 N N N N N Y N 19-21 0.9 0.57 0.18 Scan flag for "1" and combine with RLO through
logic OR
OS 0 .0 to 1023.7 N N N N N Y N 3 .7 Scan S flag for "1" and combine with RLO through
logic OR
S 0 .0 to 4095.7 N N N N N Y N 0.39
O D 0.0 to 25 5.15 N N N N N Y N 3 5-3 8 28 3.4 0.77 Scan a bit in the data block (DB/DX) for "1" and
combine with RLO through logic OR
12 13
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
time s in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Boo lean L og ic Operati ons (co ntin ued )
O T 0 to 255 N N N N N Y N 18-21 0.9 0 .5 7 0 .18 Scan a time for "1" and combine with RLO through
logic OR
O C 0 to 25 5 N N N N N Y N 17-2 0 0. 9 0.57 0.18 Scan a counter for "1" and combine with RLO
th rou gh lo gic O R
ON I 0.0 to 127.7 N N N N N Y N 1 8-2 1 0.9 0.57 0. 18 Scan input for "0" and combine with RLO through
logic OR
ON Q 0.0 to 127.7 N N N N N Y N 18-21 0.9 0.57 0 .18 Scan output for "0" and combine with RLO through
logic OR
ON F 0 .0 to 255.7 N N N N N Y N 18-21 0.9 0.57 0 .18 Scan flag for "0" and combine with RLO through
logic OR
ON S 0 .0 to 1023.7 N N N N N Y N 3 .7 Scan S flag for "0" and combine with RLO through
logic OR
S 0 .0 to 4095.7 N N N N N Y N 0.39
ON D 0.0 to 255.15 N N N N N Y N 35-3 7 28 3.4 0.77 Scan a bit in the data block (DB/DX) for "0" and
combine with RLO through logic OR
ON T 0 to 25 5 N N N N N Y N 19-21 0.9 0 .5 7 0 .18 Scan a time for "0" and combine with RLO through
logic OR
ON C 0 to 255 N N N N N Y N 16 -2 0 0. 9 0 .5 7 0 .18 Scan a counter for "0" and combine with RLO
th rou gh lo gic O R
O - N N N N N Y Y 12-14 0.8 0.57 0.18 Co m bine AND operatio ns throu gh lo gic OR
14 15
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
time s in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Boo lean L og ic Operati ons (co ntin ued )
A( - N N N N N Y Y 20 1.2 0.57 0.18 Com bine expre ssion s enclosed with pa renth eses
(8 levels) through logic AND
O( - N N N N N Y Y 21 1.2 0.57 0.18 Co m bine expre ssions en closed with pa renth eses
(8 levels) through logic OR
) - N N N N N Y N 20-22 1.2 0.57 0.18 Right parenthesis
(End of operation in parentheses)
Set/Reset O perat ions, Binary
S I 0.0 to 127.7 N N N N Y N Y 19-21 1.2 0.63 0.32 The input of the process image is set to "1" if the
RLO is "1"
S Q 0.0 to 127.7 N N N N Y N Y 19-21 1.2 0.63 0.32 The output of the process image is set to "1" if the
RLO is "1"
S F 0.0 to 255.7 N N N N Y N Y 19-21 1.2 0.63 0.32 The flag is set to "1" if the RLO is "1"
SS 0 .0 to 1023.7 N N N N Y N Y 3 .9 The S flag is set to "1" if the RLO is "1"
S 0 .0 to 4095.7 N N N N Y N Y 0.48
S D 0.0 to 255.15 N N N N Y N Y 35-37 28 0.63 0. 77 The bi t in th e data block (DB/DX) is set to "1" i f the
RLO is "1"
R I 0.0 to 127.7 N N N N Y N Y 18-22 1.2 0.63 0.32 T he input of th e process imag e is reset to "0" if the
RLO is "1"
R Q 0.0 to 127.7 N N N N Y N Y 18-22 1.2 0.63 0.32 The output of the process image is reset to "0" if
the RLO is "1"
16 17
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
time s in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Set/Reset O perat ions, Binary (contin ued)
R F 0.0 to 127.7 N N N N Y N Y 18-22 1.2 0.63 0.32 T he flag is reset to "0" if the RLO is "1"
RS 0 .0 to 1023.7 N N N N Y N Y 3 .9 The S flag is reset to "0" if the RLO is "1"
S 0 .0 to 4095.7 N N N N Y N Y 0.48
R D 0.0 to 25 5.15 N N N N Y N Y 33-38 27 3.4 0.77 The bit in the data block (DB/DX) is reset to "0" if
the RLO is "1"
= I 0.0 to 127.7 N N N N N N Y 20 1.2 0.63 0.32 The value of the RLO is assigned to the input in the
process im age
= Q 0.0 to 127.7 N N N N N N Y 20 1.2 0.63 0.32 The value of the RLO is assigned to the output in
the process image
= F 0.0 to 255.7 N N N N N N Y 20 1.2 0.63 0.32 The value of the RLO is assigned to the flag
=S 0 .0 to 1023.7 N N N N N N Y 3.9 The value of the RLO is assigned to the S flag
S 0 .0 to 4095.7 N N N N N N Y 0.48
= D 0.0 to 255.15 N N N N N N Y 37 29 3 .4 0.77 The value of the RLO is assigned to the bit in the
data block (DB/DX)
18 19C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Load Operat ion s
The original contents of ACCU 1 are passed on to ACCU 2 before
the byte, word or doub le word addre ssed is lo ad ed in to ACCU 1 .
During byte and word operations, the high bits (not loaded) of
ACCU 1 are deleted (bits 8 to 31 for byte operations, bits 16 to 31
for word operations). If you use ACCU 3 and ACCU 4, you must
insert the "ENT" operation from the supplementary operation set
to restore the accumulator contents.
L IB 0 to 12 7 N N N N N N N 22 12 0.81 0.18 Load an input byte from the PII into ACCU 1-L
L IW 0 to 126 N N N N N N N 22 1 3 0. 94 0. 50 Loa d an in put word from th e PII into ACCU 1-L:
by te n → bits 8-15, byte n+1 → bits 0-7
L ID 0 to 24 4 N N N N N N N 24 16 1.6 0.71 Load an input double word from the PII into
ACCU 1:
by te n → bits 24-31, byte n+1 → bits 16-23,
by te n+2 → bits 8-15, byte n+3 → bits 0-7
L Q B 0 to 12 7 N N N N N N N 2 1 1 2 0. 81 0. 18 Load an outp ut byte from t he PIQ into ACCU 1-L
L Q W 0 to 126 N N N N N N N 2 2 12 0.94 0 .50 L oad an outp ut word fro m the PIQ i nto ACCU 1 -L:
by te n → bits 8-15, byte n+1 → bit s 0-7
L Q D 0 to 124 N N N N N N N 2 4 16 1 .6 0.71 L oa d an ou tp ut double word from the PIQ into
ACCU 1:
by te n → bits 24-31, byte n+1 → bits 16-23,
byte n+2 → bits 8-15, byte n+3 → bit s 0 -7
L FY 0 to 25 5 N N N N N N N 2 2 1 2 0. 81 0. 18 Load a flag byte into ACCU 1-L
L FW 0 to 254 N N N N N N N 2 2 12 0.94 0 .50 Load a flag word into ACCU 1-L:
by te n → bits 8-15, byte n+1 → bits 0 -7
20 21
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad Operat ions (con tinued )
L F D 0 to 252 N N N N N N N 24 16 1.6 0.71 Load a flag double word into ACCU 1:
by te n → bits 24-31, byte n+1 → bits 16-23,
byte n+2 → bits 8-15, byte n+3 → bit s 0 -7
LSY 0 to 1023 N N N N N N N 2.4 Load an S flag byte into ACCU 1-L
SY 0 to 4095 N N N N N N N 0 .3 9
LS W 0 to 1022 N N N N N N N 2.5 Load an S flag word into ACCU 1-L:
Byte n → bit s 8-15,byte n+1 → bit s 0- 7
S W 0 to 4094 N N N N N N N 0.59
LSD 0 to 1020 N N N N N N N 3.1 Load an S flag double word into ACCU 1:
by te n → bits 24-31, byte n+1 → bits 16-23,
byte n+2 → bits 8-15, byte n+3 → bit s 0 -7
SD 0 to 4092 N N N N N N N 0. 77
LDH0 to
FFFF FFFF NNNNNNN20.1
1) 15 1.7 0.57 L oad a const ant (hexadecimal code as d ou ble
wo rd) into ACCU 1
L D L 0 to 25 5 N N N N N N N 24 14 1.7 0.50 L oa d the left byte of a d at a word of the current data
block into ACCU 1-L
1) Ope rat ion po ssible from ver sio n 09 onward s.
22 23
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
time in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad Operat ions (con tinued )
L DR 0 to 255 N N N N N N N 2 4 14 1 .7 0.50 Load the right byte of a data word of the current
data block into ACCU 1-L
L DW 0 to 255 N N N N N N N 24 14 1 .5 0.50 L oa d a d at a word of the current data block in to
ACCU 1-L
L DD 0 to 254 N N N N N N N 2 5 17 2 .0 0.68 Load a flag double word into ACCU 1:
wo rd n → bits 16-31, word n+1 → bits 0-7
L KB 0 to 25 5 N N N N N N N 1 9 8 0.63 0. 18 Load a const ant (1-byte nu mber) int o ACCU 1-L
L KC 0 to 999 N N N N N N N 20 1 4 1.2 0.39 Loa d a const an t (count in BCD) into ACCU 1-L
LKF -32768 to
+32767 N N N N N N N 20 14 1.2 0.39 Load a constant (fixed-point number) into
ACCU 1-L
L KG (see page 4) N N N N N N N 21 15 1.7 0.57 Loa d a con stan t (floatin g p oint numb er) into ACCU
1-L
L KH 0 to FFFF N N N N N N N 2 0 14 1 .2 0.39 Loa d a con stan t (hexad ecimal co de) into
ACCU 1-L
LKM bit pattern,
16 bit N N N N N N N 20 14 1.2 0.39 Load a constant (bit pattern) into ACCU 1-L
LKS (2 ASCII
characters) N N N N N N N 20 14 1.2 0.39 Loa d a constan t (2 chara cters in ASCII format) into
ACCU 1-L
L KT 0.0 to 999.3 N N N N N N N 20 14 1.2 0.39 Load a constant time (time in BCD) into ACCU 1-L
LKY 2 bytes
0 to 25 5 e ac h N N N N N N N 20 14 1.2 0.39 L oa d a const ant (2-byte nu mber) int o ACCU 1-L
24 25
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad Operat ions (con tinued )
L PY 0 to 25 5 N N N N N N N 301) 161) 1.4 1) 1.7 1) Load a peripheral byte from the digital/analog
inputs into ACCU 1-L
L PW 0 to 254 N N N N N N N 311) 211) 2.1 1) 2.69 1) Load a peripheral word from the digital/analog
inputs into ACCU 1-L:
by te n → bits 8-15,byte n+1 → bit s 0-7
L O Y 0 to 25 5 N N N N N N N 301) 161) 1.4 1) 1.7 1) Load a byte of the extended I/O area into
ACCU 1-L
L O W 0 to 254 N N N N N N N 311) 211) 2.1 1) 2.7 1) L oa d a word of the extend ed I/ O are a i nto
ACCU 1-L:
by te n → bits 8-15,byte n+1 → bit s 0-7
L T 0 to 255 N N N N N N N 25 1 4 0. 81 0. 30 Load a time in binary cod e into ACCU 1-L
L C 0 to 255 N N N N N N N 24 14 0.81 0 .30 L oad a count in bi nar y cod e into ACCU 1-L
L C T 0 to 25 5 N N N N N N N 3 8 1 6 3.7 0.39 Loa d a t ime i n BCD into ACCU 1-L
(including binary-BCD c onversion)
L C C 0 to 255 N N N N N N N 35 1 5 3.7 0.39 Load a count in BCD into ACCU 1-L
(including binary-BCD c onversion)
1) Executi on tim e fo r sing le proce ssing ope rati on an d for
immediate bus access in multiprocessing operations. I/Os
acknowledge within 0.1 µs or proportionally longer
exec u ti on time for longer ac knowledgement time.
26 27
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Transfer Operations
The contents of ACCU 1 are transferred to the operand specified.
T IB 0 to 127 N N N 0 N N N 1 5 11 0.75 0 .18 T ransfer the conte nts of ACCU 1-L (bit s 0-7) to an
inp ut byte (int o the PII)
T IW 0 to 12 6 N N N 0 N N N 1 5 1 1 0. 88 0. 41 Transfer the conte nts of ACCU 1-L (bit s 0-7) to an
inp ut word (into PII):
bits 8-15 → byte n, bits 0-7 → byte n+1
T I D 0 to 124 N N N 0 N N N 2 0 15 1 .9 0.59 T ran sfer the contents o f ACCU 1 to an inp ut doub le
wo rd (int o the PII):
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
T QB 0 to 127 N N N 0 N N N 15 11 0.75 0 .18 T ransfer the conte nts of ACCU 1-L (bit s 0-7) to an
outp ut by te ( int o the PIQ )
T QW 0 to 126 N N N 0 N N N 1 5 11 0.88 0 .41 T ransfer the conte nts of ACCU 1-L (bit s 0-7) to an
output word (into the PIQ):
bits 8-15 → byte n, bits 0-7 → byte n+1
T QD 0 to124 N N N 0 N N N 20 15 1.9 0 .5 9 Tran sfer the contents o f ACCU 1 to an ou tput
double word (into the PIQ):
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
T FY 0 to255 N N N 0 N N N 15 11 0.75 0.18 T ran sfer th e contents of ACCU 1-L to a fla g b yte
(bits 0-7)
T FW 0 to 254 N N N 0 N N N 15 11 0. 88 0.41 Tran sfer the content s o f ACCU 1-L to a fla g wo rd:
bits 8-15 → byte n, bits 0-7 → byte n+1
T F D 0 to 252 N N N 0 N N N 20 1 5 1.9 0.59 Tran sfer the contents o f ACCU 1 to a flag double
word:
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
28 29
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Transfer Operations (continued)
TSY 0 to 1023 N N N 0 N N N 2.3 Tran sfer the contents of ACCU 1-L to an S flag
byte (bits 0-7)
SY 0 to 4095 N N N 0 N N N 0.39
TS W 0 to 1022 N N N 0 N N N 2 .3 Tran sfer th e contents of ACCU 1-L to an S flag
word:
bits 8-15 → byte n, bits 0-7 → byte n+1
S W 0 to 4094 N N N 0 N N N 0.41
TSD 0 to 1020 N N N 0 N N N 3.4 T ransfer the contents o f ACCU 1 t o an S flag
doub le word :
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
SD 0 to 4092 N N N 0 N N N 0. 59
T DL 0 to 255 N N N 0 N N N 2 2 15 1 .5 0.68 T ran sfer the contents of ACCU 1-L (bits 0-7) to a
data word (left byte) in a DB/DX
T D R 0 to 255 N N N 0 N N N 22 14 1 .4 0.68 T ran sfer the contents of ACCU 1-L (bits 0-7) to a
data word (right byte) in a DB/DX
T D W 0 to 255 N N N 0 N N N 2 2 1 4 1.4 0.41 Tran sfer the contents of ACCU 1-L (bits 0-15) to a
data word in a DB/DX
T D D 0 to 254 N N N 0 N N N 25 18 1 .9 0.59 Transfer the contents of ACCU 1 to a data double
word in a DB/DX:
bits 16-31 → word n, bits 0-15 → word n+1
30 31
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Transfer Operations (continued)
TPY 0 to 127 N N N 0 N N N 27 1) 15 1) 2.0 1) 1.6 1) T ran sfer the content s o f ACCU 1-L (bits 0-7) to a
periphe ral byte of the digi tal or an alo g out puts. The
PI Q is also c orrec ted.
PY 128 to 255 N N N 0 N N N 27 1) 14 1) 1.21) 1.5 1) T ran sfer the contents of ACCU 1-L (bi ts 0-7 ) to a
periphe ral byte of the digi tal or an alo g out puts.
T
P W 0 to 126 N N N 0 N N N 30 1) 21 1) 3.2 1) 2. 6 1)
Tran sfer the content s o f ACCU 1-L (bits 0-15) to a
peripheral word of the digital or analog outputs:
bits 8-15 → byte n;bits 0-7 → byte n+1
The PIQ is also correc ted .
P W 128 to 25 4 N N N 0 N N N 30 1) 18 1) 2.0 1) 2.4 1) T ran sfer the contents of ACCU 1-L (bits 0-15) to a
peripheral word of the digital or analog outputs:
bits 8-15 → byte n;bits 0-7 → byte n+1
T OY 0 to 255 N N N 0 N N N 23 1) 14 1) 1.2 1) 1.5 1) T ransfer the contents of ACCU 1-L (bit s 0-7) to a
byte of the extended periphery of the digital or
anal og output s (no proc e ss image).
T OW 0 to 254 N N N 0 N N N 26 1) 18 1) 2.0 1) 2.4 1) Transfer the contents of ACCU 1-L to a word of the
extended periphery of the digital or analog outputs
(no process image):
bits 8-15 → byte n;bits 0-7 → byte n+1
1) Executi on tim e fo r sing le proce ssing ope rati on an d for
immediate bus access in multiprocessing operation. I/Os
acknowledge within 0.1 µs or proportionally longer
exec u ti on time for longer ac knowledgement time.
32 33
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Timer O peratio ns
SP T0 to 255 NNNNY↑NY 20/
42 1) 1.2/
18 1) 3.6 0.18 St art timer ( stored in ACCU 1 -L) as pulse
(start timer with continuous enable)
SE T0 to 255 NNNNY↑NY 21/
43 1) 1.2/
18 1) 3.6 0.18 St art timer ( stored in ACCU 1 -L) as extended pulse
(start timer with one-shot enable)
SDT0 to 255 NNNNY↑NY 20/
45 1) 1.2/
18 1) 3.6 0.18 St art timer ( stored in ACCU 1 -L) as ON de la y
SS T0 to 255 NNNNY↑NY 21/
46 1) 1.2/
18 1) 3.6 0.18 St art timer ( stored in ACCU 1 -L) as stored ON del ay
SFT0 to 255 NNNNY↓NY 22/
44 1) 1.2/
18 1) 3.6 0.18 St art timer ( stored in ACCU 1 -L) as OFF d el ay
R T0 to 255 NNNNYNY 14/
18 2) 12/
15 2) 1.4 0.18 Reset timer
1) Time a pp lies when "S5 time is not started/S5 tim e is starte d".
2) Time applies when RLO = 0 / RLO = 1.
34 35
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Counter Operations
CUC0 to 255 NNNNY↑NY 18/
23 1) 1.2/
14 1) 2.1 0.18 Counter counts up 1
CDC0 to 255 NNNNY↑NY 18/
24 1) 1.2/
14 1) 2.0 0.18 Counter counts down 1
S C0 to 255 NNNNY↑NY 17/
38 1) 16/
23 1) 3.8 0.18 Set counter with the value stored in ACCU 1-L
(BCD number from 0 to 999)
R C0 to 255 NNNNYNY 12/
16 2) 12/
14 2) 1.4 0.18 Reset counter
1) Time a pp lies when "S5 time is not started/S5 tim e is starte d".
2) Time applies when RLO = 0 / RLO = 1.
36 37
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
wi th thi s
times in µs
not po ssible
CPU Function
C
C
1
C
C
0
O
VO
S
1 2 3 CPU
922 CPU
928 CPU
928B CPU
948
Arith metic Operat ion s
The resu lt (nu me rical value ) of a n arithm eti c ope rat ion is store d in
ACCU 1. All other accumulator contents change as follows:
For +F, -F, xF, :F: For +G, -G, xG, :G, +D, -D:
ACCU-2-L: = ACCU-3-L ACCU 2: = ACCU 3
ACCU-3-L: = ACCU-4-L ACCU 3: = ACCU 4
ACCU-4-L: = ACCU-4-L ACCU 4: = ACCU 4
The o rigina l contents of ACCU 2 -L or ACCU 2 a re lost. Wheth er
the resu lt i s <0, >0 or =0 can be evalu ated via CC0 a nd CC1
(see Explan atory Notes on the Condit ion Code s).
Fixed-point numbers, 16 bits
+F - Y Y Y Y N N N 26-32 15-18 0.94 0.55 Add two fixed-point numbers:
(ACCU 1-L) + (ACCU 2-L)
-F - Y Y Y Y N N N 26-33 15-20 0.94 0.55 Subtract one fixed-point number from another:
(ACCU 2-L) - (ACCU 1-L)
xF - Y Y Y Y N N N 36-39 20-21 7.9 3.2 Multiply one fixed-point number by another:
(ACCU 1-L) x (ACCU 2-L)
:F - Y Y Y Y N N N 27-50 13-24 10.4 3.8 Divide one fixed-point number by another:
(ACCU 2-L) : (ACCU 1-L).
ACCU 1-L: result;
ACCU 2-H: remainder
38 39
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Arith metic Operat io ns (con tinued )
Floating-point numbers, 32 bits
When performing arithmetic operations with a 16-bit mantissa
(default), the eight low bits are set to "0".
+G - YYYYNNN56-86
30-33
1)
31-56
2) 9.1 3.3 Ad d two flo ati ng-point numbe r s:
ACCU 1 + ACCU 2
-G - YYYYNNN56-86
30-42
1)
31-47
2) 9.1 3.5 Subtract one floating-point number from another:
ACCU 1 - ACCU 2
xG - YYYYNNN52-74
29-39
1)
30-66
2)
12.1 1)
20.5 2) 5.2 Multiply one floating-point number by another:
ACCU 1 x ACCU 2
:G - YYYYNNN51-81
28-42
1)
31-69
2)
15.6 1)
23.3 2) 6.3
Divide one floating-point number by another:
ACCU 2: ACCU 1;
Re sult: ACCU 1 -L: mant issa lo w
ACCU 1-H: mantissa high
and exponent
1) Time in the case of 16-bit mantissa (def ault)
2) Time in the case of 24-bit mantissa
40 41
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Comparison Operations
The contents of ACCU 2 (operand) are compared with the
content s of ACCU 1 (operand 2). The RLO is se t to "1"
if the comparison condition is fulfilled or to "0" if it is not fulfilled.
Whether the contents of ACCU 2 are <, > or = those in ACCU 1,
can be evalua ted via CC0 a nd CC1
(see Explan atory Notes on the Condit ion Code s).
Fixed-point numbers, 16 bits
!=F - Y Y 0 0 N Y N 18 14-15 0.88 0.30 Co m pare two fi xed-poi nt numb ers for equal to: if
ACCU 2-L = ACCU 1-L, th e RLO is "1"
><F - Y Y 0 0 N Y N 18 14-15 0.88 0.30 Com pa re two fixed-p oint nu mbers for not equa l to :
if ACCU 2-L ≠ ACCU 1-L, the RLO is "1"
>F - Y Y 0 0 N Y N 18 13-14 0.88 0.30 Co m pare two fi xed-p oi nt numb ers for grea ter tha n:
if ACCU 2-L > ACCU 1-L, the RLO is "1"
>=F - Y Y 0 0 N Y N 18 14-15 0.88 0.30 Com pa re two fixed-p oi nt nu mbers for grea ter tha n
or equal to: if ACCU 2-L ≥ ACCU 1-L, the RLO is "1"
<F - Y Y 0 0 N Y N 18 14-15 0.88 0.30 Compare two fixed-point numbers for less than: if
ACCU 2-L < ACCU 1-L, th e RLO is "1"
<=F - Y Y 0 0 N Y N 18 14-15 0.88 0.30 Compare two fix ed-point numbers for less than or
equal to: if ACCU 2-L ≤ ACCU 1-L, the RLO is "1"
42 43
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Comparison Operations (cont inued)
Floating-point numbers
!=G - Y Y 0 0 N Y N 19-27 17-19 1.9 1.4 Co m pa re two floatin g-p oint nu mbers for equ al to: if
ACCU 2 = ACCU 1, the RLO is "1"
><G - Y Y 0 0 N Y N 19-27 17-18 1.9 1.4 Co m pare two floa ting-p oi nt numbers fo r n ot equa l
to: if ACCU 2 ≠ ACCU 1, the RLO is "1"
>G - Y Y 0 0 N Y N 19-27 16-18 1.9 1.4 Compare two floating-point numbers for greater
than: if ACCU 2 > ACCU 1, the RLO is "1"
>=G - Y Y 0 0 N Y N 19-27 17-19 1.9 1.4 Compare two floating-point numbers for greater
tha n o r equal to: if ACCU 2 ≥ ACCU 1, the RLO is
"1"
<G - Y Y 0 0 N Y N 19-27 17-19 1.9 1.4 Compare two floating-point numbers for less than:
if ACCU 2 < ACCU 1, the RLO is "1"
<=G - Y Y 0 0 N Y N 19-27 17-19 1.9 1.4 Compare two floating-point numbers for less than
or equal to: if ACCU 2 ≤ ACCU 1, the RLO is "1"
44 45
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Comparison Operations (cont inued)
Fixed-point double words, 32 bits
!=D - Y Y 0 0 N Y N 19-24 15-16 1.6 0.52 Com pa re two fixe d-p oi nt doub le word s f or e qu al to:
if ACCU 2 = ACCU 1, the RLO is "1"
><D - Y Y 0 0 N Y N 19-24 15-16 1.6 0.52 Co m pare two fi xed-p oi nt doub le word s for n ot
equal to: if ACCU 2 ≠ ACCU 1, the RLO is "1 "
>D - Y Y 0 0 N Y N 19-24 14-16 1.6 0.52 Co m pa re two fixed-poi nt do uble word s for grea te r
than: if ACCU 2 > ACCU 1, the RLO is "1"
>=D - Y Y 0 0 N Y N 19-24 15-17 1.6 0.52 Co m pare two fi xed-p oi nt doub le word s for g rea te r
tha n o r equal to: if ACCU 2 ≥ ACCU 1, the RLO is
"1"
<D - Y Y 0 0 N Y N 19-24 15-16 1.6 0.52 Co m pa re two fixed-poi nt do uble word s for les s
than: if ACCU 2 < ACCU 1, the RLO is "1"
<=D - Y Y 0 0 N Y N 19-24 15-17 1.6 0.52 Co m pare two fi xed-p oi nt doub le word s for les s t ha n
or equal to: if ACCU 2 ≤ ACCU 1, the RLO is "1"
46 47
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Exe cuti on
= Operation
with this
times in µs
not possible
CPU Function
A
N
Z
1
A
N
Z
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Block Call Operati on s
JU PB 0 to 25 5 N N N 0 N N Y 35 28 3.7 1.5/
6.0 5) Un co ndition al program block call
JU FB 0 to 255 N N N 0 N N Y 34 28 3.7 1.5/
6.0 5) Un conditional function block call
DO U F X 0 to 255 N N N 0 N N Y 41 32 4.8 1.5/
6.0 5) Un co nditi on al extende d funct ion call
JU SB 0 to 25 5 N N N 0 N N Y 35 28 3.7 1.5/
6.0 5) Unconditional sequence block call
JU OB1 to 39 N N N 0 N N Y 39 28 4.1 1.5/
6.0 5) Un co nditi onal organizatio n blo ck call
JU OB40 to 255 1) 1) 1) 1) N1) Y2) 2) 2) 2) Unco nditi on al call o f a spe cial fun ction organ izati on
block of the operating system
JC PB 0 to 25 5 N N N 03) Y1Y 12/
35 4) 0.8/
27 4) 3.7 1.6/
6.1 5) Co nd itional program block call (if RLO is "1")
JC FB 0 to 255 N N N 03) Y1Y 12/
35 4) 2.8/
28 4) 3.7 1.6/
6.1 5) Co nditional function block call (if RLO is "1 ")
1) Th e co nd itio n co des are se t or not set according to the 3) The Os bit remains unchanged if RLO = 0 (not for CPU 948).
speci al function executed (see Programming Guide -
Special Function OBs) 4) Time applies when RLO =0 / RLO = 1.
2) For exe cutio n t ime s see List of Specia l Fu nctio ns, pag e 130ff . 5) Time applies when "interruption at block limits".
48 49
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Block Call Operati on s (co ntinu ed)
DOC FX 0 to 25 5 N N N 01) Y1Y 19/
43 2) 14/
41 2) 4.8 1.6/
6.1 6) Cond ition al extende d function b lock call (i f RLO
is "1")
JC SB 0 to 25 5 N N N 01) Y1Y 12/
35 2) 0.8/
27 2) 3.7 1.6/
6.1 6) Conditional sequence block call (if RLO is "1")
JC OB1 to 39 N N N 01) Y1Y 12/
41 2) 0.8/
28 2) 4.1 1.6/
6.1 6) Cond itional organ ization block call
JC OB11 0 t o 255 3) 3) 3) 3) Y1
4) Y5) 5) 5) 5) Co nditi on al call of speci al funct ion o rga nizat ion
block of the operating system
CDB2 to 255 NNNNNNN 0.91 Call a data block
DB 3 t o 255 N N N N N N N 22 19 1.9
CX
DX1 to 255 NNNNNNN 28
Call an extended data block
DX2 to 255 NNNNNNN 22
DX 3 to 25 5 N N N N N N N 2.7 1.0
1) The OS bit rema ins uncha ng ed if RLO = 0 (not for CPU 9 48 ). 4) Only if the RLO = 0 before the OB is called, otherwise the
RLO can be influenced according to the special function
2) Time applies when RLO = 0 / RLO = 1. executed (s ee Programming Guide - Special Function OBs).
3) Th e co nd itio n co des are se t or not set according to the 5) For execution times see List of Special Functions, page 156ff.
speci al function executed (see Programming Guide -
Special Function OBs). 6) Time applies when "interruption at block limits".
50 51
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Block Call Operati on s (co ntinu ed)
GDB 2 to 255 N N N N N N N 498 Generate a data block. The number of its data
words must be stored in ACCU 1 (max. 4091 DW)
DB 3 to 255 N N N N N N N 67 48 76
GX
DX 1 to 255 N N N N N N N 67
Generate an extended data block. The number of
it s da ta words mu st be stored in ACCU 1 (ma x.
4091 DW)
DX 2 to 255 N N N N N N N 48
DX 3 to 255 N N N N N N N 76 493
Block En d Op eratio ns
BE - N N N 0 N N Y 26 11 3.8 2.0 Block end (termination of a block)
BEC - N N N 01) Y1Y 12/
27 2) 0.8/
19 2) 3.8 2.1 Block end, conditional (if RLO is "1")
BEU - N N N 0 N N Y 26 11 3.8 2.0 Block end, unconditional
1) The OS bit rema ins uncha ng ed if RLO = 0 (not for CPU 9 48 ).
2) Time applies when RLO = 0 / RLO = 1.
52 53
C79000-K8576-C124-03C79000-K8576-C124-03
Bas ic Ope rat ions
Permissible for all blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
= Operation
with this
times in µs
not possible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Null Operations
NOP
0- N N N N N N N 9 1.0 0.57 0.18 No operation (all bits set to 0)
NOP
1- N N N N N N N 9 0.8 0.57 0.18 No operation (all bits set to 1)
Stop Op erati o n
STP - NNNNNNN - - - -
Direct transition to "STOP" mode
CPU 948: transition to communication stop
(operating mode SMOOTH STOP), program
processin g aborted at cycle end or by the system
program
Display Construction Operations
B LD 0 - 255 N N N N N N N 9 0.8 0.57 0.18 Display construction statement/NOP for the
programmable controller
BLD 130 N N N N N N N 9 0.8 0.57 0.18 Display construction operation for the programmer:
generate blank line by carriage return
BLD 131 N N N N N N N 9 0.8 0.57 0.18 Display construction operation for the programmer:
switch over t o statement list (STL)
BLD 132 N N N N N N N 9 0.8 0.57 0.18 Display construction operation for the programmer:
switch over t o control system f lowcha rt CSF)
BLD 133 N N N N N N N 9 0.8 0.57 0.18 Display construction operation for the programmer:
switch over to ladder diagram (LAD)
BLD 255 N N N N N N N 9 0.8 0.57 0.18 Display construction operation for the programmer:
terminate segment
54 55
C79000-K8576-C124-03C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Binary L ogi c Op eratio n s
A= Formal operand N N N N N Y N 24 1) 24 1) 2.4 1) 0.91 1) AND operation: scan a formal operand for "1"
(pa rame ter t ype: I, Q, T, C; d ata type: BI)
AN= Formal operand N N N N N Y N 24 1) 24 1) 2.4 1) 0.91 1) AND operation: scan a formal operand for "0"
(pa rame ter t ype: I, Q, T, C; d ata type: BI)
O= Formal operand N N N N N Y N 24 1) 24 1) 2.4 1) 0.91 1) OR op era tio n: scan a fo rma l ope ran d for "1"
(pa rame ter t ype: I, Q, T, C; d ata type: BI)
ON= Formal operand N N N N N Y N 24 1) 24 1) 2.4 1) 0.91 1) OR opera tio n: scan a fo rma l ope ran d for "0"
(pa rame ter t ype: I, Q, T, C; d ata type: BI)
Digital Operations
The result (= "0" or ≠ "0" ) can be evaluated via CC0 a nd CC1
(see Explan atory Notes on the Condit ion Code s)
AW - Y 0 0 N N N N 16 11 0.57 0.18 Combine contents of ACCU 2 and ACCU 1 (word
opera tio n) thro ug h logic AND: re sult i s stored in
ACCU 1
OW - Y 0 0 N N N N 16 11 0.57 0.18 Combine contents of ACCU 2 and ACCU 1 (word
opera tio n) thro ug h logic OR: re sult is stored in
ACCU 1
XOW - Y 0 0 N N N N 16 11 0.57 0.18 Combine contents of ACCU 2 and ACCU 1 (word
opera tio n) thro ug h logic EXOR: re su lt is sto red in
ACCU 1
1) The execution time of the substituted operation must be added.
56 57
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Bit Test Operations
These operations scan the status of a bit and update it in the RLO.
T B I 0 .0 t o 127. 7 N N N N N Y N 0.48 Scan an input bit for signal status "1"
T B Q 0. 0 to 12 7.7 N N N N N Y N 0.48 Scan an output bit for signal status "1"
T B F 0.0 to 25 5.7 N N N N N Y N 0.48 Scan a flag bit for signal status "1"
TB T 0.0 to 255.15 N N N N N Y N 0.48 Scan a b it of a t imer word for signa l status "1"
TB C 0.0 to 255.15 N N N N N Y N 0.48 S can a b it of a count er word for signa l status "1"
TB D 0.0 to 255.15 N N N N N Y N 0.77 S can a b it of a d at a word (DB/DX) for signal status
"1"
TB RI 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a bit in the RI are a for signa l status "1"
TB RJ 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a bit in the RJ are a for signal status "1"
TB RS 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a b it in the RS a rea fo r signal status "1"
TB RT 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a b it in the RT area for signal status "1"
58 59
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Bit Test Operati ons (continued)
These operations scan the status of a bit and update it in the RLO.
TBN I 0. 0 to 12 7.7 N N N N N Y N 0.48 Scan an input bit for signal status "0"
TBN Q 0.0 t o 127. 7 N N N N N Y N 0.48 Scan an output bit for signal status "0"
TBN F 0.0 t o 255.7 N N N N N Y N 0.48 Scan a flag bit for signal status "0"
TBN T 0.0 to 255.15 N N N N N Y N 0.48 S can a b it of a t im er word for signal status "0"
TBN C 0.0 to 255.15 N N N N N Y N 0.48 S can a b it of a cou nter word for sig nal status "0"
TBN D 0.0 to 255.15 N N N N N Y N 0.77 S can a b it of a d at a word (DB/DX) for signal status
"0"
TBN RI 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a bit in the RI are a for signa l status "0"
TBN RJ 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a bit in the RJ are a for signal status "0"
TBN RS 0.0
to 25 5.1 5 NNNNNYN 0.48 Scan a b it in the RS a rea fo r signal status "0"
TBN RT 0 .0
to 25 5.1 5 NNNNNYN 0.48 Scan a b it in the RT area for signal status "0"
60 61
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Set/Reset O perat ions
S= Formal operand N N N N Y N Y 25 1) 23 1) 1.9 1) 0.64 1) Binary setting of a formal operand
(pa rame ter t ype: I, Q; data type: BI)
RB= Formal operand N N N N Y N Y 25 1) 22 1) 1.9 1) 0.64 1) Binary resetting of a formal operand
(pa rame ter t ype: I, Q; data type BI)
RD= Formal operand N N N N Y N Y 14 1) 13 1) 1.9 1) 0.64 1) Dig ital re se ttin g of a formal operand for ti me r s and
counters (parameter type: T, C)
== Formal operand N N N N N N Y 25 1) 23 1) 1.9 1) 0.64 1) Assignment of the RLO to a formal operand
param e ter type: I, Q; data type: BI)
SU I 0.0 to 127.7 N N N N N N Y 0.48 Set an input bit (in the PII) unconditionally
SU Q 0.0 to 127.7 N N N N N N Y 0.48 Set an output bit (in the PIO) unconditionally
SU F 0.0 to 255.7 N N N N N N Y 0.48 Set a flag bit un co nd itiona lly
SU T 0.0 to 255.15 N N N N N N Y 0.48 Set a bit of a timer word unconditionally
SU C 0.0 to 255.15 N N N N N N Y 0.48 Set a bit of a counter word unconditionally
1) The execution time of the substituted operation must be added.
62 63
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Set/Reset O perat ions (con tinued )
SU D 0.0 to 255.15 N N N N N N Y 0.77 Set a bit of a data word (DB/DX) unconditionally
SU RI 0.0
to 25 5.1 5 NNNNNNY 0.48 Set a bit in the RI area unconditionally
SU RJ 0.0
to 25 5.1 5 NNNNNNY 0.48 Set a bit in the RJ area unconditionally
RU I 0 .0 to 127.7 N N N N N N Y 0.48 Reset an input bit (in the PII) unconditionally
RU Q 0. 0 to 12 7.7 N N N N N N Y 0.48 Reset an output bit (in the PIO) unconditionally
RU F 0.0 to 25 5.7 N N N N N N Y 0.48 Reset a flag b it un conditionally
RU T 0.0 to 255.15 N N N N N N Y 0.48 Reset a bit of a timer word unconditionally
RU C 0.0 to 255.15 N N N N N N Y 0.48 Reset a bit of a counter word unconditionally
RU D 0.0 to 255.15 N N N N N N Y 0.77 Reset a bit of a data word (DB/DX) unconditionally
RU RI 0.0
to 25 5.1 5 NNNNNNY 0.48 Reset a bit in the RI area unconditionally
RU RJ 0.0
to 25 5.1 5 NNNNNNY 0.48 Reset a bit in the RJ area unconditionally
64 65
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Timer an d Counter O perat ion s
SP= Formal operand N N N N Y ↑NY 14
2) 16 2) 1.9 2) 0.64 2) Start t imer specifie d as fo rma l ope ran d as pulse
with the value stored in ACCU 1-L
(pa ram e ter type: T)
SD= Formal operand N N N N Y ↑NY 14
2) 16 2) 1.9 2) 0.64 2) Start timer specified as formal operand as ON
delay with the value stored in ACCU 1-L
(pa ram e ter type: T)
SEC= Formal operand N N N N Y ↑NY 14
2) 15 2) 1.9 2) 0.64 2)
Start timer specified as formal operand as
exte nded pulse with the value stored in ACCU 1 -L
or set counter specified as formal operand with the
count stored in ACCU 1-L
(pa ram e ter type: T, C)
SSU= Formal operand N N N N Y ↑NY 14
2) 16 2) 1.9 2) 0.64 2) Start timer specified as formal operand as stored
ON de lay with the value stored in ACCU 1 -L or
incre me nt a coun ter sp ecifie d as formal ope ran d
(pa ram e ter type: T, C)
SFD= Formal operand N N N N 1) NY 14
2) 16 2) 1.9 2) 0.64 2) Start timer specified as formal operand as stored
OFF d elay with the value stored in ACCU 1-L or
decrement a counter specified as formal operand
(pa ram e ter type: T, C)
FR= Formal operand N N N N Y ↑NY 12
2) 13 2) 1.9 2) 0.64 2) Enable formal operand (timer/counter) for cold
restart (for description see FR T or FR C);
(pa ram e ter type: T, C)
1) The RLO is evaluated according to the executed operation.
2) The execution time of the substituted operation must be added.
66 67
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Timer an d Counter O perat ion s (continu ed)
FR T 0 to 255 N N N N Y↑NY 1)
19/22
1)
15/16 1.6 0.18 Enable timer for cold restart. The operation is exe-
cuted only on the leading edge of the RLO (change
from "0" to "1"). The timer is restarted if the RLO is
"1" a t the time of the start opera tion.
FR C 0 to 255 N N N N Y↑NY 1)
17/22
1)
16/18 1.6 0.18
Enable a counter for setting or counting up or
down. This operation is executed only on the
leading edge of the RLO (change from "0" to "1").
The counter is restarted if the RLO = "1" at the time
of the set operation.
The counter is counted up or down if the RLO = "1"
at the time of the "c ounting up" (CU) or "counting
down" (CD) operation.
1) Time applies when RLO = "0"/RLO = "1".
68 69
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s
Load o pe rati on s: the value in ACCU 1 is shifte d and stored in
ACCU 2. Zeros are supplied for unused bits in ACCU 1.
L= Formal operand N N N N N N N 19 1) 16 1) 2.1 1) 0.64 1) The value of the formal operand is loaded into
ACCU 1
(parameter type: I, Q, T, C; data type: BY, D, W)
LD= Formal operand N N N N N N N 14 1) 14 1) 1.9 1) 0.64 1) Load formal operand in BCD into ACCU 1
(pa ram e ter type: T, C)
LW= Formal operand N N N N N N N 5 1) 15 1) 0.5 1) 0.50 1) Load the bit pattern of a formal operand into
ACCU 1
param e ter type: D; d at a t ype: KF, KH, KM, KY, KS,
KT, KC)
LDW= Formal operand N N N N N N N 5 1) 18 1) 0.5 1) 0.68 1) The value of the formal operand is loaded into
ACCU 1 (parameter type: D; data type: KG)
T= Formal operand N N N 0 N N N 18 1) 15 1) 2.1 1) 0.64 1) The contents of ACCU 1 are transferred to the
formal operand
(pa rame ter t ype: I, Q; data type: BY, D, W)
L RI 0 to 25 5 N N N N N N N 23 13 0.68 0.18 Load a word from the interface data range (RI) into
ACCU 1-L
L RJ 0 to 25 5 N N N N N N N 13 0.68 0.18 Load a word from the extended interface data area
range into ACCU 1-L
L RS 0 to 25 5 N N N N N N N 23 13 0.68 0.18 Load a word from the system data are a into
ACCU 1-L
L RT 0 to 255 N N N N N N N 13 0.68 0.18 Load a word from the e xt ende d system da ta area
into ACCU 1-L
1) The execution time of the substituted operation must be added.
70 71
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s (conti nued )
Load o pe rati on s: the value in ACCU 1 is shifte d and stored in
ACCU 2. Zeros are supplied for unused bits in ACCU 1.
T RI 0 to 25 5 N N N 0 N N N 15 11 0.57 0. 18 Transfer the contents of ACCU 1-L to a word in the
interface data area
T RJ 0 to 255 N N N 0 N N N 11 0.57 0.18 Transfer the contents of ACCU 1-L to a word of the
extended interface data area
T R S 6 0 to 63 N N N 0 N N N 15 1 1 0 .57 0 .1 8 Transfer the contents of ACCU 1-L to a word in the
system data area
T RT 0 to 255 N N N 0 N N N 11 0. 57 0.18 Transfer the contents of ACCU 1-L to a word of the
extended system data area
72 73
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Conversion Operations
The data in ACCU 1 is converted.
CFW - N N N N N N N 12 9 0.57 0.18 Form one’s compl emen t of ACCU 1-L (bits 0-15)
CSW - Y Y Y Y N N N 15 11 0.57 0.18 Fo rm two’ s comp leme nt of ACCU 1-L (bits 0 - 15).
Result can be evaluated via CC0/CC1 and OV
CSD - Y Y Y Y N N N 25-34
1) 13-19
1) 0.94 0.43 Fo rm two’ s comp lem ent of ACCU 1-L (bits 0 - 31 ).
Result can be evaluated via CC0/CC1 and OV
DEF - N N N N N N N 34 14 1.9 0.30 Con vert a 16-bit fixed point from BCD into binary
DUF - N N N Y N N N 37 15 3.3 0.43 Convert a 16-bit fixed point from binary into BCD
DED - N N N N N N N 68-100
1) 31 7.7 0.48 Convert a 32-b it fi xed point from BCD into binary
DUD - N N N Y N N N 60-79
1) 19-35
1) 9.8 0.62 Convert a 32-bit fixed point from binary into BCD
FDG - N N N N N N N 25-54
1) 18-36
1) 5.2 2.6 Conve r t a fixe d-point n um b er (3 2 bit s) i nto a
floating- point number
GFD - N N N Y N N N 33-64
1) 15-20
1) 4.4 1.5 Convert a floating-point number into a fixed-point
number (32 bits)
1) The tim e is depend en t o n the date in ACCU 1(non-li ne ar).
74 75
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Shi ft and Rotate Op eration s
The data in ACCU 1 is shifted or rotated. The bit shifted or
rotate d last can be e valu ated via CC0 and CC1.
SLW 0-151) Y000NNN12-19
2) 6-12
2) 1.9 0.32 Shift the contents of ACCU 1-L (word) to the left by
the value n specifie d in the p ara me te r (n = 0 to 15 ).
Positi ons b ecom in g vacant are pa dded with zeros.
SRW 0-151) Y000NNN11-18
2) 6-12
2) 2.0 0.32 Shift the contents of ACCU 1-L (word) to the right
by the value n specified in the parameter
(n = 0 to 15).
Positi ons b ecom in g vacant are pa dded with zeros.
SLD 0-321) Y000NNN23-36
2) 7-23
2) 2.6 0.48 Shi ft the cont ent s of ACCU 1 (do uble word ) to th e
left by the value specified in the para me te r
(n = 0 to 32)
Positi ons b ecom in g vacant are pa dded with zeros.
SSW 0-151) Y000NNN21-24
2) 7-13
2) 2.1 0.32 Shift the contents of ACCU 1-L (word) including its
sign to the right by the value n specified in the
param e ter (n = 0 to 15). Posit ion s beco mi ng vaca nt
are padded with the sign (bit 15)
SSD 0-321) Y000NNN26-38
2) 7-25
2) 3.5 0.48 Shi ft the cont ent s of ACCU 1 (do uble word ) to th e
rig ht by the value n specifie d in the parame te r
(n = 0 to 32). Positions becoming vacant are
padded with the sign (bit 32)
RLD 0-321) Y000NNN27-44
2) 6-26
2) 2.6 0.48 Rotate ACCU 1 to the left (32 bits wide) from
position 0 to 32
RRD 0-321) Y000NNN26-44
2) 7-26
2) 2.7 0.48 Rotate ACCU 1 to the right (32 bits wide) from
position 0 to 32
1) With the operand = "0" an NOP operation is executed;
th e co nd ition co des are no t affecte d.
2) The time is dependent on the size of the (non-linear) operand.
76 77
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep.
2 affect.
3 reload
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Jump Operations
The jump operations are executed depending on the RLO
(only opera tion JC) o r CC0/CC1 and the OV an d OS bits
(see Evaluatio n of CC0 a nd CC1, pag e 1 20)
JU= Sy mbol ic ad dress
max. 4 cha racte rs N N N N N N N 10 1.5 1.0 0.59 Unconditional jump to a symbolic address
JC= Sy mbol ic ad dress
max. 4 cha racte rs NNNNY1Y 13 1/2
1) 1.0 0.4/0.8
1) Conditional jump to a symbolic address, executed
only if RLO = 1; if RLO = "0 ", it is set to "1"
JZ= Sy mbol ic ad dress
max. 4 cha racte rs NNNNNNN 12 11/12
1) 1.4 0.4/0.8
1) Jump if result is "0": the jump is only made if
CC1 = 0 and CC0 = 0
JN= Sy mbol ic ad dress
max. 4 cha racte rs NNNNNNN 12 10/13
1) 1.4 0.4/0.8
1)
Jump if result ≠ "0": the jump is only made if 2)
CC1 = 0 and CC0 = 1 or
CC1 = 1 and CC0 = 0 or
CC1 = 1 and CC0 = 0
JP= Sy mbol ic ad dress
max. 4 cha racte rs NNNNNNN 13 10/13
1) 1.4 0.4/0.8
1) Jump if result > "0": the jump is only made if
CC1 = 1 and CC0 = 0
JM= Sy mbol ic ad dress
max. 4 cha racte rs NNNNNNN 13 12/14
1) 1.4 0.4/0.8
1) Jump if result < "0": the jump is only made if
CC1 = 0 and CC0 = 1
JO= Sy mbolic addr ess
max. 4 cha racte rs NNNNNNN 12 11/14
1) 1.4 0.4/0.8
1) Jump on "overflow": the jump is only made if the OV
bit is set.
JOS= S ymbolic addr ess
max. 4 cha racte rs NNN0NNN 17 13/14
1) 1.3 0.7/0.9
1) Jump on "stored overflow": the jump is only made if
the OS bit is set
1) Jum p cond ition: fulfil led/n ot ful filled 2) If CC 1 = "1" and CC 0 ="1", not executed for CPU 948
78 79
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Other Operations
IA - N N N N N N N 12 25 52 0.30 Disable interrupt: process interrupts are no longer
serviced
RA - N N N N N N N 12 25 52 0.30 Ena ble inte rrup t: cancels the eff ect of IA
IAE - N N N N N N N 0.32 Disab le addressing error
RAE - N N N N N N N 0.32 Enab le address in g error: cancels the effect of IAE
BAS - N N N N Y N Y 0.50 Disable output command: PIQ is no longer
affecte d, i.e., the ou tputs are no longe r changed by
the S Q, R Q, =Q, T PY, T PW operations.
BAF - N N N N Y N Y 0.50 Ena bl e o ut pu t comman d: cancels the effect of BAS
80 81
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Other Operations (continued)
D 0-255 N N N N N N N 11 9 0.57 0.18 Decreme nt the lo w byte (b its 0 to 7) o f ACCU 1 b y
the value n (n=0 to 255) (without carry)
I 0-255 N N N N N N N 11 9 0.57 0.18 In cre ment th e l ow byt e (b its 0 to 7) of ACCU 1 by
the value n (n=0 to 255) (without carry)
ENT - N N N N N N N 26 8 0.75 0.39 The contents of the accumulators are restored1).
SED 0-312) Y 0 N N N N N 32-37 23 4.1 3) 3.0 3) Set semaphore with the number specified
(operation applicable e xclusively in mul tiprocessor
mode)
SEE 0-312) Y 0 N N N N N 3 2-36 23 4 .1 3) 3.1 3) Enabl e sema ph ore with the nu mb er specified
(operation applicable e xclusively in mul tiprocessor
mode)
1) New value of : = Old value of
ACCU 1 : = ACCU 1
ACCU 2 : = ACCU 2
ACCU 3 : = ACCU 2
ACCU 4 : = ACCU 3
The orig in al content s o f ACCU 4 a re lost.
2) S emaphore l ocations on the coo rdinator module
3) Add the waiting time for the bus allocation
82 83
C79000-K8576-C124-03
C79000-K8576-C124-03
Suppl em ent ary Opera tion s
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1dep.
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Other Operations (continued)
DO= Formal operand 1) 1) 1) 1) 1) 1) 1) 12-15
2) 15 2) 1.7 2) 0.82 2) Call block as formal operand (only C DB,
JU PB/FB/SB/OB can be substitu ted)
DO DW 0 to 255 N N N N N N N 20-26 12-26 3.3 0.84 2) Process da ta word: the following operation is
executed with the parameter specified in the
data word 3)
DO FW 0 to 254 N N N N N N N 19-25 23-26 3.2 0.75 2) Process flag word: the fol lowin g op era tion is
executed with the parameter specified in the
flag word 3)
1) The co nd itio n code s are evalu at ed an d chan ge d a ccord in g t o
the operation executed.
2) The execution time of the substituted operation must
be added.
3) Th e fol lowi ng opera tions a re p os sible :
- A.., AN.., O.., ON.., S.., R..,=..
with th e are as I, Q, F a nd S,
- FR T, R T, SF T, SR T, SP T, SS T, SE T,
FR C, R C, S C, CD C, CU C,
- L.., T..
with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT,
- L T, L C,
- LC T, LC C,
- JU=, JC=, JZ=, JN=, JP=, JM=, JO=,
- SLW, SRW,
- D, I, SED, SEE,
- C DB, JU.., JC.., G DB, GX DX, CX DX, DOC FX, DOU FX
84 85
C79000-K8576-C124-03 C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affe cte d
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function 3)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s
LIR Register no .
0 to 15 N N N N N N N 26-35 2-23 45-51
2) 0.9-2.1
2) Load register with the contents of a memory word
addressed by ACCU 11)
TIR Register no.
0 to 15 N N N N N N N 26-38 5-19 36-50
2) 0.7-1.9
2) Tra nsfer reg ister conte nts into the me mo ry word
addressed by ACCU 11)
1)Registers for LIR and TIR (register width = 16 bits) 2)Execution time for single processing operation and for
immediate bus access in multiprocessing operation. l/Os
acknowledge within 0.1µs or proportionally longer
exe cu tio n tim e for longe r ackno wled ge m en t ti me .
Reg.-No. Register designation
0
1
2
3
5
6
8
9
10
11
12
15
ACCU 1-H
ACCU 1-L
ACCU 2-H
ACCU 2-L
BSP (only on
CPU 922/948)
DBA
DBL (not on
CPU 922)
ACCU 3-H
ACCU 3-L
ACCU 4-H
ACCU 4-L
SAC (not on
CPU 948)
high word ACCU 1
low word ACCU 1
high word ACCU 2
low word ACCU 2
Block Stack Pointer
Start ad dress of the current data
block (address of the first DW)
Length of the current data block
(number of data words)
high word ACCU 3
low word ACCU 3
high word ACCU 4
low word ACCU 4
Step Address Counter
3)Differences in the CPU 948:
The operations LIR/TIR operate with 20 bit absolute addresses.
Specifying the address in ACCU 1:
ACCU-1-H:Bit no . 1 5 to 4= 0
Bit no. 3 to 0= address bits nos. 19 to 16
ACCU-1-L:Bit no. 15 to 0= address bits nos. 15 to 0
- Access to the 8-bit memory:
LIR: the high byte of the register is loaded with FFH
(except on CPU 948, S flag and I/Os)
TIR: the hig h byte of the registe r is lo st
86 87
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affe cte d
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function 3)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s (conti nued )
LDI Register name
1) NNNNNNN 1.1-3.2
2)
Load th e specifie d 32 bit register with the conte nt s
of a memory word n addressed by ACCU 1-H/L
and the following word n+1 3):
register HIGH = mem ory word n
register LOW = memory word n+1
TDI Reg ister name
1) NNN0NNN 1.0-2.4
2)
Tra nsfer the conten ts of the speci fied 32 bit
register into the mem ory word n addressed b y
ACCU 1-H/L and the following word n+1 3):
me mor y word n = registe r HIGH
me mo ry word n+1 = re gister LOW
1)Registers for LDI and TDI (register width = 32 bits) 2)Execution time for single processing operation and for
immediate bus access in multiprocessing operation. l/Os
acknowledge within 0.1µs or proportionally longer
exe cu tio n tim e for longe r ackno wled ge m en t ti me .
Reg.-No. Register designation
A1
A2
SA
BA
BR
ACCU 1
ACCU 2
SAC = STEP address co unter
BA register (block start address ,
bit no. 0 to 19)
BR register (block address register,
bit no. 0 to 19)
3)Specifying the address in ACCU 1:
ACCU-1-H:Bit no . 1 5 to 4= 0
Bit no. 3 to 0= address bits nos. 19 to 16
ACCU-1-L:Bit no. 15 to 0= address bits nos. 15 to 0
- Access to the 8-bit memory:
LDI: the HIGH byte of the register is loaded with FFH
(except on CPU 948, S flag and I/Os)
TDI : th e high byte of the registe r is lo st
88 89
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
(only CPU 922/928/928B)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s (conti nued )
TNB Length of are a
0 to 255 NNN0
1) NNN 54 -
1530 66 -
1226
100-
1258
2)
Block transfer 0 to 255 bytes3):
End address of target area in ACCU 1-L
End address of source area in ACCU 2-L
TNW L eng th of area
0 to 255 NNN0
1) NNN 55 -
3010 65 -
2340
95-
2400
2)
Block transfer 0 to 255 words3):
End address of target area in ACCU 1-L
End address of source area in ACCU 2-L
1) With CPU 928/928B the OS bit is not influenced by TNB 0/TNW 0. 3) Block transfer operations function decrementally, i.e., the
number of words/bytes specified is transferred starting with
2) Executi on tim e fo r sing le proce ssing ope rati on an d for bus th e e nd add ress. Sour ce area and target are a m ust be lo cated
access in multiprocessing operation. I/Os acknowl edge completely within on e of the follo wing mem o r y a reas:
within 0.1 µs or proportionally longer execution time for
long er a c knowle dg em e nt tim e.
A con ver sio n takes place in case of block t ransfer s
betwe en 8 and 1 6 bit memory area s. Two bytes a re
convert ed into a word and vice versa.
90 91
Address area CPU 922 CPU 928 CPU 928B
0000 - 7FFF (16 bit)
8000 - DD7F (16 bit)
DD80 - E3FF (16 bit)
E400 - E7FF (8 bit)
E400 - E7FF (16 bit)
E800 - EDFF (16 bit)
AC00 - EDFF (16 bit)
EE00 - EFFF (8 bit)
F000 - F FFF (8 bit)
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
(on ly CPU 948)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Lo ad and Transf er Operatio n s (conti nued )
The b lock transfer opera tio ns of the CPU 948 listed below function
with 20 bit absolute addresses. Only these opera tion s can be
interrupted by timeout (QVZ) and power failure (NAU).
TNW L eng th of area
0 to 255 NNN0NNN
2-250
1)
3-560 Blo ck transfer in words in the 16 b it m e mo ry area 2)
TXB - N N N 0 N N N
3-180
1)
5-480
Block transfer from the 8 bit to the 16 bit memory
area 2):
The byte fro m address n is transferred into the high
byte , th e byte from a dd ress n+1 is transferred into
the low byte of the tar get dat e.
TXW - N N N 0 N N N
3-180
1)
5-480
Block transfer from the 16 bit to the 8 bit memory
area 2):
The high byte of the source date is transferred into
the byte with address n, the low byte of the source
date is transferred into the byte with address n+1.
1) Executi on tim e fo r sing le proce ssing ope rati on an d for 2) Block transfer operations function decrementally, i.e., the
immediate bus access in multiprocessing ope rati on . num be r of words specified is tran sf erre d starting with the end
I/Os acknowledge within 0.1 µs o r prop orti on all y lon ge r ad dre ss. The en d address of th e targ et are a (20 bit ) must be
execution time for longer ack nowledgement time. located in ACCU 1, the end address of the sourc e area (20 bit)
must be locat ed in ACCU 2 . Both the sour ce and the targe t
area must be completely within a memory area listed in the
table.
For TXB an d TXW ACCU 3 m u st contain the b lo ck le ngth
(number of words, 0 to 127).
A conversion takes place in c ase of block transfers between
8 and 16 bit memory areas. Two bytes are converted into a
word and vice versa.
92 93
Address area of the CPU 948
0 0 00 0 to E FBFF (16 b it)
E A000 to E AFFF (8 bit - S flag)
E FC00 to E FFFF (8 bit)
F 0000 to F FFFF (8/16 bit)
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Arith metic Operat ion s
ADD BN -128 to
+ 1 27 N N N N N N N 12 11 0.57 0.18 Add byte constant (fixed-point number) to contents
of ACCU 1-L (operation includes sign change);
ACCUs 2 to 4 remain uncha ng ed
ADD KF - 32 76 8 to
+ 3 2767 N N N N N N N 13 12 1.2 0.39 Add fixed-point constant (word) to
conten ts of ACCU 1-L ;
ACCUs 2 to 4 remain uncha ng ed
ADD DH0 to
F FFF FFFF NNNNNNN20.2
1) 14 1.7 0.57 Add fixed-point constant (double word)
to content s of ACCU 11);
ACCUs 2 to 4 remain uncha ng ed
+D - Y Y Y Y N N N 38-41
1) 17-19 1.6 0.64 Add two double word fixed-point
numbers 2): ACCU 1 + ACCU 2; result can
be evaluated via CC0/CC1
-D - Y Y Y Y N N N 42-46
1) 20-23 1.6 0.62 Sub tra ct two do uble word fixed-po in t
numbers 2): ACCU 2 - ACCU 1; result can
be evaluated via CC0/CC1
1) Operation possible from version 09
2) For changes to ACCU 2 and ACCU 3 see
Arit hmet ic Opera tions, p age 38
94 95
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Jump Operation
JUR - 3276 8 to
+ 32 767 N N N N N N N 15 11 1.2 0.68 Any jump within a function block
Other Operations
DI - 1) 1) 1) 1) 1) 1) 1) 15-19
2) 18 2) 1.7 2) 1.1 2) Execute an operation3) whose operation code is
stored in a formal operand. The number of the
formal operan d mu st be stored in ACCU 1.
DO RS 6 0 to 63 1) 1) 1) 1) 1) 1) 1) 16 2) 17 2) 0.93 2) 0.71 2) Execute an operation3) whose operation code is
stored in th e syste m dat a
TAK - N N N N N N N 24 9 0.88 0.18 2) Swap the content s of ACCU 1 and ACCU 2 .
1) The co des are evalu at ed and chan ge d accord in g t o t he 3) The following operations are possible:
operation executed. - A.., AN.., O.., ON.., S.., R.., =..
with the areas I, Q, F, and S,
2) The execution time of the operation must be added. - FR T, R T, SF T, SR T, SP T, SS T, SE T,
FR C, R C, S C, CD C, CU C,
- L.., T..
with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT,
- L T, L C,
- LC T, LC C,
- JU=, JC=, JZ=, JN=, JP=, JM=, JO=,
- SL W, SRW,
- D, I, SED, SEE,
- C DB, JU.., JC.. , G DB, GX DX, CX DX, DOC FX, D OU FX
96 97
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Other Operations (continued)
STS - N N N N N N N 2.0 1) Stop operation with direct transition to SMOOTH
STOP m od e (commu nicat ion capab ilit y with CP s)
STW - N N N N N N N - Stop operation resulting in HARD STOP mode (can
only be re set b y POWER OFF/ POWER ON)
SIM - N N N N N N N 0.48 Set in terru pt m as k (b it pa tte rn i n ACCU 1 - 32 bi t)
LIM - N N N N N N N 0.18 Load interrupt mask (32 bit) into ACCU 1
1) Add the time for the ISTACK operation (approx. 6.5 µs)
98 99
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Set Operations
SU R S 60.0 to
63.15 NNNNNNY 0.48Set a bit in the RS area unconditionally
SU RT 0.0 to
RT 255.15 NNNNNNY 0.48 Set a bit in the RT area unconditionally
RU R S 60.0 to
63.15 NNNNNNY 0.48Reset a bit in the RS area unconditionally
RU RT 0.0 to
RT 255.15 NNNNNNY 0.48 Reset a bit in the RT area unconditionally
100 101
C79000-K8576-C124-03 C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
(only for CPU 928/928B)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Regist er to Regi ster Tran sfer Operat ion s
These o pe rat ion s tran sf er the cont en ts of on e regi ster
into an other register.
MAS - N N N N N N N 9 0.88 Transfer the contents of ACCU 1 (bits 20 to 214)
into the step address counter (SAC)
MAB - N N N N N N N 12 0.62 Transfer the contents of ACCU 1 (bits 20 to 231)
into the base add ress register (BR)
MSA - N N N N N N N 11 0.69 Transfer the contents of the step address counter
(SAC) into ACCU 1
MSB - N N N N N N N 11 0.69 Transfer the contents of the step address counter
(SAC) into the base address register (BR) 1)
MBA - N N N N N N N 12 0.62 Transfer the contents of the b ase addre ss register
(BR) into ACCU 1
MBS - N N N N N N N 10 0.88 Transfer the contents of the b ase addre ss
register (BR) (bit s 20 to 214) into the step
address counter (SAC)
Load, Tran sfer and Arith metic Operati ons with the Base Add ress Register
The base address register (32 bits) allows addre ss arith me tic and
indirect load and transfer operations without using the
acc umu lators for addressing. T he fo llowing applies:
Absolute address = c on te nts of base addres s register + constant
MB R 0 to FF FFF N N N N N N N 15 1 .1 Load a 20-bit constant into the base
address register 2)
ABR - 32768 to
+ 3 2767 N N N N N N N 14 1.1 Add a 16-bit constant to the contents of the base
address register
1) The bits 215 to 231 are set to "0". 2) The bits 220 to 231of the BR register are set to "0".
.
102 103
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
(only for CPU 948)
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Regist er to Regi ster Tran sfer Operat ion s
These o pe rat ion s tran sf er the cont en ts of on e regi ster
into an other register.
MAS - N N N N N N N 0.66 Transfer the contents of ACCU 1 (bits 20 to 219)
into the step address counter (SAC)
MAB - N N N N N N N 0.30 Transfer the contents of ACCU 1 (bits 20 to 219)
into the base add ress register (BR)
MSA - N N N N N N N 0.30 Transfer the contents of the step address counter
(SAC) into ACCU 1
MSB - N N N N N N N 0.18 Transfer the contents of the step address counter
(SAC) into the base address register (BR) 1)
MBA - N N N N N N N 0.30 Transfer the contents of the b ase addre ss register
(BR) into ACCU 1
MBS - N N N N N N N 0.48 Transfer the contents of the b ase addre ss
register (BR) into the step address counter (SAC)
Load, Tran sfer and Arith metic Operati ons with the Base Add ress Register
The base address register (20 bits) allows addre ss arith me tic and
indirect load and transfer operations without using the
acc umu lators for addressing. T he fo llowing applies:
Absolute address = c on te nts of base addres s register + constant
MB R 0 to F FFFF N N N N N N N 0.48 Load a 20-bit constant into the base
address register
ABR - 32768 to
+ 3 2767 NNNNNNN 0.39 Add a 16-bit constant to the contents of the base
address register
1) The bits 220 to 231 are set to "0".
104 105
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Access to local , word-o rient ed memory: 1)
LRW - 32 768 to
+ 32 767 N N N N N N N 22 3.6 0.59 Ad d the constant specified to the contents of the
BR re giste r and load the add ress of the word
specified into ACCU 1-L 1).
LRD - 32768 to
+ 32 767 N N N N N N N 30 5.0 0.77 Ad d the constant specified to the contents of the
BR re giste r and load the add ress of the double
word specified into ACCU 1 1).
TRW - 32 768 to
+ 32 767 N N N 0 N N N 21 3.4 0.59 A dd the constant specified to the contents of the
BR register and transfer the contents of
ACCU 1-L to the address of the word specified 1).
TRD - 32768 to
+ 32 767 N N N 0 N N N 28 5.0 0.77 A dd the constant specified to the contents of the
BR re giste r and tran sfer the conten ts of ACCU 1 to
the address of the double word specifi ed 1).
Test/ set Busy locati on (global area): 1)
TSG - 32768 to
+ 32 767 YY0NNNN 26
2) 4. 7 2) 2.9 2) Add the specifie d constant to the cont en t s of the
BR register, and test and set the Busy location 1)
addressed.
1) Possible absolute addresses: 2) Execution time for single processor operation and for
b us ac cess in mult iproces sor operation. I/Os acknowledge
with in 0.1 µs or propo rtio na lly long er exe cutio n tim es
for longe r ackno wled ge m ent time .
CPU 928/928B CPU 948
LRW/TRW 000 0 to E3FF and
E800 to EDFF 0 0 00 0 to E FBFF
LRD/TRD 0 00 0 to E3FE and
E800 to EDFE 0 0 00 0 to E FBFE
TSG 000 0 to EFFF F 0 000 to F FFFF
106 107
C79000-K8576-C124-03 C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Access to global, byte-oriented memory:
LY
GB - 32768 to
+ 32 767 NNNNNNN 22
1) 3. 0 1) 1.8 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and load the byte
addressed into ACCU 1-LL 2).
LY
GW - 32768 to
+ 32 767 NNNNNNN 26
1) 3. 9 1) 2.4 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and load the word
addressed into ACCU 1-L 2).
LY
GD - 32768 to
+ 32 767 NNNNNNN 31
1) 5. 5 1) 4.4 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and load the double
word addressed into ACCU 1 2).
TY
GB - 32768to
+ 32 767 NNN0NNN 21
1) 2. 9 1) 1.8 1) Add the specifie d constant to the conten ts of
the BR register and transfer the contents
of ACCU 1-LL to the byte addressed 2).
TY
GW - 32768 to
+ 32 767 NNN0NNN 25
1) 3. 7 1) 2.5 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and transfer the contents
of ACCU 1-L to the word addressed 2).
TY
GD - 32768 to
+ 32 767 NNN0NNN 30
1) 5. 3 1) 4.0 1) Add the specifie d constant to the conten ts of
the BR register and transfer the contents of
ACCU 1 to the double word addressed 2).
1) Execution time for single processor operation and 2) Possible absolute addresses:
for bus access in multiprocessor o perati on. I/Os
acknowledge within 0.1µs or proportionally longer
execution times for longer acknowledgement time.
CPU 928/928B CPU 948
LY GB/TY GW 0 00 0 to EFFF F 0000 to F FFFF
LY GW/TY GW 000 0 to EFFE F 0000 to F FFFE
LY GD/TY GD 0000 to EFFC F 0000 to F FFFC
108 109
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Access to global, word-oriented memory:
LW
GW - 32768 to
+ 32 767 NNNNNNN 27
1) 4. 3 1) 1.8 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and load the word
addressed into ACCU 1-L 2).
LW
GD - 32768 to
+ 32 767 NNNNNNN 33
1) 5. 7 1) 2.4 1) Add th e specifie d co nstan t to t he cont ent s
of the BR regist er a nd load the doub le word
addressed into ACCU 1-L 2).
TW
GW - 32768 to
+ 32 767 NNN0NNN 26
1) 4. 0 1) 1.8 1) Add th e specifie d co nstan t to t he cont ent s
of the BR register and load the word
addressed into ACCU 1-L 2).
TW
GD - 32768 to
+ 32 767 NNN0NNN 32
1) 5. 4 1) 2.5 1) Add the specifie d constant to the cont en t s of the
BR registe r and tran sfer the conten ts of ACCU 1
to the double word addressed 2).
Op en page:
ACR - N N N N N N N 11 1) 0.571) 0.32 1) Open the page whose number is in ACCU 1-L 3).
Test/ set Busy locati on (page area):
TSC - 32768 to
+ 32 767 YY0NNNN 29
1) 5. 3 1) 3.6 1) Add th e specifie d co nstan t to t he cont ent s
of the BR regis ter and test/set the Busy
location 2) addressed on the page opened.
1) Execution time for single processor operation and 2) Poss ible absolute addresses:
for bus access in multiprocessor o perati on. I/Os
acknowledge within 0.1 µs or proportionally longer
execution times for longer acknowledgement time.
3) Possible values: 0 to 255
CPU 928/928B CPU 948
LW GB/TW GW 0000 to EFFF F 0000 to F FFFF
LW GW/ TW GW 0000 to EFFE F 0000 to F FFFE
TSC F400 to FBFF F F400 to F FBFF
110 111
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Access to byte-o riented pages:
LY
CB - 32768 to
+ 32 767 NNNNNNN 29
1) 3. 6 1) 2.6 1) Add the specifie d constant to the cont en t s of the
BR re giste r and load the byte add ressed fro m the
page opened into ACCU 1-LL 2).
LY
CW - 32768 to
+ 32 767 NNNNNNN 30
1) 4. 5 1) 3.4 1) Add the specifie d constant to the cont en t s of the
BR re giste r and load the word a dd ressed from the
page opened into ACCU 1-L 2).
LY
CD - 32768 to
+ 32 767 NNNNNNN 34
1) 6. 1 1) 5.2 1) Add the specifie d constant to the cont en t s of the
BR re giste r and load the d ouble word add ressed
from the pag e o pe ned into ACCU 1 2).
TY
CB - 32768 to
+ 32 767 NNN0NNN 28
1) 3. 5 1) 2.5 1) Add the specifie d constant to the cont en t s of the
BR register and transfer the contents of
ACCU 1-LL to the byte addressed on the page
opened 2).
TY
CW - 32768 to
+ 32 767 NNN0NNN 29
1) 4. 2 1) 3.3 1) Add the specifie d constant to the cont en t s of the
BR register and transfer the contents of
ACCU 1-L to the word addressed on the page
opened 2).
TY
CD - 32768 to
+ 32 767 NNN0NNN 34
1) 5. 9 1) 4.8 1) Add the specifie d constant to the cont en t s of the
BR re giste r and tran sfer the conten ts of ACCU 1 to
the double word addressed on the page opened 2).
1) Execution time for single processor operation and 2) Poss ible absolute addresses:
for bus access in multiprocessor o perati on. I/Os
acknowledge within 0.1 µs or proportionally longer
execution times for longer acknowledgement time. CPU 928/928B CPU 94 8
LY CB/TY CB F400 to FBFF F F400 to F FBFF
LY CW/TY CW F400 to FBFE F F400 to F FBFE
LY CD/TY CD F400 to FBFC F F400 to F FBFC
112 113
C79000-K8576-C124-03
C79000-K8576-C124-03
Sys tem Operations
Permissible only in fu nction blocks
Ope-
ra-
tion
STL
Operands
Condition
codes
affected
RLO
1 dep .
2 affect.
3 reloa d
Execution
=Ope ration
with this
times in µs
not poss ible
CPU Function
C
C
1
C
C
0
O
VO
S
123 CPU
922 CPU
928 CPU
928B CPU
948
Access to word-oriented pages: 1)
LW
CW - 32768 to
+ 32 767 NNNNNNN 34
1) 4. 9 1) 2.6 1) Add the specifie d constant to the cont en t s of the
BR re giste r and load the word a dd ressed with the
co ntent s of the BR re giste r from th e page opened
into ACCU 1-L 2).
LW
CD - 32768 to
+ 32 767 NNNNNNN 38
1) 6. 3 1) 3.4 1) Add the specifie d constant to the cont en t s of the
BR re giste r and load the d ouble word add ressed
with the contents of the BR register from the page
opened into ACCU 1 2).
TW
CW - 32768 to
+ 32 767 NNN0NNN 33
1) 4. 7 1) 2.5 1) Add the specifie d constant to the cont en t s of the
BR register and transfer the contents of
ACCU 1-L to the word addressed with the contents
of the BR register on the page opened 2).
TW
CD - 32768 to
+ 32 767 NNN0NNN 37
1) 6. 0 1) 3.3 1) Add the specifie d constant to the cont en t s of the
BR re giste r and tran sfer the conten ts of ACCU 1 to
the dou bl e wo rd ad dre ssed with the conte nt s of the
BR register on the page opened 2).
1) Execution time for single processor operation and 2) Possible absolute addresses:
for bus acc ess i n multiprocessor operati on. l/Os
acknowledge within 0.1µs or proportionally longer
execution times for longer acknowledgement time.
114 115
CPU 928/928B CPU 948
LW CW/TW CW F400 to FBFF F F400 to F FBFF
LW CD/TW CD F400 to FBFE F F40 0 to F FBFE
C79000-K8576-C124-03
C79000-K8576-C124-03
Mac hine Code
Listing
Explanation of subscripts
a + byte address
b + bit address
c + formal operand address
d + operand value
e + constant
f + block number
g + word address
h + numbe r of shifts
i + relative jump destination address
k + register number
l + blo ck le ngth in bytes
m + jump displ acem en t (16 bit s)
n + semaphore number
o + b lock leng th in words
B0 t o B5 : 1st to 6th mach ine code byte
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
0000 NOP 0
0100 CFW
020
d0
dLT
030
l0
lTNB
040
d0
dFR T
0500 BEC
060
c0
cFR=
070
c0
cA=
0800 IA
0880 RA
0900 CSW
116 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
0A0
d0
dLFY
0B0
d0
dTFY
0C0
d0
dLD T
0D0
i0
iJO=
0E0
c0
cLD=
0F0
c0
cO=
100
e0
eBLD 0-255
1082 BLD 130
1083 BLD 131
1084 BLD 132
1085 BLD 133
10FF BLD 255
110
e0
eI
120
d0
dLFW
130
d0
dTFW
140
d0
dSF T
150
i0
iJP=
160
c0
cSFD=
170
c0
cS=
180
d0
dDO RS
190
e0
eD
1A0
d0
dLFD
1B0
d0
dTFD
1C0
d0
dSE T
1D0
f0
fJC FB
C79000-K8576-C124-03 117
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
1E0
c0
cSEC=
1F0
c0
c= =
200
f0
fCDB
2120 >F
2140 <F
2160 ><F
2180 !=F
21A0 >=F
21C0 <=F
220
d0
dLDL
230
d0
dTDL
240
d0
dSD T
250
i0
iJM=
260
c0
cSD=
270
c0
cAN=
280
e0
eLKB
290
h0
hSLD
2A0
d0
dLDR
2B0
d0
dTDR
2C0
d0
dSS T
2D0
i0
iJU=
2E0
c0
cSSU=
2F0
c0
cON=
30010
e0
e0
e0
eLKC
30020
e0
e0
e0
eLKT
118 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
30040
e0
e0
e0
e
LKF
30100
e0
e0
e0
e
LKS
30200
e0
e0
e0
eLKY
30400
e0
e0e 0eLKH
30800
e0
e0
e0e LKM
3120 >G
3140 <G
3160 ><G
3180 !=G
31A0 >=G
31C0 <=G
320
d0
dLDW
330
d0
dTDW
340
d0
dSP T
350
i0
iJN=
360
c0
cSP=
370
c0
cRB=
38000
e0
e0
e0
e
LKG
1)
38400
e0
e0
e0
e
L DH 1)
3920 >D
3940 <D
3960 ><D
3980 !=D
39A0 >=D
1) 3-wo rd comm a nd with B4 an d B5, fill ed with 0 e
C79000-K8576-C124-03 119
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
39C0 <=D
3A0
d0
dLDD
3B0
d0
dTDD
3C0
d0
dRT
3D0
f0
fJU FB
3E0
c0
cRD=
3F0
c0
cLW=
4000
kLIR
4100 AW
420
d0
dLC
430
o0
oTNW
440
d0
dFR C
450
i0
iJZ=
460
c0
cL=
470
d0
dLRJ
4800
kTIR
4900 OW
4A0
d0
dLIB
4A8
d0
dLQB
4B0
d0
dTIB
4B8
d0
dTQB
4C0
d0
dLD C
4D0
f0
fJC OB
4E0
d0
dDO FW
4F0
d0
dLRT
120 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
500
e0
eADD BN
5100 XOW
520
d0
dLIW
528
d0
dLQW
530
d0
dTIW
538
d0
dTQW
540
d0
dCD C
550
f0
fJC PB
560
c0
cLDW=
570
d0
dLOW
58000
e0
e0
e0
e
ADD KF
5900 -F
5A0
d0
dLID
5A8
d0
dLQD
5B0
d0
dTID
5B8
d0
dTQD
5C0
d0
dSC
5D0
f0
fJC SB
5F0
d0
dLOY
6000 :F
6003 :G
6004 xF
60050
e0
e0
e0
e
ADD DH 1)
6007 xG
1) 3-wo rd comm a nd with B4 un d B5, fill ed with 0 e
C79000-K8576-C124-03 121
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
6008 ENT
6009 -D
600B -G
600C000
i0
iJOS=
600D +D
600F +G
6100
hSLW
620
d0
dLRS
630
d0
dTRS
640
h0
hRLD
6500 BE
6501 BEU
660
c0
cT=
670
d0
dTRJ
68000
e0
e0
e0
eLRW
680
h1SSW
6802 GFD
68030
e0
e0
e0
e
TRW
68040
e0
e0
e0
e
LRD
68050
e0
e0
e0
e
TRD
6806 FDG
6807 CSD
6808 DUF
680A DUD
680B LDI A1
122 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B2 B3 B4
LRLRLRLR
680C DEF
680E DED
680F TDI A1
6819 MAS
6829 MAB
682B LDI A2
682F TDI A2
6849 MSA
684B LDI SA
684F TDI SA
6869 MSB
6889 MBA
6899 MBS
689B LDI BA
689F TDI BA
68AB LDI BR
68AF TDI BR
6900
hSRW
6A0
d0
dLRI
6B0
d0
dTRI
6C0
d0
dCU C
6D0
f0
fJU OB
6E0
d0
dDO DW
6F0
d0
dTRT
7000 STS
C79000-K8576-C124-03 123
Machine Code Opera-
tion Ope-
rand
B0 B2 B3 B4
LRLRLRLR
7002 TAK
7003 STP
7004 STW
700B0
m0
m0
m0
mJUR
700C LIM
700D SIM
700E00
b0
g0
g
RU RT
700E40
b0
g0
g
SU RT
700E80
b0
g0
g
TBN RT
700EC0
b0
g0
g
TB RT
700F TXW
701500
b0
g0
g
RU C
701540
b0
g0
g
SU C
701580
b0
g0
gTBN C
7015C0
b0
g0
gTB C
701E00
b0
g0
gRU RJ
701E40
b0
g0
g
SU RJ
701E80
b0
g0
g
TBN RJ
701EC0
b0
g0
g
TB RJ
701F TXB
702500
b0
g0
g
RU T
702540
b0
g0
g
SU T
702580
b0
g0
g
TBN T
7025C0
b0
g0
gTB T
703800
b0
a0
aRU I
124 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B2 B3 B4
LRLRLRLR
703800
b8
a0
a
RU Q
703840
b0
a0
a
SU I
703840
b8
a0
aSU Q
703880
b0
a0
aTBN I
703880
b8
a0
aTBN Q
7038C0
b0
a0
a
TB I
7038C0
b8
a0
a
TB Q
704600
b0
g0
g
RU D
704640
b0
g0
g
SU D
704680
b0
g0
g
TBN D
7046C0
b0
g0
g
TB D
704700
b0
g0
g
RU RI
704740
b0
g0
g
SU RI
704780
b0
g0
gTBN RI
7047C0
b0
g0
gTB RI
704900
b0
a0
aRU F
704940
b0
a0
a
SU F
704980
b0
a0
a
TBN F
7049C0
b0
a0
a
TB F
705700
b0
g0
g
RU RS
705740
b0
g0
g
SU RS
705780
b0
g0
g
TBN RS
7057C0
b0
g0
g
TB RS
710
h0
hSSD
720
d0
dLPY
C79000-K8576-C124-03 125
Machine Code Opera-
tion Ope-
rand
B0 B2 B3 B4
LRLRLRLR
730
d0
dTPY
740
h0h RRD
750
f0
fJU PB
760
c0
cDO=
770
d0
dTOW
7800 IAE
7801010
f0
c
DOU FX
7802090
f0c DOC FX
7803110
f0
f
CX DX
7804000
f0f GX DX
7805000
f0
f
GDB
7806000
n0
n
SED
7807000
n0
n
SEE
780
e90
e0
e0
e0
eMBR
780A0
o0
o0
o0o ABR
780B0
b0
a0
a0a AS
780D0
e0
e0e 0e LYCB
780E0
e0e 0e0eLYGB
7810 RAE
781B0
b0a 0a0aOS
781D0
e0
e0e 0e LYCW
781E0
e0e 0e0eLYGW
782B0
b0
a0a 0a SS
782D0
e0e 0e0eLYCD
782E0
e0
e0e 0e LYGD
126 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B2 B3 B4
LRLRLRLR
783B0
b0
a0a 0a =S
783D ACR
783F00
b0
g0g AD
783F10
b0g 0gOD
783F20
b0
g0g AN D
783F30
b0g 0gON D
783F40
b0
g0g SD
783F50
b0g 0gRD
783F60
b0
g0g =D
784B0
b0a 0a0aAN S
785B0
b0
a0a 0a ON S
785D0
e0
e0
e0
e
LWCW
785E0
e0
e0
e0
e
LWGW
786B0
b0
a0
a0
aRS
786D0
e0
e0
e0
eLWCD
786E0
e0
e0
e0
eLWGD
788D0
e0
e0
e0
e
TYCB
788E0
e0
e0
e0
e
TYGB
789D0
e0
e0
e0
e
TYCW
789E0
e0
e0
e0
e
TYGW
78AB00
d0
d0
d
LSY
78AD0
e0
e0
e0
e
TYCD
78AE0
e0
e0
e0
e
TYGD
78BB00
d0
d0
dTSY
78CB00
d0
d0
dLSW
C79000-K8576-C124-03 127
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
78CD0
e0
e0
e0
e
TSC
78CE0
e0
e0
e0
e
TSG
78DB00
d0
d0
dTSW
78DD0
e0
e0
e0
eTWCW
78DE0
e0
e0
e0
eTWGW
78EB00
d0
d0
d
LSD
78ED0
e0
e0
e0
e
TWCD
78EE0
e0
e0
e0
e
TWGD
78FB00
d0
d0
d
TSD
7900 +F
7A0
d0
dLPW
7B0
d0
dTPW
7C0
d0
dRC
7D0
f0
fJU SB
7E00 DI
7F0
d0
dTOY
80
b0
a0
aAF
88
b0
a0
aOF
90
b0
a0
aSF
98
b0
a0
a=F
A0
b0
a0
aAN F
A8
b0
a0
aON F
B0
b0
a0
aRF
B80
d0
dAC
B90
d0
dOC
128 C79000-K8576-C124-03
Ma chi ne Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
BA0 0 A(
BB00 O(
BC0
d0
dAN C
BD0
d0
dON C
BE00 BAS
BF00 )
C0
b0
a0
aAI
C0
b8
a0
aAQ
C8
b0
a0
aOI
C8
b8
a0
aOQ
D0
b0
a0
aSI
D0
b8
a0
aSQ
D8
b0
a0
a=I
D8
b8a 0a=Q
E0
b0
a0
aAN I
E0
b8
a0
aAN Q
E8
b0
a0a ON I
E8
b8a 0aON Q
F0
b0
a0
aRI
F0
b8
a0
aRQ
F80
d0
dAT
F90
d0d OT
FA0
i0
iJC=
FB00 O
FC0
d0
dAN T
C79000-K8576-C124-03 129
Machine Code Opera-
tion Ope-
rand
B0 B1 B2 B3
LRLRLRLR
FD0
d0
dON T
FE00 BAF
FFFF NOP 1
130 C79000-K8576-C124-03
Alph abe tical Index
of Ope rat ions
(wit h Mach ine Code )
For expla na tion of su b scrip ts see pa ge 11 6.
Operation Operand Page Machine Code
AC
D
F
I
Q
S
T
10
10
10
10
10
10
10
B8 0
d 0 d
783F 00
b 0 g 0 g
80
b 0 a 0 a
C0
b0 a0 a
C0
b 8 a 0 a
780B 0
b 0 a 0 a 0 a
F8 0
d 0 d
A( --- 16 BA 0 0
A = Formal oper. 56 07 0
c 0 c
ABR Constant 102 780A 0
o 0 o 0 o 0 o
ACR --- 110 783D
ADD BN
DH
KF
94
94
94
50 0
e 0 e
6005 0
e 0 e 0 e 0 e
0 e0 e 0 e 0 e
5800 0
e 0 e 0 e 0 e
AN C
D
F
12
12
12
BC 0
d 0 d
783F 40
b
0
g 0 g
A0
b 0 a 0 a
C79000-K8576-C124-03 131
Operation Operand Page Machine Code
AN I
Q
S
T
10
10
12
12
E0
b 0 a 0 a
E0
b 8 a 0 a
784B 0
b 0 a 0 a 0 a
FC 0
d 0 d
AN= Formal oper. 56 27 0
c 0 c
AW --- 56 4100
BAF --- 80 FE 0 0
BAS --- 80 BE 0 0
BE --- 52 6500
BEC --- 52 0500
BEU --- 52 6501
BLD 0 - 255
130
131
132
133
255
54
54
54
54
54
54
10 0
e 0 e
1082
1083
1084
1085
10 F F
CDB 50 20 0
f0
f
CD C3654 0
d 0 d
CFW --- 74 0100
CSD --- 74 6807
CSW --- 74 0900
CU C366C0
d 0 d
CX DX 50 7803 110
f 0 f
D0 - 255 82 19 0
e 0 e
DED --- 74 680E
DEF --- 74 680C
132 C79000-K8576-C124-03
Operation Operand Page Machine Code
DI --- 96 7E 0 0
DO DW
FW
RS
84
84
96
6E 0
d 0 d
4E 0
d 0 d
18 0
d 0 d
DO = Formal oper. 84 76 0
c 0 c
DOC FX 50 7802 090
f 0 f
DOU FX 48 7801 010
f 0 f
DUD --- 74 680A
DUF --- 74 6808
ENT --- 82 6008
FDG --- 74 6806
FR C
T
68
68
44 0
d 0 d
04 0
d 0 d
FR = Formal oper. 66 06 0
c 0 c
GDB 52 7805 000
f 0 f
GFD --- 74 6802
GX DX 52 7804 000
f 0 f
I0 - 255 82 11 0
e 0 e
IA --- 80 0800
IAE --- 80 7800
JC FB
OB
PB
SB
48
50
48
50
1D0
f 0 f
4D0
f 0 f
55 0
f 0 f
5D0
f 0 f
JC = Symb. ad dr. 78 FA0
i 0 i
JM = Symb. ad dr . 78 25 0
i 0 i
JN = Symb. ad dr. 78 35 0
i 0 i
JO = Sy mb. addr. 78 0D0
i 0 i
C79000-K8576-C124-03 133
Operation Operand Page Machine Code
JOS = Symb. addr. 78 600C 000
i 0 i
JP = Symb. ad dr . 78 15 0
i 0 i
JU FB
OB
PB
SB
48
48
48
48
3D0
f 0 f
6D0
f 0 f
75 0
f 0 f
7D0
f 0 f
JU = Symb. ad dr. 78 2D0
i 0 i
JUR Constant 96 700B 0
m
0
m
0
m
0
m
JZ = Symb. ad dr . 78 45 0
i 0 i
LC
DD
DH
DL
DR
DW
FD
FW
FY
IB
ID
IW
KB
KC
KF
KG
26
24
22
22
24
24
22
20
20
20
20
20
24
24
24
24
42 0
d 0 d
3A0
d 0 d
3840 0
e 0 e 0 e 0 e
0 e 0 e 0 e 0 e
22 0
d 0 d
2A0
d 0 d
32 0
d 0 d
1A0
d 0 d
12 0
d 0 d
0A0
d 0 d
4A0
d 0 d
5A0
d 0 d
52 0
d 0 d
28 0
e 0 e
3001 0
e 0 e 0 e 0 e
3004 0
e 0 e 0 e 0 e
3800 0
e 0 e 0 e 0 e
0 e 0 e 0 e 0 e
134 C79000-K8576-C124-03
Operation Operand Page Machine Code
LKH
KM
KS
KT
KY
OW
OY
PW
PY
QB
QD
QW
RI
RJ
RS
RT
SD
SW
SY
T
24
24
24
24
24
26
26
26
26
20
20
20
70
70
70
70
22
22
22
26
3040 0
e 0 e 0 e 0 e
3080 0
e 0 e 0 e 0 e
3010 0
e 0 e 0 e 0 e
3002 0
e 0 e 0 e0 e
3020 0
e 0 e 0 e 0 e
57 0
d 0 d
5F 0
d 0 d
7A0
d 0 d
72 0
d 0 d
4A8
d 0 d
5A8
d 0 d
52 8
d 0 d
6A0
d 0 d
47 0
d 0 d
62 0
d
0
d
4F 0
d 0 d
78 E B 0 0
d 0 d 0 d
78 CB 0 0
d 0 d 0 d
78 AB 0 0
d 0 d 0 d
02 0
d 0 d
L = Formal oper. 70 46 0
c 0 c
LC C
T
26
26
4C0
d 0 d
0C0
d 0 d
LDI A1
A2
BA
88
88
88
680B
682B
689B
C79000-K8576-C124-03 135
Operation Operand Page Machine Code
LDI BR
SA
88
88
68 AB
684B
LD = Formal oper. 70 0E 0
c 0 c
LDW = Formal oper. 70 56 0
c 0 c
LIM --- 98 700C
LIR Reg ister no. 86 4000
k
LRD Constant 106 6804 0
e 0 e 0 e 0 e
LRW Constant 106 6800 0
e 0 e 0 e 0 e
LW = Formal oper. 70 3F 0
c 0 c
LW CD Constant 114 786D 0
e 0 e 0 e 0 e
LW CW Constant 114 785D 0
e 0 e 0 e 0 e
LW GD Constant 110 786E 0
e 0 e 0 e 0 e
LW GW Constant 110 785E 0
e 0 e 0 e 0 e
LY CB Constant 112 780D 0
e 0 e 0 e 0 e
LY CD Constant 112 782D 0
e 0 e 0 e 0 e
LY CW Constant 112 781D 0
e 0 e 0 e 0 e
LY GB Constant 108 780E 0
e 0 e 0 e 0 e
LY GD Constant 108 782E 0
e 0 e 0 e 0 e
LY GW Constant 108 781E 0
e 0 e 0 e 0 e
MAB --- 104 6829
MAS --- 104 6819
MBA --- 104 6889
MBR Constant 104 78 0
e 90
e 0 e 0 e 0 e
MBS --- 104 6899
MSA --- 104 6849
MSB --- 104 6869
NOP 0 --- 54 0000
NOP 1 --- 54 FFFF
136 C79000-K8576-C124-03
Operation Operand Page Machine Code
OC
D
F
I
Q
S
T
---
14
12
12
12
12
12
14
14
B9 0
d 0 d
783F 10
b 0 g 0 g
88
b 0 a 0 a
C8
b 0 a 0 a
C8
b 8 a 0 a
781B 0
b 0 a 0 a 0 a
F9 0
d 0 d
FB 0 0
O( --- 16 BB 0 0
O = Formal oper. 56 0F 0
c 0 c
ON C
D
F
I
Q
S
T
14
14
14
14
14
14
14
BD 0
d 0 d
783F 30
b 0 g 0 g
A8
b 0 a 0 a
E8
b 0 a 0 a
E8
b 8 a 0 a
785B 0
b 0 a 0 a 0 a
FD0
d 0 d
ON = Formal oper. 56 2F 0
c 0 c
OW --- 56 4900
RC
D
F
I
Q
S
T
36
18
18
16
16
18
34
7C0
d 0 d
783F 50
b
0
g 0 g
B0
b 0 a 0 a
F0
b 0 a 0 a
F0
b 8 a 0 a
786B 0
b 0 a 0 a 0 a
3C0
d 0 d
RA --- 80 0880
C79000-K8576-C124-03 137
Operation Operand Page Machine Code
RAE --- 80 7810
RB = Formal oper. 62 37 0
c 0 c
RD = Formal oper. 62 3E 0
c 0 c
RLD Constant 76 64 0
h 0 h
RRD Constant 76 74 0
h 0 h
RU C
D
F
I
Q
RI
RJ
RS
RT
T
64
64
64
64
64
64
64
100
100
64
7015 00
b
0
g
0
g
7046 00
b
0
g
0
g
7049 00
b
0
g
0
g
7038 00
b
0
a
0
a
7038 00
b
8
a
0
a
7047 00
b
0
g
0
g
701E 00
b
0
g
0
g
7057 00
b
0
g
0
g
700E 00
b
0
g
0
g
7025 00
b
0
g
0
g
SC
D
F
I
Q
S
36
16
16
16
16
16
5C0
d 0 d
783F 40
b
0
g 0 g
90
b 0 a 0 a
D0
b 0 a 0 a
D0
b 8 a 0 a
782B 0
b 0 a 0 a 0 a
S = Formal oper. 62 17 0
c 0 c
SD T3424 0
d 0 d
SD = Formal oper. 66 26 0
c 0 c
SE T341C0
d 0 d
SEC = Formal oper. 66 1E 0
c 0 c
SED Constant 82 7806 000
n 0 n
138 C79000-K8576-C124-03
Operation Operand Page Machine Code
SEE Constant 82 7807 000
n 0 n
SF T3414 0
d 0 d
SFD = Formal oper. 66 16 0
c 0 c
SIM --- 98 700D
SLD Constant 76 29 0
h 0 h
SLW Constant 76 6100
h
SP T3434 0
d 0 d
SP = Formal oper. 66 36 0
c 0 c
SRW Constant 76 6900
h
SS T342C0
d 0 d
SSD Constant 76 71 0
h 0 h
SSU = Formal oper. 66 2E 0
c 0 c
SSW Constant 76 68 0
h 1
STP --- 54 7003
STS --- 98 7000
STW --- 98 7004
SU C
D
F
I
Q
RI
RJ
RS
RT
T
62
64
62
62
62
64
64
100
100
62
7015 40
b
0
g
0
g
7046 40
b
0
g
0
g
7049 40
b
0
g
0
g
7038 40
b
0
a
0
a
7038 40
b
8
a
0
a
7047 40
b
0
g
0
g
701E 40
b
0
g
0
g
7057 40
b
0
g
0
g
700E 40
b
0
g
0
g
7025 40
b
0
g
0
g
C79000-K8576-C124-03 139
Operation Operand Page Machine Code
TDD
DL
DR
DW
FD
FW
FY
IB
30
30
30
30
28
28
28
28
3B0
d 0 d
23 0
d 0 d
2B0
d 0 d
33 0
d 0 d
1B0
d 0 d
13 0
d 0 d
0B0
d 0 d
4B0
d 0 d
ID
IW
OW
OY
PW
PY
QB
QD
QW
RI
RJ
RS
RT
SD
SW
SY
28
28
32
32
32
32
28
28
28
72
72
72
72
30
30
30
5B0
d 0 d
53 0
d 0 d
77 0
d 0 d
7F 0
d 0 d
7B0
d 0 d
73 0
d 0 d
4B8
d 0 d
5B8
d 0 d
53 8
d 0 d
6B0
d 0 d
67 0
d 0 d
63 0
d 0 d
6F 0
d 0 d
78 F B 0 0
d 0 d 0 d
78 DB 0 0
d 0 d 0d
78 B B 0 0
d
0
d 0 d
T = Formal oper. 70 66 0
c 0 c
TB C
D
58
58
7015 C0
b
0
g
0
g
7046 C0
b
0
g
0
g
140 C79000-K8576-C124-03
Operation Operand Page Machine Code
TB F
I
Q
RI
RJ
RS
RT
T
58
58
58
58
58
58
58
58
7049 C0
b
0
a
0
a
7038 C0
b
0
a
0
a
7038 C0
b
8
a
0
a
7047 C0
b
0
g
0
g
701E C0
b
0
g
0
g
7057 C0
b
0
g
0
g
700E C0
b
0
g
0
g
7025 C0
b
0
g
0
g
TBN C
D
F
I
Q
RI
RJ
RS
RT
T
60
60
60
60
60
60
60
60
60
60
7015 80
b
0
g
0
g
7046 80
b
0
g
0
g
7049 80
b
0
a
0
a
7038 80
b
0
a
0
a
7038 80
b
8
a
0
a
7047 80
b
0
g
0
g
701E 80
b
0
g
0
g
7057 80
b
0
g
0
g
700E 80
b
0
g
0
g
7025 80
b
0
g
0
g
TAK --- 96 7002
TDI A1
A2
BA
BR
SA
88
88
88
88
88
680F
682F
689F
68 AF
684F
TIR Reg ister no. 86 4800
k
TNB Constant 90 03 0
l 0 l
TNW Constant 90 43 0
o 0 o
C79000-K8576-C124-03 141
Operation Operand Page Machine Code
TRD Constant 106 6805 0
e 0 e 0 e 0 e
TRW Constant 106 6803 0
e 0 e 0 e 0 e
TSC Constant 110 78 CD 0
e 0 e 0 e 0 e
TSG Constant 106 78 CE 0
e 0 e 0 e 0 e
TW CD Constant 114 78 E D 0
e 0 e 0 e 0 e
TW CW Constant 114 78 DD 0
e 0 e 0 e 0 e
TW GD Constant 110 78 E E 0
e 0 e 0 e 0 e
TW GW Constant 110 78 DE 0
e 0 e 0 e 0 e
TXB --- 92 701F
TXW --- 92 700F
TY CB Constant 112 788D 0
e 0 e 0 e 0 e
TY CD Constant 112 78 AD 0
e 0 e 0 e 0 e
TY CW Constant 112 789D 0
e 0 e 0 e 0 e
TY GB Constant 108 788E 0
e 0 e 0 e 0 e
TY GD Constant 108 78 AE 0
e 0 e 0 e 0 e
TY GW Constant 108 789E 0
e 0 e 0 e 0 e
XOW --- 56 5100
)16 BF 0 0
=D
F
I
Q
S
18
18
18
18
18
783F 60
b 0 g 0 g
98
b 0 a 0 a
D8
b 0 a 0 a
D8
b 8 a 0 a
783B 0
b 0 a 0 a 0 a
= = Formal oper. 62 1F 0
c 0 c
>D --- 46 3920
<D --- 46 3940
><D --- 46 3960
!=D --- 46 3980
142 C79000-K8576-C124-03
Operation Operand Page Machine Code
>=D --- 46 39 A0
<=D --- 46 39 C 0
+D --- 94 600D
-D --- 94 6009
:F --- 38 6000
xF --- 38 6004
+F --- 38 7900
-F --- 38 5900
!=F --- 42 2180
>F --- 42 2120
<F --- 42 2140
><F --- 42 2160
>=F --- 42 21 A0
<=F --- 42 21 C 0
>G --- 44 3120
<G --- 44 3140
><G --- 44 3160
!= G --- 44 3180
>=G --- 44 31 A0
<=G --- 44 31 C 0
:G --- 40 6003
xG --- 40 6007
+G --- 40 600F
-G --- 40 600B
C79000-K8576-C124-03 143
Exp lan ato ry Notes on
the Cond itio n Code s
Structu re o f the Co ndi tion Co de Byte
CC1 CC0 OV OS OR STA RLO ERAB
Bit 76543210
Abbreviations Description
CC 0 / CC 1 Condition codes 0/1
(see Evaluation of CC 0 and CC 1)
OV Overflow. This condition code is set if the
maximum number range is exceeded during
arit hm et i c operation s.
OS Store d overflow. The overflo w bit is store d.
This is an indication of whether and when an
overfl ow e rror has occurred in the course of
arit hm et i c operation s.
OR Int ern al co nd ition co de of the processor
rela tin g to AND an d OR operatio ns .
STA STATUS; Signal status of the b it scanned .
RLO Result of Logic Operation. Contains the result
of individu al bit operation s a nd comparison
operations.
ERAB First bit scanned. ERAB = 0 iden tifie s th e
beginning and the end of a string of logic
operations. The first operation of the string
se t s the ERAB bit to "1". Only at the end of the
string is the ERAB bit reset (e.g. by a set/re se t
operation).
W ord co des Bit codes
144 C79000-K8576-C124-03
Evaluation of CC0 and C C1
C
C
1
C
C
0
Arith-
metic
Opera-
tions
Digital
Logic
Opera-
tions
Com-
parison
Opera-
tions
Shift
Opera-
tions
For
SED,
SEE
Jump
Opera-
tions
Exe-
cuted
00
Result
= 0 Result
= 0 ACCU 2
=
ACCU 1
shifted
bit
= 0
Sema-
phore
has
been
set
JZ
01
Result
< 0 -ACCU 2
<
ACCU 1
--JM
JN
10
Result
> 0 Result
≠ 0 ACCU 2
>
ACCU 1
shifted
bit
= 1
Sema-
phore
is set
now
JP
JN
11
Divide
by 0 ----JN 1)
1) not executed with CPU 948
C79000-K8576-C124-03 145
Lis t of Orga nizat ion
Blocks
Organization
Block
= OB available on this CPU
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
OBs for Program Processing
OB 1 1) 1) 1) OB for cyclic program processing
OB 2 3) I nterrupt-dr iven pro gram pro ce ssing
OB 3 to OB 8 3) I nterrupt-dr iven pro gram pro ce ssing
OB 6 3) Delay interrupt
OB 9 3) T ime-dr iven pro gram proce ssing
O B 10 10 ms 10 ms 0.1 s 2) 3)
Time interrupts with set time grid
O B 11 20 ms 20 ms 0.2 s 2) 3)
O B 12 50 ms 50 ms 0.5 s 2) 3)
OB 13 100 ms 100 ms 100 ms 1.0 s 2) 3)
O B 14 200 ms 200 ms 2.0 s 2) 3)
O B 15 500 ms 500 ms 5.0 s 2) 3)
OB 16 1 s 1 s 10.0 s 2) 3)
OB 17 2 s 2 s 20.0 s 2) 3)
OB 18 5 s 5 s 50.0 s 2) 3)
1) alternative FB 0 3) Details about the functions of these OBs of the CPU 948 c an
be fo und in the "CPU 9 48 Prog ramm ing Guide" .
2) De fau lt se tting, can be chan ge d via DX 0
146 147
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
= OB available on this CPU
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
OBs for Program Processing (continued)
OB 31 1) Set c ycle mon itoring time
OB 39 Organ ization of the cyclic pro gram for
communication in SMOOTH STOP
OBs for Start-up Proced ures
OB 20 Ma nual or aut om ati c cold restart
(can be set in DX 0)
OB 21 Ma nu al warm restart
OB 22 Auto ma tic warm restart after power fail ure
OB 38 Org ani zation of the restart beh avio r for
communication in SMOOTH STOP
1) The se ttin g of the cycle moni tori ng time vi a OB 31 has
a higher priority than the setting via DX 0 (CPU 948).
148 149
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
= OB not available on this CPU
= OB not available on this CPU Cause of error Reaction
without
OB
CPU
922 CPU
928 CPU
928B
OBs for Handling Controller Errors
in the CPU 922/928/928B
OB 19 Call of a block not programmed (LZF) Stop
OB 23 Timeo ut in the case of direct access to the I/O m odul e
(QVZ) none
OB 24 Tim eo ut whe n up da ting t he pro ce ss im a ge and
tran sf errin g int erprocessor communication flags none
OB 25 Addressing error (ADF) Stop
OB 26 Scan time exceeded (ZYK-FE) Stop
OB 27 Substitution error (BCF) Stop
OB 28 Stop by PG function/Stop switch/S5-BUS (ABBR) Stop1)
OB 29 Operatio n error (BCF) Stop
OB 30 Parameter assignment error (BCF) Stop
OB 31 Other execution time errors (LZF) Stop
1) Switchover to the STOP state always occurs independently of
whether OB 28 is programmed and how it is programmed.
150 151
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
= OB available on this CPU
= OB not available on this CPU Cause of error Reaction
without
OB
CPU
922 CPU
928 CPU
928B
OBs for Handling Controller Errors
in th e CPU 922/928/928B (continued)
OB 32 1) Transfer errors in the case of data blocks (LZF)1) Stop
OB 33 Collision of two timed interrupts (WECK-FE) Stop
OB 34 Error in PID controller processing Stop
OB 35 Interface error none
1) On CPU 92 8B also loadi ng erro r
152 153
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block Cause of error Reaction
without OB Organization
Bloc k Caus e of e rror Reaction
without OB
OB s for Handling Contro lle r Errors
in the CPU 948 OBs for Handling Controller Errors
in the CPU 948 (continued)
OB 19
Call a block that is not loaded
(KB)
Ope n a dat a bloc k that i s not
loa ded (KDB)
none
Stop
OB 29
Timeout for distributed peripherals for
the address areas:
- F 0000H to F EFFFH,
F F200H to F FFFFH none
OB 23
Timeout during direct access
(user program) to CP, IP, COR
or I/O modules via the S5 bus
(QVZ) none OB 30 Parity error and QVZ in the user
memory (PARE) Stop
OB 24 Timeout while updating the
process image or transferring
the IPC flags none OB 32 Load/transfer error (TLAF) Stop
OB 25 Addressing error (ADF) 1)
Stop
OB 33
Collision of time interrupts:
- Queue overflow (WEFES)
- The time interrupt pulse has been
masked for too long (WEFEH)
Stop
none
OB 26 Cycle time exceed ed (ZYK) Stop OB 34 Error while generating a data block
with G DB or GX DX (FEDBX) Stop
OB 27 Substitution error (SUF) Stop
OB 28 Timeout in input byte IB 0
(QVZ) Stop
1) if not inhibited by IAE
154 155
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Special Fu nct ion OB s
O B 11 0 31 - 34 1) 18 - 20 1.7 Ac cess to the cond itio n-code byte
OB 111 12 1.2 Reset accumulators
OB 112 14 2.0 Roll up accumulator
OB 113 14 2.0 Roll down accumulator
O B 12 0 70 - 76 1) 36 - 128 68 Activate/deactivate "Disable all int errupts"
OB 121 36 - 136 68 Activate/deactivate "Disable cyclic time inte rrupts
individually"
58 - 78 Set/read system time (compatible to CPU 946/947)
OB 122 47 - 52 1) 37 - 39 73 Activate/deactivate "Delay all interrupts"
26 Activate/deactivate "Disable all interrupts"
OB 123 39 - 54 73 Ativate/deactivate "Delay cyclic time interrupts
individually"
OB 124 1327 De lete STEP 5 bl oc ks
OB 125 1477 Generate STEP 5 blocks
OB 126 93 Define an d transfer process i mages
1) OB only available from version 09
156 157
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Special Function s OBs (con ti n ued)
OB 129 15 D etermine batter y status
OB 131 1.8 Delete Accu 1 to 4
OB 132 2.2 Accu roll up
OB 133 2.4 Accu roll down
OB 141 47 Activate/deactivate "Disable cyclic time interrupts
individually"
OB 142 49 Activate/deactivate "Delay all interrupts"
OB 143 47 Ativate/deactivate "Delay cyclic time interrupts
individually"
OB 150 265 266 Set system time
132 153 Re ad system t im e
OB 151
Clock-controlled time interrupt
Job
type Function
125 262 0 set
ma x. 267 m ax. 2 84 1 to 7
123 166 0 read
max. 152 202 1 to 7
158 159
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Speci al Fun cti on OBs (co n tinu ed )
OB 152 90 Cycle scan statistic
OB 153
Delay interrupt
Function no. Function
66 110 1 Define and start delay time
60 72 2 Stop delay time
70 80 3 Rea d curren t re main ing time
O B 16 0 - 163 21 - 23 1) 11 - 14 1.1 Repeat loops
OB 170 55 + n * 27.5 1) 34 + n * 15.8 60 + n * 13.3 Read block stack (BSTACK); n =
number of BSTACK elements
OB 180 16 1.0 76 Random data block access
O B 18 1 40 - 53 1) 24 - 29 3.6 38 Test data blocks (DB/DX)
OB 182 171 + n * 0.65 170+n ⋅ 1 2)
170+n ⋅ 10 .5 3) Copy data area; 4)
n = number of da ta word s
1) OB only available from version 09. 4) CPU 948: The copy direction "decrementing" is standard. The
direction "incrementing" is only selected if the data areas
2) For copy direction decrementing overlap each other. This includes that the start address of the
source area is smaller than the end address of the source area.
3) For copy direction incrementing
160 161
C79000-K8576-C124-03 C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Speci al Fun cti on OBs (co n tinu ed )
OB 190
1) 47 + n * 0.75
2)
48.5 + n * 0.5
3)
25 + n * 0.5 2)
25 + n * 0.3 3) 54 + n * 0.5 2)
55 + n * 0.3 3)
Transfer flag byte by byte into data block;
n = number of flag bytes
OB 191
1) 47 + n * 0.75
2)
48 + n * 0.5 3) 25 + n * 0.5 2)
25 + n * 0.3 3) 54 + n * 0.5 2)
55 + n * 0.3 3) Transfer dat a field byte by byte into fla g area;
n = number of flag bytes
OB 192
1) 46 + n * 2.8 2)
46 + n * 2.55
3) 25 + n * 1.8 2)
40 + n * 0.57 3) 51 + n * 1.8 2)
53 + n * 0.57 3) Transfer flag word by word into a data block;
n = number of flag bytes
OB 193
1) 46 + n * 2.8 2)
46 + n * 2.55
3) 25 + n * 1.8 2)
40 + n * 0.57 3) 51 + n * 1.8 2)
53 + n * 0.57 3) Transfer data field word by word into flag area;
n = number of flag bytes
O B 200,
202 - 205 4) 4) 4) 4) I nterpro ce ssor commu nicat ion in multip rocessor
mode
OB 216 31.8 - 42.5 28 - 35 58 - 65 Access to page frames
OB 217 32.6 - 43.1 30 - 35 60 - 66 Access to page frames
O B 218 26.3 21 54 Access to page frames
1) OB only available from version 09.
2) If number of first flag byte is uneven.
3) If number of first flag byte is even.
4) See manu al of relevant CPU.
162 163
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Speci al Fun cti on OBs (co n tinu ed )
OB 220 25 14 0.57 Convert the contents of ACCU 1 from a 16-bit fixed-
poi nt nu mb er to a 32-b it fixed-point num be r
O B 221 44.5 36 62 Set and trigger a new scan time monitor
O B 222 21.5 18 48 35 Retrigger the scan time monitor
OB 223 39 18 48 13 Change to stop status in case of non-uniform
re st art mode s in multi pro ce ssor mo de
OB 224 23 11 41 Block transf er of the interprocessor c omm unicat ion
flag s in mu ltipro cessor mo de
OB 226 29 19 53 Read the contents of a system program memory
location
OB 227 31 14 48 Read the check sum of the system program
memory
O B 228 34.51) 21 56 Read status information of a program
processing level
O B 23 0 - 237 2) 2) 2) 2) Functions for handling blocks
1) OB only available from version 09 2) See Manual "SIMATIC S5 - Standard Function Blocks
Handling Block s CPU 92 2, CPU 92 8, CPU 928 B
S5-135U, S5-155U Programmable Controllers"
164 165
C79000-K8576-C124-03
C79000-K8576-C124-03
Lis t of Orga nizat ion
Blocks
Organization
Block
Execution times in µs
= OB not available on this CPU Function
CPU
922 CPU
928 CPU
928B CPU
948
Special Function OBs (con tin ued )
OB 240 120 - 805 73 + n * 12 105 + n * 12 Initialize a shift register; n = number of pointers
OB 241 42 - 110 28 + n * 12 60 + n * 9 Call a shift register; n = number of pointers
OB 242 12 17 46 Delete a shift register
O B 250 158 114 144 Initialize a PID controller
OB 251 < 730 425 455 Call a PID cont roll er
OB 254 85 + n * 1 80 + n * 0.2 112 + n * 0.7 1472 - 2869 Copy a DX data block (extension); n = number of
data words to be transferred
OB 255 85 + n * 1 80 + n * 0.2 112 + n * 0.7 1472 - 2869 Copy a DB data block ; n = number of dat a words
to be transferred
166 167
C79000-K8576-C124-03
C79000-K8576-C124-03
Intent ionally blank!
168 C79000-K8576-C124-03
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