AK8130
MS0598-E-04 Aug-10
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1
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Features
27MHz Crystal Input
Four Frequency-Selectable Clock Outputs
One 27MHz-Reference Output
Selectable Clock out Frequencies:
- 54.000,74.1758, 74.250MHz
- 25.000MHz
- 4.9152MHz
- 24.576, 33.333MHz
Built-in VCXO
- Pull Range: ±110ppm (Min.)
Low Jitter Performance
- Period Jitter:
150 psec (Typ.) at CLK1-4
- Long Term Jitter :
160 psec (Typ.) at REFOUT
Low Current Consumption:
16.5mA (Typ.) at 3.3V
Supply Voltage:
3.0 – 3.6V
Operating Temperature Range:
-20 to +85℃
Package:
16-pin TSSOP (Lead free)
Description
The AK8130 is a member of AKM’s low power
multi clock generator family designed for a feature
rich DTV or STB, requiring a range of system
clocks with high performance. The AK8130
generates different frequency clocks from a 27MHz
crystal oscillator and provides them to up to four
outputs configured by pin-setting. The on-chip
VCXO accepts a voltage control input to allow the
output clocks to vary by ±110 ppm for
synchronizing to the external clock system. Both
circuitries of VCXO and PLL in AK8130 are derived
from AKM’s long-term-experienced clock device
technology, and enable clock output to perform low
jitter and to operate with very low current
consumption. The AK8130 is available in a
16-pin SSOP package.
Applications
Digital TV Sets
Personal Video Recorders
Set-Top-Boxes
Multi Media Receivers
Block Diagram
AK8130 Multi Clock Generator
Low Power
Multiclock Generator with VCXO
AK8130
PLL1
PLL2
CLK1
CLK2
CLK3
CLK4
REFOUT
GND
PLL1
S0
S1
S2
Divide
Logic
and
Output
Control
VDD
PLL3
Voltage
Controlled
Crystal
Oscillator
X1
X2
VIN
AK8130
Aug-10 MS0598-E-04
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Pin Descriptions
Package: 16-Pin TSSOP(Top View)
Pin
No.
Pin
Name
Pin
Type
Description
1
X1 XO
Crystal connection, Connect to 27.000MHz crystal
2
S0 IN Clock Out Frequency Select 0, See Table 1 for the selection (1)
3
S1 IN Clock Out Frequency select 1, See Table 1 for the selection (1)
4
VIN IN VCXO Control Voltage Input
5
VDD1
-- Power Supply 1
6
GND1
-- Ground 1
7
CLK1
OUT
Clock output 1, See Table 1 for its selectable frequency
8
CLK2
OUT
Clock output 2, See Table 1 for its selectable frequency (2)
9
REF
OUT
OUT
Reference Clock Output of VCXO based on 27.000MHz Crystal
10
CLK3
OUT
Clock output 3, See Table 1 for its selectable frequency (2)
11
CLK4
OUT
Clock output 4, See Table 1 for its selectable frequency (2)
12
GND2
-- Ground 2
13
VDD2
-- Power Supply 2
14
S2 IN Clock Out Frequency select 1, See Table 1 for the selection (1)
15
VDD3
-- Power Supply 3
16
X2 XI Crystal connection, Connect to 27.000MHz crystal
(1) Internal pull up 360kΩ
(2) Internal pull down 510kΩ
Ordering Information
Part Number Marking Shipping
Packaging Package Temperature
Range
AK8130 8130 Tape and Reel 16-pin ＴSSOP -20 to 85 ℃
16
15
14
13
12
11
10
9
X1
S0
S1
VIN
VDD1
GND1
CLK1
CLK2
X2
VDD3
S2
VDD2
GND2
CLK4
CLK3
REFOUT
1
2
3
4
5
6
7
8
AK8130
MS0598-E-04 Aug-10
- 3 -
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted (1)
Items Symbol
Ratings Unit
Supply voltage VDD -0.3 to 4.6 V
Input voltage Vin VSS-0.3 to VDD+0.3 V
Input current (any pins except supplies) IIN ±10 mA
Storage temperature Tstg -55 to 130 °C
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter Symbol
Conditions Min Typ Max Unit
Operating temperature Ta -20 85 °C
Supply voltage (1) VDD 3.0 3.3 3.6 V
Cp1 Pin: CLK1-4 15 pF
Output Load Capacitance Cp2 Pin: REFOUT 25 pF
Note:
(1) Power to VDD1, VDD2 and VDD3 requires to be supplied from a single source. A decoupling capacitor of
0.1µF for power supply line should be installed close to each VDD pin.
ESD Sensitive Device
AK8130
Aug-10 MS0598-E-04
- 4 -
DC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta: -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter Symbol
Conditions MIN TYP MAX Unit
High Level Input Voltage VIH Pin: S0,S1,S2 0.7VDD
V
Low Level Input Voltage VIL Pin: S0,S1,S2 0.3VDD
V
Input Current 1 IL1 Pin: S0,S1,S2 -20 +10 μA
Input Current 2 IL2 PIN: VIN -3 +3 μA
High Level Output
Voltage VOH Pin: CLK1-4, REFOUT
IOH=-4mA 0.8VDD
V
Low level Output
Voltage VOL Pin: CLK1-4, REFOUT
IOL=+4mA 0.2VDD
V
Current Consumption IDD Clock out selection by note (1)
No load,Ta=25℃ 16.5 mA
(1) Pin setting for output clock selection: [S2:S0] = HLH
AC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta: over -20 to +85℃, 27MHz Crystal, unless otherwise noted
(1) Measured with load capacitance of 15pF
(2) Measured with load capacitance of 25pF
(3) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB.
Min. ±110ppm is applied to AKM’s authorized test condition.
(4) ±3σ in 1000 sampling or more
(5) ±3σ in 5000 sampling or more
(6) Time to settle output into ±20ppm of specified frequency
Parameter Symbol
Conditions MIN TYP MAX Unit
Crystal Clock Frequency 27.0000
MHz
VCXO Pullable Range (3) VIN at over 0 to VDD V ±110 ppm
VCXO Gain GVCXO
VIN range at 1.5V±1.0V 150 ppm/
V
Period Jitter (4) CLK1-4 150 ps
CLK1 at 54.000MHz
1000 cycle delay 0.5 ns
CLK1 at 74.250MHz
1000 cycle delay 0.85 ns
Long Term Jitter (5)
REFOUT at 27.000MHz
1000 cycle delay 160 ps
Pin: CLK1-4 (1) 45 50 55 %
Output Clock Duty
Cycle Pin: REFOUT (2) 40 50 60 %
Pin: CLK1-4 (1) 1.5 ns
Output Clock Rise Time trise Pin: REFOUT (2 ) 2.5 ns
Pin: CLK1-4 (1) 1.5 ns
Output Clock Fall Time tfall Pin: REFOUT (2 ) 2.5 ns
Power-up Time Pin: CLK1-4 (1) 5 ms
Output Transition Time (6) Pin: CLK1 at
74.25 or 74.175MHz 200 µs
AK8130
MS0598-E-04 Aug-10
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Output clock frequency selection
The AK8130 generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs and
provides to up to four assigned outputs. A frequency selection at assigned output pin is configured by
pin-setting of S0 (Pin2), S1 (Pin3), and S2 (Pin14).
The selectable frequency is shown in Table 1..
Table 1: Clock output Frequency
Selection Pin Clock Output Frequency (MHz)
S2
(Pin 14)
S1
(Pin 3)
S0
(Pin 2)
CLK1
(Pin 7) CLK2
(Pin 8) CLK3
(Pin 10) CLK4
(Pin 11)
L L L 74.250 25.000 OFF 33.333
L L H 74.250 25.000 4.9152 OFF
L H L 74.250 25.000 OFF 24.576
L H H 54.000 OFF 4.9152 24.576
H L L 74.1758 25.000 OFF 33.333
H L H 74.1758 25.000 4.9152 OFF
H H L 74.1758 25.000 OFF 24.576
H H H 74.1758 OFF 4.9152 24.576
Voltage Control Crystal Oscillator (VCXO)
The AK8130 has a voltage control crystal oscillator (VCXO), featuring fine frequency tuning for 27MHz of
primary clock frequency by external DC voltage control. This tuning enables output clock frequency to
synchronize the external clock system. VIN (Pin 4) accepts DC voltage control from a processor or a
system controller, and pulls the primary frequency of crystal to higher or lower. This pulling range is
determined by crystal characteristic, on-chip load capacitor, and stray capacitance of PCB. The AK8130
is designed to range ±110ppm of primary frequency in AKM’s authorized condition, and the typical pulling
profile is shown in Figure 1. For details about the condition and other specific crystal application case,
refer the AK8130 Family application note.
27.0MHz VCXO Characteristics NDK AT-41CD2
（
CL=12.0pF
）
（
Cext1=18.0pF,Cext2=5.0pF)
-150
-100
-50
0
50
100
150
0 0.5 1 1.5 2 2.5 3 3.5
VIN(V)
Δf(ppm)
Figure 1: Typical VCXO Pulling Profile
AK8130
Aug-10 MS0598-E-04
- 6 -
Typical Connection Diagram
Figure 2: Typical Connection Diagram
C1, C2, C3: 0.1µF
Cext1, Cext2: Depends on crystal characteristics. Refer the specification of the crystal.
R11, C11: In case of interface by PWM. For right configuration, refer the specification of the
applied processor.
PCB Layout Consideration
The AK8130 is a high-accuracy and low-jitter multi clock generator. For proper performances specified in
this datasheet, careful PCB layout should be taken. The followings are layout guidelines based on the
typical connection diagram shown in Figure 2
Power supply line – AK8130 has three power supply pins (VDD1-3) which deliver power to internal
circuitry segments. A 0.1µF decoupling capacitor should be placed as close to each VDD pin as possible.
Ground pin connection – AK8130 has two ground pins (GND1-2). These pin require connecting to plane
ground which will eliminate any common impedance with other critical switching signal return. 0.1µF
decoupling capacitors placed at VDD1, VDD2, and VDD3 should be grounded at close to the GND1pin, the
GND2 pin, and the GND2, respectively.
Crystal connection – Proper oscillation performance and pullable range are susceptible to stray or
parasitic capacitors around crystal. The wiring traces to a crystal form X1 (Pin 1) and X2 (Pin 14) have
equal lengths with no via and as short in length as possible. These traces should be also located away
from any traces with switching signal.
1:X1
2:S0
3:S1
4:VIN
5:VDD1
6:GND1
7:CLK1
8:CLK2
X2:16
VDD3:15
S2:14
VDD2:13
GND2:12
CLK4:11
CLK3:10
REFOUT:9
AK
8130
+3.3V typ.
GND
Cext1 Cext2
C1
C2
C3
REF CLK IN
CTL OUT2
CTL OUT0
CTL OUT1
27.0MHz AT Cut Crystal
DC Voltage
CTL OUT
(PWM)
IEEE1394
24.576MHz
Modem
4.9152MHz
Ethernet I/F
25.0MHz
HDMI LVDS I/F
74.25/74.1758MHz
R11
C11
MPEG
-
TS
DECODER
AK8130
MS0598-E-04 Aug-10
- 7 -
Package Information
• Mechanical data
0.
1
±
0.
1
0
-
10
°
Detail A
0.1
5
±
0.
1
0.
22
±
0.
05
0.
6
5
5.0
A
1
8
9
16
16
pin SSOP (Unit: mm)
4.4
±
0.2
6.4
±
0.3
0.5
±
0.2
1.15
±
0.1
0.1
±
0.1
+0.3
-0.1
0.1
• Marking
a: #1 Pin Index
b: Product Family Logo
c: Part number
d Date code (5 digits)
.
• RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
1
16
8
9
AKM
8130
XXXXX
a
b
c
d
AK8130
Aug-10 MS0598-E-04
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IMPORTANT NOTICE
l These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
l Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application
examples of the semiconductor products. You are fully responsible for the incorporation of
these external circuits, application circuits, software and other related information in the
design of your equipments. AKM assumes no responsibility for any losses incurred by you or
third parties arising from the use of these information herein. AKM assumes no liability for
infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
l Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
l AKM products are neither intended nor authorized for use as critical componentsNote1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably
be expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet very
high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
l It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes
of, or otherwise places the product with a third party, to notify such third party in advance of
the above content and conditions, and the buyer or distributor agrees to assume any and all
responsibility and liability for and hold AKM harmless from any and all claims arising from the
use of said product in the absence of such notification.
