TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1992, Texas Instruments Incorporated
1
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
•High-Performance Operation:
fmax (no feedback)
TIBPAL16R’-5C Series . . . 125 MHz Min
TIBPAL16R’-7M Series . . . 100 MHz Min
fmax (internal feedback)
TIBPAL16R’-5C Series . . . 125 MHz Min
TIBPAL16R’-7M Series . . . 100 MHz Min
fmax (external feedback)
TIBPAL16R’-5C Series . . . 117 MHz Min
TIBPAL16R’-7M Series . . . 74 MHz Min
Propagation Delay
TIBPAL16L8-5C Series . . . 5 ns Max
TIBPAL16L8-7M Series . . . 7 ns Max
TIBPAL16R’-5C Series
(CLK-to-Q) . . . 4 ns Max
TIBPAL16R ’-7M Series
(CLK-to-Q) . . . 6.5 ns Max
•Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
•Preload Capability on Output Registers
Simplifies Testing
•Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•Security Fuse Prevents Duplication
DEVICE I
INPUTS 3-STATE
O OUTPUTS REGISTERED
Q OUTPUTS
I/O
PORT
S
’PAL16L8 10 2 0 6
’PAL16R4 8 0 4 (3-state buffers) 4
’PAL16R6 8 0 6 (3-state buffers) 2
’PAL16R8 8 0 8 (3-state buffers) 0
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
IVCC
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
I/O
QI/O
I
GND
VCC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
Q
QQ
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
TIBPAL16L8-5C, TIBPAL16R4-5C
TIBPAL16L8-7M, TIBPAL16R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16L8’
TIBPAL16R4’
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
32 X 64
10 16
166
7
7
7
7
7
7
7
7
6
16 x
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
16 x
≥1
&
32 X 64 ≥1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16R6’
TIBPAL16R8’
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
16 x
≥1
&
32 X 64 ≥1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I816
168
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
32 X 64 ≥1
OE
8Q
8Q
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
INCREMENT
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
FIRST
FUSE
NUMBERS
TIBPAL16L8-5C
TIBPAL16L8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
logic diagram (positive logic)
04812 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
INCREMENT
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
FIRST
FUSE
NUMBERS
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
TIBPAL16R4-5C
TIBPAL16R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
INCREMENT
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
FIRST
FUSE
NUMBERS
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
TIBPAL16R6-5C
TIBPAL16R6-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
11
INCREMENT
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
FIRST
FUSE
NUMBERS
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
Q
19
C1
1D
I = 0
Q
12
C1
1D
I = 0
TIBPAL16R8-5C
TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
logic diagram (positive logic)
UNITPARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
tpd ns
TIBPAL16L8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current –3.2 mA
IOL Low-level output current 24 mA
TAOperating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –0.8 –1.5 V
VOH VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZH‡VCC = 5.25 V, VO = 2.7 V 100 µA
IOZL‡VCC = 5.25 V, VO = 0.4 V –100 µA
IIVCC = 5.25 V, VI = 5.5 V 100 µA
IIH‡VCC = 5.25 V, VI = 2.7 V 25 µA
IIL‡VCC = 5.25 V, VI = 0.4 V –250 µA
IOS§VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 180 mA
Cif = 1 MHz, VI = 2 V 8.5 pF
Cof = 1 MHz, VO = 2 V 10 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16L8-5CFN TIBPAL16L8-5CJ
TIBPAL16L8-5CN
MIN MAX MIN MAX
I, I/O O, I/O with up to 4 outputs
switching 1.5 5 1.5 5
I, I/O O, I/O with more than 4
outputs switching 1.5 5 1.5 5.5
ten I, I/O O, I/O 2 7 2 7 ns
tdis I, I/O O, I/O 2 7 2 7 ns
ns
Pulse duration, clocktw
TIBPAL16R4-5C, TIBPAL16R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current –3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 125 MHz
High 4
Low 4
tsu Setup time, input or feedback before clock↑4.5 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
VO = 2 V
VI = 2 Vf = 1 MHz,
f = 1 MHz,
Ci
Co
pF
pF
UNITPARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS
TIBPAL16R4-5C, TIBPAL16R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –0.8 –1.5 V
VOH VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZH‡VCC = 5.25 V, VO = 2.7 V 100 µA
IOZL‡VCC = 5.25 V, VO = 0.4 V –100 µA
IIVCC = 5.25 V, VI = 5.5 V 100 µA
IIH‡VCC = 5.25 V, VI = 2.7 V 25 µA
IIL‡VCC = 5.25 V, VI = 0.4 V –250 µA
IOS§VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 200 mA
I 7
CLK/OE 5
I/O 10
Q 7
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16R4-5CFN
TIBPAL16R6-5CFN
TIBPAL16R4-5CJ
TIBPAL16R6-5CJ
TIBPAL16R4-5CN
TIBPAL16R6-5CN
MIN TYP†MAX MIN TYP†MAX
without feedback 125 125
fmax¶with internal feedback (counter configuration) 125 125 MHz
with external feedback 117 111
tpd CLK↑Q 1.5 4 1.5 4.5 ns
tpd CLK↑Internal feedback R1 = 200 Ω, 3.5 3.5 ns
tpd I, I/O I/O R2 = 200 Ω, 1.5 5 1.5 5 ns
ten OE↓QSee Figure 8 1.5 6 1.5 6 ns
tdis OE↑Q 1 6.5 1 7 ns
ten I, I/O I/O 2 7 2 7 ns
tdis I, I/O I/O 2 7 2 7 ns
tr1.5 1.5 ns
tf1.5 1.5 ns
tsk(o)#Skew between registered outputs 0.5 0.5 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
¶See ’fmax Specification’ near the end of this data sheet.
#tsk(o) is the skew time between registered outputs.
ns
Pulse duration, clocktw
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current –3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 125 MHz
High 4
Low 4
tsu Setup time, input or feedback before clock↑4.5 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PARAMETER TEST CONDITIONS UNIT
VI = 2 Vf = 1 MHz,CipF
UNITPARAMETER FROM
(INPUT) TO
(OUTPUT) TEST
CONDITIONS
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
tpd ns
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of T exas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
electrical characteristics over recommended operating free-air temperature range
TIBPAL16R8-5CFN TIBPAL16R8-5CJ
TIBPAL16R8-5CN
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.75 V, II = –18 mA –0.8 –1.5 –0.8 –1.5 V
VOH VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 2.4 2.7 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 0.3 0.5 V
IOZH VCC = 5.25 V, VO = 2.7 V 100 100 µA
IOZL VCC = 5.25 V, VO = 0.4 V –100 –100 µA
IIVCC = 5.25 V, VI = 5.5 V 100 100 µA
IIH VCC = 5.25 V, VI = 2.7 V 25 25 µA
IIL VCC = 5.25 V, VI = 0.4 V –250 –250 µA
IOS‡VCC = 5.25 V, VO = 0.5 V –30 –70 –130 –30 –70 –130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 180 180 mA
I 8.5 6.5
CLK/OE 7.5 5.5
Cof = 1 MHz, VO = 2 V 10 8 pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16R8-5CFN TIBPAL16R8-5CJ
TIBPAL16R8-5CN
MIN TYP†MAX MIN TYP†MAX
without feedback 125 125
fmax§with internal feedback (counter configuration) 125 125 MHz
with external feedback 117 111
CLK↑Qwith up to 4 outputs
switching 1.5 4 1.5 4
CLK↑Qwith more than 4
outputs switching 1.5 4 1.5 4.5
tpd¶CLK↑Internal feedback 3.5 3.5 ns
ten OE↓Q 1.5 6 1.5 6 ns
tdis OE↑Q 1 6.5 1 7 ns
tr1.5 1.5 ns
tf1.5 1.5 ns
tsk(o)#Skew between outputs 0.5 0.5 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
§See ’fmax Specification’ near the end of this data sheet.
¶This parameter is calculated from the measured fmax with internal feedback in a counter configuration (see Figure 2 for illustration).
#tsk(o) is the skew time between registered outputs.
ns
Pulse duration, clocktw†
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
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14
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current –2 mA
IOL Low-level output current 12 mA
fclock†Clock frequency 0 100 MHz
High 5
Low 5
tsu†Setup time, input or feedback before clock↑7 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature –55 25 125 °C
†fclock, tw, tsu, and th do not apply to TIBPAL16L8’
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
µAVI = 2.7 V
VO = 2.7 V
VCC = 5.5 V,
IIH
IOZH VCC = 5.5 V, µA
VI = 2 Vf = 1 MHz,CipF
VO = 0.4 V
IOZL VCC = 5.5 V, µA
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
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PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –0.8 –1.5 V
VOH VCC = 4.5 V, IOH = –2 mA 2.4 2.7 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.5 V
0, Q outputs 20
I/O ports 100
0, Q outputs –20
I/O ports –250
IIVCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
All others 25
IIL VCC = 5.5 V, VI = 0.4 V –250 µA
IOS‡VCC = 5.5 V, VO = 0.5 V –30 –70 –130 mA
ICC VCC = 5.5 V, VI = GND, OE = VIH,Outputs open 210 mA
I 8.5
CLK/OE 7.5
Cof = 1 MHz, VO = 2 V 10 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITION MIN MAX UNIT
without feedback 100
fmax§with internal feedback
(counter configuration) 100 MHz
with external feedback R1 = 390 Ω, 74
tpd I, I/O O, I/O R2 = 750 Ω, 1 7 ns
tpd CLK Q See Figure 8 1 7 ns
ten OE↓Q 1 8 ns
tdis OE↑Q 1 10 ns
ten I, I/O O, I/O 1 9 ns
tdis I, I/O O, I/O 1 10 ns
§See ’fmax Specification’ near the end of this data sheet. fmax does not apply for TIBPAL16L8’. fmax with external feedback is not production tested
and is calculated from the equation located in the fmax specifications section.
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
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16
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
asynchronous preload procedure for registered outputs (see Figure 1 and Note 3)†
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Lower Pin 11 to 5 V.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
tsu + th
tdtd
VIHH
VIL
VOH
VOL
Registered Output
Pin 11
VIH
VIL
OutputInput
5 V
Figure 1. Asynchronous Preload Waveforms †
†Not applicable for TIBPAL16L8-5C and TIBPAL16L8-7M.
NOTE 3: td = tsu = th = 100 ns to 1000 ns
VIHH = 10.25 V to 10.75 V
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
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power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu‡
tpd†
twVIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
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18
fmax SPECIFICATIONS
fmax without feedback (see Figure 3)
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (tsu + th).
However, the minimum fmax is determined by the minimum clock period (tw high + tw low).
Thus, fmax without feedback
+
1
(twhigh
)
twlow) or 1
(tsu
)
th).
CLK
Logic
Array
tsu + th
or
tw high + tw low
C1
1D
Figure 3. fmax Without Feedback
fmax with internal feedback (see Figure 4)
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, fmax with internal feedback
+
1
(tsu
)
tpd CLK
*
to
*
FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
tsu tpd CLK-to-FB
C1
1D
Figure 4. fmax With Internal Feedback
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
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fmax SPECIFICATIONS
fmax with external feedback (see Figure 5)
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(tsu
+ tpd CLK-to-Q).
Thus, fmax with external feedback
+
1
(tsu
)
tpd CLK
*
to
*
Q).
tpd CLK-to-Q tsu
CLK
Logic
Array Next Device
tsu
C1
1D
Figure 5. fmax With External Feedback
TIBPAL16R8-5C
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THERMAL INFORMATION
thermal management of the TIBPAL16R8-5C
Thermal management of the TIBPAL16R8-5CN and TIBPAL16R8-5CFN is necessary when operating at certain
conditions of frequency, output loading, and outputs switching simultaneously. The device and system
application will determine the appropriate level of management.
Determining the level of thermal management is based on factors such as power dissipation (PD), ambient
temperature (T A), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient
temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be
determined at a particular ambient temperature and device power dissipation level in order to ensure the device
specifications.
Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching
simultaneously . It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fully
loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
4020100
0
200
400
600
800
1000
(a) TIBPAL16R8-5CN
60 70
Minimum Transverse Air Flow – ft/min
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
8050
30
TA – Ambient Temperature – °C
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
PD = 0.8 W
PD = 0.6 W
4020100
0
200
400
600
800
1000
(b) TIBPAL16R8-5CFN
60 70
Minimum Transverse Air Flow – ft/min
8050
30
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
TA – Ambient Temperature – °C
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
PD = 0.8 W
PD = 0.6 W
Figure 6
TIBPAL16R8-5C
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THERMAL INFORMATION
1000
800
6001 4 10 40 100
Figure 7
1200
f – Frequency – MHz
1400
2 20 200
PD – Power Dissipation – mW
POWER DISSIPATION
vs
FREQUENCY
VCC = 5 V
TA = 25 °C
CL = 50 pF
1600
1800
8 Outputs Switching
7 Outputs Switching
6 Outputs Switching
5 Outputs Switching
4 Outputs Switching
3 Outputs Switching
2 Outputs Switching
1 Output Switching
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
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PARAMETER MEASUREMENT INFORMATION
tsu
S1
From Output
Under Test Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
1.5 V
1.5 V
th
1.5 V
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
3 V
0
3 V
0
(see Note B)
1.5 V 1.5 V
1.5 V 1.5 V
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note C)
W aveform 2
S1 Open
(see Note C)
1.5 V 1.5 V
3 V
0
(see Note B)
≈ 2.7 V
VOL
VOH
VOH – 0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
R1
3 V
3 V
0
(see Note B)
0
VOL + 0.5 V
5 V
tr
tf
tr
tf
80 %
20 %
20 %
80 %
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: For C suffix, PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%; For M suffix,
PRR ≤ 10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 8. Load Circuit and Voltage Waveforms
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
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metastable characteristics of TIBPAL16R4-5C, TIBPAL16R6-5C, and TIBPAL16R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V , the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (∆t) after system clock (SCLK). The exclusive
OR gate detects the occurrence of a failure and increments the failure counter.
C1
C1 +
1D
1D
C1
C1
1D
VIH
Comparator
VIL
Comparator
Noise
Generator DUT MTBF
Counter
1D
Data in
SCLK
SCLK + ∆t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
∆t
∆t
SCLK + ∆t
trec = ∆t – CLK to Q (max)
MTBF
+
Time (sec)
# Failures
Data in
SCLK
Figure 10. Timing Diagram
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
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24
By using the described test circuit, MTBF can be determined for several different values of ∆t (see Figure 9).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 11 shows the results for the TIBPAL16’-5C operating at 1 MHz.
0 10203040506070
MTBF – Mean Time Between Failures – s
101
102
103
104
105
106
107
108
109
∆t – Time Difference – ns
fclk = 1 MHz
fdata = 500 kHz
10 yr
1 yr
1 mo
1 day
1 wk
1 hr
1 min
10 s
Figure 11. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
The metastable equation: 1
MTBF
+
fSCLK xf
data xC1e(
*
C2 x
D
t)
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
these constants can be solved for: C1 = 4.37 X 10–3 and C2 = 2.01
Therefore
1
MTBF
+
fSCLK xf
data x4.37x10
*
3e(
*
2.01 x
D
t)
definition of variables
DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
fSCLK (system clock frequency): Actual clock frequency for the DUT.
fdata (data frequency): Actual data frequency for a specified input to the DUT.
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
MTBF failure rate. trec = ∆t – tpd (CLK to Q, max)
∆t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL16R4/R6/R8-5C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25
TYPICAL CHARACTERISTICS
0
–10
–15
–20
–0.8 –0.6 –0.4 –0.2 0 0.2
Figure 12
10
15
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
20
0.4 0.6 0.8
5
–5
VOL – Low-Level Output Voltage – V
IOL – Low-Level Output Current – mA
–40
–60
–70
0 0.5 1 1.5 2 2.5
Figure 13
–20
–10
0
3
–30
–50
IOH – High-Level Output Current – mA
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
VOH – High-Level Output Voltage – V
–80
–90
–100
160
140
120
100
–75 –50 –25 0 25 50
Figure 14
180
200
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
220
75 100 125
TA – Free-Air Temperature – °C
ICC – Supply Current – mA
VCC = 4.5 V
VCC = 4.75 V
VCC = 5 V
VCC = 5.5 V
VCC = 5.25 V
VCC = 5 V,
TA = 25 °CVCC = 5 V,
TA = 25 °C
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
26
TYPICAL CHARACTERISTICS
4
2
1
0
–75 –50 –25 0 25 50
Figure 17
Propagation Delay Time – ns
6
75 100 125
5
3
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
TA – Free-Air Temperature – °C
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPLH (CLK to Q) tPHL (CLK to Q)
4
2
1
04.5 4.75 5
Figure 16
Propagation Delay Time – ns
6
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
5.25 5.5
5
3
VCC – Supply Voltage – V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
CL – Load Capacitance – pF
8
4
2
0100 200 300 400
Figure 18
Propagation Delay Time – ns
12
14
16
500
10
6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
0 600
900
800
7001 4 10 40 100
Figure 15
1000
f – Frequency – MHz
1100
2 20 200
PD – Power Dissipation – mW
POWER DISSIPATION
vs
FREQUENCY
8-BIT COUNTER MODE
VCC = 5 V
TA = 0 °C
TA = 25 °C
TA = 80 °C
TA = 80 °C
TA = 0 °C
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27
TYPICAL CHARACTERISTICS
Number of Outputs Switching
0.4
0.2
0.1
023 4 5 6
Figure 19
0.6
0.7
0.8
78
0.5
0.3
SKEW BETWEEN OUTPUTS
vs
NUMBER OF OUTPUTS SWITCHING
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 200 Ω
CL = 50 pF
8-Bit Counter
tsk(o) – Skew Between Outputs Switching – ns
Outputs Switching in the Same Direction
Outputs Switching in the Opposite Direction
4
2
1
012345
Figure 20
Propagation Delay Time – ns
6
678
5
3
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 200 Ω
Number of Outputs Switching
= tPHL (I, I/O to O, I/O)
= tPLH (I, I/O to O, I/O)
= tPHL (CLK to Q)
= tPLH (CLK to Q)
D0892
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SRPS011D
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-85155212A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8515521RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
5962-8515521SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
TIBPAL16L8-5CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI
TIBPAL16L8-5CN OBSOLETE PDIP N 20 TBD Call TI Call TI
TIBPAL16R4-5CN OBSOLETE PDIP N 20 TBD Call TI Call TI
TIBPAL16R6-5CFN ACTIVE PLCC FN 20 46 TBD CU SNPB Level-1-220C-UNLIM
TIBPAL16R6-5CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL16R8-5CFN ACTIVE PLCC FN 20 46 TBD CU SNPB Level-1-220C-UNLIM
TIBPAL16R8-5CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL16R8-7MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL16R8-7MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16R8-7MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Jan-2010
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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