+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 1 of 7
http://www.imicorp.com
Product Features
• Zero delay 9-output buffer with internal loop filter
• High frequency operation (150 MHz)
• Low jitter <+/- 100 pS
• Low skew <200 pS
• Extended Temperature Range 0°C to 85°C
• Spread Spectrum compatible
• Integrated series damping resistors specifically
designed for registered SDRAM applications
• Externally controllable output delay
• 45-55% output dut y cycle
• OE pins for separate output enable control
• 24 Pin TSSOP package
Block Diagram
Product Description
The Z9509 is a 3.3V zero delay buffer designed to
distribute high speed clocks in PC, workstation,
datatcom, telecom and other high performance
applications. It is ideal for use in SDRAM memory
applications.
The Z9509 has two banks of outputs with
independent output enable controls. Input to output
skew can be adjusted by varying load/delay on
feedback path.
Function Table
INPUT PINS OUTPUT PINS
OEA OEB CLKA
(0:3) CLKB
(0:4) FBOUT
LOW LOW LOW LOW REF
LOW HIGH LOW REF REF
HIGH LOW REF LOW REF
HIGH HIGH REF REF REF
Note: See test mode description for additional logic
configurations. REF is fixed frequency input.
Pin Configuration
1
MUX
0
SEL
FBIN
REF
VDDA
CLKB4
CLKB3
CLKB2
CLKB1
CLKB0
OEB
CLKA3
CLKA2
OEA
CLKA1
CLKA0
FBOUT
V
SSA
V
DD
CLKB0
CLKB1
CLKB2
V
SS
V
SS
CLKB3
CLKB4
V
DD
OEB
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF
V
DDA
V
DD
CLKA0
CLKA1
V
SS
V
SS
CLKA2
CLKA3
V
DD
OEA
FBIN
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 2 of 7
http://www.imicorp.com
Pin Description
Pin No. Pin Name I/O Description
24 REF I Input reference pin.
12 FBOUT O Output feedback pin, no OE controls.
13 FBIN I This pin is to be connected to the FBOUT pin. A timing delay may be inserted to
change the device’s actual skew.
14 OEA I Output Enable for Bank A clocks (high active). See diagram on page 1.
11 OEB I Output Enable for Bank B clocks (high active). See diagram on page 1.
22, 10,
15, 22 VDD PWR 3.3V supply for core logic, inputs, and outputs.
23 VDDA PWR Power for internal analog circuitry. This supply should have separate decoupling.
For test purposes, when VDDA’s are strapped to ground the internal PLL is
bypassed and REF is buffered directly to device outputs (see Test Mode Table).
21, 20,
17, 16 CLKA
(0:3) O Low skew clock outputs (Bank A). Outputs enabled by OEA in high state.
3, 4, 5,
8, 9 CLKB
(0:4) O Low skew clock outputs (Bank B). Outputs enabled by OEB in high state.
6, 7, 18,
19 VSS PWR Ground pins for the core logic and I/Os.
1V
SSA PWR Ground pin for analog circuitry.
Absolute Maximum Ratings(1)
Symbol Rating Commercial Unit
VDD, VDDA Supply Voltage Range -0.5 to +4.6 V
VI(2) Input Voltage Range -0.5 to +6.5 V
VO(2) Voltage range applied to any output in the high or low state -0.5 to VDD + 0.5 V
IIK (VI<0) Input clamp current -50 mA
IOK (VO<0 or VO>VDD) Terminal Voltage with respect to VSS (inputs VIH2.5, VIL2.5) +/- 50 mA
IO (VO = 0 to VDD) Continuous Output Current +/- 50 mA
VDD or VSS Continuous Current +/- 100 mA
TA = 50°C (in still air)3Maximum power dissipation 0.7 W
TSTG Storage Temperature Range -65°C to + 150°C°C
Notes:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are
stress rating only and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum pack age power dissipation is calculated using a junction temperature of 150°C and a board trace length of
750 mils.
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 3 of 7
http://www.imicorp.com
Capacitance(1)
Parameter Description Min Typ Max Unit
CIN Input Capacitance Vj = VDD or VSS 5pF
C
OOutput Capacita nce VO = VDD or VSS 6pF
C
LLoad Capacitance 30 pF
Note: Unused inputs must be held high or low to prevent them from floating.
Test Mode Table (VDDA = 0 V)
Inputs Outputs
OEA OEB REF CLKA(0:3) CLKB(0:4) FBOUT
LOW LOW LOW LOW LOW LOW
LOW HIGH HIGH LOW HIGH HIGH
LOW LOW HIGH LOW LOW HIGH
HIGH LOW HIGH HIGH LOW HIGH
HIGH HIGH HIGH HIGH HIGH HIGH
DC Parameters (Tamb = 0° to + 85° C) (VDD = VDDA = 3.0 V to 3.6 V)
Symbol Parameter Test Conditions Min Typ(1) Max. Unit
VIH HIGH level input voltage 2.0 - - V
VIL LOW level input voltage - 0.8 V
Min to Max IOH = -100
AV
DD – 0.2 - -
VDD = 3 V IOH = - 12 mA 2.1 - -
VOH
HIGH level output voltage
VDD = 3 V IOH = - 6 mA 2.4 - - V
Min to Max IOL = 100
A--0.2
V
DD = 3 V IOL = 12 mA - - 0.8
VOL
LOW level output voltage
VDD = 3 V IOL = 6 mA - - 0.55 V
VDD = 3.135 V VO = 1 V -32 - -
VDD = 3.3 V VO = 1.65 V - -36 -
IOH HIGH level output current
VDD = 3.465 V VO = 3.135 V - - -12
mA
VDD = 3.135 V VO = 1.95 V 34 - -
VDD = 3.3 V VO = 1.65 V - 40 -
IOL LOW level output current
VDD = 3.465 V VO = 0.4 V - - 14
mA
VIK Clamp Voltage VDD = 3 V IIN = -18 mA - - -1.2 V
IIInput leakage current per pin VDD = 3.6V VI =VDD or VSS -± 5
A
I
DD Supply Current VDD = 3.6V Io = 0
VIN = VDD or VSS
-10
A
I
DD Additional quiescent supply
current VDD = 3.6V Io = 0
input at VDD - .6V - 500
A
Notes:
1. All typical values are measured at Tamb = 25 ° C
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 4 of 7
http://www.imicorp.com
AC Electrical Characteristics(3)(6) (Tamb = 0° to + 85° C)
VDD = 3.3V +/- 0.165V VDD = 3.3V +/- 0.3 V
Parameters From (Input)/Condition To (Output) Min Typ Max Min Typ Max Unit
Fout Operating Frequency
(output) 25 150 25 150 MHz
tPHASE e rror(5) REF = 66 to 100 MHz FBIN -50 50 -50 50 pS
Duty cycle 45 55 45 55 %
tSK(o)(1) Any clock out (100 MHz) Any clock out 200 pS
Jitter (cycle-to-
cycle) Ref = 100 MHz Any clock out
or FBOUT |100| |100| pS
tR(6)(7) Any clock out
or FBOUT 1.3 1.9 0.8 2.1 nS
tF(6)(7) Any clock out
or FBOUT 1.7 2.5 1.2 2.7 nS
Tstabil Stabilization Time(4) 1mS
Notes:
1. The tSK(0)
specification is only valid for equal loading of all outputs (30 pF//500Ω).
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time as elapsed.
3. Ref Duty Cycle must be 50% +/- 5%.
4. Time required for the integrated PLL circuit to obtain phase lock of its feed back signal to its reference signal. For phase
lock to be obtained, a fixed-frequency, fixed-phase reference signal must be pres ent at CLK. Until phase lock is obtained,
the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not
applicable.
5. Uses the averaging feature of the scope to remove the jitter component.
6. The test load is 30pF//500Ω.
7. TR/TF
are measured at 0.4V to 2.0V.
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 5 of 7
http://www.imicorp.com
Parameter Me asurement Information
Notes:
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: Input Frequency < 100 MHz, ZO = 50 Ω, tr
<1.2 ns, tf<1.2ns.
C. The outputs are measured one at a time with one transition per measurem ent.
Figure 1. Load Circuit and Voltage Waveforms
Figure 2. Phase Err or and Sk e w Calcu lat ions
From Output
Under Test
30 pF 500 Ohm
Input
Output
50% VDD 3 V
0 V
VOH
VOL
tpd 2 V
0.4 V 50% VDD 2 V 0.4 V
tr tf
Load Circuit for Outputs Volta
g
e Waveforms Propa
g
ation Delay Times
CLKIN
FBIN
FBOUT
Any Y
Any Y
Any Y
t
phase error
t
sk(o)
t
sk(o)
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 6 of 7
http://www.imicorp.com
Package Drawing and Dimensions
BO
SURFACES ROUGHNESS: 6+ 27n(RZ)
D
-B-
385
E1
L20
R0.1
B
e
-C- C
0.07
RD
4
[10° TYP
R1.30
1.0
0.10~0.15 0.00 ~ 0.05
SECTION V-V
A1
0.25
A2 R
L1
L
A
8°
b
cc1
b1
DETAIL B
.08 CB A
DETAIL A
24 Pin TSSOP Dimensions
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A - - 0.0279 - - 1.10
A1 0.0013 - 0.0038 0.05 - 0.15
A2 0.0216 0.0228 0.0267 0.85 0.90 1.05
L 0.0127 0.0152 0.0178 0.50 0.60 0.70
b 0.0048 - 0.0076 0.19 - 0.30
b1 0.0048 0.0056 0.0064 0.19 0.22 0.25
c 0.0023 - 0.0051 0.09 - 0.20
c1 0.0023 0.0032 0.0041 0.09 0.127 0.16
θ0°-8°0°-8°
e 0.026 BSC 0.65 BSC
D 0.19812 BSC 7.80 BSC
E 0.16256 6.40 BSC
E1 0.168 0.173 0.178 4.3 4.4 4.5
0.05 MAX.
0.05 MAX.
1.0
1.0
E
R0.15
A
14° TYP
+/+
…when timing is critical
Z9509
Nine Output Zero Delay Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev. 1.0 11/1/1999
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571 Page 7 of 7
http://www.imicorp.com
Ordering Information
Part Number Package Type Production Flow
Z9509ATB 24 Pin TSSOP 0°C to +85°C
Note: The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
Z9509ATB
Date Code, Lot #
Z9509ATB Flow
B = 0°C to + 85°C
Package
T = TSSOP
Revision
IMI Device Number
