1
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
Typical applicaTion
FeaTures
applicaTions
DescripTion
14-Bit, 125/105/80Msps
Ultralow Power 1.8V ADCs
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
n 73.4dB SNR
n 85dB SFDR
n Low Power: 127mW/106mW/89mW
n Single 1.8V Supply
n CMOS, DDR CMOS or DDR LVDS Outputs
n Selectable Input Ranges: 1V
P-P
to 2V
P-P
n 800MHz Full-Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
The LTC
®
2261-14/LTC2260-14/LTC2259-14 are sam-
pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 73.4dB SNR and 85dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17psRMS
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal) and no missing codes over temperature. The transition
noise is a low 1.2LSBRMS.
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
2-Tone FFT, fIN = 70MHz and 75MHz
–
+
INPUT
S/H
CORRECTION
LOGIC OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
D13
•
•
•
D0
125MHz
CLOCK
ANALOG
INPUT
226114 TA01a
CMOS
OR
LVDS
1.2V
TO 1.8V
1.8V
VDD
OVDD
OGND
GND FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
226114 TA01b
L, LT, LTC , LT M , Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2261-14
LTC2260-14/LTC2259-14
2
226114fc
For more information www.linear.com/LTC2261-14
absoluTe MaxiMuM raTings
Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................. –0.3V to 3.9V
(Notes 1, 2)
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
AIN+
AIN–
GND
REFH
REFH
REFL
REFL
PAR/SER
VDD
VDD
D9
D8
CLKOUT+
CLKOUT–
OVDD
OGND
D7
D6
D5
D4
VDD
SENSE
VREF
VCM
OF
DNC
D13
D12
D11
D10
ENC+
ENC–
CS
SCK
SDI
SDO
D0
D1
D2
D3
21
30
10
1
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
AIN+
AIN–
GND
REFH
REFH
REFL
REFL
PAR/SER
VDD
VDD
D8_9
DNC
CLKOUT+
CLKOUT–
OVDD
OGND
D6_7
DNC
D4_5
DNC
VDD
SENSE
VREF
VCM
OF
DNC
D12_13
DNC
D10_11
DNC
ENC+
ENC–
CS
SCK
SDI
SDO
DNC
D0_1
DNC
D2_3
21
30
10
1
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
3940 38 37 36 35 34 33 32 31
11 20
12 13 14 15
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16 17 18 19
22
23
24
25
26
27
28
29
9
8
7
6
5
4
3
2
AIN+
AIN–
GND
REFH
REFH
REFL
REFL
PAR/SER
VDD
VDD
D8_9+
D8_9–
CLKOUT+
CLKOUT–
OVDD
OGND
D6_7+
D6_7–
D4_5+
D4_5–
VDD
SENSE
VREF
VCM
OF+
OF–
D12_13+
D12_13–
D10_11+
D10_11–
ENC+
ENC–
CS
SCK
SDI
SDO
D0_1–
D0_1+
D2_3–
D2_3+
21
30
10
1
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
pin conFiguraTions
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range:
LTC2261C, LTC2260C, LTC2259C ............ 0°C to 70°C
LTC2261I, LTC2260I, LTC2259I ...........–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
3
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
converTer characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTC2261-14 LTC2260-14 LTC2259-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l14 14 14 Bits
Integral Linearity Error Differential Analog Input (Note 6) l–3.75 ±1 3.75 –3.75 ±1 3.75 –3.5 ±1 3.5 LSB
Differential Linearity Error Differential Analog Input l–0.9 ±0.3 0.9 –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 LSB
Offset Error (Note 7) l–9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV
Gain Error Internal Reference
External Reference
l
–1.5
±1.5
±0.4
1.5
–1.5
±1.5
±0.4
1.5
–1.5
±1.5
±0.4
1.5
%FS
%FS
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise External Reference 1.2 1.2 1.2 LSBRMS
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2261CUJ-14#PBF LTC2261CUJ-14#TRPBF LTC2261UJ-14 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2261IUJ-14#PBF LTC2261IUJ-14#TRPBF LTC2261UJ-14 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2260CUJ-14#PBF LTC2260CUJ-14#TRPBF LTC2260UJ-14 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2260IUJ-14#PBF LTC2260IUJ-14#TRPBF LTC2260UJ-14 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2259CUJ-14#PBF LTC2259CUJ-14#TRPBF LTC2259UJ-14 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2259IUJ-14#PBF LTC2259IUJ-14#TRPBF LTC2259UJ-14 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2261-14
LTC2260-14/LTC2259-14
4
226114fc
For more information www.linear.com/LTC2261-14
analog inpuT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) lVCM – 100mV VCM VCM + 100mV V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V
IINCM Analog Input Common Mode Current Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
µA
µA
µA
IIN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l–1 1 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA
IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.17 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz
DynaMic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2261-14 LTC2260-14 LTC2259-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input
70MHz Input
140MHz Input
l
71.3
73.4
73.2
72.7
71.3
73.4
73.2
72.7
70.9
73.1
72.9
72.4
dB
dB
dB
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
70MHz Input
140MHz Input
l
76
88
85
82
76
88
85
82
79
88
85
82
dB
dB
dB
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
70MHz Input
140MHz Input
l
85
90
90
90
83
90
90
90
85
90
90
90
dB
dB
dB
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l
70.2
73
72.6
72
70.2
73
72.6
72
70.4
72.9
72.6
72
dB
dB
dB
inTernal reFerence characTerisTics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V
VCM Output Temperature Drift ±25 ppm/°C
VCM Output Resistance –600µA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±25 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
5
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
DigiTal inpuTs anD ouTpuTs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID Differential Input Voltage (Note 8) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)
l
1.1
1.2
1.6
V
V
VIN Input Voltage Range ENC+, ENC– to GND l0.2 3.6 V
RIN Input Resistance (See Figure 10) 10 kΩ
CIN Input Capacitance (Note 8) 3.5 pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD = 1.8V l1.2 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
VIN Input Voltage Range ENC+ to GND l0 3.6 V
RIN Input Resistance (See Figure 11) 30 kΩ
CIN Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 3.6V l–10 10 µA
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance (Note 8) 4 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL D ATA RATE AND DOUBLE-DATA RATE)
OVDD = 1.8V
VOH High Level Output Voltage IO = –500µA l1.750 1.790 V
VOL Low Level Output Voltage IO = 500µA l0.010 0.050 V
OVDD = 1.5V
VOH High Level Output Voltage IO = –500µA 1.488 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
OVDD = 1.2V
VOH High Level Output Voltage IO = –500µA 1.185 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l247 350
175
454 mV
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l1.125 1.250
1.250
1.375 V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
LTC2261-14
LTC2260-14/LTC2259-14
6
226114fc
For more information www.linear.com/LTC2261-14
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2261-14 LTC2260-14 LTC2259-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double-Data Rate
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.1 1.9 1.1 1.9 1.1 1.9 V
IVDD Analog Supply Current DC Input
Sine Wave Input
l70.5
71.8
83.2 58.6
59.8
69.1 49.2
50.2
58.1 mA
mA
IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 3.9 3.3 2.5 mA
PDISS Power Dissipation DC Input
Sine Wave Input, OVDD=1.2V
l127
134
150 106
112
125 89
93
105 mW
mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.7 1.9 1.7 1.9 1.7 1.9 V
IVDD Analog Supply Current Sine Wave Input l75.4 89 63.4 74.8 53.8 63.5 mA
IOVDD Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
20.7
40.5
26
47.8
20.7
40.5
26
47.8
20.7
40.5
26
47.8
mA
mA
PDISS Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
173
209
207
246
151
187
182
221
134
170
161
201
mW
mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 0.5 0.5 mW
PNAP Nap Mode Power 9 9 9 mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10 10 10 mW
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2261-14 LTC2260-14 LTC2259-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 10) l1 125 1 105 1 80 MHz
tLENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
tHENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
tAP Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.7 3.1 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.4 2.6 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double-Data Rate Mode
5.0
5.5
Cycles
Cycles
7
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (LVDS Mode)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.8 3.2 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.5 2.7 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency 5.5 Cycles
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
tSCS to SCK Setup Time l5 ns
tHSCK to CS Setup Time l5 ns
tDS SDI Setup Time l5 ns
tDH SDI Hold Time l5 ns
tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l125 ns
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V
DD
= OV
DD
= 1.8V, f
SAMPLE
= 125MHz (LTC2261),
105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal
termination disabled, differential ENC+/ENC– = 2V
P-P
sine wave, input
range = 2V
P-P
with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: V
DD
= 1.8V, f
SAMPLE
= 125MHz (LTC2261), 105MHz (LTC2260),
or 80MHz (LTC2259), ENC+ = single-ended 1.8V square wave, ENC– = 0V,
input range = 2V
P-P
with differential drive, 5pF load on each digital output
unless otherwise noted.
Note 10: Recommended operating conditions.
TiMing DiagraMs
Full-Rate CMOS Output Mode Timing
All Outputs Are Single Ended and Have CMOS Levels
tH
tD
tC
tL
N – 5 N – 4 N – 3 N – 2 N – 1
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
CLKOUT+
CLKOUT–
D0-D13, OF
226114 TD01
LTC2261-14
LTC2260-14/LTC2259-14
8
226114fc
For more information www.linear.com/LTC2261-14
TiMing DiagraMs
Double-Data Rate CMOS Output Mode Timing
All Outputs Are Single Ended and Have CMOS Levels
tH
tD
•
•
•
tD
tCtC
tL
OFN-5 OFN-4 OFN-3 OFN-2
D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2
D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
D0_1
D12_13
CLKOUT+
CLKOUT–
OF
226114 TD02
Double-Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tH
tDtD
tCtC
tL
OFN-5 OFN-4 OFN-3 OFN-3
D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2
D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
D0_1+
D0_1–
D12_13+
D12_13–
CLKOUT+
CLKOUT–
OF+
OF–
226114 TD03
•
•
•
9
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
TiMing DiagraMs
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
226114 TD04
CS
SCK
SDI R/W
SDO HIGH IMPEDANCE
Typical perForMance characTerisTics
LTC2261-14: Integral
Non-Linearity (INL)
LTC2261-14: Differential
Non-Linearity (DNL)
LTC2261-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
OUTPUT CODE
0
–2.0
–0.5
–1.0
–1.5
INL ERROR (LSB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
226114 G01
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
226114 G02
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
226114 G03
010 20 30 40 50 60
LTC2261-14
LTC2260-14/LTC2259-14
10
226114fc
For more information www.linear.com/LTC2261-14
Typical perForMance characTerisTics
LTC2261-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
LTC2261-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 125Msps
LTC2261-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
LTC2261-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
LTC2261-14: Shorted Input
Histogram
LTC2261-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTC2261-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
226114 G04
10 20 30 40 50 60
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
226114 G05
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
226114 G06
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
226114 G07
OUTPUT CODE
8178
1000
0
3000
2000
COUNT
4000
5000
6000
8180 8182 8184 8186
226114 G08
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
226114 G12
dBFS
dBc
SAMPLE RATE (Msps)
0
75
60
65
70
55
50
80
IVDD (mA)
25 50 75 100 125
226114 G13
LVDS OUTPUTS
CMOS OUTPUTS
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
74
73
SNR (dBFS)
50 100 150 200 250 300 350
226114 G09
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
226114 G10
LTC2261-14: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTC2261-14: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps
11
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
LTC2261-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2261-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTC2260-14: Integral Non-Linearity
(INL)
LTC2260-14: Differential
Non-Linearity (DNL)
LTC2260-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
LTC2260-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
Typical perForMance characTerisTics
SAMPLE RATE (Msps)
0
25
10
15
20
5
0
45
30
35
40
I
OVDD
(mA)
25 50 75 100 125
226114 G14
1.75mA LVDS
1.8V CMOS
1.2V CMOS
3.5mA LVDS
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
73
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
226114 G15
OUTPUT CODE
0
–2.0
–0.5
–1.0
–1.5
INL ERROR (LSB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
226114 G21
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
226114 G22
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
226114 G23
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
226114 G24
FREQUENCY (MHz)
0
–80
–90
–100
–110
–120
–130
–50
–60
–70
AMPLITUDE (dBFS)
–40
–30
–20
–10
0
10 20 30 40 50 60
226114 G16
FREQUENCY (MHz)
0
–130
–80
–90
–100
–110
–120
–50
–60
–70
AMPLITUDE (dBFS)
–40
–30
–20
–10
0
10 20 30 40 50 60
226114 G17
SAMPLE RATE (Msps)
CMOS
LVDS
0
66
72
70
68
SNR (dBFS)
74
25 50 75 125100
226114 G18
DDR CMOS
LTC2261-14: 128k Point Averaged FFT,
fIN = 70MHz, –65dBFS, 125Msps,
RAND OFF, ABP OFF
LTC2261-14: SNR vs Sample Rate
and Digital Output Mode, 30MHz Sine
Wave Input, –1dB
LTC2261-14: 128k Point Averaged FFT,
fIN = 70MHz, –65dBFS, 125Msps,
RAND ON, ABP ON
LTC2261-14
LTC2260-14/LTC2259-14
12
226114fc
For more information www.linear.com/LTC2261-14
LTC2260-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2260-14: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2260-14: Shorted Input
Histogram
LTC2260-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
Typical perForMance characTerisTics
OUTPUT CODE
8195
1000
0
3000
2000
COUNT
4000
5000
6000
8197 8199 8201 8203
226114 G28
SAMPLE RATE (Msps)
0
60
45
50
55
40
65
IVDD (mA)
25 50 75 100
226114 G33
LVDS OUTPUTS
CMOS OUTPUTS
SAMPLE RATE (Msps)
25
10
15
20
5
0
45
30
35
40
I
OVDD
(mA)
226114 G34
1.75mA LVDS
1.8V CMOS
1.2V CMOS
3.5mA LVDS
0 25 50 75 100
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
226114 G32
dBFS
dBc
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
74
73
SNR (dBFS)
50 100 150 200 250 300 350
226114 G29
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
226114 G30
LTC2260-14: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2260-14: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2260-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
LTC2260-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
226114 G25
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
226114 G26
LTC2260-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
226114 G27
13
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
LTC2260-14: SNR vs SENSE,
fIN = 5MHz, –1dB
Typical perForMance characTerisTics
LTC2259-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTC2259-14: Shorted Input
Histogram
LTC2259-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
LTC2259-14: 8k Point FFT, fIN = 70MHz
–1dBFS, 80Msps
LTC2259-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
LTC2259-14: Integral Non-Linearity
(INL)
LTC2259-14: Differential
Non-Linearity (DNL)
LTC2259-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
73
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
226114 G35
OUTPUT CODE
0
–2.0
–0.5
–1.0
–1.5
INL ERROR (LSB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
226114 G41
OUTPUT CODE
0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
226114 G42
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
226114 G43
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
226114 G44
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
226114 G45
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
226114 G46
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
226114 G47
OUTPUT CODE
8184
1000
0
3000
2000
COUNT
4000
5000
6000
8186 8188 8190 8192
226114 G48
LTC2261-14
LTC2260-14/LTC2259-14
14
226114fc
For more information www.linear.com/LTC2261-14
Typical perForMance characTerisTics
LTC2259-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2259-14: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
LTC2259-14: SNR vs SENSE,
fIN = 5MHz, –1dB
SAMPLE RATE (Msps)
0
25
10
15
20
5
0
45
30
35
40
IOVDD (mA)
20 40 60 80
226114 G54
1.75mA LVDS
1.8V CMOS
1.2V CMOS
3.5mA LVDS
SAMPLE RATE (Msps)
0
50
35
40
45
55
I
VDD
(mA)
20 40 60 80
226114 G53
LVDS OUTPUTS
CMOS OUTPUTS
SENSE PIN (V)
0.6
71
68
69
70
67
66
72
73
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
226114 G55
LTC2259-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
10
0
80
70
SFDR (dBc AND dBFS)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
226114 G52
dBFS
dBc
INPUT FREQUENCY (MHz)
0
72
71
70
69
68
67
66
74
73
SNR (dBFS)
50 100 150 200 250 300 350
226114 G49
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR (dBFS)
50 100 150 200 250 300 350
226114 G50
LTC2259-14: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2259-14: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
15
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
pin FuncTions
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1µF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double-
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = VDD), SDO is not used
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OVDD (Pin 26): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
VCM (Pin 37): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
VREF (Pin 38): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
LTC2261-14
LTC2260-14/LTC2259-14
16
226114fc
For more information www.linear.com/LTC2261-14
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double-
Data Rate Digital Outputs. Tw o data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8, D10,
D12) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double-Data Rate
Digital Outputs. Tw o data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output.
OF+ is high when an overflow or underflow has occurred.
17
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
FuncTional block DiagraM
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2µF
0.1µF 0.1µF
0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
REFH REFL
ENC–
SHIFT REGISTER
AND CORRECTION
SDOCS
OGND
OF
OVDD
D13
CLKOUT
–
CLKOUT
+
D0
226114 F01
INPUT
S/H
SENSE
VREF
AIN–
AIN+
1µF
VCM
0.1µF
VDD/2
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCKPAR/SER SDI
•
•
•
VDD
GND
LTC2261-14
LTC2260-14/LTC2259-14
18
226114fc
For more information www.linear.com/LTC2261-14
CONVERTER OPERATION
The LTC2261-14/LTC2260-14/LTC2259-14 are low power
14-bit 125Msps/105Msps/80Msps A/D converters that are
powered by a single 1.8V supply. The analog inputs should
be driven differentially. The encode input can be driven
differentially, or single ended for lower power consump-
tion. The digital outputs can be CMOS, double-data rate
CMOS (to halve the number of output lines), or double-data
rate LVDS (to reduce digital noise in the system.) Many
additional features can be chosen by programming the
mode control registers through a serial SPI port. See the
Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range,
the inputs should swing from VCM – 0.5V to VCM + 0.5V.
There should be 180° phase difference between the inputs.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer-Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
CSAMPLE
3.5pF
RON
25Ω
RON
25Ω
VDD
VDD
LTC2261-14
AIN+
226114 F02
CSAMPLE
3.5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10Ω
10Ω
25Ω
25Ω 25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
12pF
0.1µF
VCM
LTC2261-14
ANALOG
INPUT
0.1µF T1
1:1
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226114 F03
Figure 2. Equivalent Input Circuit
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
applicaTions inForMaTion
19
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 170MHz to 270MHz
Figure 6. Recommended Front-End Circuit for
Input Frequencies Above 270MHz
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 70MHz to 170MHz
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driv-
ing the A/D.
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
4.7pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
226114 F04
LTC2261-14
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
1.8pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
226114 F05
LTC2261-14
25Ω
25Ω
50Ω
0.1µF
2.7nH
2.7nH
AIN+
AIN–
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226114 F06
LTC2261-14
LTC2261-14
LTC2260-14/LTC2259-14
20
226114fc
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
25Ω
25Ω
200Ω
200Ω
0.1µF AIN+
AIN–
12pF
0.1µF
VCM
LTC2261-14
226114 F07
––
++
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
Figure 7. Front-End Circuit Using a High
Speed Differential Amplifier
Reference
The LTC2261-14/LTC2260-14/LTC2259-14 have an inter-
nal 1.25V voltage reference. For a 2V input range using
the internal reference, connect SENSE to VDD. For a 1V
input range using the internal reference, connect SENSE
to ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9.)
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
VREF
REFH
SENSE
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.65V < VSENSE < 1.300V
1.25V
REFL
0.1µF2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
226114 F08
LTC2261-14
5Ω
0.8x
DIFF AMP
INTERNAL ADC
LOW REFERENCE
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
1µF
0.1µF
0.1µF
Figure 8. Reference Circuit
SENSE
1.25V
EXTERNAL
REFERENCE
1µF
1µF
VREF
226114 F09
LTC2261-14
Figure 9. Using an External 1.25V Reference
The VREF
, REFH and REFL pins should be bypassed as
shown in Figure 8. The 0.1µF capacitor between REFH
and REFL should be as close to the pins as possible (not
on the back side of the circuit board).
21
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinu-
soidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For good
jitter performance ENC+ and ENC– should have fast rise
and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
VDD
LTC2261-14
226114 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
30k
ENC+
ENC–
226114 F11
0V
1.8V TO 3.3V
LTC2261-14
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
100Ω
100Ω
25Ω
D1
ENC+
ENC–
0.1µF
0.1µF
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
226114 F12
LTC2261-14
T1
1:4
Figure 12. Sinusoidal Encode Drive
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1µF
0.1µF
226114 F13
LTC2261-14
Figure 13. PECL or LVDS Encode Drive
LTC2261-14
LTC2260-14/LTC2259-14
22
226114fc
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50%(±5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2261-14/LTC2260-14/LTC2259-14 can operate
in three digital output modes: full-rate CMOS, double-
data rate CMOS (to halve the number of output lines),
or double-data rate LVDS (to reduce digital noise in the
system). The output mode is set by mode control regis-
ter A3 (serial programming mode), or by SCK (parallel
programming mode). Note that double-data rate CMOS
cannot be selected in the parallel programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 14 digital outputs (D0-D13),
overflow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate CMOS Mode
In double-data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 7 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13), overflow (OF), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
When using double-data rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100MHz.
Double-Data Rate LVDS Mode
In double-data rate LVDS mode, two data bits are
multiplexed and output on each differential output pair.
There are 7 LVDS output pairs (D0_1+/D0_1– through
D12_13+/D12_13–) for the digital output data. Overflow
(OF+/OF–) and the data output clock (CLKOUT+/CLKOUT–)
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
23
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2261-14/LTC2260-14/LTC2259-14 can also phase
shift the CLKOUT+/CLKOUT– signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase shifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
applicaTions inForMaTion
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
226114 F14
ENC+
Figure 14. Phase Shifting CLKOUT
LTC2261-14
LTC2260-14/LTC2259-14
24
226114fc
For more information www.linear.com/LTC2261-14
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied—an
exclusive-OR operation is applied between the LSB and
all other bits. The LSB, OF and CLKOUT outputs are not
affected. The output randomizer is enabled by serially
programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
that is centered around mid-scale, the digital outputs toggle
between mostly 1s and mostly 0s. This simultaneous
switching of most of the bits will cause large currents in the
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. To first order, this cancels
current flow in the ground plane, reducing the digital noise.
applicaTions inForMaTion
CLKOUT CLKOUT
OF
D13/D0
D12/D0
•
•
•
D2/D0
D1/D0
D0
116114 F15
OF
D13
D12
D2
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
•
•
•
D2
D1
D0
116114 F16
D0
D1/D0
D2/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2261-14
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital
Output Signal
25
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alter-
nate bit polarity mode is independent of the digital output
randomizer—either, both or neither function can be on
at the same time. When alternate bit polarity mode is on,
the data format is offset binary and the 2’s complement
control bit has no effect. The alternate bit polarity mode is
enabled by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF
,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the applica-
tion demands very accurate DC settling then an additional
50µs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2261-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double-Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
applicaTions inForMaTion
LTC2261-14
LTC2260-14/LTC2259-14
26
226114fc
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serial interface that program the A/D mode control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serial data is only written and read back is not needed, then
SDO can be left floating and no pull-up resistor is needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bit 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero at the End of the SPI Write
Command.
The Reset Register Is Write Only.
Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X PWROFF1 PWROFF0
Bits 7-2 Unused, Don’t Care Bits.
Bits 1-0 PWROFF1:PWROFF0 Power Down Control Bits
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
27
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, Don’t Care Bits.
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0
Bit 7 Unused, Don’t Care Bit.
Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
Bit 2 OUTOFF Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double-Data Rate LVDS Output Mode
10 = Double-Data Rate CMOS Output Mode
11 = Not Used
applicaTions inForMaTion
LTC2261-14
LTC2260-14/LTC2259-14
28
226114fc
For more information www.linear.com/LTC2261-14
applicaTions inForMaTion
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP
Bit 7-6 Unused, Don’t Care Bits.
Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 101 0101 0101 0101 and 010 1010 1010 1010
111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 000 0000 0000 0000 and 111 1111 1111 1111
Note: Other Bit Combinations are not Used
Bit 2 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0 TWOSCOMP Tw o ’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Tw o ’s Complement Data Format
Note: ABP = 1 Forces the Output Format to be Offset Binary
GROUNDING AND BYPASSING
The LTC2261-14 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The VCM capacitor should be located as close to the pin
as possible. To make space for this the capacitor on VREF
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2261-14 is trans-
ferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board.
29
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
Typical applicaTions
AIN+
AIN–
GND
REFH
REFH
REFL
REFL
PAR/SER
VDD
VDD
D9
D8
CLKOUT+
CLKOUT–
OVDD
OGND
D7
D6
D5
D4
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
R13
100Ω
ENCODE CLOCK
SPI BUS
226114 TA02
C20
2.2µF
C15
0.1µF
PAR/SER
R27 10Ω
R16
100Ω
R28 10Ω
C21
0.1µF
GND ENC+ENC–CS SCK SDI SDO D0 D1 D2 D3
20191817161514131211
31323334353637383940
41
VDD SENSE VREF VCM OF+OF–D13 D12 D11 D10
0V
DD
C37
0.1µF
LTC2261CUJ
C23
1µF
SENSE
C17
1µF
C13
1µF
C51
4.7pF
R14
1k
R39
33.2Ω
1%
R40
33.2Ω
1%
C12
0.1µF
R15 100Ω
R10 10Ω
R9 10Ω
ANALOG INPUT
T2
MABAES0060
• •
C19
0.1µF
C18
0.1µF
DIGITAL
OUTPUTS
DIGITAL
OUTPUTS
VDD
VDD
LTC2261 Schematic
LTC2261-14
LTC2260-14/LTC2259-14
32
226114fc
For more information www.linear.com/LTC2261-14
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
6.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
0.40 ±0.10
4039
1
2
BOTTOM VIEW—EXPOSED PAD
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
4.42 ±0.05
4.42 ±0.05
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UJ40) QFN REV Ø 0406
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
4.50 ±0.05
(4 SIDES)
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
R = 0.10
TYP
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
33
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 08/12 Corrected IOVDD to IOVDD.
Corrected RESET REGISTER A0, D7 description.
Attached VDD to pins 9,10 and 40 on schematic.
14
26
29
C 01/14 Corrected “external reference” to “internal reference” for 1V input range. 20
(Revision history begins at Rev B)
LTC2261-14
LTC2260-14/LTC2259-14
34
226114fc
LINEAR TECHNOLOGY CORPORATION 2008
LT 0114 REV C • PRINTED IN USA
For more information www.linear.com/LTC2261-14
relaTeD parTs
PART NUMBER DESCRIPTION COMMENTS
LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LT1994 Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2215 16-Bit, 65Msps, Low Noise ADC 700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN
LTC2216 16-Bit, 80Msps, Low Noise ADC 970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN
LTC2217 16-Bit, 105Msps, Low Noise ADC 1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205 16-Bit, 65Msps, 3.3V ADC 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2209 16-Bit, 160Msps, 3.3V ADC, LVDS Outputs 1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249 14-Bit, 80Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2259-12/
LTC2260-12/
LTC2261-12
12-Bit, 80/105/125Msps 1.8V ADCs, Ultralow
Power
87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/
CMOS Outputs, 6mm × 6mm QFN Package
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299 Dual 14-Bit, 80Msps ADC 230mW, 71.6dB SNR, 5mm × 5mm QFN Package
LT5517 40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5527 400MHz to 3.7GHz High Linearity Downconverting
Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
LT5557 400MHz to 3.8GHz High Linearity Downconverting
Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB,
3.3V Supply Operation, Integrated Transformer
LT5575 800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
Integrated RF and LO Transformer
LTC6400-20 1.8GHz Low Noise, Low Distortion Differential ADC
Driver for 300MHz IF Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
LT6604-2.5/
LT6604 -5/
LT6604-10/
LT6604-15
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter
with ADC Driver
Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
Distortion Amplifiers
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2261-14
