Acapella Optical Modem IC Full duplex serial transmission through a single fiber-optic cable without the need for expensive WDM devic Ping Pong system supporting bi-directional Laser Duplex Devices or PPLEDs. Block diagram of ACS405 chip-set Laser TCLE: sl 5 TPOS he So TNEG a RCLE PIN: Diode [EE SSEORBOS 4 RNRG Laser Duplex Device Single fiber full duplex system using ACS405 chip-set with a T1/E1 Framer IC and Laser Duplex Device. The ACS405 is acomplete controller, driver and receiver IC, supporting full-duplex synchronous transmission up to 8.448/6.312Mbps over a single-optical fiber. The designer can share the available bandwidth over 1 to 8 main channels by selecting the appropriate combination on the DRinput pins. In addition to the main channels, the ACS405 provides a single auxiliary maintenance channel of 64Kbps. The internal machine cycle provides for link lengths up to 25/50Km. On the electrical side HDB3/AMI/NRZ/B8ZS interfaces are selectable. Communicating modems automatically maintain synchronisation with each other, such that the receive phase of one modem is lined-up with the transmit phase of the other, compensating for the propagation delay presented by the link. Link lengths from zero to maximum distance are catered for automatically.The ACS405 Chip-set The ACS405 comprises a chip-set of two highly integrated devices, the ACS405A and ACS405B. The ACS405A is an analogue device and the ACS405B is predominately a digital device. The ACS405A contains the Laser/LED driver as well as the PIN receiver circuitry. Since the device does not transmit and receive concurrently (ping-pong), there is no risk of noise generated by the transmitter interfering with the sensitive receive circuitry. The ACS405B comprises the logic necessary to time compress and decompress the data, plus all the logic associated with window synchronisation and locking. For the purpose of this specification the chip-set will be referred to as the ACS405 and the individual devices as the ACS405A or ACS405B. Inter-Modem Coding The inter-IC coding between communication modems is 8B10B. Whilst transparent to the user, 8B10B encoding ensures that there is no DC component in the signal, and provides frequent data transitions, factors which ease the task of data recovery and clock extraction. The coding rules are continuously checked to ensure the integrity of the link, and errors are indicated on the ERRL and ERRC pins ( see section headed ERRC and ERRL - Error Detection ). The Transmit and Receiver Functions Data presented at the near-end TPOS/TNEG is time- compressed, encoded in the 8B10B format and transmitted over the link in a high frequency burst. The optical interface is then configured as a receiver ready to accept data from the far-end. The received data is decoded, time decompressed and de-jittered and then presented to the RPOS/RNEG data output pins. PORB The Power-On Reset (PORB) pin resets the device if forced low for 2ms or more. In normal operation PORB should be held High. It is recommended that PORB is connected to VD+ via a 100KQ resistor and to GND via a 100nF capacitor. PORB has a special function when used in conjunction with memory lock (see section headed Diagnostic Modes). System Clock The system clock on the ACS405 may be derived from an external source or generated locally using the on-chip crystal oscillator. The oscillator (XTO/I) requires the use of a fundamental parallel resonance crystal with appropriate padding capacitors. The input pin, SCEXT should be connected to GND. Contact Acapella for a source of suitable crystals. If it is required to drive the device with an externally generated system clock source, then the clock source should be connected to input pin ECLK with SCEXT connected to VD+. It is often more convenient to drive boards containing multi ACS405 chip-sets from a single system clock source. The system clock frequency is determined by the choice of data rates and is tabulated in section headed, Data Rate Selection. For example, for E2 operation, the appropriate frequency is 33.792MHz and for T2 operation, 31.560MHz. The system clock defines the burst frequency at which data is transmitted over the optical link via the optical interface. The receive circuitry within the ACS405B recovers the clock from the received data at the Rxdat inputs and produces a clock that is synchronised to the incoming data stream. The system clock must have a maximum tolerance of +/- 50 ppm over the desired temperature range. Optical Operational Modes The ACS405 has four optical operational modes controlled by the pins LASER, LASRX and PINRX on the ACS405A device. All of the duplex modes in Table 1 may be converted to dual fiber operation simply by interfacing to separate transmitting and receiving devices. Mode Optical Device 1 Laser Duplex using 4-pin Laser. 2 Laser Duplex using 3-pin Laser. 3 LED Duplex. 4 LED (ping-pong). Table 1 Mode 1 - Laser Duplex using 4-pin Laser In mode 1, the device is configured for use with a Laser duplex device containing a 4-pin laser. The diagram below shows the connections to the ACS405A device. The operational control pins found on the ACS405A are configured as follows: ACS405_ Issue 4.0 December 1998.Duplex Device LAP VA+ PMN LAN Single Fiber PINP PINN Laser Duplex Device containing 4-pin Laser. VA+ = the TxVDD power supply to the ACS405A. MODE 1 LASER = VA+ LASRX = GND PINRX = VA+ For the Bookham transceiver module, the following connections should be made: Monitor pd p side - pin2 = PMN Monitor pd n side - pin3 = LAP Laser diode n side - pind = LAN Laser diode p side - pin6 = LAP Receive pd p side - ping = PINP Receive pd n side - pin 10 = PINP pin 1, 4, 7, 8, 11, 14 should be tied to GND Mode 2 - Laser Duplex using 3-pin Laser In mode 2, the device is configured for use with a Laser duplex device containing a 3-pin laser. The diagram below shows the connections to the ACS405A device. The operational control pins found on the ACS405A are configured as follows: LASER = VA+ LASRX = GND PINRX = VA+ Duplex Device LAP PMN LAN Single Fiber PINP PINN LED Duplex device containing 3-pin Laser. MODE 2 Mode 3 - LED Duplex Device In mode 3, the device is configured for use with an LED duplex device. The diagram below shows the connections to the ACS405A device. The operational control pins found on the ACS405A are configured as follows: Duplex Device LAP LAN PINP PINN LED Duplex device containing LED and PIN. MODE3 LASER = GND LASRX = GND PINRX = VA+ Mode 4 - LED Ping Pong In mode 4, the modemis configured for use with a ping- pong LED device (PPLED). The diagram below shows the connections to the ACS405A device. Ping-Pong LEDs are standard LEDs which exhibit good photo-detection (high responsivity, low capacitance) characteristics when reverse biased. Ping-Pong LEDs are available from several manufacturers as well as from Acapella. PPLED LAP Single Fiber LAN Ping-Pong LED MODE 4 LASER = GND LASRX = VA+ PINRX = GND ACS405_ Issue 4.0 December 1998.Control of LED current During the transmit cycle, the LED drive current is directly proportional to the programmed reference current. To minimise switching delay, a permanent bias current is maintained through the LED. The data modulation produces bursts of high light and low light to represent logic high and low levels respectively. The low light level is set by a current equal to 10% of the drive current generated for the high light level. Since LEDs have a linear relationship between current and optical output power, this results in a optical high power of 10 times the optical low power. The optical power is controlled by a variable resistor (Rtset) connected between TSET and Ground (GND). The lower the value of Rtset the greater the current, for this reason the lower limit for Rtset should be 1KQ, which equates to a nominal peak transmit current of 100mA. A practical maximum for Rtset is 50kQ. Acapella, therefore recommends that Rtset should comprise a fixed resistor of 1KQ in series with a logarithmic potentiometer of 50KQ, thus, affording overload protection for the LED together with precise control of current. I = 100/Rtset LED (High) I = 10/Rtset LED (Low) * where Rtset > 1K Q, tolerance = +/- 20%. | = Amps Control of Laser Current During the transmit cycle, the Laser drive current is controlled so as to maintain a constant optical output power from the Laser. The monitor-pin resident in the Laser converts the incident light power (from the Laser itself} to a monitor-current, which is directly compared to a preset programmed current ( the current flowing through TSET). The Laser drive current is automatically adjusted to maintain the original preset light level over the recommended temperature and voltage range. The designer should be aware that whilst the control loop maintains the current generated by the monitor- pin within a tolerance of 2%, there is additional uncertainty attributed to the monitor-pin's temperature coefficient of responsivity. Data relating to the Laser characteristics should be acquired from the Laser supplier. The monitor-pin current is set by a variable resistor (Rtset), connected between TSET and Ground (GND). Acapella recommends that Rtset should comprise a logarithmic potentiometer of value 50KQ. It is important to ensure that the Rtset resistor is inserted and adjusted to its maximum resistance value of 50KQ prior to applying power to the ACS405A for the first time and prior to following the procedure detailed in section headed, Laser Adjustment Procedure. I = 2.0/Rtset PIN (High) * Tolerance = +/- 20%. | = Amps TxMN and TxFLG TXMN is used to monitor the current delivered to the LED or Laser. TXMN is a current source that proportionally mirrors the current flow through the LED or Laser. By placing an appropriate resistor (Rtxmn) between TXMN and GND, the voltage developed (referenced to GND), will be proportional to the transmit current. During the Laser setup procedure TxMN should be monitored to ensure that the Laser manufacturer's maximum current specification is not exceeded (see section headed Laser Adjustment Procedure). TXMN may also be employed during normal operation to continuously check the Laser current. The voltage developed across Rtxmn is compared within an internally generated reference voltage of 1.25V. In the event that the reference voltage is exceeded, the TxFLG is set high, otherwise it is set low. The relationship between the transmit current and the TXMN current is : * _ * I LASER (High) ~ 100 * TxMN * Tolerance = +/- 10%. | = Amps IF Rtxmn = 1KQ, then TxFLG = 1 when the Laser current exceeds 125mA. Laser Adjustment Procedure The output power from the Laser should be measured with a optical power meter during the setup procedure. Select one of the Laser drive modes in accordance with section headed, Operational Modes. Start with the highest resistance for Rtset ( At least 50KQ is recommended). This defines the monitor-pin reference current. Select the Laser setup mode on the ACS405B by asserting SETB low, this forces the Laser into a continuous transmit mode and applies dc-balanced data (equal number of ones and zeros) to the Txdat input of the ACS405A device. As Rtset is reduced in value, the current to the Laser will increase. The current to the Laser should be monitored at the TxMN in accordance with section headed, TXMN and TxXFLAG. The Laser current will be stable when the Laser starts to lase, and produces enough optical power for the PIN feedback current to equal the current flowing through Rtset. The Rtset impedance should be decreased until the desired Laser output high-power is achieved. Once the setup procedure has been completed, the SETB pin should then be set high to return the device to the ACS405_ Issue 4.0 December 1998.operation mode. The preset Laser power will then be maintained over the recommended temperature and voltage range. Receive Monitor The ACS405A incorporates a power meter which generates a current source which is proportional to the received optical current. I =6*! RXMN (PIN) * Tolerance = +/- 20%. | = Amps | ean lows through a resistor, internal to the ACS405A, connected between RxMN and GND. The internal resistor has a value of 260KQ +/- 20 %. RxMN is compared with 1.25V. If RxMN exceeds 1.25V, then output RxFLG is set = 1, otherwise RxFLG is set = 0. With the internal resistor of 260KQ, the default threshold for the RxFLG is a input current of 800nA +/- 25%. By adding an external parallel resistor between RxMN and GND, this threshold may be increased. The voltage on RXMN will modulate with receive data bursts. It will settle to its correct value within 4us following the start of a receive burst, and will collapse to OV after a burst ends. Transmission Clock TCLK There are two independent transmit clocks on the ACS405, TCLK1 and TCLK2. For the purpose of this specification, these signals will be referred to collectively as TCLK. The ACS405 gives a choice between internally and externally generated transmit clocks. When the CKC pin is held Low, TCLK is configured as an output producing a clock at the frequency defined by DR(4:1). When the CKC pin is held High, TCLK is configured as an input, and will accept an externally produced transmission clock with a tolerance of up to 250ppm with respect to the transmission rate determined by DR(4:1). Input data appearing on the TPOS/TNEG inputs is latched into the device on the falling edge of TCLK for both internally and externally generated transmission clocks. Receive Clock RCLK There are two independent receive clocks on the ACS405, RCLK1 and RCLK2. For the purpose of this specification, these signals will be referred to collectively as RCLK. The data appearing on RPOS/RNEG is valid on the rising or falling edge of the RCLK clock dependent on the setting of RESEL (see Figure 1. Timing diagrams). To ensure that the average receive frequency is the same as the transmitted frequency, RCLK is generated from a Digital Phase-Lock Loop (DPLL) system (except where master mode has been selected). The DPLL makes periodic corrections to the output RCLK clock by subtracting or adding a single crystal clock bit-period, so that the average frequency of the RCLK clock tracks the average frequency of the transmit clock of the far-end modem (or system master clock). This decompression/de- jittering function is covered in more detail in section headed, Jitter Characteristics. Data Codin The main synchronous channels may use any of the following coding methods; NRZ, AMI, HDB3, B&8SZ. The desired mode is selected by POL1 and POL2 input pins, as shown in Table 2. Data Coding POL2 POLI AMI 0 0 HDB3 0 1 B8SZ 1 0 NRZ 1 1 Table 2 For Non-Return-to-Zero (NRZ) coding, data is applied directly to TPOS inputs, and outout data appears only on the RPOS output pins (except for 8-channel mode, see section headed, Multi-Channel Operation). When using NRZ code, unconnected TNEG input pins will automatically pull-up to VD+. In addition, the ACS405 will assert a continuous Low on redundant RNEG output pins. AMI, B8SZ and HDB3 coding is normally bipolar. However, it is possible to interface with the ACS405 using two inputs and outputs rather than a single bipolar interface. Data equivalent to positive excursions of the bipolar AMI/B8SZ/HDB3 signal are applied as a logic High to TPOS, while data equivalent to negative excursions are applied as a logic High to TNEG. Similarly, AMI/B8SZ/HDB3 positive excursions will appear as a logic High on RPOS and negative excursions will appear as a logic High on RNEG. It is anticipated that most users of the ACS405 will interface directly with a E1/T1 framers. All the popular framers provide POS/NEG bipolar interfaces which will directly connect to the ACS405B. If required, a detailed description of the AMI/HDB3 coding rules are available from Acapella. ACS405 Issue 4.0 December 1998.Data Rate Selection For the purpose of this specification TPN1 represents the set of signals TPOS1 and TNEG1, and RPN1 represents the set of signals RPOS1 and RNEG1. See section headed, Data Coding for a description of the coding types. The maximum recommended crystal (XTAL) is 33.792MHz, this gives a maximum bandwidth of 8.448MHz (E2). This bandwidth can be utilised in various ways, it may be divided up over 1,2,4,8 channels. It may be required to support 2 independent clocks, in which case the available bandwidth is reduced to 4.224MHz. Single clock operation is known as mode TX1 and dual clock as TX2. There is a third mode of operation known as HT mode (High Tolerance), which is more fully described later. For the purpose of this specification these transmission modes are known collectively as the Tmodes. The data rate selection pins DR(4:1), determine the frequency of the TCLK clock, the number of channels and the transmission mode (TMode) in accordance with the Table 3. DR Pins TCLK Nos. of Tmode 4321 freq channels 114141 XTAL/4 1 Tx1 1110 XTAL/5 1 Tx1 1101 XTAL/16 2 Tx2 1100 XTAL/20 2 Tx2 10411 XTAL/16 1 HT 10410 XTAL/20 1 HT 1001 XTAL/16 4 Tx1 1000 XTAL/20 4 Tx1 01141 XTAL/32 4 Tx2 0110 XTAL/64 4 Tx2 0101 XTAL/32 8 Tx1 0100 XTAL/64 8 Tx2 0011 XTAL/128 8 Tx2 0010 XTAL/256 8 Tx2 0001 XTAL/8 1 Tx1* 0000 XTAL/10 1 Tx1* * 50 Km modes Table 3 Asymmetrical Data Rates It is possible to configure the DR pins setting on each side of the link differently (with input Fhold) as long as identical crystal values are observed on the communicating devices. For example, the near-end ACS405 may be configured to transmit 8 channels at 1Mbps and the far-end modem may be configured to transmit 1 channel at 8Mbps. For asymmetrical communication, set fhold = 0, this will lead to the receive circuitry reading the DR pins settings from the far-end ACS405 rather than locally. It is important that the receive circuitry is aware of the configuration and formatting of the data so that it can correctly interpret it. Prior to lock (when DCD = 0}, the receive circuitry will default to the local DR pin settings. For symmetrical communication (with input Fhold = 1), DR pins setting sent over the link are ignored and the receive circuitry will always read the locally set DR pin values. It is expected that for the vast majority of applications symmetrical communication will be employed. When asymmetrical mode is selected (Fhold = 0), the only valid DM settings are the Full Duplex modes. The other modes of Remote-Loop-back, Local-Loop-back, master and slave (as described in the section headed, Diagnostic modes) are not available. Multi-Channel Operation There are four choices for multi-channel operation on the ACS405, selected by the DR(4:1) pins, namely, 1,2, 4 or 8 channel operation. 1-Channel Operation In 1-channel operation TPOS1/TNEG1 and RPOS1/ RNEG1 is the only active channel. Data appearing on other TPN inputs is ignored. All other RPN outputs are forced low. 2-Channel Operation In 2-channel operation channel mappings can be seen in Table 4. Channel Nos. Input Output 1 TPOS1/TNEG1 RPOS1/RNEG1 2 TPOS2/TNEG2 RPOS2/RNEG2 Table 4 Data appearing on all other TPN inputs is ignored. All other RPN outputs are forced low. 4-Channel Operation In 4-channel operation the mappings can be seen in Table 5. Channel Nos. Input Output 1 TPOS1/TNEG1 RPOS1/RNEG1 2 TPOS2/TNEG2 RPOS2/RNEG2 3 TPOS3/TNEGS3 RPOS3/RNEG3 4 TPOS4/TNEG4 RPOS4/RNEG4 Table 5 ACS405_ Issue 4.0 December 1998.8-Channel Operation If one of the 8-channel modes is selected by the DR(4:1) inputs, then the ACS405 must be configured to expect Non-Return-to-Zero (NRZ) transmission data using the POL1/2 settings. The otherwise redundant TNEG and RNEG pins are then available to carry 4 additional data channels. The mapping of transmission pins for 8-channel NRZ operation can be seen in Table 6. Channel Nos. Input Output 1 TPOS1 RPOS1 2 TNEG1 RNEG1 3 TPOS2 RPOS2 4 TNEG2 RNEG2 5 TPOS3 RPOS3 6 TNEG3 RNEG3 7 TPOS4 RPOS4 8 TNEG4 RNEG4 Table 6 Transmission Modes (TMode) There are three transmission modes available on the ACS405 selected by the DR(4:1) pins, these are TX1, TX2 and HT modes. TX1 mode In TX1 mode all of the data channels (TPN/RPN) are related to the clocks TCLK1/RCLK1. TX2 mode In TX2 mode there are two system clocks, half the signals are aligned to the clock TCLK1/RCLK1 and the remaining half are aligned to the clock TCLK2/ RCLK2. For dual channel operation, channel 1 is aligned to clock TCLK1/RCLK1 and channel 2 is aligned to clock TCLK2/RCLK2. For four channel operation, channels 1-2 are aligned to clock TCLK1/RCLK1 and channels 3-4 are aligned to clock TCLK2/RCLk2. For eight channel operation, channels 1-4 are aligned to clock TCLK1/RCLK1 and channels 5-8 are aligned to clock TCLK2/RCLk2. HT Mode Acapella recognises that a large number of designers using the ACS405 modem will be employing the device for single channel T1 or single channel E1 operation. In such cases, the available bandwidth far exceeds the bandwidth required. To exploit this otherwise redundant bandwidth, the ACS405 incorporates a High Tolerant (HT) transmission mode. In HT mode, by virtue of on-chip error-correction, the device is extremely tolerant to data errors. All modes in the ACS405 generate regular unique Synchronisation Words (SWs) in order to re-enforce 8B10B word boundary synchronisation. This prevents single bit-errors causing an avalanche of errors due to word boundary slippage, often referred to as "error extension". In HT mode, SWs are interleaved with the data-words such that alternate words are SWs, ensuring that the effect of 8B10B word boundary errors will not propagate beyond one received data word. In HT mode the single data channel is aligned to the TCLK1/RCLK1 clock. 50Km long haul Mode Some customers will require a modem capable of supporting a longer distance than the standard 25kKm. To support this Acapella have implemented a 50Km mode for a single E1 or T1 channel. This is achieved with an XTAL of value half of that used for the standard E1 or T1 for 25Km modes in combination with the appropriate configuration of the DR(4:1) pins. NOTE: The designer should be aware that the use of lower value crystal will proportionally increase the end-to-end data delay through the system in accordance with the formula found in section headed, Data Delay (Latency). Therefore, for the 50Km mode the latency will double compared to the standard 25Km modes. Example Data Rate Selection A set of example configurations follow: E2 Selection In orderto select one E2 operation then set DR4 = DR3 = DR2=DR1 =1, together with acrystal of 33.792MHz as shown in the Table 7. DR4 DR3- DR2_ DRI XTAL TCLK Divide (MHz) 1 1 1 1 4 8.448 crystal = 33.792 MHz Table 7 T2 Selection In order to select one T2 channel then set DR4 = DR3 = DR2 = 1; DR1 = 0, together with a crystal of 31.560MHz as shown in the Table 8. ACS405_ Issue 4.0 December 1998.DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 1 1 0 5 6.312 crystal = 31.560 MHz Table 8 2 * El Channel Selection In order to select two independent E1 channels in TX2 mode then set DR4 = DR3 = DR1 = 1; DR2 = 0, together with a crystal of 32.768MHz as shown in the Table 9. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 1 0 1 16 2.048 crystal = 32.768 MHz Table 9 2 * T1 Channel Selection In order to select two independent E1 channels in TX2 mode then set DR4 = DR3 = 1; DR1 = DR2 = 0, together with a crystal of 30.88MHz as shown in the Table 10. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 1 0 0 20 1.544 crystal = 30.88 MHz Table 10 1 * E1 Channel Selection HT mode In order to select one E1 channel operating in High Tolerance (HT) mode then set DR4 = DR2 = DRI = 1; DR3 = 0, together with a crystal of 32.768MHz as shown in the Table 11. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 0 1 1 16 2.048 crystal = 32.768 MHz Table 11 1 * E1 Channel Selection at 5}0Km In order to double the available transmission distance from 25Km to 50Km, the value of the crystal must be reduced by half. For a single E1 channel set DR4 = DR3 = DR2 = 0; DR1 = 1, together with a crystal of 16.384MHz as shown in Table 12. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 0 0 0 1 8 2.048 crystal = 16.384 MHz Table 12 1 * T1 Channel Selection in HT mode In order to set the device for one T1 channels operating in High Tolerance Mode (HT) then DR4 = DR2=1; DR38 = DR= 0, together with a crystal of 30.88MHz as shown in the Table 13. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 0 1 0 20 1.544 crystal = 30.88 MHz Table 13 1 * T1 Channel Selection at 5}0Km In order to double the available transmission distance from 25Km to 50Km, the value of the crystal must be reduced by half. For a single T1 channel set DR4 = DR3 = DR2 = DR1 = 0, together with a crystal of 15.44MHz as shown in Table 14. DR4 DR3 DR2 ~~ DRI XTAL TCLK Divide (MHz) 0 0 0 0 20 1.544 crystal = 15.44 MHz Table 14 4 * E1 Channel Selection In order to set the device for four E1 channels then DR4 = DR1=1; DR3 = DR2= 0, together with a crystal of 32.768MHz as shown in the Table 15. DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 0 0 1 16 2.048 crystal = 32.768 MHz Table 15 4 * T1 Channel Selection In order to set the device for four T1 channels then DR3 = DR2 = DR1 = 0; DR4=1, together with a crystal of 30.88MHz a shown in the Table 16. ACS405_ Issue 4.0 December 1998.DR4 DR3 DR2~ DRI XTAL TCLK Divide (MHz) 1 0 0 0 20 1.544 crystal = 30.88 MHz Table 16 Other Transmission Data Rates Other standard frequencies may be obtained by setting the appropriate DR(4:1) combination with a 32.768MHz crystal as shown in the Table 17. DR4 DR3 DR2_ DRI Nos. of XTAL = TCLK Chann. Divide (KHz) 0 1 1 1 4 32 1024 0 1 1 0 4 64 512 0 1 0 1 8 32 1024 0 1 0 0 8 64 512 0 0 1 1 8 128 256 0 0 1 0 8 256 128 crystal = 32.768 MHz Table 17 Asynchronous Communication In order to propagate asynchronous data through the ACS405, the device should be configured with CKC = 0 so that the device produces a TCLK output clock. The TCLK clock asynchronously over-samples the data applied to TPOS at the rate defined by DR(4:1). The choice of TCLK frequency defines the sample rate of the input data and therefore the sampling-jitter appearing at RPOS of the far-end modem. Example: 8 - asynchronous 115 Kbps channels. XTAL = 32.768MHz DR4/3/2/1 = O/1/0/1 CKC = 0 TCLK clock = 1.024MHz TPOS/TNEG data rate = 115Kbps Over-sample factor = 8.9 11%. the maintenance used to convey Sampling Jitter (approx.') Similar considerations apply to channel, which may also be asynchronous data. Support channels There are up to two support channels on the ACS405: TmD1/RmD1 and TmD2/RmD2. For the purpose of this specification these will be referred to collectively as TmD and RmD. The support channels can be used in one of two ways selected by the input Frame. Maintenance channel mode with Frame = 0 When Frame = 0 then maintenance mode is selected. This mode only support channel TmD1/RmD1. which is known as the maintenance channel. TmD2/RmD2 is not available for data transmission. TmD1/RmD1 may be considered as an independent maintenance channel that supports data rates of 64Kbps or 32Kbps depending on the setting of the DR(4:1) pins. See Table 18. Input data appearing on the TmD1 input is latched into the device on the falling edge of TmCLK and appears at the RmD1 output of the far-end modem on the rising edge of RMCLK. The ACS405 gives a choice between internally and externally generated TmCLK clocks. When the CKM pin is held Low, TmCLK is configured as an output producing a clock at 64KHz or 32KHz. When the CKM pin is held High, TmCLK is configured as an input, and will accept an externally produced transmission clock at 64KHz or 32KHz with a tolerance of 500ppm. The TmD1/RmD1 is an independent channel and consequently there is not a fixed phase relationship between the maintenance channel and the main TPOS/TNEG data transmission channels. DR4 DR3 DR2 DRI XTAL XTAL TmCLK (MHz) DC (KHz) 1 1 1 1 33.792 528 64 1 1 1 0 31.560 493.125 64 1 1 0 1 32.768 512 64 1 1 0 0 30.88 482.5 64 1 0 1 1 32.768 512 64 1 0 1 0 30.88 482.5 64 1 0 0 1 32.768 528 64 1 0 0 0 30.88 482.5 64 0 1 1 1 32.768 512 64 0 1 1 0 32.768 512 64 0 1 0 1 32.768 512 64 0 1 0 0 32.768 512 64 0 0 1 1 32.768 512 64 0 0 1 0 32.768 512 64 0 0 0 1 16.384 512 32 0 0 0 0 15.440 482.5 32 Table 18 Each DR(4:1) mode is designed to achieve a particular communication frequency by the combination of the XTAL value and DC value. Table 18 shows the recommended XTAL and the Divide Constant (DC) for each DR(4:1) selection. If the recommended XTALs are not employed, then the frequency of the TmCLK clock can be calculated from the Divide Constant. ACS405_ Issue 4.0 December 1998.Frame channel mode with Frame = 1 When Frame = 1 the channels TmD1/RmD1 and TmD2/RmD2 become support channels to the main TPOS/TNEG data channels. Data appearing on inputs TmD1/2 are latched into the device on the falling edge of TCLK for both internally and externally generated transmission clocks. Output data appearing on RmD1/2 is valid on the rising or falling edge of the RCLK clock depending on the setting of RESEL (see Figure 1. Timing diagrams). For 1-channel operation in either TX1 or HT mode then TmD1/RmD1 will be available for transmission but data appearing on TmD2 will be ignored. For 2-channel operation in TX2 mode then both TmD1/RmD1 and TmD2/RmD2 are available for transmission. TmD1 is associated with channel 1 and is clocked by TCLK1/RCLK1. TmD2 is associated with channel 2 and is clocked by TCLK2/RCLk2. For all other data formats, frame mode is currently unavailable. Although, the data applied to the TmD1/2 is clocked by TCLK with the same resolution as TCLK the number of transitions allowed on these inputs is restricted according to the rules below. TX1_ mode A maximum of 2 transitions are permitted on TmD1 for each 512 TCLK1 clock period. If two transitions occur sequentially (on two successive TCLK cycles) then this may be counted as one transition. TX2_ mode A maximum of 2 transitions may occur on both TmD1/ 2 for each 128 TCLK1/2 clock period. If two transitions occur sequentially (on two successive TCLK1/2 cycles) then this may be counted as one transition. HT mode A maximum of 2 transitions may occur on TmD1 for each 128 TCLK1 clock period. If two transitions occur sequentially (on two successive TCLK1 cycles) then this may be counted as one transition. In frame mode, TPOS/TNEG and the associated TmD data are transmitted over the link in phase and will appear in phase at the RPOS/RNEG and RmD outputs at the far-end ACS405. A typical application of frame mode follows: In an E1 frame, only 30 of the available 32 symbols are available for data transmission, the remaining two symbols are deployed for frame synchronisation and signalling. In a proprietary system, it would be possible to use the TmD1/2 support channels to mark 10 the first bit or first word of each frame, thus freeing up extra bandwidth in the main data channels. Diagnostic Modes The ACS405 has eight diagnostic modes controlled by DM(8:1) as shown in Table 19. The diagnostic modes apply equally tothe TPN/RPN and TmD/RmD channels. Diagnostic Mode Lock DM3 DM2 DMI Full-duplex Drift 0 0 0 Full-duplex Memory 0 0 1 Remote loopback Active 0 1 0 Full-duplex Random 0 1 1 Local loopback Drift 1 0 0 Full-duplex slave Active 1 0 1 Full-duplex master Drift 1 1 0 Full-duplex Active 1 1 1 Table 19 Full-Duplex In the full-duplex configuration, the RCLK clock of both devices track the average frequency of the corresponding TCLK clock of the opposite end of the link. The receiving Digital-Phase-Lock Loop (DPLL) system makes periodic adjustments to the RCLK clock to ensure that the average frequency is exactly the same as the far-end TCLK clock. In summary, each TCLK is an independent master clock and each RCLK a slave of the far-end TCLK clock. The relationship between TmCLK and RmCLK are treated similarly. Full-Duplex Slave In slave mode, the TCLK and RCLK clock is derived from the TCLK clock of the far-end modem, such that their average frequencies are identical. Clearly, it is essential that only one modem within a communicating pair is configured in slave mode. The CKC pin should be forced to GND, so that TCLK is always configured as an output. Since only one device in the modem pair may be configured in slave mode, the mode also selects active lock. See section headed, Locking Modes. The relationship between TmCLK and RmCLK are treated similarly. The CKM pin should be forced to GND, so that TmCLK is always configured as an output. Full-Duplex Master In master mode, the local RCLK clock is internally generated from the local TCLK clock. The local TCLK clock may be internally or externally generated. Master mode is only valid if the far-end device is configured in slave mode or if the far-end TCLK ACS405_ Issue 4.0 December 1998.clock is derived from the far-end RCLK clock. Only one modem within a communicating pair may be configured as a master. The relationship between TmCLK and RmCLK are treated similarly. Local Loopback In local loopback mode, TPN and TmD data is looped back inside the near-end modem and is output at its own RPN and RmD outputs. Data received from the far-end device is ignored, except to maintain lock. If concurrent requests occur for local and remote loopback, local loopback is selected. The local loopback diagnostic mode is used to test data flow up to, and back from, the local ACS405 and does not test the integrity of the link itself. Therefore, local loopback operates independently of synchronisation with a second modem (i.e. DCD may be High or Low). Remote Loopback In remote loopback mode, the near-end modem sends a request to the far-end modem to loopback its received data, thus returning the data so that it appears at the RPN and RmD of the initiating modem. Both modems are exercised completely, as well as the Lasers/LEDs and the fiber optic link. The remote loopback test is normally used to check the integrity of the entire link from the near-end (initiating modem). Whilst a device is responding to a request for remote loopback from the far-end, requests from the near- end to initiate remote loopback will be ignored. Locking Modes Drift Lock Communicating modems attain a sTable state when the transmit window of one modem coincides with the receive window of the other, allowing for delay through the optical link. Adjustments to machine cycles are made automatically during operation, to compensate for differences in XTAL frequencies which would otherwise cause loss of synchronisation. When both modems are configured in drift lock, synchronisation described above depends on a difference in the XTAL or system clock frequencies at each end of the link, and the greater the difference the faster the locking. Therefore, if the difference between XTAL frequencies is very small (a few ppm), automatic locking may take tens of seconds or even minutes. For this reason, normally only one modem in the communication pair will be configured in drift lock mode. Drift lock will not succeed if the two modems are I] driven by an external XTAL clock derived from a single source (i.e. tolerance of 0 ppm). Active Lock Mode Active lock mode may be used to accelerate synchronisation of a pair of communicating modems so that they achieve lock in less than 1 second. Active lock reduces the machine cycle of the device by 0.5% ensuring that the receive window moves swiftly through the transmit window of the opposing modem. To effect active lock, one modem should be permanently configured in drift lock and the other in active lock. If this is not possible because the system mandates that all modems are peers ( configured identically ), then the same effect may be realised by temporarily invoking lock for a short time after power-up. This is achieved as follows: connect pins DM1, DM2 and DMS together attaching the node to an RC arrangement, with the capacitor to VDD and the resistor to GND, to create a5 Vto OV ramp on power-up. The RC time-constant should be Ca. 5 seconds. Active lock will succeed even when communicating devices are driven from clocks derived from a single source (0 ppm). Random Lock This mode achieves moderate locking times (typically 2 seconds, worst case 3 seconds) with the advantage that the ACS405s are configured as peers. Communicating modems may be permanently configured in this mode (i.e. with hard-wired pins). Random lock will succeed even when communicating devices are driven from clocks derived from a single source (0 ppm). Random lock mode is compatible with drift lock and active lock. Memory Lock Following the assertion of a reset (PORB = 0) communicating devices will initiate an arbitration process where within 2 seconds (typically) the communicating modems will achieve synchronisation, one establishing itself as an active-lock modem and the other establishing itself as a drift-lock modem. On subsequent attempts to lock, synchronisation will be achieved within 1 second. It is only necessary to apply PORB to one device in the communicating pair to initiate an arbitration process. Since memory lock status (Active or Drift) uses on- chip storage, loss of power to the IC will require a new reset (PORB = 0). Furthermore, should there be a need to synchronise with a third modem, a new reset will be required. ACS405_ Issue 4.0 December 1998.Mixing Lock Modes It is possible to mix all combinations of locking modes once the modems are locked, however, prior to synchronisation two modems configured in active lock will not operate. The effect of mixing locking modes on locking speed can be seen in Table 20. DeviceA DeviceB Locking Speed Mode Mode Drift Drift Drift Drift Active Active Drift Random Random Drift Memory Random Active Active Not allowed Active Random Random Active Memory Random Random Random Random Random Memory Random Memory Memory Active* * Memory lock has random lock speed for the first synchronisation (arbitration). Table 20 ERRC and ERRL - Error Detection These signals can be used to give an indication of the quality of the optical link. Even when a DC signal is applied to the data, maintenance and TCLK inputs, the ACS405 modem transmits approximately 11Mbps over the link in each direction. This control data is used to maintain the timing and the relative positioning of transmit and receive windows. The transmit and control data is constantly monitored to make sure it is compatible with the 8B10B format. If a coding error is detected ERRL will go High and will remain High until reset. ERRL may be reset by asserting PORB, or by removing the fiber optic cable from one side of the link thereby forcing the device temporarily out of lock. ERRC produces a pulse on detection of each coding error. These pulses may be accumulated by means of an external electronic counter. Please note that ERRL and ERRC detect coding errors and not data errors, nevertheless because of the complexity of the coding rules employed on the ACS405, the absence of detected errors on these pins will give a good indication of a high quality link. Laser/LED Considerations Since LEDs or Lasers from different suppliers may emit different wavelengths, it is recommended that the Lasers/LEDs in a communicating pair of modems are obtained from the same supplier. Acapella can supply details. 12 Power Supply Decoupling The ACS405A contains a highly sensitive amplifier, capable of responding to extremely low current levels. To exploit this sensitivity it is important to reduce external noise to a low level compared to the input signal from the Laser/LED. The modem should have an independent power trace to the point where power enters the board. Figure 4, shows the recommended power supply decoupling. The Laser/LED should be sited very close to the PMN, PINP, PINN, LAN and LAP pins. A generous ground plane should be provided, especially surrounding the sensitive PINP and PINN tracks from the ACS405A pins to the optical component. The modem should be protected from EMI/RFI sources in the standard ways. Link Budgets The link budget is the difference between the power coupled to the fiber via the transmit Laser/LED and the power required to realise the minimum input- amplifier current via the receive PIN/LED. The link budget is normally specified in dB, and represents the maximum attenuation allowed between communicating Lasers/LEDs. The budget is utilised in terms of the cable length, cable connectors and splices. It usually includes an operating margin to allow for degradation in LASER/LED performance. The power coupled to the cable is a function of the efficiency of the Laser/LED, the current applied to the Laser/LED and the type of the fiber optic cable employed. Digital Mode The ACS405B may be used as a controller and data compression/decompression engine, which allows the device to be used with an external circuitry for non- fiber applications. Check with Acapella for details. LOSS (Loss Of Synchronisation) There are two conditions that will make LOSS go to logic 1: i) Loss of synchronisation - ping-pong windows incorrectly aligned i.e DCD = 0. ii) 64 received symbols break the 8B10B encoding rules in a sequence of 256 symbols. In order to return LOSS to the logic state 0 the following criteria must be met. i) The devices must be synchronised - ping-pong windows correctly aligned i.e DCD = 1. ii) There are no received symbols in a sequence of 256 symbols which break the 8B10B coding rules. ACS405_ Issue 4.0 December 1998.Data Delay (Latency) Although the ACS405 is a full-duplex modem, at the fiber level the device operates in a half-duplex manner. Typically, half-duplex systems allow bidirectional transmission by alternating the direction of data flow. This means that data must be stored until the link is configured in the appropriate direction. Storage inevitably leads to delay or latency. Acapella has designed the ACS405 to minimise latency by very rapidly switching direction at the fiber level, minimising the need to store data. The latency through the system applies to the main data TPOS/TNEG channels and the support channels TmD/RmD and is a function of the XTAL frequency. For a given implementation, the latency has three components: 1) A Constant Delay (CD) set by the machine cycle and system clock at a frequency of 32,768MHz then CD = 0.7ms. 2) A Transmission Rate Delay (TRD) which is equal to 125 bit periods worst case (de-jittering buffer and internal registers) 3) Fiber length Dependent Delay (FDD) which is equal to 2 * (fiber delay) The Latency formula is: (0.7 * 108 * 32.768 * 105/XTAL) + (125 * transmit bit period) + (2 * fiber delay) where the fiber delay is typically 5us per Km. Example Latency calculation Latency calculation: Fiber length =10Km (~ 50us) XTAL = 33.792MHz DR mode = 4* 2.048Mbps ( transmit bit period = 488ns) Latency = (0.7 * 10 * 32.768 * 10*/33.792 * 10 10 +2*50 * 10*) =0.84ms Jitter Characteristics + 125 * 488* There are three parameters of jitter performance which must be considered, these are: 1) Input jitter tolerance 2) Outputjitter generation 3) Jittertransfer. The ACS405 has on-board time compression and decompression circuitry. The transmit compression ram acts to attenuate jitter components of 1KHz or greater. The receive decompression ram acts to attenuate jitter components of 100Hz or greater. Below 100Hz the system tracks the input jitter. The overall effect is that the system will exceed the performance requirements of the AT&T 62411 and G.823 At the time of writing the specification, the full jitter behavioural characteristics had not been established. This will be included in the next major release of the specification. 13 ACS405_ Issue 4.0 December 1998.t t c h : wl TmCLK and RmCLK clock pulse widths TmCLK/TCLK RmCLK/RCLK t sut t ht Cour Une TmD 4 RmD 4 Transmit set-up and hold times Receive set-up and hold times The active RmCLK edge is defined by input RESEL. Figure 1. Timing diagrams TCLK it _X Symbol 1 \ Symbol 2 \ Symbol 3 I TPOS/TNEG . a TmD TLL La a RCLK if X Symbol 1 X Symbol 2 x Symbol 3 I ir RPOS/RNEG ee RmD Figure 2. Use of support signals to identify symbols in E1/E2 frame ACS405_ Issue 4.0 December 1998. 14t wh Ca t tc | r f 90 % 90 % 10 % 0% TCLK and RCLK clock pulse widths Digital outputs rise and fall times TCLK RCLK t sut Che t sur Che TPOS/TNEG 4 RPOS/RNEG Transmit set-up and hold times Receive set-up and hold times The active RCLK edge is defined by input RESEL. Figure 3. Timing diagrams VA+ 2 5 VD+ pins are 9, 10, o 26, 38, 39, 63, 75 $ VDD = vD+ Rxdat- I Zz GND pins are 2, 4, 17, 30, 41 100 nF GND VB RxVDD TO VAt+ 100 nF VAt+ { ACS405B VAt+ Lt TxVDD 100 nF ACS405A GND GND 100 oT GND 2 2 CI GND g z GND L=47pHR< 19 VB GND pins are 11, L L ee 12, 27, 29, 37, 51, GND GND 54, 55, 61,62, 74 Vp ont L=47pHR< 19 VA+ (VDD)+5V O + = 100nF (GND) OV 100 nF 100 nF GND Figure 4. Power Supply ACS405_ Issue 4.0 December 1998. I5axe ie 2 Ao (AND) dUuOOr ASH(AdA) nL, +VA OL> UH Ly=T m4 = 4 8 AUOOT ada ZZ oO OWT +)epx qA OL> WH" Ly = 7 LA sive vepxa aHOON FF os LA NWXL aXUNng XING > yepxL NNId C) vagy | INId N WASVI req > o1surg TI NVI OO xasvi/-7 NWd wi xe > 1xL9}-R dv1 vel zH09 -J stort | oqagxy 1agoo|-_T Lasa+--j]H L_] xX +VA OTA LASL - 3} 4 = 7 OR = S adaa o OU ZLASU 100 n 100 n By aalAap xa[dnp Jase] & dALIp 0} panSyuos FSOPSDV PUB VSOFPSOV SULMOYS UBISeIGY * QINSLY 6802 6802] 6802 Adal ILX OLX +18 PXy aXUNna XIN Jepxy WTIOUY equa qua eMXTION IY1IOU IDUNY 1SOda CDOUNA cSOda CDOUNA eSOda POUNY rSOda SOT dod Tadd oud -]epxy ano adsOvVSOV A a +VA + aqaod dTOHA oUIe LT TASHY aLas WD ou0 U/710d Uz/ewa Uefa WIOWL ZaW, Taw CXTOL INTOL IDYUNL ISOd.L COUNL cSOd.L CDANL SOdL POUNL PSOdL MDa LXHOS i a 100 nF 100 nF 4 001 OA 001 ACS405_ Issue 4.0 December 1998. 16Fiber type Fiber size Single Fiber LED link Minimum transmit couple power to fiber (aW) Minimum LED responsivity (A/W) Minimum ACS405 sensitivity (nA) Minimum input power to ACS405 amplifier (aW) Link budget (dB) Link Budget Example (Rtset set so LED launch current = 100 mA peak) Plastic Glass Glass 1000 micron 62.5micron 50 micron 1000 100 50 0.01 0.1 0.12 1500 1500 1500 100 15 12.5 10 8.24 6.0 Fiber type Fiber size Single Fiber LASER link Minimum transmit couple power to fiber (aW) Minimum LASER & PIN responsivity (A/W) Minimum ACS405 sensitivity (nA) Minimum input power to ACS405 amplifier (aW) Link Budget Example (Rtset set so LASER launch current = 25 mA peak) Glass (single mode) 9 micron 1000 0.25 1000 4 Link budget (dB) (single mode fiber attenuation = 0.3 dB/km) 24 Pin Description ACS405B part 1 Pin |Sym |IO|Name Description Receive Clock Support channel receive clock 76 RmCLK | O (support channel) | With frame = 'O' then nominal frequency = 64 KHz 11,12 27,29 37,51 54,55 GND - Ground Power Supply 61,62 74 19 TPOS1 Transmit channel 1, corresponds to +ve in bipolar signal. 21 TPOS2 . Transmit channel 2, corresponds to +ve in bipolar signal. 23 TPOS3 I Transmit Data Pos Transmit channel 3, corresponds to +ve in bipolar signal. 25 TPOS4 Transmit channel 4, corresponds to +ve in bipolar signal. 18 TNEG1 Transmit channel 1, corresponds to -ve in bipolar signal. 20 TNEG2 . Transmit channel 2, corresponds to -ve in bipolar signal. 22 TNEG3 I Transmit Data Neg Transmit channel 3, corresponds to -ve in bipolar signal. 24 TNEG4 Transmit channel 4, corresponds to -ve in bipolar signal. 2 RPOS1 Receive channel 1, corresponds to +ve in bipolar signal. 4 RPOS2 . Receive channel 2, corresponds to +ve in bipolar signal. 6 RPOS3 0 Receive Data Pos Receive channel 3, corresponds to +ve in bipolar signal. 8 RPOS4 Receive channel 4, corresponds to +ve in bipolar signal. ACS405_ Issue 4.0 December 1998. 17Pin Description ACS405B part 2 Pin |Sym |IO |Name Description 9,10 26,38 39.63 VD+ - +ve power supply | Power supply, 4.75 - 5.25 Volts. 75 49 VA+ _ +ve power supply Power supply for Clock Recovery PLL, 4.75 - 5.25 Volts. 15 TCLK1 . Transmit Clock 1/2, samples TPOS/TNEG data on falling 14 TCLK2 YO | Transmit clocks edge. 1 RNEG1 Receive channel 1, corresponds to -ve in bipolar signal. 3 RNEG2 . Receive channel 2, corresponds to -ve in bipolar signal. 5 RNEG3 0 Receive Data Neg Receive channel 3, corresponds to -ve in bipolar signal. 7 RNEG4 Receive channel 4, corresponds to -ve in bipolar signal. 78 RCLK1 0 Receive clock Receive Clock, RPOS/RNEG data is valid on edge 77 | RCLK2 CCENE COCKS | selected by input "RESEL". 48 XTY _ System Clock Connect fundamental parallel resonance crystal with 47 XTO Crystal appropriate padding capacitor to GND. Transmit Transmit maintenance clock. Samples TmD on falling 13 TmCLK | I/O . edge when device is not in valid frame mode. See input maintenance CLK |, ' FRAME. Receive Ed When RESEL = 1, RPOS/RNEG and RmD data is valid 40 RESEL |I Sek . oe on the rising edge of RCLK/RmCLK. When RESEL = 0, ee the data is valid on the falling edge of RCLK/RmCLK. 16 TmD1 Transmit NRZ maintenance channel. TmD is sampkd on falling 7 TmD? I maintenance Data edge of TmCLK clock when frame mode is valid else data is sampled on falling edge of TCLK . NRZ maintenance channel. Data is set-up with repect to 80 RmD1 O Receive RCLK clock when frame mode is valid else data is set- 79 RmD2 maintenance Data | up with respect to RmCLK. Data is valid on the clock edge selected by RESEL. Data Carrier When DCD = 1, then the communicating modems have 64 DCD O . . Detect synchronized, and are communicating. Will initialise the device when PORB= 0. PORB is normally connected to an RC circuit so that a POR is 66 PORB I Power-On Reset automatically invoked on power-up. PORB= 1 for normal operation. ACS405_ Issue 4.0 December 1998. 18Pin Description ACS405B part 3 Pin |Sym |IO |Name Description 46 DMI . . DM1,DM2,DM3 select the Diagnostic Modes such as 45 DM2 I Diagnostic Modes local loopback and te-loopback AA DM3 local-loopback and remote-loopback. If errors are detected in the 8B10B coding rules ERRL 68 ERRL |O Error Latch will be forced high.. ERRL will be reset low if the device is forced out of synchronisation e.g. PORB = 0. ERRC will go high coincident with each error detected in 69 ERRC |O Error count the 8B10 coding rules. Errors may be accumulated by means of an external electronic counter. 73 DR1 72 DR2 The DR(14) input select the Data Rates and number of 71 DR3 I Data Rate Select channels. See section headed Data Rate Selection. 70 DR4 When CKC = 0, TCLK 1/2 is configured as an output. 95 fCKE JT | Clock Sekect When CKC = 1, TCLK1/2 is configured as an input When CKM = 0, TmCLK1/2 is configured as an output. 36 |CKM |T | Clock Select When CKM = 1, TmCLK1/2 is configured as an input SETB = 0, to adjust the LASER output power. 42 |SETB {I LASER set-up SETB = 1, in operational mode. . When LOS = 1, receive data is unreliable. 65 LOS 0 LOSS of Signal When LOS = 0, receive data is reliable. 43 Frame {I Frame Mode When Frame = '1' , Support channels are configured in frame mode. When Fhold = '0', the device is configured for asymmetrical data communication.The most common 41 Fhold 1 Format Hold setting for this input is Fhold = '1' supporting symmetrical communications. 60 POLI I Polarj Defines the polarity of input signal TROS/TNEG. 59 |POL2 olanity NRZ,HDB3, B8SZ or AMI. When SCEXT = '1' , then the system clock will be the 57 SCEXT |I Select Clock external clock applied to input 'ECLK'. When SCEXT = External 'O' , then the system clock will be the crystal clock generated at XTI/XTO. External system clock input. Only valid when SEXT = 'T. 30 FECL JT | External Clock | Gicck must have at east 40% High and 40% Low time. 50) IREE II Current reference A 51 KQ 1% resistor should be placed between IREF and GND. This determines the slicing level for input Rxdat+. Should 53 Redat- II Rxdat -Ve input be set at DVDD / 2. On the next generation of devices this is likely to be derived from the ACS405A device . Backward compatibilty will be maintained. ACS405_ Issue 4.0 December 1998. 19Pin Description ACS405A part 1 Pin |Sym |IO|Name Description 3 RSET2 | - PLL frequency set | Tie to DVDD at all times. LASER = 1, when interfacing to a LASER. 6 LASER 1 LASER LASER = 0, when interfacing to a LED. . . Internally sets the bias current for the analogue cells. 7 RSET : Receive Bias Set Connect a 10nF capacitor between RSET and GND. . When LASRX = 1, LAP and LAN are connected to the 8 LASRX I LAP/LAN Receive receiver. Required for LED ping-pong applications. 13 PINRX |I PINP/PINN When PINRX = 1, PINP and PINN are connected to the Receive receiver. 15 RxMN_ |O Receive Monitor Receive power monitor. 16 RxVDD |- Receive Power Power supply, 4.75 - 5.25 Volts. Supply 17 RxGND | - Ground Power supply. 18 COEF1 |_ Compensation Differential offset compensation capacitor. 19 COEF2 Capacitor Connect a InF capacitor between pins 18,19. 24 PINP PIN Anode . . 4. . 95 PINN - PIN Cathode Connections for pin-diode receiver. 26 PMN - LASER monpin Connection to Anode of LASER monitor-pin. 27 TxVDD |- Transmit Power Power supply, 4.75 - 5.25 Volts. Supply 28 LAP LASER Anode . 29 LAN - LASER Cathode Connections to LASER OR LED. 30,41 | TXGND |- Ground Power supply. When using LEDs: Place a 10 nF capacitor between CTX1 and GND. 31 CTX1 ; Driver Smoothing Place a 10 nF capacitor between CTX2 and GND. 35 CTX2 Capacitor When using LASERs: Place a 10 nF capacitor between CTX1 and GND. Connect CTX2 directly to GND. Transmit Power . . 36 TxMN_ | - Monitor Monitors transmit output power. 37 TxFLG 10 Transmit Power When TxFLG = 1, transmit power > TxMN threshold. Flag When TxFLG = 0, transmit power < TXMN threshold. 14 RELG 10 Receive Power When RxFLG = 1, receiver power > RxMN threshold. Flag When RxFLG = 0, receive power < RxMN threshold. 38 TSET ; Transmit Power A 40 Kohm resistor placed between TSET and GND will set Setting the appropriate transmit power level. ) pvpp |- Rxdat Slicing level | Provides the appropriate slicing level for Rxdat+. voltage Use resistor arrangement seen in fig 5 of this specification. ACS405_ Issue 4.0 December 1998. 20PIN Description of interface signals between ACS405A and ACS405B. Pin|Sym |IO|Name Description 32 O . Transmit window active (ACS405B). 39 [ENTX |, | Enable Transmit | Enable transmit (ACS405A). 31 O . Receive Window active (ACS405B). g |ENRXB {| | Enable Receive | Enable receive (ACS405A). 0 ENCOERB | 1 ours DE Enables the DC offset compensation - ENCOFB is . normally connected to ENRXB (ACS405A). Compensation 28 Txdat O Transmit Burst Transmit burst data out (ACS405B). 40 I Data. Transmit burst data in (ACS405A). 5 0 Receive Burst Positive Differential receive burst data out 59 Rxdat+ I Data (ACS405A). Positive Differential receive burst data in (ACS405B). ACS405_ Issue 4.0 December 1998. 211 Ic Ic 44 2 GND RES 43 3 RSET2 DVDD 42 4 GND A GND 41 5 Rxdat+ = & 5 & g 8 x ~ 2 Txdat 40 6 LASER 1 330] ENTX 39 7 RSET TSET 38 8 LASRX 2 32H TxFLG 37 9 ENRXB 3 310 TxMN 36 10 RES 4 300 CTX2 35 11 RES 5 ACAPELLA 290 RES 34 12 RES 6 ACS405A 280 RES 33 13 PINRX RES 32 14 RxELG : 1-Fiber Modem as CTXI 31 15 RxMN TxGND 30 16 RxVDD 9 25) LAN 29 17 RxGND 10 240 LAP 28 18 COEF1 11 230 TxVDD 27 19 COEF2 wD PMN 26 20 ENCOFB PINN 25 21 RES PINP 24 22 RES RES 23 RES = Reserved, IC = Internally Connected Figure 6. Top view of 44 pin TQFP package 1 RNEG1 RmD1_ 80 2 RPOS1 RmD2 79 3. RNEG2 RCLK1 78 4 RPOS2 RCLK2 77 5 RNEG3 RmCLK 76 6 RPOS3 VD+ 75 7 RNEG4 GND 74 8 RPOS4 DR1 73 9 VD+ 1 60 O DR2 72 10 VD+ 2 so DR3 71 11 GND 3 53 DR4 70 12 GND A ERRC 69 13 TmCLK 4 57 ERRL 68 14 TCLK2 5 56H Ic 67 15 TCLK1 6 550 PORB 66 16 TmD1 7 54 LOSS 65 17 Tn? ACAPELLA s3 ff = bebo 18 TNEG1 + 19 TPOS1 52H GND 62 20 TNEG2 10 ACS405B 51 GND 61 21 TPOS2 11 50 POL1 60 22 TNEG3 12 : 49 0 POL2 59 33 TPOS3 3 1-Fiber Modem as H Ic 58 24 TNEG4 H SCEXT 57 25 TPOS4 Ic 56 26 VD+ U GND 55 27 GND H GND 54 28 Txdat O Rxdat- 53 29 GND 0 Rxdatt 52 30 ECLK H GND 51 31 ENRXB IREF 50 32 ENTX H VAt 49 33 IC XIN 48 34 IC XOUT 47 35 CKC DM1 46 36 CKM DM2 45 37 GND : : DM3 44 38 VDE Figure 7. Top view of 80 pin TQFP package FRAME 43 io NEEL RES = Reserved, IC = Internally Connected OD 4h 22 ACS405_ Issue 4.0 December 1998.a ] hil TQFP44 7.00 0.80 12.00 max 1.60 | 0.15 | 1.45 0.45 |0.75 | 7 0.10 min 0.05 | 1.35 0.22 | 0.45 | 0 TQFP80 14.00 0.65 16.00 max 1.60 | 0.15 | 1.45 0.38 | 0.75 | 7 0.10 Package information for the TQFP 44 and 80 pin packages ACS405_ Issue 4.0 December 1998. 23ACS405 ACS405 TUN. TEN NUN TPOS1/TNEG1 RPOS1/RNEG1 TPOS2/TNEG2 RPOS2/RNEG2 TPOS3/TNEG3 RPOS3/RNEG3 TPOS4/RNEG4 RPOS4/RNEG4 TCLK1 RCLK1 TCLK2 RCLK2 TmD1 RmD1 TmD2 RmD2 TmCLK RmCLK RPOS1/RNEG1 TPOS1/TNEG1 RPOS2/RNEG2 TPOS3/TNEG3 RPOS3/RNEG3 TPOS4/RNEG4 RPOS4/RNEG4 TPOS4/TNEG4 RCLK1 TCLK1 RCLK2 TCLK2 RmD1 TmD1 RmD2 TmD2 RmCLK TmCLK NIU NI NIU Figure 8. Shows the relationship between data channels Absolute Maximum Ratings Power supply VD+, VA+, RxVDD, TxVDD VDD -0.3 6.0 Vv Input Voltage Vin GND - 03 VDD + 0.3 Vv (non-supply pins) Input current (except LAN, LAP, PINN, PINP, | Iin - 10.0 mA PMN) Input current ( LAN, LAP, PINN, PINP, lina - 1.0 mA PMN) Storage temperature Tstor -50 160 C Operating Conditions Power supply VD+,VA+, TxVDD, RxVDD VDD 5.25 Ambent temperature range TA 85 C Static Digital Input Conditions (for specified operating conditions) For input pins: TCLK1/2 (as input), TmCLK (as input), PORB. Vin High Vih 2.0 - - Vv Vin Low Vil - - 0.8 Vv Input current Tin - - 10 uA 24 ACS405_ Issue 4.0 December 1998.Static Digital Input Conditions (for specified operating conditions) For input pins: Rxdat+(ACS405B), Rxdat- (ACS405B) Vin High . (Rxdat+) - (Rxdat-) Vihdif 100 - 200 mV Vin Low . (Rxdat+) - (Rxdat-) Vildif -100 - -200 mV Input current Tin - - 10 uA Static Digital Input Conditions (for specified operating conditions) For TTL logic level input pins: TPOS1/2/3/4, TNEG1/2/3/4, TmD1/TmD2. Vin High Vih 2.0 - - V Vin Low Vil - - 0.8 V Pull-up resistor PU 18K - 55K Q Input current Tin - - 277 uA Static Digital Input Conditions (for specified operating conditions) For CMOS logic level input pins: CKM, CKC,RESEL, DM1/2/3, DR1/2/3/4, POL1/2, SETB, FRAME, FHOLD, SCEXT, ECLK, ENTX(ACS405A), Txdat (ACS405A), LASER, LASRX, PINRX, ENRXB(ACS405A), ENCOFB (ACS405A) . Vin High Vih 65% VDD - - Vv Vin Low Vil - - 35% VDD Vv Pull-up resistor PU 75K 125K 175K Q Input current Tin - - 100 uA Static Digital Output Conditions (for specified operating conditions) For output pins: RPOS1/2/3/4, RNEG1/2/3/4, RCLK1/2, RmCLK, RmD1/2, DCD, ERRL, ERRC, LOS, ENRXB (ACS405B), ENTX(ACS405B), Txdat (ACS405B), RxFLG(ACS405A), Rxdat+(ACS405A), TXFLG (ACS405A), TCLK1/2 (output), TmCLK (output). Vout Low lol = 4mA Voh 0 - 0.5 Vv Vout High Joh = 4mA Vol VDD-0.5 - VDD Vv Max load capacitance Cl - - 50 pr ACS405_ Issue 4.0 December 1998. 25Dynamic Characteristics continued (for specified operating conditions) Crystal frequency XTYXTO XTAL 16 32.768 35 MHz Extemal System CLK (ECLK) I High or Low time tclp 40 " 60 TPOS/TNEG data rate fclf 0 - XTAL/4 bps RCLK and TCLK duty cyck twh I (with TCLK= output) twl 40 50 60 Frequency deviation at TCLK from selected value (with TCLK = | Fd -250 - 250 ppm input) TPOS/TNEG to TCLK set-up tsut 20) _ _ ns time TPOS/TNEG to TCLK hold time | tht 10 - - ns BPOSIRNES tO RELI set-up sur O.4*I/RCLK | 0.5*1/RCLK | 0.6*1/RCLK | 9 RPOS/RNEG to RCLK hold time | thr 0.4*1/RCLK | 0.5*1I/RCLK | 0.6*1/RCLK | S RmCLK and TmCLK duty cycle | twh 30 50) 70 % (with TmCLK= output) twl When frame = '0'; TmD1/2 data rate When frame = '1' ; fclmf 0 - 64K bps special data transmission rules apply (see support channels). Frequency deviation at TmCLK from selected value (with TmCLK | Fd -400 - 400 ppm = input) TmD1/2 to TmCLK set-up time tsut 20 - - ns TmD1/2 to TmCLK hold time tht 10 - - ns RmD1/2 to RmCLK set-up time tsur 0.4*1/RmCLK | 0.5*1/RmCLK | 0.6*1/RmCLK | S RmD1/2 to RmCLK hold time thr 0.4*1/RmCLK | 0.5*1/RmCLK | 0.6*1/RmCLK | Digital output - fall time tf 10 ns 50 pF load Digital output- rise time tr 10 ns 50 pF load Power consumption with LASER/LED = 50 mA in operational mode. PC mW ACS405A - - 150 ACS405B - - 125 ACS405_ Issue 4.0 December 1998. 26Matching Characteristics (for specified operating conditions) Crystal tolerance using fundamenal Ct 50) _ 50) ppm paralkl resonance crystals Minimum amplifier input current LED: Irec - - 1500 nA LASER: 1000 Maximum amplifier input current I uA (see Acapella if this is restrictive) 400 " " Rtset placed between TSET and GND Rtset 1K - 40K Maximum Monitor PIN current _| Ipin 2.0 mA LASER Current (LASER = 1) TxMN = 0.5 mA Tlaser 45 50 55 mA Rtset < 40 Kohms bs Current limit (LASER = Tlser 100 _ _ mA LED Current (LASER = 0) Rtset = 1Kohms Tled 75 100 125 mA Rtset = 40K ohms 2.0 2.5 3.0 LED as receiver (ping-pong) vt _ _ 14 Vv reverse bias LED as receiver (ping-pong) Cled _ _ 50) pF capacitance ( vr = 0) LED as receiver (ping-pong) nA leakage ( vr = 1.4) Cleak " " 150 PIN Diode receiver Vib _ _ 4 Vv reverse bias PIN Diode leakage current nA Vib = 4.0V Pleak " " 100 DVDD Input Voltage DVDDV 3.3 3.6 Vv DVDD input current DVDDI - - 500 uA IREF resistor RIFREF 49.5 51 51.5 KQ 27 ACS405_ Issue 4.0 December 1998.\. ) Acapella Ltd. UK Tel. 01703 769 008 Delta House UK Fax. 01703 768 612 Chilworth Research Centre Southampton S016 7NS Intn'l. Tel. +44 (0)1703 769 008 United Kingdom Intn'l. Fax. +44 (0)1703 768 612 Email: sales@acapella.co.uk Web: www.acapella.co.uk Acapella - a wholly owned subsidiary of In the interest of further product development Acapella reserve the right to change this specification without further notice. Copyright, Acapella Ltd, 1998 ACS405_ Issue 4.0 December 1998. 28