EBE10RD4AGFA-5C-E - Elpida Memory, Inc.

Document No. E0795E20 (Ver. 2.0)

Date Published October 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2005

DATA SHEET

1GB Registered DDR2 SDRAM DIMM

EBE10RD4AGFA (128M words × 72 bits, 1 Rank)

Description

The EBE10RD4AGFA is a 128M words × 72 bits, 1

rank DDR2 SDRAM Module, mounting 18 pieces of

DDR2 SDRAM sealed in FBGA (µBGA) package.

Read and write operations are performed at the cross

points of the CK and the /CK. This high-speed data

transfer is realized by the 4bits prefetch-pipelined

architecture. Data strobe (DQS and /DQS) both for

read and write are available f or high spe ed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. This module provides high density

mounting without utilizing surface mount technology.

Decoupling capacitors ar e mounted beside each FBGA

(µBGA) on the module board.

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

Features

• 240-pin socket type dual in l in e memory module

(DIMM)

 PCB height: 30.0mm

 Lead pitch: 1.0mm

 Lead-free (RoHS compliant)

• Power supply: VDD = 1.8V ± 0.1V

• Data rate: 667Mbps/533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs; center

aligned with dat a for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each p ositive CK e dge; data

referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

 7.8µs at 0°C ≤ TC ≤ +85°C

 3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 2 pieces of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Ordering Information

Part number Data rate

Mbps (max.)

Component

JEDEC speed bin*1

(CL-tRCD-tRP)

Package Contact

pad

Mounted devices

EBE10RD4AGFA-6E-E 667 DDR2-667 (5-5-5) EDE5104AGSE-6E-E

EBE10RD4AGFA-5C-E 533 DDR2-533 (4-4-4) EDE5104AGSE-6E-E

EDE5104AGSE-5C-E

EBE10RD4AGFA-4A-E 400 DDR2-400 (3-3-3)

240-pin DIMM

(lead-free) Gold EDE5104AGSE-6E-E

EDE5104AGSE-5C-E

EDE5104AGSE-4A-E

Note: 1. Module /CAS latency = component CL + 1

Pin Configurations

1 pin Front side

Back side

64 pin65 pin 120 pin

121 pin 184 pin 185 pin 240 pin

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 61 A4 121 VSS 181 VDD

2 VSS 62 VDD 122 DQ4 182 A3

3 DQ0 63 A2 123 DQ5 183 A1

4 DQ1 64 VDD 124 VSS 184 VDD

5 VSS 65 VSS 125 DQS9 185 CK0

6 /DQS0 66 VSS 126 /DQS9 186 /CK0

7 DQS0 67 VDD 127 VSS 187 VDD

8 VSS 68 NC/Par_In 128 DQ6 188 A0

9 DQ2 69 VDD 129 DQ7 189 VDD

10 DQ3 70 A10 130 VSS 190 BA1

11 VSS 71 BA0 131 DQ12 191 VDD

12 DQ8 72 VDD 132 DQ13 192 /RAS

13 DQ9 73 /WE 133 VSS 193 /CS0

14 VSS 74 /CAS 134 DQS10 194 VDD

15 /DQS1 75 VDD 135 /DQS10 195 ODT0

16 DQS1 76 NC 136 VSS 196 A13

17 VSS 77 NC 137 NC 197 VDD

18 /RESET 78 VDD 138 NC 198 VSS

19 NC 79 VSS 139 VSS 199 DQ36

20 VSS 80 DQ32 140 DQ14 200 DQ37

21 DQ10 81 DQ33 141 DQ15 201 VSS

22 DQ11 82 VSS 142 VSS 202 DQS13

23 VSS 83 /DQS4 143 DQ20 203 /DQS13

24 DQ16 84 DQS4 144 DQ21 204 VSS

25 DQ17 85 VSS 145 VSS 205 DQ38

26 VSS 86 DQ34 146 DQS11 206 DQ39

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

27 /DQS2 87 DQ35 147 /DQS11 207 VSS

28 DQS2 88 VSS 148 VSS 208 DQ44

29 VSS 89 DQ40 149 DQ22 209 DQ45

30 DQ18 90 DQ41 150 DQ23 210 VSS

31 DQ19 91 VSS 151 VSS 211 DQS14

32 VSS 92 /DQS5 152 DQ28 212 /DQS14

33 DQ24 93 DQS5 153 DQ29 213 VSS

34 DQ25 94 VSS 154 VSS 214 DQ46

35 VSS 95 DQ42 155 DQS12 215 DQ47

36 /DQS3 96 DQ43 156 /DQS12 216 VSS

37 DQS3 97 VSS 157 VSS 217 DQ52

38 VSS 98 DQ48 158 DQ30 218 DQ53

39 DQ26 99 DQ49 159 DQ31 219 VSS

40 DQ27 100 VSS 160 VSS 220 NC

41 VSS 101 SA2 161 CB4 221 NC

42 CB0 102 NC 162 CB5 222 VSS

43 CB1 103 VSS 163 VSS 223 DQS15

44 VSS 104 /DQS6 164 DQS17 224 /DQS15

45 /DQS8 105 DQS6 165 /DQS17 225 VSS

46 DQS8 106 VSS 166 VSS 226 DQ54

47 VSS 107 DQ50 167 CB6 227 DQ55

48 CB2 108 DQ51 168 CB7 228 VSS

49 CB3 109 VSS 169 VSS 229 DQ60

50 VSS 110 DQ56 170 VDD 230 DQ61

51 VDD 111 DQ57 171 NC 231 VSS

52 CKE0 112 VSS 172 VDD 232 DQS16

53 VDD 113 /DQS7 173 NC 233 /DQS16

54 NC 114 DQS7 174 NC 234 VSS

55 NC/Err_Out 115 VSS 175 VDD 235 DQ62

56 VDD 116 DQ58 176 A12 236 DQ63

57 A11 117 DQ59 177 A9 237 VSS

58 A7 118 VSS 178 VDD 238 VDDSPD

59 VDD 119 SDA 179 A8 239 SA0

60 A5 120 SCL 180 A6 240 SA1

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Pin Description

Pin name Function

A0 to A13 Address input

Row address A0 to A13

Column address A0 to A9, A11

A10 (AP) Auto precharge

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

CB0 to CB7 Check bit (Data input/output)

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/CS0 Chip select

CKE0 Clock enable

CK0 Clock input

/CK0 Differential clock input

DQS0 to DQS17, /DQS0 to /DQS17 Input and output data strobe

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VDD Power for internal circuit

VDDSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

ODT0 ODT control

/RESET Reset pin (forces register and PLL inputs low) *1

Par_In*2 Parity bit for the address and control bus

Err_Out*2 Parity error found on the address and control bus

NC No connection

Note: 1. Reset pin is connected to both OE of PLL and reset to register.

2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and

command parity.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Serial PD Matrix*1

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0 Number of bytes utilized by module

manufacturer 1 0 0 0 0 0 0 0 80H 128 bytes

1 Total number of bytes in serial PD

device 0 0 0 0 1 0 0 0 08H 256 bytes

2 Memory type 0 0 0 0 1 0 0 0 08H DDR2 SDRAM

3 Number of row address 0 0 0 0 1 1 1 0 0EH 14

4 Number of column address 0 0 0 0 1 0 1 1 0BH 11

5 Number of DIMM ranks 0 1 1 0 0 0 0 0 60H 1

6 Module data width 0 1 0 0 1 0 0 0 48H 72

7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H SSTL 1.8V

9 DDR SDRAM cycle time, CL = 5

-6E 0 0 1 1 0 0 0 0 30H 3.0ns*1

-5C 0 0 1 1 1 1 0 1 3DH 3.75ns*1

-4A 0 1 0 1 0 0 0 0 50H 5.0ns*1

10 SDRAM access from clock (tAC)

-6E 0 1 0 0 0 1 0 1 45H 0.45ns*1

-5C 0 1 0 1 0 0 0 0 50H 0.5ns*1

-4A 0 1 1 0 0 0 0 0 60H 0.6ns*1

11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs

13 Primary SDRAM width 0 0 0 0 0 1 0 0 04H × 4

14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H × 4

15 Reserved 0 0 0 0 0 0 0 0 00H 0

16 SDRAM device attributes:

Burst length supported 0 0 0 0 1 1 0 0 0CH 4,8

17 SDRAM device attributes: Number of

banks on SDRAM device 0 0 0 0 0 1 0 0 04H 4

18 SDRAM device attributes:

/CAS latency 0 0 1 1 1 0 0 0 38H 3, 4, 5

19 DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H 4.00mm max.

20 DIMM type information 0 0 0 0 0 0 0 1 01H Registered

21 SDRAM module attributes 0 0 0 0 0 0 0 0 00H Normal

22 SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H Weak Driver 50Ω

ODT Support

23 Minimum clock cycle time at CL = 4

-6E, -5C 0 0 1 1 1 1 0 1 3DH 3.75ns*1

-4A 0 1 0 1 0 0 0 0 50H 5.0ns*1

24 Maximum data access time (tAC) from

clock at CL = 4

-6E, -5C 0 1 0 1 0 0 0 0 50H 0.5ns*1

-4A 0 1 1 0 0 0 0 0 60H 0.6ns*1

25 Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H 5.0ns*1

26 Maximum data access time (tAC) from

clock at CL = 3 0 1 1 0 0 0 0 0 60H 0.6ns*1

27 Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH 15ns

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

28 Minimum row active to row active delay

(tRRD) 0 0 0 1 1 1 1 0 1EH 7.5ns

29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH 15ns

30 Minimum active to precharge time

(tRAS)

-6E, -5C 0 0 1 0 1 1 0 1 2DH 45ns

-4A 0 0 1 0 1 0 0 0 28H 40ns

31 Module rank density 0 0 0 0 0 0 0 1 01H 1GB

32 Address and command setup time

before clock (tIS)

-6E 0 0 1 0 0 0 0 0 20H 0.20ns*1

-5C 0 0 1 0 0 1 0 1 25H 0.25ns*1

-4A 0 0 1 1 0 1 0 1 35H 0.35ns*1

33 Address and command hold time after

clock (tIH)

-6E 0 0 1 0 1 0 0 0 28H 0.28ns*1

-5C 0 0 1 1 1 0 0 0 38H 0.38ns*1

-4A 0 1 0 0 1 0 0 0 48H 0.48ns*1

34 Data input setup time before clock

(tDS)

-6E, -5C 0 0 0 1 0 0 0 0 10H 0.10ns*1

-4A 0 0 0 1 0 1 0 1 15H 0.15ns*1

35 Data input hold time after clock (tDH)

-6E 0 0 0 1 1 0 0 0 18H 0.18ns*1

-5C 0 0 1 0 0 0 1 1 23H 0.23ns*1

-4A 0 0 1 0 1 0 0 0 28H 0.28ns*1

36 Write recovery time (tWR) 0 0 1 1 1 1 0 0 3CH 15ns*1

37 Internal write to read command delay

(tWTR)

-6E, -5C 0 0 0 1 1 1 1 0 1EH 7.5ns*1

-4A 0 0 1 0 1 0 0 0 28H 10ns*1

38 Internal read to precharge command

delay (tRTP) 0 0 0 1 1 1 1 0 1EH 7.5ns*1

39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H TBD

40 Extension of Byte 41 and 42 0 0 0 0 0 0 0 0 00H Undefined

41 Active command period (tRC)

-6E, -5C 0 0 1 1 1 1 0 0 3CH 60ns*1

-4A 0 0 1 1 0 1 1 1 37H 55ns*1

42 Auto refresh to active/

Auto refresh command cycle (tRFC) 0 1 1 0 1 0 0 1 69H 105ns*1

43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H 8ns*1

44 Dout to DQS skew

-6E 0 0 0 1 1 0 0 0 18H 0.24ns*1

-5C 0 0 0 1 1 1 1 0 1EH 0.30ns*1

-4A 0 0 1 0 0 0 1 1 23H 0.35ns*1

45 Data hold skew (tQHS)

-6E 0 0 1 0 0 0 1 0 22H 0.34ns*1

-5C 0 0 1 0 1 0 0 0 28H 0.40ns*1

-4A 0 0 1 0 1 1 0 1 2DH 0.45ns*1

46 PLL relock time 0 0 0 0 1 1 1 1 0FH 15µs

47 to 61 0 0 0 0 0 0 0 0 00H

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

62 SPD Revision 0 0 0 1 0 0 1 0 12H Rev. 1.2

63 Checksum for bytes 0 to 62

-6E 0 0 0 0 1 1 0 1 0DH

-5C 0 1 0 1 0 0 0 1 51H

-4A 1 1 0 0 1 0 1 1 CBH

64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation

code

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location × × × × × × × × ×× (ASCII-8bit

code)

73 Module part number 0 1 0 0 0 1 0 1 45H E

74 Module part number 0 1 0 0 0 0 1 0 42H B

75 Module part number 0 1 0 0 0 1 0 1 45H E

76 Module part number 0 0 1 1 0 0 0 1 31H 1

77 Module part number 0 0 1 1 0 0 0 0 30H 0

78 Module part number 0 1 0 1 0 0 1 0 52H R

79 Module part number 0 1 0 0 0 1 0 0 44H D

80 Module part number 0 0 1 1 0 1 0 0 34H 4

81 Module part number 0 1 0 0 0 0 0 1 41H A

82 Module part number 0 1 0 0 0 1 1 1 47H G

83 Module part number 0 1 0 0 0 1 1 0 46H F

84 Module part number 0 1 0 0 0 0 0 1 41H A

85 Module part number 0 0 1 0 1 1 0 1 2DH —

86 Module part number

-6E 0 0 1 1 0 1 1 0 36H 6

-5C 0 0 1 1 0 1 0 1 35H 5

-4A 0 0 1 1 0 1 0 0 34H 4

87 Module part number

-6E 0 1 0 0 0 1 0 1 45H E

-5C 0 1 0 0 0 0 1 1 43H C

-4A 0 1 0 0 0 0 0 1 41H A

88 Module part number 0 0 1 0 1 1 0 1 2DH —

89 Module part number 0 1 0 0 0 1 0 1 45H E

90 Module part number 0 0 1 0 0 0 0 0 20H (Space)

91 Revision code 0 0 1 1 0 0 0 0 30H Initial

92 Revision code 0 0 1 0 0 0 0 0 20H (Space)

93 Manufacturing date × × × × × × × × ×× Year code

(BCD)

94 Manufacturing date × × × × × × × × ×× Week code

(BCD)

95 to 98 Module serial number

99 to 127 Manufacture specific data

Note: 1. These specifications are defined based on compo nent specification, not module.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Block Diagram

DQSDM

DQ0 to DQ3 4

DQS0 R

/CS

/RCS0

VSS

DQ8 to DQ11 4

DQS1

/CS*2

BA0 to BA1

A0 to A13

/RAS

/CAS

CKE0

/WE

ODT0

/RCS0 -> /CS: SDRAMs D0 to D17

RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17

RA0 to RA13 -> A0 to A13: SDRAMs D0 to D17

/RRAS -> /RAS: SDRAMs D0 to D17

/RCAS -> /CAS: SDRAMs D0 to D17

RCKE0 -> CKE: SDRAMs D0 to D17

/RWE -> /WE: SDRAMs D0 to D17

RODT0 -> ODT0: SDRAMs D0 to D17

/PCK7*

/RESET*

/DQS0

/DQS

DQSDM /CS

/DQS

/DQS1

DQ16 to DQ19 4

DQS2

DQSDM /CS

/DQS

/DQS2

DQ24 to DQ27 4

DQS3

DQS

DM /CS

/DQS

/DQS3

DQ32 to DQ35 4

DQS4

DQSDM /CS

/DQS

/DQS4

DQ40 to DQ43 4

DQS5

DQSDM /CS

/DQS

/DQS5

DQ48 to DQ51 4

DQS6

DQS

DM /CS

/DQS

/DQS6

DQ56 to DQ59 4

DQS7

DQSDM /CS

/DQS

/DQS7

CB0 to CB3 4

DQS8

DQ0

to DQ3

DQSDM /CS

/DQS

/DQS8

DQSDM

DQ4 to /DQ7 4

DQS9

/CS

DQ12 to DQ15 4R

/DQS9

/DQS

DQSDM /CS

D10

/DQS

DQ20 to DQ23 4R

DQSDM /CS

D11

/DQS

DQ28 to DQ31 4R

DQS

DM /CS

D12

/DQS

DQ36 to DQ39 4R

DQSDM /CS

D13

/DQS

DQ44 to DQ47 4R

DQSDM /CS

D14

/DQS

DQ52 to DQ55 4R

DQS

DM /CS

D15

/DQS

DQ60 to DQ63 4R

DQSDM /CS

D16

/DQS

CB4 to CB7 4R

DQSDM /CS

D17

/DQS

DQS10

/DQS10

DQS11

/DQS11

DQS12

/DQS12

DQS13

/DQS13

DQS14

/DQS14

DQS15

/DQS15

DQS16

/DQS16

DQS17

/DQS17

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

DQ0

to DQ3

/RST

PCK7*

Notes:

1. DQ wring may be changed within a nibble.

2. /CS connects to D/CS of register and /CSR of register2.

/CSR of register1 and D/CS of register2 connects to VDD.

3. /RESET, PCK7 and /PCK7 connect to both registers.

Other signals to one of two registers.

CK0

/CK0

/RESET

PCK0 to PCK6, PCK8, PCK9 -> CK: SDRAMs D0 to D17

/PCK0 to /PCK6, /PCK8, /PCK9 -> /CK: SDRAMs D0 to D17

PCK7 -> CK: register

/PCK7 -> /CK: register

D0 to D17: 512M bits DDR2 SDRAM

U0: 2k bits EEPROM

: 22Ω

PLL: CUA877

Serial PD

SDA

A0 A1 A2

SA0SA1SA2

SCL SCL

SDA

Serial PD

D0 to D17

VDDSPD

VSS

VREF

VDD

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Differential Clock Net Wiring (C K0, /CK0)

120Ω

0ns (nominal)

120Ω

CK0

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the

input pin of the PLL as possible.

/CK0

SDRAM

PLL

Feedback in

OUT1

OUT'N'

Feedback out

120Ω

SDRAM

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Electrical Specifications

• All voltages are referenced to VSS (GND).

Absolute Maximum Ratings

Parameter Symbol Value Unit Note

Voltage on any pin relative to VSS VT –0.5 to +2.3 V 1

Supply voltage relative to VSS VDD –0.5 to +2.3 V

Short circuit output current IOS 50 mA 1

Power dissipation PD 18 W

Operating case temperature TC 0 to +95 °C 1, 2

Storage temperature Tstg –55 to +100 °C 1

Note: 1. DDR2 SDRAM component specificati on.

2. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in

frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of

EMRS (2) bit A7 is required.

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

DC Operating Conditions (TC = 0°C to +85°C) (DDR2 SDRAM Component Specification)

Parameter Symbol min. typ. max. Unit Notes

Supply voltage VDD, VDDQ 1.7 1.8 1.9 V 4

VSS 0 0 0 V

VDDSPD 1.7 — 3.6 V

Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 2

Termination voltage VTT VREF − 0.04 VREF VREF + 0.04 V 3

DC input logic high VIH (DC) VREF + 0.125  VDDQ + 0.3 V

DC input low VIL (DC) −0.3  VREF – 0.125 V

AC input logic high

-6E VIH (AC) VREF + 0.200   V

-5C, -4A VIH (AC) VREF + 0.250   V

AC input low

-6E VIL (AC)   VREF – 0.200 V

-5C, -4A VIL (AC)   VREF − 0.250 V

Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is e xpected to b e about 0 .5 × VDDQ of the transm itting devic e and V R EF are e xpected

to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ must be equal to VDD.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)

Parameter Symbol Grade max. Unit Test condition

Operating current

(ACT-PRE) IDD0 -6E

-5C

-4A

2570

2440

2120 mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE) IDD1 -6E

-5C

-4A

2920

2760

2430 mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-down

standby current IDD2P -6E

-5C

-4A

750

700

620 mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge quiet standby

current IDD2Q -6E

-5C

-4A

1020

970

840 mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Idle standby current IDD2N -6E

-5C

-4A

1200

1060

930 mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F -6E

-5C

-4A

1290

1240

1110 mA Fast PDN Exit

MRS(12) = 0

Active power-down standby

current

IDD3P-S -6E

-5C

-4A

1020

970

840 mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and

address bus inputs are

STABLE;

Data bus inputs are

FLOATING

Slow PDN Exit

MRS(12) = 1

Active standby current IDD3N -6E

-5C

-4A

1850

1720

1580 mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating) IDD4R -6E

-5C

-4A

4270

3660

3060 mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP

(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write operating) IDD4W -6E

-5C

-4A

4090

3660

3060 mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Parameter Symbol Grade max. Unit Test condition

Auto-refresh current IDD5 -6E

-5C

-4A

5440

5030

4630 mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current IDD6 150 mA

Self Refresh Mode;

CK and /CK at 0V;

CKE ≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving) IDD7 -6E

-5C

-4A

6380

6250

5770 mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),

tRCD = 1 × tCK (IDD);

CKE is H, CS is H between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly init ialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD

values must be met with all combinations of EMRS bits 10 and 1 1.

5. Definitions for IDD

L is defined as VIN ≤ VIL (AC) (max.)

H is defined as VIN ≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-667 DDR2-533 DDR2-400

Parameter 5-5-5 4-4-4 3-3-3 Unit

CL(IDD) 5 4 3 tCK

tRCD(IDD) 15 15 15 ns

tRC(IDD) 60 60 55 ns

tRRD(IDD) 7.5 7.5 7.5 ns

tCK(IDD) 3 3.75 5 ns

tRAS(min.)(IDD) 45 45 40 ns

tRAS(max.)(IDD) 70000 70000 70000 ns

tRP(IDD) 15 15 15 ns

tRFC(IDD) 105 105 105 ns

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter Symbol Value Unit Notes

Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS

Output leakage current ILO 5 µA VDDQ ≥ VOUT ≥ VSS

Minimum required output pull-up under AC

test load VOH VTT + 0.603 V 5

Maximum required output pull-down under

AC test load VOL VTT − 0.603 V 5

Output timing measurement reference level VOTR 0.5 × VDDQ V 1

Output minimum sink DC current IOL +13.4 mA 3, 4, 5

Output minimum source DC current IOH −13.4 mA 2, 4, 5

Notes: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.7V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

5. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V.

DC Characteristics 3 (TC = 0°C to + 85°C, VDD, VDDQ = 1.8V ± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter Symbol min. max. Unit Notes

AC differential input voltage VID (AC) 0.5 VDDQ + 0.6 V 1, 2

AC differential cross point voltage VIX (AC) 0.5 × VDDQ − 0.175 0.5 × VDDQ + 0.175 V 2

AC differential cross point voltage VOX (AC) 0.5 × VDDQ − 0.125 0.5 × VDDQ + 0.125 V 3

Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true

input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as

/CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) − VIL(AC).

2. The typical value of VIX(AC ) is expected to be about 0.5 × VDDQ of the transmitting device and VI X(AC)

is expected to track variations in VDDQ . VIX(AC) indicates the voltag e at which differential input signal s

must cross.

3. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and

VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential

output signals must cross.

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

VDDQ

Differential Signal Levels*1, 2

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

ODT DC Electrical Characteristics (TC = 0°C to + 85°C, VDD, VDDQ = 1.8V ± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter Symbol min. typ. max. Unit Note

Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω Rtt1(eff) 60 75 90 Ω 1

Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω Rtt2(eff) 120 150 180 Ω 1

Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω Rtt3(eff) 40 50 60 Ω 1

Deviation of VM with respect to VDDQ/2 ∆VM −6  +6 % 1

Note: 1. Test condition for Rtt measurements.

Measurement Definition for Rtt(eff)

Apply VIH (AC) and VIL (AC) to test pin separatel y, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.

VIH(AC), and VDDQ values defined in SSTL_18.

VIH(AC) − VIL(A C)

I(VIH(AC)) − I(VIL(AC))

Rtt(eff) =

Measurement Definition for VM

Measure voltage (VM) at test pin (midpoint) with no load.

2 × VM

VDDQ

∆VM = × 100%

− 1

OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter min typ. max. Unit Notes

Output impedance 12.6 18 23.4 Ω 1

Pull-up and pull-down mismatch 0  4 Ω 1, 2

Output slew rate 1.5  5 V/ns 3, 4

Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.

Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;

VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.

2. Mismatch is absolute value between pull up and pull down, both ar e measured at same temperature and

voltage.

3. Slew rate measured from VIL(AC) to VIH(AC).

4. The absolute value of the slew rate as me asured from DC to DC is equa l to or greater than the sl ew rate

as measured from AC to AC. This is guaranteed by design and characterization.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Pin Capacitance (T A = 25°C, VDD = 1.8V ± 0.1V)

Parameter Symbol Pins min. max. Unit Notes

Input capacitance CI1 Address, /RAS, /CAS,

/WE, /CS, CKE, ODT 2.5 3.5 pF 1

Input capacitance CI2 CK, /CK 2 3 pF 2

Data and DQS input/output

capacitance

-6E CO DQ, DQS, /DQS, CB 2.5 3.5 pF 3

-5C, -4A 2.5 4.0 pF 3

Notes: 1. Register component specification.

2. PLL component specification.

3. DDR2 SDRAM component specification.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)

(DDR2 SDRAM Component Specification)

-6E -5C -4A

Frequency (Mbps) 667 533 400

Parameter Symbol min. max. min. max. min. max. Unit Notes

/CAS latency CL 5 5 4 5 3 5 tCK

Active to read or write command

delay tRCD 15  15  15  ns

Precharge command period tRP 15  15  15  ns

Active to active/auto refresh

command time tRC 60  60  55  ns

DQ output access time from CK,

/CK tAC −450 +450 −500 +500 −600 +600 ps

DQS output access time from

CK, /CK tDQSCK −400 +400 −450 +450 −500 +500 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK half period tHP min.

(tCL, tCH)  min.

(tCL, tCH)  ps

Clock cycle time tCK 3000 8000 3750 8000 5000 8000 ps

DQ and DM input hold time tDH 175  225  275  ps 5

DQ and DM input setup time tDS 100  100  150  ps 4

Control and Address input pulse

width for each input tIPW 0.6  0.6  0.6  tCK

DQ and DM input pulse width

for each input tDIPW 0.35  0.35  0.35  tCK

Data-out high-impedance time

from CK,/CK tHZ  tAC max.  tAC max.  tAC max. ps

Data-out low-impedance time

from CK,/CK tLZ tAC min. tAC max. tAC min. tAC max. tAC min. tAC max. ps

DQS-DQ skew for DQS and

associated DQ signals tDQSQ  240  300  350 ps

DQ hold skew factor tQHS  340  400  450 ps

DQ/DQS output hold time from

DQS tQH tHP – tQHS  tHP – tQHS  tHP – tQHS  ps

Write command to first DQS

latching transition tDQSS WL − 0.25 WL + 0.25 WL − 0.25 WL + 0.25 WL − 0.25 WL + 0.25 tCK

DQS input high pulse width tDQSH 0.35  0.35  0.35  tCK

DQS input low pulse width tDQSL 0.35  0.35  0.35  tCK

DQS falling edge to CK setup

time tDSS 0.2  0.2  0.2  tCK

DQS falling edge hold time from

CK tDSH 0.2  0.2  0.2  tCK

Mode register set command

cycle time tMRD 2  2  2  tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35  0.35  0.35  tCK

Address and control input hold

time tIH 275  375  475  ps 5

Address and control input setup

time tIS 200  250  350  ps 4

Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

-6E -5C -4A

Frequency (Mbps) 667 533 400

Parameter Symbol min. max. min. max. min. max. Unit Notes

Active to precharge command tRAS 45 70000 45 70000 40 70000 ns

Active to auto-precharge delay tRAP tRCD min.  tRCD min.  tRCD min.  ns

Active bank A to active bank B

command period tRRD 7.5  7.5  7.5  ns

Write recovery time tWR 15  15  15  ns

Auto precharge write recovery +

precharge time tDAL (tWR/tCK)+

(tRP/tCK)  (tWR/tCK)+

(tRP/tCK)  tCK 1

Internal write to read command

delay tWTR 7.5  7.5  10  ns

Internal read to precharge

command delay tRTP 7.5  7.5  7.5  ns

Exit self refresh to a non-read

command tXSNR tRFC + 10  tRFC + 10  tRFC + 10  ns

Exit self refresh to a read

command tXSRD 200  200  200  tCK

Exit precharge power down to

any non-read command tXP 2  2  2  tCK

Exit active power down to read

command tXARD 2  2  2  tCK 3

Exit active power down to read

command

(slow exit/low power mode) tXARDS 7− AL  6 − AL  6 − AL  tCK 2, 3

CKE minimum pulse width (high

and low pulse width) tCKE 3  3  3  tCK

Output impedance test driver

delay tOIT 0 12 0 12 0 12 ns

Auto refresh to active/auto

refresh command time tRFC 105  105  105  ns

Average periodic refresh interval

(0°C ≤ TC ≤ +85°C) tREFI  7.8  7.8  7.8 µs

(+85°C < TC ≤ +95°C) tREFI  3.9  3.9  3.9 µs

Minimum time clocks remains

ON after CKE asynchronously

drops low tDELAY tIS + tCK +

tIH  tIS + tCK +

tIH  ns

Notes: 1. For each of the terms above, if not already an integer, round to the next higher i nteg er.

2. AL: Additive Latency.

3. MRS A12 bit defines which active power down exit timing to be applied.

4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the

VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device u nder test.

5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the

VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.

DQS

/DQS

tDS tDH tDS tDH VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

/CK

tIS tIH tIS tIH VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

Input Waveform Timing 1 (tDS, tDH) Input Waveform Timing 2 (tIS, tIH)

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)

Parameter Symbol min. max. Unit Notes

ODT turn-on delay tAOND 2 2 tCK

ODT turn-on

-6E tAON tAC(min) tAC(max) + 700 ps 1

-5C, -4A tAON tAC(min) tAC(max) + 1000 ps 1

ODT turn-on (power down mode) tAONPD tAC(min) + 2000 2tCK + tAC(max) + 1000 ps

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max) + 600 ps 2

ODT turn-off (power down mode) tAOFPD tAC(min) + 2000 2.5tCK + tAC(max) + 1000 ps

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

AC Input Test Conditions

Parameter Symbol Value Unit Notes

Input reference voltage VREF 0.5 × VDDQ V 1

Input signal maximum peak to peak swing VSWING(max.) 1.0 V 1

Input signal maximum slew rate SLEW 1.0 V/ns 2, 3

Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the

device under test.

2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)

(min.) for rising edges and the range from VIH(DC) (m in.) to VIL(AC) (max.) for falling edges as shown in

the below figure.

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive

transitions and VIH(AC) to VIL(AC) on the negative transitions.

VSWING(max.)

∆TR

∆TF

Start of falling edge input timing Start of rising edge input timing

VIH (DC)(min.)

−

VIL (AC)(max.)

∆TF

Falling slew =

VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

VIH (AC) min.

−

VIL (DC)(max.)

∆TR

Rising slew =

AC Input Test Signal Wave forms

VTT

Measurement point

DQ RT =25 Ω

Output Load

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Pin Functions

CK, /CK (input pin)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross

point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross

point of the CK and the /CK. When a write operation, DQs are referred to the cross point of the DQS and the VREF

level. DQSs for write operation are referred to the cross point of the CK and the /CK.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See “Command operation”.

A0 to A13 (input pins)

Row address (AX0 to AX13) i s determined by the A0 to the A13 level at th e cross point of the CK rising edge and the

VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9

and A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This

column address becomes the starting address of a burst operation.

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge

command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write

command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.

BA0, BA1 (input pin)

BA0, BA1 are bank select signals (BA). T he memory array is divided into bank 0, bank 1 , bank 2 and bank 3. (See

Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE controls power down and self-refresh. The po wer down and the sel f-refresh commands are entered when the

CKE is driven low and exited when it resumes to high.

The CKE level must be k ept for 1 CK cycle at least, that is , if CKE changes at the cross point of the CK risin g edge

and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold

time tIH.

DQ, CB (input and output pins)

Data are input to and output from these pins.

DQS (input and output pin)

DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

VDD (power supply pins)

1.8V is applied. (VDD is for the internal circuit.)

VDDSPD (power supply pin)

1.8V is applied (For serial EEPROM).

VSS (power supply pin)

Ground is connected.

/RESET(input pin)

LVCMOS reset input. When /RESET is Low, all registers are reset.

Par_IN (Parity input pin)

Parity bit for the address and control bus.

Err_Out (Error output pin)

Parity error found on the address and co ntrol bus.

Detailed Operation Part and Timing Waveforms

Refer to the EDE5104AGSE, EDE5108AGSE datasheet (E0715E). DM pins of component dev ice fixed to VSS level

on the module board. DIMM /CAS latency = compo nent CL + 1 for registered type.

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

Physical Outline

Detail A

0.20 ± 0.15

2.50 ± 0.20

1.00

133.35

(DATUM -A-)

63.00 55.00

1 120

240

121

FULL R

0.80 ± 0.05

Unit: mm

1.27 ± 0.10

3.00

4.00 min

10.00

4.00

17.80

30.00

4.00 max 0.5 min

Component area

(Front)

Component area

(Back)

5.00

Detail B

3.80

1.50 ± 0.10

2.50

4.00

FULL R

(DATUM -A-)

ECA-TS2-0093-01

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as

the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on

these components to prevent damaging them.

In particular, do not push module cover or drop the modules in order to protect from mechanical defects,

which would be electrical defects.

When re-packing memory modules, be sure the modules are not touching each other.

Modules in contact with other modules may cause excessive mechanical stress, which may damage the

modules.

MDE0202

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

EBE10RD4AGFA

Data Sheet E0795E20 (Ver. 2.0)

µBGA is a registered trademark of Tessera, Inc.

All other trademarks are the intellectual prop erty of their respective owners.

M01E0107

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.