CS5361-KZ - Cirrus Logic, Inc.

Preliminary Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

CS5361

114 dB, 192 kHz, Multi-Bit Audio A/D Converter

Features

!Advanced Multi-bit Delta-Sigma Architecture

!24-Bit Conversion

!114 dB Dynamic Range

!-105 dB THD+N

!System Sampling Rates up to 192 kHz

!135 mW Power Consumption

!High Pass Filter and DC Offset Calibration

!Supports Logic Levels Between 5 and 2.5 V

!Differential Analog Architecture

!Linear Phase Digital Anti-Alias Filtering

!Overflow Detection

General Description

The CS5361 is a complete analog-to-digital converter for

digital audio systems. It performs sampling, analog-to-

digital conversion and anti-alias filtering, generating 24-

bit values for both left and right inputs in serial form at

sample rates up to 192 kHz per channel.

The CS5361 uses a 5th-order, multi-bit delta-sigma

modulator followed by digital filtering and decimation,

which removes the need for an external anti-alias filter.

The ADC uses a differential architecture which provides

excellent noise rejection.

The CS5361 is ideal for audio systems requiring wide dy-

namic range, negligible distortion and low noise, such as

A/V receivers, DVD-R, CD-R, digital mixing consoles,

and effects processors.

ORDERING INFORMATION

CS5361-KS -10° to 70°C 24-pin SOIC

CS5361-KZ -10° to 70°C 24-pin TSSOP

CS5361-BZ -40° to 85°C 24-pin TSSOP

CS5361-DZ -40° to 85°C 24-pin TSSOP

CDB5361 Evaluation Board

Voltage Reference Serial Output Interface

Digital

Filter

High

Pass

Filter

High

Pass

Filter

Decimation

Digital

Filter

Decimation

DAC

S/H

DAC

S/H

AINR+

SCLK SDOUT MCLK

RST

VQ LRCK

AINR-

AINL+

AINL-

FILT+ I

S/LJ

M/S

HPF

MODE0

MODE1

REFGND V

MDIV

LP Filter

∆Σ

OVFL

MAR ‘03

DS467PP3

CS5361
2
TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS (CS5361-KS/KZ) .................................................................... 5
ANALOG CHARACTERISTICS (CS5361-BZ/DZ) .................................................................... 6
DIGITAL FILTER CHARACTERISTICS.................................................................................... 7
DC ELECTRICAL CHARACTERISTICS................................................................................. 10
DIGITAL CHARACTERISTICS ............................................................................................... 10
THERMAL CHARACTERISTICS............................................................................................ 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 11
2.0 PIN DESCRIPTIONS ............................................................................................................ 14
3.0 TYPICAL CONNECTION DIAGRAM .................................................................................... 15
4.0 APPLICATIONS .................................................................................................................... 16
4.1 Operational Mode/Sample Rate Range Select ................................................................ 16
4.2 System Clocking .............................................................................................................. 16
4.2.1 Slave Mode ......................................................................................................... 16
4.2.2 Master Mode ....................................................................................................... 17
4.3 Power-up Sequence ........................................................................................................ 18
4.4 Analog Connections ......................................................................................................... 18
4.5 High Pass Filter and DC Offset Calibration ..................................................................... 19
4.6 Overflow Detection ........................................................................................................... 19
4.6.1 OVFL Output Timing ........................................................................................... 19
4.7 Grounding and Power Supply Decoupling ....................................................................... 19
4.8 Synchronization of Multiple Devices ................................................................................ 20
5.0 PARAMETER DEFINITIONS ................................................................................................ 21
6.0 PACKAGE DIMENSIONS .................................................................................................. 22
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without
notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
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work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
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terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
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ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.

CS5361
3
LIST OF FIGURES
Figure 1. Single Speed Mode Stopband Rejection ..................................................... 8
Figure 2. Single Speed Mode Transition Band ........................................................... 8
Figure 3. Single Speed Mode Transition Band (Detail) .............................................. 8
Figure 4. Single Speed Mode Passband Ripple ......................................................... 8
Figure 5. Double Speed Mode Stopband Rejection ................................................... 8
Figure 6. Double Speed Mode Transition Band ......................................................... 8
Figure 7. Double Speed Mode Transition Band (Detail) ............................................. 9
Figure 8. Double Speed Mode Passband Ripple ....................................................... 9
Figure 9. Quad Speed Mode Stopband Rejection ...................................................... 9
Figure 10. Quad Speed Mode Transition Band .......................................................... 9
Figure 11. Quad Speed Mode Transition Band (Detail) ............................................. 9
Figure 12. Quad Speed Mode Passband Ripple ........................................................ 9
Figure 13. Master Mode, Left Justified SAI .............................................................. 12
Figure 14. Slave Mode, Left Justified SAI ................................................................ 12
Figure 15. Master Mode, I2S SAI .............................................................................. 12
Figure 16. Slave Mode, I2S SAI ................................................................................ 12
Figure 17. OVFL Output Timing ............................................................................... 12
Figure 18. Left Justified Serial Audio Interface ......................................................... 13
Figure 19. I2S Serial Audio Interface ........................................................................ 13
Figure 20. OVFL Output Timing, I2S Format ............................................................ 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................. 13
Figure 22. Typical Connection Diagram ................................................................... 15
Figure 23. CS5361 Master Mode Clocking ............................................................... 17
Figure 24. CS5361 Recommended Analog Input Buffer .......................................... 18
LIST OF TABLES
Table 1. CS5361 Mode Control .............................................................................. 16
Table 2. CS5361 Slave Mode Clock Ratios ........................................................... 16
Table 3. CS5361 Common Master Clock Frequencies .......................................... 17

CS5361

1.0 CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at typical supply voltages

and TA=25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V.)

ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR

latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Unit

DC Power Supplies: Positive Analog

Positive Digital

Positive Logic

4.75

3.1

2.37

5.0

3.3

5.25

Ambient Operating Temperature Commercial (-KS/-KZ)

Industrial (-BZ)

Automotive (-DZ)

TAC

TAI

TAA

-10

-40

°C

Parameter Symbol Min Max Units

DC Power Supplies: Analog

Logic

Digital

-0.3

+6.0

Input Current (Note 2) Iin -±10 mA

Analog Input Voltage (Note 3) VIN GND - 0.7 VA + 0.7 V

Digital Input Voltage (Note 3) VIND -0.7 VL + 0.7 V

Ambient Operating Temperature (Power Applied) TA-50 +95 °C

Storage Temperature Tstg -65 +150 °C

CS5361

ANALOG CHARACTERISTICS (CS5361-KS/KZ) (Test conditions (unless otherwise speci-

fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.)

Notes: 4. Referred to the typical full-scale input voltage.

5. Measured between AIN+ and AIN-

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

108

105

114

111

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N

-105

-91

-51

-99

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-105

-91

-51

-102

-99

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-105

-91

-51

-102

-99

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -±5%

Gain Drift - ±100 - ppm/°C

Offset Error HPF enabled

HPF disabled

100

LSB

Analog Input Characteristics

Full-scale Input Voltage (at VA = 5 V) 1.9 2.0 2.1 Vrms

Input Impedance (Differential) (Note 5) 37 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS5361

ANALOG CHARACTERISTICS (CS5361-BZ/DZ) (Test conditions (unless otherwise speci-

fied): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.)

Parameter Symbol Min Typ Max Unit

Single Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

106

103

114

111

Total Harmonic Distortion + Noise

-1 dB

-20 dB

-60 dB

THD+N

-105

-91

-51

-97

Double Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-105

-91

-51

-102

-97

Quad Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

106

103

114

111

108

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-105

-91

-51

-102

-97

Dynamic Performance for All Modes

Interchannel Isolation - 110 - dB

Interchannel Phase Deviation - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -±5%

Gain Drift - ±100 - ppm/°C

Offset Error HPF enabled

HPF disabled

100

LSB

Analog Input Characteristics

Full-scale Input Voltage (at VA = 5 V) 1.8 2.0 2.2 Vrms

Input Impedance (Differential) (Note 5) 37 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

CS5361

DIGITAL FILTER CHARACTERISTICS

Notes: 6. The filter frequency response scales precisely with Fs.

7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

Parameter Symbol Min Typ Max Unit

Single Speed Mode (2 kHz to 50 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.47 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 6) 0.58 - - Fs

Stopband Attenuation -95 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd - 12/Fs - s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

Double Speed Mode (50 kHz to 100 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.45 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 6) 0.68 - - Fs

Stopband Attenuation -92 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs- s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

Quad Speed Mode (100 kHz to 200 kHz sample rates)

Passband (-0.1 dB) (Note 6) 0 - 0.24 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 6) 0.78 - - Fs

Stopband Attenuation -97 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs- s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 7)

-1

Phase Deviation @ 20 Hz (Note 7) - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time 105/Fs s

CS5361

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 1. Single Speed Mode Stopband Rejection Figure 2. Single Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 3. Single Speed Mode Transition Band (Detail)

Figure 4. Single Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

Figure 5. Double Speed Mode Stopband Rejection Figure 6. Double Speed Mode Transition Band

CS5361

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 7. Double Speed Mode Transition Band (Detail) Figure 8. Double Speed Mode Passband Ripple

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Frequency (normalized to Fs)

Amplitude (dB)

Figure 9. Quad Speed Mode Stopband Rejection Figure 10. Quad Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25

Frequency (normalized to Fs)

Amplitude (dB)

Figure 11. Quad Speed Mode Transition Band (Detail) Figure 12. Quad Speed Mode Passband Ripple

CS5361

DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground.

MCLK=12.288 MHz; Master Mode)

Notes: 8. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Power Supply Current VA

(Normal Operation) VL,VD = 5 V

VL,VD = 3.3 V

17.5

14.5

Power Supply Current VA

(Power-Down Mode) (Note 8) VL,VD=5 V

Power Consumption

(Normal Operation) VL, VD=5 V

VL, VD = 3.3 V

(Power-Down Mode)

198

135

235

161

Power Supply Rejection Ratio (1 kHz) (Note 9) PSRR - 65 - dB

VQNominal Voltage

Output Impedance

Maximum allowable DC current source/sink

2.5

0.01

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

0.01

kΩ

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VL) VIH 70% - - V

Low-Level Input Voltage (% of VL) VIL --30%V

High-Level Output Voltage at Io=100µA(%ofVL)V

OH 70% - - V

Low-Level Output Voltage at Io=100µA(%ofVL)V

OL --15%V

OVFL Current Sink Iovfl --4.0mA

Input Leakage Current Iin --±10 µA

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature - - 135 °C

Junction to Ambient Thermal Impedance θJA -70 -°C/W

CS5361

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic"0"=GND=0V;

Logic "1" = VL, CL=20pF)

Parameter Symbol Min Typ Max Unit

Input Sample Rate Single Speed Mode

Double Speed Mode

Quad Speed Mode

100

200

kHz

OVFL to LRCK edge setup time tsetup 16/fsclk --s

OVFL to LRCK edge hold time thold 1/fsclk --s

OVFL time-out on overrange condition

Fs = 44.1, 88.2, 176.4 kHz

Fs = 48, 96, 192 kHz

740

680

MCLK Specifications

MCLK Period tclkw 40 - 1953 ns

MCLK Pulse Width High tclkh 16 - - ns

MCLK Pulse Width Low tclkl 16 - - ns

Master Mode

SCLK falling to LRCK tmslr -20 - 20 ns

SCLK falling to SDOUT valid tsdo 0 - 32 ns

SCLK Duty Cycle - 50 - %

Slave Mode

Single Speed

Output Sample Rate Fs 2 - 50 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 163 - - ns

SCLK High/Low tsclkhl 20 - - ns

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Double Speed

Output Sample Rate Fs 50 - 100 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 163 - - ns

SCLK High/Low tsclkhl 20 - - ns

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Quad Speed

Output Sample Rate Fs 100 - 200 kHz

LRCK Duty Cycle 40 50 60 %

SCLK Period tsclkw 81 - - ns

SCLK High/Low tsclkhl 20 - - ns

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -10 - 10 ns

CS5361

SCLK output

tmsl

SDOUT

tsd

LRCK

output

MSB MSB-1

SCLK input

LRCK input

sclkl

dss

MSB MSB-1 MSB-2

lrdss

sclkh

tsclkw

SDOUT

srdl

Figure 13. Master Mode, Left Justified SAI Figure 14. Slave Mode, Left Justified SAI

SCLK

output

tmslr

SDOUT

tsdo

LRCK output

MSB

SCLK input

LRCK input

sclkl

dss

MSB MSB-1

sclkh

tsclkw

SDOUT

Figure 15. Master Mode, I2S SAI Figure 16. Slave Mode, I2SSAI

OVFL

tsetup

LRCK

thold

Figure 17. OVFL Output Timing

CS5361

SDATA 23 22 7 623 22

SCLK

LRCK

23 2254321087654321089 9

Left Channel Right Channel

Figure 18. Left Justified Serial Audio Interface

SDATA 23 22 8 723 22

SCLK

LRCK

23 2265432108765432109 9

Left Channel Right Channel

Figure 19. I2S Serial Audio Interface

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

Figure 20. OVFL Output Timing, I2S Format

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

Figure 21. OVFL Output Timing, Left-Justified Format

CS5361

2.0 PIN DESCRIPTIONS

RST 124FILT+

M/S 223REFGND

LRCK 322VQ

SCLK 421AINR+

MCLK 520AINR-

VD 619VA

GND 718GND

VL 817AINL-

SDOUT 916AINL+

MDIV 10 15 OVFL

HPF 11 14 M1

I2S/LJ 12 13 M0

Pin Name #Pin Description

RST 1Reset (Input) - The device enters a low power mode when low.

M/S 2Master/Slave Mode (Input) - Selects operation as either clock master or slave.

LRCK 3Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SCLK 4Serial Clock (Input/Output) - Serial clock for the serial audio interface.

MCLK 5Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VD 6Digital Power (Input)-Positive power supply for the digital section.

GND 7,18 Ground (Input) - Ground reference. Must be connected to analog ground.

VL 8Logic Power (Input)-Positive power for the digital input/output.

SDOUT 9Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MDIV 10 MCLK Divider (Input)-Enables a master clock divide by two function.

HPF 11 High Pass Filter Enable (Input)-Enables the Digital High-Pass Filter.

I2S/LJ 12 Serial Audio Interface Format Select (Input) -Selects either the left-justified or I2S format for the SAI.

13,

Mode Selection (Input) - Determines the operational mode of the device.

OVFL 15 Overflow (Output, open drain) -Detects an overflow condition on both left and right channels.

AINL+

AINL-

16,

Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma

modulators via the AINL+/- pins.

VA 19 Analog Power (Input)-Positive power supply for the analog section.

AINR-

AINR+

20,

Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-sigma

modulators via the AINR+/- pins.

VQ 22 Quiescent Voltage (Output) -Filter connection for the internal quiescent reference voltage.

REF_GND 23 Reference Ground (Input) - Ground reference for the internal sampling circuits.

FILT+ 24 Positive Voltage Reference (Output)-Positive reference voltage for the internal sampling circuits.

CS5361

3.0 TYPICAL CONNECTION DIAGRAM

FILT+

AINL+

AINL-

0.1 µF

A/D CONVERTER

SCLK

CS5361

M/S

MCLK

AINR+

AINR-

47 µF

RST

VA V L

+5V

1µF

+5V to 2.5V

5.1 Ω

1µF

SDOUT

GND

I2S/LJ

LRCK

GND

Power Down

and Mode

Settings

Audio Data

Processor

Timing Logic

and Clock

0.1 µF

HPF

REFGND

MDIV

+5 V to 3.3 V

1µF0.1 µF

1µF

Analog

Input

Buffer

(Figure 3)

Analog

Input

Buffer

(Figure 3)

OVFL

10 kΩ

Figure 22. Typical Connection Diagram

CS5361

4.0 APPLICATIONS

4.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2 kHz to 200 kHz. The CS5361 must be set to

the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.

4.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are

synchronously generated on-chip, or Slave Mode, which requires external generation of the

left/right and serial clocks. The device also includes a master clock divider in Master Mode where

the master clock will be internally divided prior to any other internal circuitry when MDIV is en-

abled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.

4.2.1 Slave Mode

LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously

derived from the master clock and be equal to Fs. It is also recommended that the serial clock

be synchronously derived from the master clock and be equal to 64x Fs to maximize system

performance. Refer to Table 2 for required clock ratios.

Table2.CS5361SlaveModeClockRatios

M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)

0 0 Single Speed Mode 2 kHz - 50 kHz

0 1 Double Speed Mode 50 kHz - 100 kHz

1 0 Quad Speed Mode 100 kHz - 200 kHz

11Reserved

Table 1. CS5361 Mode Control

Single Speed Mode

Fs = 2 kHz to 50 kHz

Double Speed Mode

Fs = 50 kHz to 100 kHz

Quad Speed Mode

Fs = 100 kHz to 200 kHz

MCLK/LRCK Ratio 256x, 512x 128x, 256x 128x

SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 64x

CS5361

4.2.2 Master Mode

In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are inter-

nally derived from the master clock with the left/right clock equal to Fs and the serial clock equal

to 64x Fs, as shown in Figure 2. Refer to Table 3 for common master clock frequencies.

÷128

÷256

÷64

M0M1

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

÷2

÷4

÷1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

÷2

÷10

MCLK

MDIV

Figure 23. CS5361 Master Mode Clocking

SAMPLE RATE (kHz)

MDIV = 0

MCLK (MHz)

MDIV = 1

MCLK (MHz)

32 8.192 16.384

44.1 11.2896 22.5792

48 12.288 24.576

64 8.192 16.384

88.2 11.2896 22.5792

96 12.288 24.576

176.4 11.2896 22.5792

192 12.288 24.576

Table 3. CS5361 Common Master Clock Frequencies

CS5361

4.3 Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies,

clocks and configuration pins are stable. It is also recommended that reset be enabled if the an-

alog or digital supplies drop below the minimum specified operating voltages to prevent power

glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore,

there is a delay between the release of reset and the generation of valid output, due to the finite

output impedance of FILT+ and the presence of the external capacitance.

4.4 Analog Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will

reject signals within the stopband of the filter. However, there is no rejection for input signals

which are (n ×6.144 MHz) the digital passband frequency, where n=0,1,2,...Refer to Figure 3

which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition

to providing the optimum source impedance for the modulators. The use of capacitors which

have a large voltage coefficient (such as general purpose ceramics) must be avoided since these

can degrade signal linearity.

Please see the Addendum at the end of the data sheet for an analog input buffer that can be used

with both the CS5351 as well as the CS5361 with a simple change in the bill of materials.

CS5361 AIN+

CS5361 AIN-

COG

2700 pF

AIN+

AIN-

10 µF

100 kΩ

634 kΩ

91 Ω

10 kΩ

100 kΩ

634 Ω

91 Ω

470 pF

COG

470 pF

COG

Figure 24. CS5361 Recommended Analog Input Buffer

CS5361

4.5 High Pass Filter and DC Offset Calibration

The operational amplifiers in the input circuitry driving the CS5361 may generate a small DC off-

set into the A/D converter. The CS5361 includes a high pass filter after the decimator to remove

any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching

between devices in a multichannel system.

The high pass filter continuously subtracts a measure of the DC offset from the output of the dec-

imation filter. If the HPF pin is taken high during normal operation, the current value of the DC

offset register is frozen and this DC offset will continue to be subtracted from the conversion re-

sult. This feature makes it possible to perform a system DC offset calibration by:

1) Running the CS5361 with the high pass filter enabled until the filter settles. See the Digital

Filter Characteristics for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path be-

tween the calibration point and the CS5361.

4.6 Overflow Detection

The CS5361 includes overflow detection on both the left and right channels. This time multi-

plexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and

OVFL_R data will go to a logical low as soon as an overrange condition in either channel is de-

tected. The data will remain low as specified in the Switching Characteristics - Serial Audio Port

section. This ensures sufficient time to detect an overrange condition regardless of the speed

mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has

not been any other overrange condition detected. Please note that an overrange condition on ei-

ther channel will restart the timeout period for both channels.

4.6.1 OVFL Output Timing

In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S

format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23

and 24. In both cases the OVFL data can be easily demultiplexed by using the LRCK to latch the

data. In left-justified format, the rising edge of LRCK would latch the right channel overflow sta-

tus, and the falling edge of LRCK would latch the left channel overflow status. In I2S format, the

falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK

would latch the left channel overflow status.

4.7 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5361 requires careful attention to power supply and

grounding arrangements if its potential performance is to be realized. Figure 22 shows the rec-

ommended power arrangements, with VA and VL connected to clean supplies. VD, which pow-

ers the digital filter, may be run from the system logic supply or may be powered from the analog

supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling

capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being

the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in

CS5361

order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors,

particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF-

GND. The CDB5361 evaluation board demonstrates the optimum layout and power supply ar-

rangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.

4.8 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sam-

pling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the

CS5361’s in the system. If only one master clock source is needed, one solution is to place one

CS5361 in Master mode, and slave all of the other CS5361’s to the one master. If multiple master

clock sources are needed, a possible solution would be to supply all clocks from the same exter-

nal source and time the CS5361 reset with the inactive edge of MCLK. This will ensure that all

converters begin sampling on the same clock edge.

CS5361

5.0 PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.

This technique ensures that the distortion components are below the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society,

AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response

at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

CS5361

6.0 PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51

C 0.009 0.013 0.23 0.32

D 0.598 0.614 15.20 15.60

E 0.291 0.299 7.40 7.60

e 0.040 0.060 1.02 1.52

H 0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27

∝0°8°0°8°

24L SOIC (300 MIL BODY) PACKAGE DRAWING

∝

SEATING

PLANE

CS5361

Notes: 1.“D”and “E1”are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2.Dimension “b”does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b”dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b”by more than 0.07 mm at least material condition.

3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.303 0.307 0.311 7.70 7.80 7.90 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝0°4°8°0°4°8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

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