Preliminary User's Manual 78K0/KE2 8-Bit Single-Chip Microcontrollers PD78F0531 PD78F0532 PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537 PD78F0537D The PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Document No. U17260EJ3V1UD00 (3rd edition) Date Published August 2005 N CP(K) 2004 Printed in Japan [MEMO] 2 Preliminary User's Manual U17260EJ3V1UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Preliminary User's Manual U17260EJ3V1UD 3 EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. * The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. * Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5D 02. 11-1 4 Preliminary User's Manual U17260EJ3V1UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 Preliminary User's Manual U17260EJ3V1UD 5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KE2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KE2: PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KE2 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/KE2 78K/0 Series User's Manual User's Manual (This Manual) Instructions * Pin functions * CPU functions * Internal block functions * Instruction set * Interrupts * Explanation of each instruction * Other on-chip peripheral functions * Electrical specifications (target) How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark shows major revised points. * How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0. * To check the details of a register when you know the register name: See APPENDIX C REGISTER INDEX. * To know details of the 78K/0 Series instructions: Refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 6 Preliminary User's Manual U17260EJ3V1UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: xxx (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ... xxxx or xxxxB Numerical representations: Binary Related Documents Decimal ... xxxx Hexadecimal ... xxxxH The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/KE2 User's Manual This manual 78K/0 Series Instructions User's Manual U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Ver. 3.80 Assembler Package CC78K0 Ver. 3.70 C Compiler SM+ System Simulator Document No. Operation U17199E Language U17198E Structured Assembly Language U17197E Operation U17201E Language U17200E Operation U17246E External Part User Open Interface U17247E Specifications ID78K0-QB Ver. 2.90 Integrated Debugger Operation PM+ Ver. 5.20 U17437E U16934E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name Document No. QB-78K0KX2 In-Circuit Emulator U17341E QB-78K0MINI On-Chip Debug Emulator U17029E Documents Related to Flash Memory Programming Document Name PG-FP4 Flash Memory Programmer User's Manual Document No. U15260E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Preliminary User's Manual U17260EJ3V1UD 7 Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 8 Preliminary User's Manual U17260EJ3V1UD CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features .................................................................................................................................... 17 Applications ............................................................................................................................. 18 Ordering Information ............................................................................................................... 19 Pin Configuration (Top View).................................................................................................. 23 78K0/Kx2 Series Lineup .......................................................................................................... 26 Block Diagram.......................................................................................................................... 29 Outline of Functions ................................................................................................................ 30 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 32 2.1 2.2 2.3 Pin Function List...................................................................................................................... 32 Description of Pin Functions .................................................................................................. 36 2.2.1 P00 to P06 (port 0).....................................................................................................................36 2.2.2 P10 to P17 (port 1).....................................................................................................................37 2.2.3 P20 to P27 (port 2).....................................................................................................................38 2.2.4 P30 to P33 (port 3).....................................................................................................................38 2.2.5 P40 to P43 (port 4).....................................................................................................................39 2.2.6 P50 to P53 (port 5).....................................................................................................................39 2.2.7 P60 to P63 (port 6).....................................................................................................................39 2.2.8 P70 to P77 (port 7).....................................................................................................................39 2.2.9 P120 to P124 (port 12)...............................................................................................................40 2.2.10 P130 (port 13) ............................................................................................................................40 2.2.11 P140, P141 (port 14)..................................................................................................................41 2.2.12 AVREF .........................................................................................................................................41 2.2.13 AVSS ...........................................................................................................................................41 2.2.14 RESET .......................................................................................................................................41 2.2.15 REGC.........................................................................................................................................41 2.2.16 VDD and EVDD .............................................................................................................................42 2.2.17 VSS and EVSS .............................................................................................................................42 2.2.18 FLMD0 .......................................................................................................................................42 Pin I/O Circuits and Recommended Connection of Unused Pins....................................... 43 CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 47 3.1 Memory Space.......................................................................................................................... 47 3.1.1 3.2 Internal program memory space ................................................................................................56 3.1.2 Memory bank (PD78F0536, 78F0537, and 78F0537D only)....................................................58 3.1.3 Internal data memory space.......................................................................................................58 3.1.4 Special function register (SFR) area ..........................................................................................59 3.1.5 Data memory addressing ...........................................................................................................59 Processor Registers ................................................................................................................ 67 3.2.1 Control registers.........................................................................................................................67 3.2.2 General-purpose registers .........................................................................................................71 3.2.3 Special function registers (SFRs)...............................................................................................72 Preliminary User's Manual U17260EJ3V1UD 9 3.3 Instruction Address Addressing ............................................................................................ 77 3.3.1 3.4 Relative addressing................................................................................................................... 77 3.3.2 Immediate addressing ............................................................................................................... 78 3.3.3 Table indirect addressing .......................................................................................................... 79 3.3.4 Register addressing .................................................................................................................. 79 Operand Address Addressing ................................................................................................ 80 3.4.1 Implied addressing .................................................................................................................... 80 3.4.2 Register addressing .................................................................................................................. 81 3.4.3 Direct addressing ...................................................................................................................... 82 3.4.4 Short direct addressing ............................................................................................................. 83 3.4.5 Special function register (SFR) addressing ............................................................................... 84 3.4.6 Register indirect addressing...................................................................................................... 85 3.4.7 Based addressing...................................................................................................................... 86 3.4.8 Based indexed addressing ........................................................................................................ 87 3.4.9 Stack addressing....................................................................................................................... 88 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) ......................................................... 89 4.1 4.2 4.3 Memory Bank............................................................................................................................ 89 Memory Bank Select Register (BANK)................................................................................... 90 Selecting Memory Bank........................................................................................................... 91 4.3.1 Referencing values between memory banks............................................................................. 91 4.3.2 Branching instruction between memory banks .......................................................................... 93 4.3.3 Subroutine call between memory banks.................................................................................... 95 4.3.4 Instruction branch to bank area by interrupt .............................................................................. 97 CHAPTER 5 PORT FUNCTIONS ........................................................................................................... 99 5.1 5.2 5.3 5.4 5.5 Port Functions .......................................................................................................................... 99 Port Configuration ................................................................................................................. 101 5.2.1 Port 0........................................................................................................................................102 5.2.2 Port 1........................................................................................................................................108 5.2.3 Port 2........................................................................................................................................113 5.2.4 Port 3........................................................................................................................................114 5.2.5 Port 4........................................................................................................................................116 5.2.6 Port 5........................................................................................................................................117 5.2.7 Port 6........................................................................................................................................118 5.2.8 Port 7........................................................................................................................................120 5.2.9 Port 12......................................................................................................................................121 5.2.10 Port 13......................................................................................................................................123 5.2.11 Port 14......................................................................................................................................124 Registers Controlling Port Function .................................................................................... 125 Port Function Operations...................................................................................................... 130 5.4.1 Writing to I/O port .....................................................................................................................130 5.4.2 Reading from I/O port...............................................................................................................130 5.4.3 Operations on I/O port..............................................................................................................130 Settings of Port Mode Register and Output Latch When Using Alternate Function....... 131 CHAPTER 6 CLOCK GENERATOR .................................................................................................... 134 10 Preliminary User's Manual U17260EJ3V1UD 6.1 6.2 6.3 6.4 6.5 6.6 Functions of Clock Generator .............................................................................................. 134 Configuration of Clock Generator........................................................................................ 135 Registers Controlling Clock Generator ............................................................................... 137 System Clock Oscillator........................................................................................................ 146 6.4.1 X1 oscillator .............................................................................................................................146 6.4.2 XT1 oscillator ...........................................................................................................................146 6.4.3 When subsystem clock is not used ..........................................................................................149 6.4.4 Internal high-speed oscillator ...................................................................................................149 6.4.5 Internal low-speed oscillator.....................................................................................................149 6.4.6 Prescaler..................................................................................................................................149 Clock Generator Operation ................................................................................................... 150 Controlling Clock ................................................................................................................... 153 6.6.1 Controlling high-speed system clock........................................................................................153 6.6.2 Example of controlling internal high-speed oscillation clock.....................................................156 6.6.3 Example of controlling subsystem clock...................................................................................158 6.6.4 Example of controlling internal low-speed oscillation clock ......................................................160 6.6.5 Clocks supplied to CPU and peripheral hardware....................................................................160 6.6.6 CPU clock status transition diagram ........................................................................................161 6.6.7 Condition before changing CPU clock and processing after changing CPU clock ...................166 6.6.8 Time required for switchover of CPU clock and main system clock .........................................167 6.6.9 Conditions before clock oscillation is stopped..........................................................................168 6.6.10 Peripheral hardware and source clocks ...................................................................................169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 ........................................................ 170 7.1 7.2 7.3 7.4 7.5 7.6 Functions of 16-Bit Timer/Event Counters 00 and 01 ........................................................ 170 Configuration of 16-Bit Timer/Event Counters 00 and 01.................................................. 171 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ......................................... 176 Operation of 16-Bit Timer/Event Counters 00 and 01 ........................................................ 188 7.4.1 Interval timer operation ............................................................................................................188 7.4.2 Square wave output operation .................................................................................................191 7.4.3 External event counter operation .............................................................................................194 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input....................................197 7.4.5 Free-running timer operation....................................................................................................213 7.4.6 PPG output operation...............................................................................................................222 7.4.7 One-shot pulse output operation..............................................................................................225 7.4.8 Pulse width measurement operation ........................................................................................230 Special Use of TM0n .............................................................................................................. 239 7.5.1 Rewriting CR01n during TM0n operation .................................................................................239 7.5.2 Setting LVS0n and LVR0n .......................................................................................................239 Cautions for 16-Bit Timer/Event Counters 00 and 01......................................................... 241 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 245 8.1 8.2 8.3 8.4 Functions of 8-Bit Timer/Event Counters 50 and 51 .......................................................... 245 Configuration of 8-Bit Timer/Event Counters 50 and 51.................................................... 245 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ........................................... 248 Operations of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 253 8.4.1 Operation as interval timer .......................................................................................................253 8.4.2 Operation as external event counter ........................................................................................255 Preliminary User's Manual U17260EJ3V1UD 11 8.5 8.4.3 Square-wave output operation .................................................................................................256 8.4.4 PWM output operation..............................................................................................................257 Cautions for 8-Bit Timer/Event Counters 50 and 51 ........................................................... 261 CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 262 9.1 9.2 9.3 9.4 Functions of 8-Bit Timers H0 and H1 ................................................................................... 262 Configuration of 8-Bit Timers H0 and H1............................................................................. 262 Registers Controlling 8-Bit Timers H0 and H1 .................................................................... 266 Operation of 8-Bit Timers H0 and H1 ................................................................................... 271 9.4.1 Operation as interval timer/square-wave output .......................................................................271 9.4.2 Operation as PWM output ........................................................................................................274 9.4.3 Carrier generator operation (8-bit timer H1 only)......................................................................280 CHAPTER 10 WATCH TIMER.............................................................................................................. 287 10.1 10.2 10.3 10.4 10.5 Functions of Watch Timer ..................................................................................................... 287 Configuration of Watch Timer............................................................................................... 288 Register Controlling Watch Timer ........................................................................................ 289 Watch Timer Operations........................................................................................................ 291 10.4.1 Watch timer operation ..............................................................................................................291 10.4.2 Interval timer operation.............................................................................................................291 Cautions for Watch Timer ..................................................................................................... 292 CHAPTER 11 WATCHDOG TIMER ..................................................................................................... 293 11.1 11.2 11.3 11.4 Functions of Watchdog Timer .............................................................................................. 293 Configuration of Watchdog Timer ........................................................................................ 294 Register Controlling Watchdog Timer ................................................................................. 295 Operation of Watchdog Timer............................................................................................... 296 11.4.1 Controlling operation of watchdog timer ...................................................................................296 11.4.2 Setting overflow time of watchdog timer...................................................................................297 11.4.3 Setting window open period of watchdog timer ........................................................................298 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 300 12.1 12.2 12.3 12.4 Functions of Clock Output/Buzzer Output Controller ........................................................ 300 Configuration of Clock Output/Buzzer Output Controller ................................................. 301 Registers Controlling Clock Output/Buzzer Output Controller......................................... 301 Operations of Clock Output/Buzzer Output Controller ...................................................... 303 12.4.1 Operation as clock output.........................................................................................................303 12.4.2 Operation as buzzer output ......................................................................................................303 CHAPTER 13 A/D CONVERTER ......................................................................................................... 304 13.1 13.2 13.3 13.4 12 Function of A/D Converter .................................................................................................... 304 Configuration of A/D Converter ............................................................................................ 305 Registers Used in A/D Converter.......................................................................................... 307 A/D Converter Operations ..................................................................................................... 315 13.4.1 Basic operations of A/D converter ............................................................................................315 13.4.2 Input voltage and conversion results ........................................................................................317 Preliminary User's Manual U17260EJ3V1UD 13.4.3 13.5 13.6 A/D converter operation mode .................................................................................................318 How to Read A/D Converter Characteristics Table ............................................................ 320 Cautions for A/D Converter................................................................................................... 322 CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 326 14.1 14.2 14.3 14.4 Functions of Serial Interface UART0 ................................................................................... 326 Configuration of Serial Interface UART0 ............................................................................. 327 Registers Controlling Serial Interface UART0 .................................................................... 330 Operation of Serial Interface UART0.................................................................................... 335 14.4.1 Operation stop mode................................................................................................................335 14.4.2 Asynchronous serial interface (UART) mode ...........................................................................336 14.4.3 Dedicated baud rate generator ................................................................................................342 CHAPTER 15 SERIAL INTERFACE UART6 ...................................................................................... 347 15.1 15.2 15.3 15.4 Functions of Serial Interface UART6 ................................................................................... 347 Configuration of Serial Interface UART6 ............................................................................. 351 Registers Controlling Serial Interface UART6 .................................................................... 354 Operation of Serial Interface UART6.................................................................................... 363 15.4.1 Operation stop mode................................................................................................................363 15.4.2 Asynchronous serial interface (UART) mode ...........................................................................364 15.4.3 Dedicated baud rate generator ................................................................................................377 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11................................................................ 384 16.1 16.2 16.3 16.4 Functions of Serial Interfaces CSI10 and CSI11 ................................................................. 384 Configuration of Serial Interfaces CSI10 and CSI11 .......................................................... 385 Registers Controlling Serial Interfaces CSI10 and CSI11.................................................. 388 Operation of Serial Interfaces CSI10 and CSI11 ................................................................. 393 16.4.1 Operation stop mode................................................................................................................393 16.4.2 3-wire serial I/O mode ..............................................................................................................394 CHAPTER 17 SERIAL INTERFACE IIC0 ........................................................................................... 406 17.1 17.2 17.3 17.4 Functions of Serial Interface IIC0......................................................................................... 406 Configuration of Serial Interface IIC0 .................................................................................. 409 Registers to Control Serial Interface IIC0............................................................................ 412 I2C Bus Mode Functions ........................................................................................................ 425 17.4.1 17.5 Pin configuration ......................................................................................................................425 2 I C Bus Definitions and Control Methods............................................................................ 426 17.5.1 Start conditions ........................................................................................................................426 17.5.2 Addresses ................................................................................................................................427 17.5.3 Transfer direction specification ................................................................................................427 17.5.4 Acknowledge (ACK) .................................................................................................................428 17.5.5 Stop condition ..........................................................................................................................429 17.5.6 Wait..........................................................................................................................................430 17.5.7 Canceling wait..........................................................................................................................432 17.5.8 Interrupt request (INTIIC0) generation timing and wait control.................................................432 17.5.9 Address match detection method.............................................................................................433 17.5.10 Error detection .........................................................................................................................433 Preliminary User's Manual U17260EJ3V1UD 13 17.6 17.5.11 Extension code.........................................................................................................................434 17.5.12 Arbitration.................................................................................................................................435 17.5.13 Wakeup function.......................................................................................................................436 17.5.14 Communication reservation......................................................................................................437 17.5.15 Other cautions ..........................................................................................................................440 17.5.16 Communication operations.......................................................................................................442 17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence................................................................449 Timing Charts ......................................................................................................................... 470 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) .................... 477 18.1 18.2 18.3 18.4 Functions of Multiplier/Divider ............................................................................................. 477 Configuration of Multiplier/Divider ....................................................................................... 477 Register Controlling Multiplier/Divider ................................................................................ 481 Operations of Multiplier/Divider............................................................................................ 482 18.4.1 Multiplication operation.............................................................................................................482 18.4.2 Division operation.....................................................................................................................484 CHAPTER 19 INTERRUPT FUNCTIONS ............................................................................................ 486 19.1 19.2 19.3 19.4 Interrupt Function Types....................................................................................................... 486 Interrupt Sources and Configuration ................................................................................... 486 Registers Controlling Interrupt Functions .......................................................................... 491 Interrupt Servicing Operations ............................................................................................. 499 19.4.1 Maskable interrupt acknowledgement ......................................................................................499 19.4.2 Software interrupt request acknowledgement ..........................................................................501 19.4.3 Multiple interrupt servicing........................................................................................................502 19.4.4 Interrupt request hold ...............................................................................................................505 CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 506 20.1 20.2 20.3 Functions of Key Interrupt .................................................................................................... 506 Configuration of Key Interrupt.............................................................................................. 506 Register Controlling Key Interrupt ....................................................................................... 507 CHAPTER 21 STANDBY FUNCTION .................................................................................................. 508 21.1 21.2 Standby Function and Configuration................................................................................... 508 21.1.1 Standby function.......................................................................................................................508 21.1.2 Registers controlling standby function......................................................................................508 Standby Function Operation................................................................................................. 511 21.2.1 HALT mode ..............................................................................................................................511 21.2.2 STOP mode .............................................................................................................................516 CHAPTER 22 RESET FUNCTION........................................................................................................ 521 22.1 Register for Confirming Reset Source................................................................................. 529 CHAPTER 23 POWER-ON-CLEAR CIRCUIT...................................................................................... 530 23.1 14 Functions of Power-on-Clear Circuit ................................................................................... 530 Preliminary User's Manual U17260EJ3V1UD 23.2 23.3 23.4 Configuration of Power-on-Clear Circuit............................................................................. 531 Operation of Power-on-Clear Circuit ................................................................................... 531 Cautions for Power-on-Clear Circuit.................................................................................... 534 CHAPTER 24 LOW-VOLTAGE DETECTOR ....................................................................................... 536 24.1 24.2 24.3 24.4 24.5 Functions of Low-Voltage Detector ..................................................................................... 536 Configuration of Low-Voltage Detector............................................................................... 536 Registers Controlling Low-Voltage Detector ...................................................................... 537 Operation of Low-Voltage Detector ..................................................................................... 540 24.4.1 When used as reset .................................................................................................................541 24.4.2 When used as interrupt ............................................................................................................546 Cautions for Low-Voltage Detector...................................................................................... 551 CHAPTER 25 OPTION BYTE............................................................................................................... 554 25.1 25.2 Functions of Option Bytes .................................................................................................... 554 Format of Option Byte ........................................................................................................... 555 CHAPTER 26 FLASH MEMORY.......................................................................................................... 558 26.1 26.2 26.3 26.4 26.5 26.6 Internal Memory Size Switching Register ........................................................................... 558 Internal Expansion RAM Size Switching Register.............................................................. 560 Writing with Flash Programmer ........................................................................................... 561 Programming Environment................................................................................................... 564 Communication Mode ........................................................................................................... 564 Handling of Pins on Board.................................................................................................... 566 26.6.1 26.7 26.8 26.9 FLMD0 pin ...............................................................................................................................566 26.6.2 Serial interface pins..................................................................................................................566 26.6.3 RESET pin ...............................................................................................................................568 26.6.4 Port pins...................................................................................................................................568 26.6.5 REGC pin.................................................................................................................................568 26.6.6 Other signal pins ......................................................................................................................568 26.6.7 Power supply ...........................................................................................................................568 Programming Method............................................................................................................ 569 26.7.1 Controlling flash memory .........................................................................................................569 26.7.2 Flash memory programming mode ..........................................................................................569 26.7.3 Selecting communication mode ...............................................................................................570 26.7.4 Communication commands......................................................................................................571 Security Settings.................................................................................................................... 572 Flash Memory Programming by Self-Programming........................................................... 574 26.9.1 Boot swap function...................................................................................................................576 CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY) ............................................ 578 27.1 On-Chip Debug Security ID................................................................................................... 579 CHAPTER 28 INSTRUCTION SET ...................................................................................................... 580 28.1 Conventions Used in Operation List.................................................................................... 580 28.1.1 Operand identifiers and specification methods ........................................................................580 Preliminary User's Manual U17260EJ3V1UD 15 28.2 28.3 28.1.2 Description of operation column ...............................................................................................581 28.1.3 Description of flag operation column ........................................................................................581 Operation List ......................................................................................................................... 582 Instructions Listed by Addressing Type ............................................................................. 590 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 593 CHAPTER 30 PACKAGE DRAWINGS ................................................................................................ 612 CHAPTER 31 CAUTIONS FOR WAIT................................................................................................. 617 31.1 31.2 Cautions for Wait.................................................................................................................... 617 Peripheral Hardware That Generates Wait .......................................................................... 618 APPENDIX A DEVELOPMENT TOOLS............................................................................................... 619 A.1 A.2 A.3 A.4 A.5 A.6 Software Package .................................................................................................................. 622 Language Processing Software............................................................................................ 622 Control Software .................................................................................................................... 623 Flash Memory Writing Tools ................................................................................................. 623 Debugging Tools (Hardware) ................................................................................................ 624 A.5.1 When using in-circuit emulator QB-78K0KX2...........................................................................624 A.5.2 When using on-chip debug emulator QB-78K0MINI.................................................................625 Debugging Tools (Software) ................................................................................................. 625 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 626 APPENDIX C REGISTER INDEX ......................................................................................................... 628 C.1 C.2 Register Index (In Alphabetical Order with Respect to Register Names) ........................ 628 Register Index (In Alphabetical Order with Respect to Register Symbol) ....................... 632 APPENDIX D REVISION HISTORY ..................................................................................................... 636 D.1 D.2 16 Major Revisions in This Edition............................................................................................ 636 Revisions History up to Previous Edition ........................................................................... 643 Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE 1.1 Features { Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) { General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) { ROM, RAM capacities Item Program Memory (ROM) Part Number PD78F0531 Flash memory Note Data Memory Internal High-Speed RAM Note Internal Expansion RAM Note - 16 KB 768 bytes PD78F0532 24 KB 1 KB PD78F0533 32 KB PD78F0534 48 KB 1 KB PD78F0535 60 KB 2 KB PD78F0536 96 KB 4 KB PD78F0537, 78F0537D 128 KB 6 KB Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). For IMS and IXS, see 26.1 Memory Size Switching Register and 26.2 Internal Expansion RAM Size Switching Register. { On-chip single-power-supply flash memory { Self-programming (with boot swap function) { On-chip debug function (PD78F0537D only)Note { On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) { On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock) { On-chip multiplier/divider (16 bits x 16 bits, 32 bits / 16 bits) (PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only) { On-chip key interrupt function { On-chip clock output/buzzer output controller { I/O ports: 55 (N-ch open drain: 4) Note The PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the restriction on the number of times the flash memory can be rewritten. NEC Electronics does not accept any complaint about this product. Preliminary User's Manual U17260EJ3V1UD 17 CHAPTER 1 OUTLINE { Timer PD78F0531, 78F0532, 78F0533: 7 channels PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 8 channels * 16-bit timer/event counter: 2 channelsNote * 8-bit timer/event counter: 2 channels * 8-bit timer: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel Note PD78F0531, 78F0532, 78F0533: 1 channel { Serial interface PD78F0531, 78F0532, 78F0533: 3 channels PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 4 channels * UART (LIN (Local Interconnect Network)-bus supported: 1 channel * CSI/UARTNote1: * CSI Note2 1 channel : 1 channel * I2C: 1 channel Notes 1. Select either of the functions of these alternate-function pins. 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only { 10-bit resolution A/D converter (AVREF = 2.3 to 5.5 V): 8 channels { Power supply voltage: VDD = 1.8 to 5.5 V { Operating ambient temperature: * TA = -40 to +85C: (T), (S), (R) products * TA = -40 to +125C: (T2) product 1.2 Applications { Automotive equipment ((A), (A1), (A2) grade products, under development) * System control for body electricals (power windows, keyless entry reception, etc.) * Sub-microcontrollers for control { Car audio { AV equipment, home audio { PC peripheral equipment (keyboards, etc.) { Household electrical appliances * Air conditioners * Microwave ovens, electric rice cookers { Industrial equipment * Pumps * Vending machines * FA (Factory Automation) 18 Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE 1.3 Ordering Information * Flash memory version (1/4) Part Number PD78F0531GB(T)-UEU-A PD78F0531GB(T2)-UEU-A PD78F0531GB(S)-UEU-A PD78F0531GB(R)-UEU-A PD78F0531GC(T)-UBS-A PD78F0531GC(T2)-UBS-A PD78F0531GC(S)-UBS-A PD78F0531GC(R)-UBS-A PD78F0531GK(T)-UET-A PD78F0531GK(T2)-UET-A PD78F0531GK(S)-UET-A PD78F0531GK(R)-UET-A PD78F0531GA(T)-9EV-A PD78F0531GA(T2)-9EV-A PD78F0531GA(S)-9EV-A PD78F0531GA(R)-9EV-A PD78F0531FC(T)-AA1-A PD78F0531FC(S)-AA1-A PD78F0531FC(R)-AA1-A PD78F0532GB(T)-UEU-A PD78F0532GB(T2)-UEU-A PD78F0532GB(S)-UEU-A PD78F0532GB(R)-UEU-A PD78F0532GC(T)-UBS-A PD78F0532GC(T2)-UBS-A PD78F0532GC(S)-UBS-A PD78F0532GC(R)-UBS-A PD78F0532GK(T)-UET-A PD78F0532GK(T2)-UET-A PD78F0532GK(S)-UET-A PD78F0532GK(R)-UET-A PD78F0532GA(T)-9EV-A PD78F0532GA(T2)-9EV-A PD78F0532GA(S)-9EV-A PD78F0532GA(R)-9EV-A PD78F0532FC(T)-AA1-A PD78F0532FC(S)-AA1-A PD78F0532FC(R)-AA1-A Package 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) Preliminary User's Manual U1260EJ3V1UD 19 CHAPTER 1 OUTLINE * Flash memory version (2/4) Part Number PD78F0533GB(T)-UEU-A PD78F0533GB(T2)-UEU-A PD78F0533GB(S)-UEU-A PD78F0533GB(R)-UEU-A PD78F0533GC(T)-UBS-A PD78F0533GC(T2)-UBS-A PD78F0533GC(S)-UBS-A PD78F0533GC(R)-UBS-A PD78F0533GK(T)-UET-A PD78F0533GK(T2)-UET-A PD78F0533GK(S)-UET-A PD78F0533GK(R)-UET-A PD78F0533GA(T)-9EV-A PD78F0533GA(T2)-9EV-A PD78F0533GA(S)-9EV-A PD78F0533GA(R)-9EV-A PD78F0533FC(T)-AA1-A PD78F0533FC(S)-AA1-A PD78F0533FC(R)-AA1-A PD78F0534GB(T)-UEU-A PD78F0534GB(T2)-UEU-A PD78F0534GB(S)-UEU-A PD78F0534GB(R)-UEU-A PD78F0534GC(T)-UBS-A PD78F0534GC(T2)-UBS-A PD78F0534GC(S)-UBS-A PD78F0534GC(R)-UBS-A PD78F0534GK(T)-UET-A PD78F0534GK(T2)-UET-A PD78F0534GK(S)-UET-A PD78F0534GK(R)-UET-A PD78F0534GA(T)-9EV-A PD78F0534GA(T2)-9EV-A PD78F0534GA(S)-9EV-A PD78F0534GA(R)-9EV-A PD78F0534FC(T)-AA1-A PD78F0534FC(S)-AA1-A PD78F0534FC(R)-AA1-A 20 Package 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE * Flash memory version (3/4) Part Number PD78F0535GB(T)-UEU-A PD78F0535GB(T2)-UEU-A PD78F0535GB(S)-UEU-A PD78F0535GB(R)-UEU-A PD78F0535GC(T)-UBS-A PD78F0535GC(T2)-UBS-A PD78F0535GC(S)-UBS-A PD78F0535GC(R)-UBS-A PD78F0535GK(T)-UET-A PD78F0535GK(T2)-UET-A PD78F0535GK(S)-UET-A PD78F0535GK(R)-UET-A PD78F0535GA(T)-9EV-A PD78F0535GA(T2)-9EV-A PD78F0535GA(S)-9EV-A PD78F0535GA(R)-9EV-A PD78F0535FC(T)-AA1-A PD78F0535FC(S)-AA1-A PD78F0535FC(R)-AA1-A PD78F0536GB(T)-UEU-A PD78F0536GB(T2)-UEU-A PD78F0536GB(S)-UEU-A PD78F0536GB(R)-UEU-A PD78F0536GC(T)-UBS-A PD78F0536GC(T2)-UBS-A PD78F0536GC(S)-UBS-A PD78F0536GC(R)-UBS-A PD78F0536GK(T)-UET-A PD78F0536GK(T2)-UET-A PD78F0536GK(S)-UET-A PD78F0536GK(R)-UET-A PD78F0536GA(T)-9EV-A PD78F0536GA(T2)-9EV-A PD78F0536GA(S)-9EV-A PD78F0536GA(R)-9EV-A PD78F0536FC(T)-AA1-A PD78F0536FC(S)-AA1-A PD78F0536FC(R)-AA1-A Package 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) Preliminary User's Manual U1260EJ3V1UD 21 CHAPTER 1 OUTLINE * Flash memory version (4/4) Part Number PD78F0537GB(T)-UEU-A PD78F0537GB(T2)-UEU-A PD78F0537GB(S)-UEU-A PD78F0537GB(R)-UEU-A PD78F0537GC(T)-UBS-A PD78F0537GC(T2)-UBS-A PD78F0537GC(S)-UBS-A PD78F0537GC(R)-UBS-A PD78F0537GK(T)-UET-A PD78F0537GK(T2)-UET-A PD78F0537GK(S)-UET-A PD78F0537GK(R)-UET-A PD78F0537GA(T)-9EV-A PD78F0537GA(T2)-9EV-A PD78F0537GA(S)-9EV-A PD78F0537GA(R)-9EV-A PD78F0537FC(T)-AA1-A PD78F0537FC(S)-AA1-A PD78F0537FC(R)-AA1-A PD78F0537DGB(T)-UEU-ANote PD78F0537DGC(T)-UBS-ANote PD78F0537DGK(T)-UET-ANote PD78F0537DGA(T)-9EV-ANote PD78F0537DFC(T)-AA1-ANote Package 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic FLGA (5x5) 64-pin plastic LQFP (10x10) 64-pin plastic LQFP (14x14) 64-pin plastic LQFP (12x12) 64-pin plastic TQFP (7x7) 64-pin plastic FLGA (5x5) Note The PD78F0537D has an on-chip debug function. Do not use this product for mass production, because its reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints about this product. Remark Products with -A at the end of the part number are lead-free products. The standard quality versions of this product are classified by production process as follows. (T), (T2): General 22 (S): Individual contract (R): For automobile accessories Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) * 64-pin plastic LQFP (10 x 10) * 64-pin plastic LQFP (14 x 14) * 64-pin plastic LQFP (12 x 12) P140/PCL/INTP6 P141/BUZ/INTP7 P00/TI000 P01/TI010/TO00 P02/SO11Note2 P03/SI11Note2 P04/SCK11Note2 P130 P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 * 64-pin plastic TQFP (7 x 7) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P120/INTP0/EXLVI P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK/OCD0BNote1 P121/X1/OCD0ANote1 REGC VSS EVSS VDD EVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSS AVREF P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10 P13/TxD6 P14/RxD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P53 P52 P51 P50 P31/INTP2/OCD1ANote1 P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TO01Note2/TI011Note2 P05/SSI11Note2/TI001Note2 P32/INTP3/OCD1BNote1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes 1. PD78F0537D (product with on-chip debug function) only 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 F: target). 3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. Preliminary User's Manual U1260EJ3V1UD 23 CHAPTER 1 OUTLINE * 64-pin plastic FLGA (5 x 5) Top View Bottom View 8 7 6 5 4 3 2 1 H G F E D C B A A B C D E F G H Index mark Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name A1 AVSS C1 P24/ANI4 E1 P130 A2 AVREF C2 P23/ANI3 E2 P20/ANI0 Note2 Pin No. Pin Name G1 P141/BUZ/INTP7 G2 P140/PCL/INTP6 G3 P43 A3 P11/SI10/RxD0 C3 P27/ANI7 E3 P03/SI11 A4 P13/TxD6 C4 P10/SCK10/TxD0 E4 P42 G4 RESET A5 P16/TOH1/INTP5 C5 P17/TI50/TO50 E5 P77/KR7 G5 REGC A6 P53 C6 P30/INTP1 E6 P33/TI51/TO51/INTP4 G6 VSS A7 P51 C7 P31/INTP2/ E7 P74/KR4 G7 VDD E8 P76/KR6 G8 P61/SDA0 F1 P01/TI010/TO00 H1 P120/INTP0/EXLVI F2 P00/TI000 H2 P124/XT2/EXCLKS H3 P123/XT1 FLMD0 OCD1A A8 C8 P32/INTP3/ OCD1B Note1 Note1 P06 /TO01 TI011 Note2 / Note2 B1 P25/ANI5 D1 P21/ANI1 B2 P26/ANI6 D2 P22/ANI2 B3 P12/SO10 D3 P04/SCK11 B4 P15/TOH0 D4 B5 P14/RxD6 D5 Note2 Note2 F3 P02/SO11 P72/KR2 F4 P41 H4 P70/KR0 F5 P40 H5 P122/X2/EXCLK /OCD0B B6 P52 B7 P50 B8 P05/SSI11 TI001 Note2 / D6 P71/KR1 F6 P60/SCL0 H6 P121/X1/OCD0A D7 P75/KR5 F7 P62/EXSCL0 H7 EVSS D8 P73/KR3 F8 P63 H8 EVDD Note2 Notes 1. PD78F0537D (product with on-chip debug function) only 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only Cautions 1. Make AVSS the same potential as VSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 F: target). 3. ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 24 Note1 Preliminary User's Manual U17260EJ3V1UD Note1 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input P60 to P63: Port 6 AVREF: Analog reference voltage P70 to P77: Port 7 AVSS: Analog ground P120 to P124: Port 12 BUZ: Buzzer output P130: Port 13 EVDD: Power supply for port P140, P141: Port 14 EVSS: Ground for port PCL: Programmable clock output EXCLK: External clock input REGC Regulator capacitance (main system clock) RESET: Reset Receive data External clock input RxD0, RxD6: (subsystem clock) SCK10, SCK11 Note2, External potential input SCL0: Serial clock input/output for low-voltage detector SDA0: Serial data input/output EXSCL0: External serial clock input SI10, SI11 Note2: Serial data input FLMD0: Flash programming mode SO10, SO11 Note2: Serial data output EXCLKS: EXLVI: Note2 INTP0 to INTP7: External interrupt input SSI11 KR0 to KR7: Key return TI000, TI010, OCD0A Note1, OCD0B Note1 OCD1A Note1 : Serial interface chip select input TI001 Note2, TI011 Note2, TI50, TI51: , TO00, TO01 , Timer input Note2 , OCD1B Note1: On chip debug input/output TO50, TO51, P00 to P06: Port 0 TOH0, TOH1: Timer output P10 to P17: Port 1 TxD0, TxD6: Transmit data P20 to P27: Port 2 VDD: Power supply P30 to P33: Port 3 VSS: Ground P40 to P43: Port 4 X1, X2: Crystal oscillator (main system clock) P50 to P53: Port 5 XT1, XT2: Crystal oscillator (subsystem clock) Notes 1. PD78F0537D (product with on-chip debug function) only 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only Preliminary User's Manual U1260EJ3V1UD 25 CHAPTER 1 OUTLINE 1.5 78K0/Kx2 Series Lineup ROM RAM 128 KB 7 KB 96 KB 60 KB 78K0/KB2 78K0/KC2 78K0/KD2 30 Pins 44 Pins 48 Pins - - - 5 KB - - 3 KB - - 78K0/KE2 52 Pins PD78F0527D 78K0/KF2 64 Pins Note PD78F0537D 80 Pins Note PD78F0547DNote PD78F0527 PD78F0537 PD78F0547 PD78F0526 PD78F0536 PD78F0546 PD78F0525 PD78F0535 PD78F0545 PD78F0514 PD78F0524 PD78F0534 PD78F0544 PD78F0513 PD78F0523 PD78F0533 - - PD78F0515D Note PD78F0515 48 KB 32 KB 2 KB 1 KB - PD78F0503D - Note PD78F0503 PD78F0513D Note PD78F0513 1 KB PD78F0502 PD78F0512 PD78F0522 PD78F0532 - 16 KB 768 B PD78F0501 PD78F0511 PD78F0521 PD78F0531 - 8 KB PD78F0500 - - - - 24 KB 512 B Note Product with on-chip debug function 26 Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx2 Series is shown below. (1/2) Part Number 78K0/KB2 Item 78K0/KC2 30/36 Pins Flash memory (KB) RAM (KB) 44 Pins 48 Pins 8 16 24 32 16 24 32 16 24 32 48 60 0.5 0.75 1 1 0.75 1 1 0.75 1 1 2 3 Bank (flash memory) - Power supply voltage VDD = 1.8 to 5.5 V Regulator Provided 0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 s (5 MHz: VDD = 1.8 to 5.5 V) Clock Main Minimum instruction execution time High-speed system 20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V Internal high-speed oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V - Subsystem 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Timer Port Internal low-speed oscillation 240 kHz (TYP.): VDD = 1.8 to 5.5 V Total 23 37 41 N-ch O.D. (6 V tolerance) 2 4 4 16 bits (TM0) 1 ch 8 bits (TM5) 2 ch 8 bits (TMH) 2 ch - Watch 1 ch Serial interface WDT 1 ch 3-wire CSI - Automatic transmit/ receive 3-wire CSI - UART/3-wire CSI Note 1 ch UART supporting LINbus 1 ch 2 I C bus Interrupt 10-bit A/D 1 ch 4 ch 8 ch External 6 Internal 14 16 - 4 ch Key interrupt 7 Reset RESET pin POC LVI Provided 1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MAX.)) The detection level of the supply voltage is selectable in 16 steps. WDT Provided - Clock output/buzzer output Operating ambient temperature Clock output only - Multiplier/divider On-chip debug function 8 PD78F0503D only PD78F0513D only Provided PD78F0515D only -40 to +85C ((T), (R), (S) products), -40 to +125C ((T2) product) Note Select either of the functions of these alternate-function pins. Preliminary User's Manual U1260EJ3V1UD 27 CHAPTER 1 OUTLINE (2/2) Part Number 78K0/KD2 Item 78K0/KE2 52 Pins Flash memory (KB) RAM (KB) 64 Pins 24 32 48 60 96 128 16 24 32 48 60 96 128 48 60 96 128 0.75 1 1 2 3 5 7 0.75 1 1 2 3 5 7 2 3 5 7 4 6 4 6 4 6 - - Power supply voltage Provided 0.1 s (20 MHz: VDD = 4.0 to 5.5 V)/0.2 s (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 s (5 MHz: VDD = 1.8 to 5.5 V) Clock Main Minimum instruction execution time High-speed system 20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V Internal high-speed oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V Subsystem 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Port Internal low-speed oscillation 240 kHz (TYP.): VDD = 1.8 to 5.5 V Total 45 55 71 N-ch O.D. (6 V tolerance) 4 4 4 Timer 16 bits (TM0) 1 ch 2 ch 8 bits (TM5) 2 ch 8 bits (TMH) 2 ch Watch 1 ch WDT 1 ch - Serial interface 3-wire CSI - Automatic transmit/ receive 3-wire CSI UART/3-wire CSI 1 ch 1 ch Note 1 ch UART supporting LINbus 1 ch 2 1 ch 10-bit A/D 8 ch I C bus Interrupt - VDD = 1.8 to 5.5 V Regulator External 8 Internal 9 16 19 Key interrupt Provided 1.59 V 0.15 V (rise time to 1.8 V: 3.6 ms (MAX.)) POC LVI The detection level of the supply voltage is selectable in 16 steps. WDT Provided Clock output/buzzer output Multiplier/divider On-chip debug function Operating ambient temperature 20 8 ch RESET pin Reset 80 Pins 16 Bank (flash memory) Clock output only - Provided PD78F0527D only Provided - Provided PD78F0537D only PD78F0547D only -40 to +85C ((T), (R), (S) products), -40 to +125C ((T2) product) Note Select either of the functions of these alternate-function pins. 28 78K0/KF2 Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 TI000/P00 (LINSEL) RxD6/P14 (LINSEL) 16-bit TIMER/ EVENT COUNTER 00 TO01Note2/TI011Note2/P06 16-bit TIMER/ EVENT COUNTER 01Note2 TI001Note2/P05 TOH0/P15 PORT 0 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 4 P30 to P33 PORT 4 4 P40 to P43 PORT 5 4 P50 to P53 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 PORT 12 5 P120 to P124 8-bit TIMER H0 TOH1/P16 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER 8-bit TIMER/ EVENT COUNTER 50 TI50/TO50/P17 8-bit TIMER/ EVENT COUNTER 51 TI51/TO51/P33 WATCH TIMER PORT 13 78K/0 CPU CORE BANK RxD0/P11 TxD0/P10 SERIAL INTERFACE UART0 RxD6/P14 TxD6/P13 SERIAL INTERFACE UART6 LINSEL SI10/P11 SO10/P12 SCK10/P10 SERIAL INTERFACE CSI10 SI11Note2/P03 SO11Note2/P02 SCK11Note2/P04 SSI11Note2/P05 Notes 1. INTERNAL HIGH-SPEED RAM INTERNAL EXPANSION RAMNote2 P140, P141 BUZZER OUTPUT BUZ/P141 CLOCK OUTPUT CONTROL PCL/P140 POWER ON CLEAR/ LOW VOLTAGE INDICATOR KEY RETURN POC/LVI CONTROL 8 EXLVI/P120 KR0/P70 to KR7/P77 RESET CONTROL SERIAL INTERFACE IIC0 ON-CHIP DEBUGNote3 8 SYSTEM CONTROL A/D CONVERTER VDD, VSS, FLMD0 EVDD EVSS 4 INTP5/P16 INTP6/P140, INTP7/P141 2 MULTIPLIER& DIVIDERNote2 RxD6/P14 (LINSEL) INTP0/P120(LINSEL) INTP1/P30 to INTP4/P33 PORT 14 Note1 SERIAL INTERFACE CSI11Note2 EXSCL0/P62 SDA0/P61 SCL0/P60 ANI0/P20 to ANI7/P27 AVREF AVSS FLASH MEMORY P130 INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 INTERNAL HIGH-SPEED OSCILLATOR VOLTAGE REGULATOR 2 OCD0ANote3/X1, OCD1ANote3/P31 OCD0BNote3/X2, OCD1BNote3/P32 REGC Available only in the PD78F0536, 78F0537, and 78F0537D. 2. Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 3. Available only in the PD78F0537D. Preliminary User's Manual U1260EJ3V1UD 29 CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) PD78F0531 PD78F0532 PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537 PD78F0537D Item Internal memory (bytes) Flash memory (self-programming Note 1 supported) 16 K 24 K 768 1K 32 K Expansion RAM Note 1 60 K - Note 2 Memory bank High-speed RAM 48 K - Note 1 1K 2K 96 K 128 K 4 6 4K 6K Memory space 64 KB Main system High-speed system clock clock (oscillation frequency) Internal high-speed oscillation clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V, 1 to 5 MHz: VDD = 1.8 to 5.5 V Subsystem clock (oscillation frequency) XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V Internal low-speed oscillation clock (for TMH1, WDT) Internal oscillation 240 kHz (TYP.): VDD = 1.8 to 5.5 V General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Internal oscillation 8 MHz (TYP.): VDD = 1.8 to 5.5 V Minimum instruction execution time 0.1 s (high-speed system clock: @ fXH = 20 MHz operation) 0.25 s (TYP.) (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation) 122 s (subsystem clock: @ fSUB = 32.768 kHz operation) Instruction set * 8-bit operation, 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, and Boolean operation) I/O ports Total: 55 CMOS I/O: 50 CMOS output: * BCD adjust, etc. 1 N-ch open-drain I/O (6 V tolerance): 4 Timers * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * 8-bit timer: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel Timer outputs * * * * * 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels 8-bit timer: 2 channels Watch timer: 1 channel Watchdog timer: 1 channel 5 (PWM output: 4, PPG output: 1) 6 (PWM output: 4, PPG output: 2) Clock output * 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (peripheral hardware clock: @ fPRS = 20 MHz operation) * 32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation) Buzzer output 2.44 kHz, 4.88 kHz, 9.77 kHz, 19.54 kHz (peripheral hardware clock: @ fPRS = 20 MHz operation) A/D converter 10-bit resolution x 8 channels (AVREF = 2.3 to 5.5 V) Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). 2. Banks to be used can be changed using the bank select register (BANK). 30 Preliminary User's Manual U17260EJ3V1UD CHAPTER 1 OUTLINE (2/2) PD78F0531 PD78F0532 PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537 PD78F0537D Item Serial interface * * * * * UART mode supporting LINbus: 1 channel * 3-wire serial I/O mode/UART Note mode : 1 channel 2 * I C bus mode: 1 channel * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits remainder of 16 bits (division) - Multiplier/divider UART mode supporting LIN-bus: 1 channel Note 3-wire serial I/O mode/UART mode : 1 channel 3-wire serial I/O mode: 1 channel 2 I C bus mode: 1 channel Vectored Internal interrupt sources External 16 19 Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). Reset * * * * 9 Reset using RESET pin Internal reset by watchdog timer Internal reset by power-on-clear Internal reset by low-voltage detector - On-chip debug function Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature * TA = -40 to +85C ((T), (R), (S) products) Package * * * * * Provided * TA = -40 to +125C ((T2) product) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic LQFP (12 x 12) 64-pin plastic TQFP (7 x 7) 64-pin plastic FLGA (5 x 5) Note Select either of the functions of these alternate-function pins. Caution The operating voltage range may be changed after evaluation of the device. An outline of the timer is shown below. 16-Bit Timer/ Event Counters Note 1 00 and 01 TM00 3. Watchdog Timer TM50 TM51 TMH0 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel - - - - PPG output 1 output 1 output - - - - - - PWM output - - 1 output 1 output 1 output 1 output - - Pulse width measurement 2 inputs 2 inputs - - - - - - Square-wave output 1 output 1 output 1 output 1 output 1 output 1 output - - Carrier generator - - - - - Watch Timer - - - - - - Watchdog timer - - - - - - - 1 channel 2 2 1 1 1 1 1 - Interrupt source 2. Watch Timer 1 channel External event counter Notes 1. Note 1 8-Bit Timers H0 and H1 1 channel Function Interval timer TM01 8-Bit Timer/ Event Counters 50 and 51 TMH1 - Note 2 1 channel 1 channel 1 output Note 3 - 1 channel - - Note 2 Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. In the watch timer, the watch timer function and interval timer function can be used simultaneously. TM51 and TMH1 can be used in combination as a carrier generator mode. Preliminary User's Manual U1260EJ3V1UD 31 CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 and P121 to P124 VDD * P121 to P124 * Pins other than port (1) Port functions (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 Note1 SO11 Use of an on-chip pull-up resistor can be specified by a software P03 TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Alternate Function SI11 setting. Note1 P04 SCK11 P05 TI001 Note1 / SSI11 P06 P10 I/O Port 1. Input port 8-bit I/O port. P11 TI011 Note1 TO01 Note1 / SCK10/TxD0 SO10 Use of an on-chip pull-up resistor can be specified by a software P13 Note1 SI10/RxD0 Input/output can be specified in 1-bit units. P12 Note1 TxD6 setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 I/O Port 2. Analog input ANI0 to ANI7 Input port INTP1 8-bit I/O port. Input/output can be specified in 1-bit units. P30 P31 P32 P33 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note2 INTP3/OCD1B Note2 TI51/TO51/INTP4 Notes 1. Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 2. PD78F0537D only 32 INTP2/OCD1A Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2) Function Name P40 to P43 I/O I/O Function Port 4. After Reset Alternate Function Input port - Input port - 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P53 I/O Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P60 I/O Port 6. Input port 4-bit I/O port. P61 SDA0 Output of P60 to P63 is N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. P62 SCL0 EXSCL0 - P63 P70 to P77 I/O Port 7. Input port KR0 to KR7 Input port INTP0/EXLVI 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 5-bit I/O port. P121 X1/OCD0A Input/output can be specified in 1-bit units. P122 Note X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 XT1 specified by a software setting. P124 P130 Note XT2/EXCLKS Output Port 13. Output port - 1-bit output-only port. P140 P141 I/O Port 14. Input port 2-bit I/O port. PCL/INTP6 BUZ/INTP7 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note PD78F0537D only Preliminary User's Manual U17260EJ3V1UD 33 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (1/2) Function Name I/O Input INTP0 Function External interrupt request input for which the valid edge (rising After Reset Input port edge, falling edge, or both rising and falling edges) can be INTP1 Alternate Function P120/EXLVI P30 specified P31/OCD1A Note2 INTP3 P32/OCD1B Note2 INTP4 P33/TI51/TO51 INTP5 P16/TOH1 INTP6 P140/PCL INTP7 P141/BUZ INTP2 SI10 SI11 Input Serial data input to serial interface Input port P11/RxD0 Output Serial data output from serial interface Input port P12 Note1 P03 SO10 SO11 Note1 P02 SDA0 SCK10 SCK11 I/O Serial data I/O for serial interface Input port P61 I/O Clock input/output for serial interface Input port P10/TxD0 Note1 P04 SCL0 P60 EXSCL0 Input External clock input for serial interface. Input port P62 To input an external clock, input a clock of 6.4 MHz. SSI11 Note1 RxD0 Input Chip select input for serial interface Input port P05/TI001 Input Serial data input to asynchronous serial interface Input port P11/SI10 RxD6 P14 Output TxD0 Serial data output from asynchronous serial interface Input port TxD6 P10/SCK10 P13 TI000 Input External count clock input to 16-bit timer/event counter 00 Input port P00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 Note1 External count clock input to 16-bit timer/event counter 01 TI001 P05/SSI11 Note1 Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01 Capture trigger input to capture register (CR000) of 16-bit TI010 P01/TO00 timer/event counter 00 Note1 Capture trigger input to capture register (CR001) of 16-bit TI011 P06/TO01 Note timer/event counter 01 Output TO00 TO01 TI50 TI51 Note1 16-bit timer/event counter 00 output 16-bit timer/event counter 01 output Input External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 Notes 1. PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only 2. PD78F0537D only 34 Input port Preliminary User's Manual U17260EJ3V1UD P01/TI010 P06/TI011 Input port Note1 P17/TO50 P33/TO51/INTP4 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Function Name TO50 I/O Output Function 8-bit timer/event counter 50 output After Reset Input port Alternate Function P17/TI50 TO51 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 8-bit timer H0 output P15 TOH1 8-bit timer H1 output P16/INTP5 PCL Output Clock output (for trimming of high-speed system clock, Input port P140/INTP6 subsystem clock) BUZ Output Buzzer output Input port P141/INTP7 ANI0 to ANI7 Input A/D converter analog input Analog input P20 to P27 AVREF Input A/D converter reference voltage input and positive power - - - - supply for P20 to P27 and A/D converter - AVSS A/D converter ground potential. Make the same potential as EVSS or VSS. KR0 to KR7 Input - REGC Key interrupt input Connecting regulator output (2.5 V) stabilization capacitance Input port P70 to P77 - - - - for internal operation. Connect to VSS via a capacitor (0.47 F: target). RESET Input System reset input EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0 X1 Input Connecting resonator for main system clock Input port P121/OCD0A X2 - P122/EXCLK/ OCD0B EXCLK Input External clock input for main system clock Input port Input XT2 - EXCLKS Input Connecting resonator for subsystem clock External clock input for subsystem clock Note P122/X2/ OCD0B XT1 Note Note Input port P123 Input port P124/EXCLKS Input port P124/XT2 VDD - Positive power supply (P121 to P124 and except for ports) - - EVDD - Positive power supply for ports (except for P20 to P27 and - - P121 to P124) VSS - Ground potential (P121 to P124 and except for ports) - - EVSS - Ground potential for ports (except for P20 to P27 and P121 to - - - - P124) - FLMD0 OCD0A Note OCD1A Note OCD0B Note OCD1B Note Input Flash memory programming mode setting Connection for on-chip debug mode setting pins (PD78F0537D only) - Input port P121/X1 P31/INTP2 P122/X2/EXCLK P32/INTP3 Note PD78F0537D only Preliminary User's Manual U17260EJ3V1UD 35 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output port in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input. (a) TI000, TI001Note These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01. (b) TI010, TI011Note These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01Note These are timer output pins of 16-bit timer/event counters 00 and 01. (d) SI11Note This is a serial data input pin of serial interface CSI11. (e) SO11Note This is a serial data output pin of serial interface CSI11. (f) SCK11Note This is a serial clock I/O pin of serial interface CSI11. (g) SSI11Note This is a chip select input pin of serial interface CSI11. Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only 36 Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output port in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial data input pin of serial interface CSI10. (b) SO10 This is a serial data output pin of serial interface CSI10. (c) SCK10 This is a serial clock I/O pin of serial interface CSI10. (d) RxD0 This is a serial data input pin of serial interface UART0. (e) RxD6 This is a serial data input pin of serial interface UART6. (f) TxD0 This is a serial data output pin of serial interface UART0. (g) TxD6 This is a serial data output pin of serial interface UART6. (h) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (i) TO50 This is a timer output pin of 8-it timer/event counter 50. (j) TOH0, TOH1 These are the timer output pins of 8-bit timers H0 and H1. (k) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Preliminary User's Manual U17260EJ3V1UD 37 CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter. Caution ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input and timer I/O. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin from 8-bit timer/event counter 51. Caution In the PD78F0537D, be sure to pull the P31 pin down before a reset release to prevent malfunction. Remark Only for the PD78F0537D, P31 and P32 can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). 38 Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.5 P40 to P43 (port 4) P40 to P43 function as a 4-bit I/O port. P40 to P43 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). 2.2.6 P50 to P53 (port 5) P50 to P53 function as a 4-bit I/O port. P50 to P53 can be set to input or output port in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (PU5). 2.2.7 P60 to P63 (port 6) P60 to P63 function as a 4-bit I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and external clock input. The following operation modes can be specified in 1-bit units. (1) Port mode P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). Output of P60 to P63 is N-ch open-drain output (6 V tolerance). (2) Control mode P60 to P63 function as serial interface data I/O, clock I/O, and external clock input. (a) SDA0 This is a serial data I/O pin for serial interface IIC0. (b) SCL0 This is a serial clock I/O pin for serial interface IIC0. (c) EXSCL0 This is an external clock input pin to serial interface IIC0. To input an external clock, input a clock of 6.4 MHz. 2.2.8 P70 to P77 (port 7) P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P77 function as key interrupt input pins. (a) KR0 to KR7 These are the key interrupt input pins Preliminary User's Manual U17260EJ3V1UD 39 CHAPTER 2 PIN FUNCTIONS 2.2.9 P120 to P124 (port 12) P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. The following operation modes can be specified in 1-bit units. (1) Port mode P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. (a) INTP0 This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are the pins for connecting a resonator for main system clock. (d) EXCLK This is an external clock input pin for main system clock. (e) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. (f) EXCLKS This is an external clock input pin for subsystem clock. Remark Only for the PD78F0537D, X1 and X2 can be used as on-chip debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For how to connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). 2.2.10 P130 (port 13) P130 functions as a 1-bit output-only port. Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure for Remark in 5.2.10 Port 13). 40 Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.2.11 P140, P141 (port 14) P140 and P141 function as a 2-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output. The following operation modes can be specified in 1-bit units. (1) Port mode P140 and P141 function as a 2-bit I/O port. P140 and P141 can be set to input or output port in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 and P141 function as external interrupt request input, clock output, buzzer output. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) PCL This is a clock output pin. (c) BUZ This is a buzzer output pin. 2.2.12 AVREF This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27 and A/D converter. When the A/D converter is not used, connect this pin directly to EVDD or VDDNote. Note Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. 2.2.13 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin. 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 F: target). REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. Preliminary User's Manual U17260EJ3V1UD 41 CHAPTER 2 PIN FUNCTIONS 2.2.16 VDD and EVDD VDD is the positive power supply pin for other than P121 to P124 and ports. EVDD is the positive power supply pin for ports other than P20 to P27 and P121 to P124. 2.2.17 VSS and EVSS VSS is the ground potential pin for other than P121 to P124 and ports. EVSS is the ground potential pin for ports other than P20 to P27 and P121 to P124. 2.2.18 FLMD0 This is a pin for setting flash memory programming mode. Connect FLMD0 to EVSS or VSS in the normal operation mode. In flash memory programming mode, connect this pin to the flash programmer. 42 Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (1/2) Pin Name I/O Circuit Type P00/TI000 5-AH I/O P03/SI11 Note 1 P05/SSI11 P06/TI011 Input: Independently connect to EVDD or EVSS via a resistor. 5-AG 5-AG (PD78F0531, Note 1 P04/SCK11 Recommended Connection of Unused Pins Output: Leave open. P01/TI010/TO00 P02/SO11 I/O 78F0532, 78F0533), Note 1 Note 1 Note 1 /TI001 Note 1 Note 1 /TO01 P10/SCK10/TxD0 5-AH (PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) 5-AH P11/SI10/RxD0 5-AG P12/SO10 P13/TxD6 P14/RxD6 5-AH P15/TOH0 5-AG P16/TOH1/INTP5 5-AH P17/TI50/TO50 P20/ANI0 to P27/ANI7 11-G Note 2 <Analog setting> Connect to AVREF or AVSS. <Digital setting> Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 5-AH P30/INTP1 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P31/INTP2 P32/INTP3 P33/TI51/TO51/INTP4 P40 to P43 5-AG P50 to P53 P60/SCL0 13-AD Input: Connect to EVSS. Output: Leave this pin open at low-level output after clearing P61/SDA0 the output latch of the port to 0. P62/EXSCL0 P63 13-P P70/KR0 to P77/KR7 5-AH P120/INTP0/EXLVI Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Notes 1. Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 2. P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset. Preliminary User's Manual U17260EJ3V1UD 43 CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type Note 1 P121/X1 37 P122/X2/EXCLK P123/XT1 I/O Recommended Connection of Unused Pins Input: I/O Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Note 1 Note 1 P124/XT2/EXCLKS Note 1 P130 3-C Output Leave open. P140/PCL/INTP6 5-AH I/O Input: P141/BUZ/INTP7 RESET 2 Input FLMD0 38 Input AVREF AVSS Independently connect to EVDD or EVSS via a resistor. Output: Leave open. - - - Connect to EVSS or VSS. Connect directly to EVDD or VDD Note 2 . Connect directly to EVSS or VSS. Notes 1. Use recommended connection above in I/O port mode (see Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 2. Make the same potential as the VDD pin when port 2 is used as a digital port. 44 Preliminary User's Manual U17260EJ3V1UD CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AH EVDD Pull-up enable P-ch EVDD IN Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch EVSS Input enable Type 3-C Type 11-G AVREF Data P-ch EVDD IN/OUT Output disable P-ch Data N-ch OUT AVSS P-ch Comparator + N-ch _ N-ch Series resistor string voltage EVSS AVSS Input enable Type 5-AG Type 13-P EVDD Pull-up enable P-ch IN/OUT Data EVDD Data Output disable N-ch P-ch EVSS IN/OUT Output disable N-ch Input enable EVSS Input enable Preliminary User's Manual U17260EJ3V1UD 45 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-AD Type 38 IN/OUT Data Output disable IN N-ch EVSS Input enable Input enable Type 37 RESET Data EVDD P-ch X2, XT2 Output disable N-ch EVSS Data EVDD P-ch RESET N-ch Input enable P-ch X1, XT1 Output disable N-ch EVSS Input enable 46 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KE2 can access a 64 KB memory space. Figures 3-1 to 3-8 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE2 are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. 2. To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) Flash Memory Version IMS IXS (78K0/KE2) PD78F0531 04H PD78F0532 0CH ROM Internal High-Speed Internal Expansion Capacity RAM Capacity RAM Capacity - 16 KB 768 bytes C6H 24 KB 1 KB PD78F0533 C8H 32 KB PD78F0534 CCH 0AH 48 KB 1 KB PD78F0535 CFH 0BH 60 KB 2 KB PD78F0536 CCH PD78F0537, 78F0537D CCH Note Note 04H 96 KB Note 00H 128 KB Note 4 KB 6 KB Note The PD78F0536, 78F0537, and 78F0537D have internal ROMs of 96 KB and 128 KB, respectively. However, the set value of IMS of these devices is the same as those of the 48 KB product because memory banks are used. For how to set the memory banks, see 4.2 Memory Bank Select Register (BANK). Preliminary User's Manual U17260EJ3V1UD 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (PD78F0531) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits 3FFFH Program area Internal high-speed RAM 768 x 8 bits FC00H FBFFH 1FFFH 1085H 1084H 1080H 107FH areaNote1 Option byte 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Reserved Program area 1915 x 8 bits 0085H 0084H 0080H 007FH 4000H 3FFFH Program memory space Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits Flash memory 16384 x 8 bits 0000H 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Setting). 48 Preliminary User's Manual U17260EJ3V1UD Security CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F0532) FFFFH FF00H FEFFH FEE0H FEDFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits 5FFFH Program area Internal high-speed RAM 1024 x 8 bits FB00H FAFFH 1FFFH 1085H 1084H 1080H 107FH Note1 Option byte area 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits Reserved 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H 0080H 007FH 6000H 5FFFH Program memory space Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits Flash memory 24576 x 8 bits 0000H 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security Setting). Preliminary User's Manual U17260EJ3V1UD 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F0533) FFFFH FF00H FEFFH FEE0H FEDFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits 7FFFH Program area Internal high-speed RAM 1024 x 8 bits FB00H FAFFH 1FFFH 1085H 1084H 1080H 107FH areaNote1 Option byte 5 x 8 bits Boot cluster 1 Program area Data memory space 1000H 0FFFH CALLF entry area 2048 x 8 bits Reserved 0800H 07FFH 0085H 0084H 0080H 007FH 8000H 7FFFH Program memory space Program area 1915 x 8 bits Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits Flash memory 32768 x 8 bits 0000H 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Setting). 50 Preliminary User's Manual U17260EJ3V1UD Security CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD78F0534) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits BFFFH Program area Internal high-speed RAM 1024 x 8 bits FB00H FAFFH 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote1 5 x 8 bits Boost cluster 1 Reserved Program area Data memory space 1000H 0FFFH F800H F7FFH CALLF entry area 2048 x 8 bits Program RAM area RAM spcae in which instruction can be fetched Internal expansion RAM 1024 x 8 bits 0800H 07FFH Program area 1915 x 8 bits F400H F3FFH 0085H 0084H Reserved 0080H 007FH C000H BFFFH Program memory space Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits Flash memory 49152 x 8 bits 0000H 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security Setting). Preliminary User's Manual U17260EJ3V1UD 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD78F0535) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits EFFFH Program area Internal high-speed RAM 1024 x 8 bits FB00H FAFFH 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote1 5 x 8 bits Boot cluster 1 Reserved Program area Data memory space 1000H 0FFFH F800H F7FFH CALLF entry area 2048 x 8 bits Program RAM area RAM spcae in which instruction can be fetched Internal expansion RAM 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H F000H EFFFH 0080H 007FH Flash memory 61440 x 8 bits Program memory space 0000H Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Setting). 52 Preliminary User's Manual U17260EJ3V1UD Security CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (PD78F0536) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits 7FFFH FB00H FAFFH Program area 1085H 1084H 1080H 107FH Reserved Data memory space F800H F7FFH Program RAM area RAM spcae in which instruction can be fetched E800H E7FFH Boot cluster 1 Program area Internal expansion RAM 4096 x 8 bits CALLF entry area 2048 x 8 bits (Memory bank 2) 0800H 07FFH Program area 1915 x 8 bits C000H BFFFH Common area Option byte 5 x 8 bits 1000H 0FFFH Reserved Bank area Program 8000H memory 7FFFH space 1FFFH areaNote1 0085H 0084H Flash memory 16384 x 8 bits (memory bank 0) 0080H 007FH 0000H (Memory bank 1) Boot cluster 0Note2 CALLT table area 64 x 8 bits (Memory bank 3) Flash memory 32768 x 8 bits Option byte areaNote1 5 x 8 bits 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security Setting). Preliminary User's Manual U17260EJ3V1UD 53 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Memory Map (PD78F0537) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits 7FFFH FB00H FAFFH Program area 1085H 1084H 1080H 107FH Reserved Data memory space F800H F7FFH Program RAM area RAM spcae in which instruction can be fetched E000H DFFFH (Memory bank 2) 1000H 0FFFH 0800H 07FFH Program area 1915 x 8 bits C000H BFFFH Common area Boot cluster 1 CALLF entry area 2048 x 8 bits Reserved Bank area Program 8000H memory 7FFFH space Option byte areaNote1 5 x 8 bits Program area (Memory bank 4) Internal expansion RAM 6144 x 8 bits 1FFFH 0085H 0084H Flash memory 16384 x 8 bits (memory bank 0) 0080H 007FH (Memory bank 5) (Memory bank 3) Flash memory 32768 x 8 bits 0000H Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 CALLT table area 64 x 8 bits 0040H 003FH (Memory bank 1) Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Setting). 54 Preliminary User's Manual U17260EJ3V1UD Security CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map (PD78F0537D) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH 7FFFH General-purpose registers 32 x 8 bits Program area 1FFFH 108FH 108EH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH 1085H 1084H 1080H 107FH On-chip debug security ID setting areaNote1 10 x 8 bits Option byte areaNote1 5 x 8 bits Boot cluster 1 Program area Reserved 1000H 0FFFH Data memory space F800H F7FFH Program RAM area RAM spcae in which instruction can be fetched E000H DFFFH (Memory bank 2) Internal expansion RAM 6144 x 8 bits 008FH 008EH Reserved Program memory space 0085H 0084H Flash memory 16384 x 8 bits (memory bank 0) 8000H 7FFFH Common area 0800H 07FFH Program area 1905 x 8 bits C000H BFFFH Bank area CALLF entry area 2048 x 8 bits (Memory bank 4) 0080H 007FH (Memory bank 5) (Memory bank 3) Flash memory 32768 x 8 bits 0000H On-chip debug security ID setting areaNote1 10 x 8 bits Boot cluster 0Note2 Option byte areaNote1 5 x 8 bits CALLT table area 64 x 8 bits 0040H 003FH (Memory bank 1) Vector table area 64 x 8 bits 0000H Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to 0085H to 008EH. When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH. 2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 26.8 Security Setting). Preliminary User's Manual U17260EJ3V1UD 55 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KE2 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure PD78F0531 Flash memory Capacity 16384 x 8 bits (0000H to 3FFFH) PD78F0532 24576 x 8 bits (0000H to 5FFFH) PD78F0533 32768 x 8 bits (0000H to 7FFFH) PD78F0534 49152 x 8 bits (0000H to BFFFH) PD78F0535 61440 x 8 bits (0000H to EFFFH) PD78F0536 98304 x 8 bits (0000H to 7FFFH (common area) + 8000H to BFFFH (bank area) x 4) PD78F0537, 131072 x 8 bits 78F0537D (0000H to 7FFFH (common area) + 8000H to BFFFH (bank area) x 6) The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. 56 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 0000H RESET input, POC, LVI, WDT 0020H INTTM000 0004H INTLVI 0022H INTTM010 0006H INTP0 0024H INTAD 0008H INTP1 0026H INTSR0 000AH INTP2 0028H INTWTI 000CH INTP3 002AH INTTM51 000EH INTP4 002CH INTKR 0010H INTP5 002EH INTWT 0012H INTSRE6 0030H INTP6 0014H INTSR6 0032H INTP7 0016H INTST6 0034H INTIIC0/INTDMU 0018H INTCSI10/INTST0 0036H Note INTCSI11 001AH INTTMH1 0038H Note INTTM001 Note 001CH INTTMH0 003AH Note INTTM011 Note 001EH INTTM50 003EH Note Note BRK Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, see CHAPTER 25 OPTION BYTE. (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). (5) On-chip debug security ID setting area (PD78F0537D only) A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at 0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). Preliminary User's Manual U17260EJ3V1UD 57 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Memory bank (PD78F0536, 78F0537, and 78F0537D only) The 16 KB area 8000H to BFFFH is assigned to memory banks 0 to 3 in the PD78F0536, and assigned to memory banks 0 to 5 in the PD78F0537 and 78F0537D. The banks are selected by using a memory bank select register (BANK). For details, see CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY)). Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branch and access cannot be directly executed between different memory banks. Execute branch or access between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. 3.1.3 Internal data memory space 78K0/KE2 products incorporate the following RAMs. (1) Internal high-speed RAM Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM PD78F0531 768 x 8 bits (FC00H to FEFFH) PD78F0532 1024 x 8 bits (FB00H to FEFFH) PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537, 78F0537D The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. 58 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE (2) Internal expansion RAM Table 3-5. Internal Expansion RAM Capacity Part Number Internal Expansion RAM PD78F0531 - PD78F0532 PD78F0533 PD78F0534 1024 x 8 bits (F400H to F7FFH) PD78F0535 2048 x 8 bits (F000H to F7FFH) PD78F0536 4096 x 8 bits (E800H to F7FFH) PD78F0537, 78F0537D 6144 x 8 bits (E000H to F7FFH) The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see Table 3-6 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KE2, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-9 to 3-15 show correspondence between data memory and addressing. For details of each addressing mode, see 3.4 Operand Address Addressing. Preliminary User's Manual U17260EJ3V1UD 59 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing (PD78F0531) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 768 x 8 bits FE20H FE1FH FC00H FBFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H 60 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing (PD78F0532) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 6000H 5FFFH Flash memory 24576 x 8 bits 0000H Preliminary User's Manual U17260EJ3V1UD 61 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Correspondence Between Data Memory and Addressing (PD78F0533) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 8000H 7FFFH Flash memory 32768 x 8 bits 0000H 62 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Correspondence Between Data Memory and Addressing (PD78F0534) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Reserved Direct addressing Register indirect addressing F800H F7FFH Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH Reserved C000H BFFFH Flash memory 49152 x 8 bits 0000H Preliminary User's Manual U17260EJ3V1UD 63 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing (PD78F0535) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Reserved Direct addressing Register indirect addressing F800H F7FFH Based addressing Based indexed addressing Internal expansion RAM 2048 x 8 bits F000H EFFFH Flash memory 61440 x 8 bits 0000H 64 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Correspondence Between Data Memory and Addressing (PD78F0536) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Direct addressing FA00H F9FFH F800H F7FFH Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 4096 x 8 bits 16384 x 8 bits Note (memory bank 2) E800H E7FFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0) Note 8000H 7FFFH Flash memory 32768 x 8 bits 16384 x 8 bits (memory bank 3)Note 16384 x 8 bits Note (memory bank 1) 0000H Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. Preliminary User's Manual U17260EJ3V1UD 65 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Correspondence Between Data Memory and Addressing (PD78F0537, 78F0537D) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FA20H FA1FH Reserved Direct addressing FA00H F9FFH F800H F7FFH Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 6144 x 8 bits 16384 x 8 bits Note (memory bank 4) 16384 x 8 bits Note (memory bank 2) E000H DFFFH Reserved C000H BFFFH Flash memory 16384 x 8 bits (memory bank 0) Note 8000H 7FFFH 16384 x 8 bits Note (memory bank 5) Flash memory 32768 x 8 bits 16384 x 8 bits Note (memory bank 3) 16384 x 8 bits Note (memory bank 1) 0000H Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. 66 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KE2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-16. Format of Program Counter 0 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 3-17. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 0 ISP CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI instruction execution. Preliminary User's Manual U17260EJ3V1UD 67 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (see 19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-18. Format of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-19 and 3-20. Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. 68 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP SP FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 Preliminary User's Manual U17260EJ3V1UD 69 CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP SP 70 FEE0H FEDDH FEE0H FEDFH PSW FEDEH PC15 to PC8 FEDDH PC7 to PC0 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-21. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FEFFH H Register bank 0 HL L FEF8H D Register bank 1 DE E FEF0H B BC Register bank 2 C FEE8H A AX Register bank 3 X FEE0H 15 0 7 0 (b) Absolute name 16-bit processing 8-bit processing FEFFH R7 Register bank 0 RP3 R6 FEF8H R5 Register bank 1 RP2 R4 FEF0H R3 RP1 Register bank 2 R2 FEE8H R1 RP0 Register bank 3 R0 FEE0H 15 0 Preliminary User's Manual U17260EJ3V1UD 7 0 71 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-6 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and SM+ for 78K0/KX2, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. 72 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit 8 Bits 16 Bits After Reset FF00H Port register 0 P0 R/W - 00H FF01H Port register 1 P1 R/W - 00H FF02H Port register 2 P2 R/W - 00H FF03H Port register 3 P3 R/W - 00H FF04H Port register 4 P4 R/W - 00H FF05H Port register 5 P5 R/W - 00H FF06H Port register 6 P6 R/W - 00H FF07H Port register 7 P7 R/W - 00H FF08H 10-bit A/D conversion result register ADCR R - - 0000H ADCRH R - - 00H RXB6 R - - FFH FF09H FF0AH 8-bit A/D conversion result register Receive buffer register 6 FF0BH Transmit buffer register 6 TXB6 R/W - - FFH FF0CH Port register 12 P12 R/W - 00H FF0DH Port register 13 P13 R/W - 00H FF0EH Port register 14 P14 R/W - 00H FF0FH Serial I/O shift register 10 SIO10 R - - 00H FF10H 16-bit timer counter 00 TM00 R - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H 16-bit timer capture/compare register 010 CR010 R/W - - 0000H FF16H 8-bit timer counter 50 TM50 R - - 00H FF17H 8-bit timer compare register 50 CR50 R/W - - 00H FF18H 8-bit timer H compare register 00 CMP00 R/W - - 00H FF19H 8-bit timer H compare register 10 CMP10 R/W - - 00H FF1AH 8-bit timer H compare register 01 CMP01 R/W - - 00H FF1BH 8-bit timer H compare register 11 CMP11 R/W - - 00H FF1FH 8-bit timer counter 51 TM51 R - - 00H FF20H Port mode register 0 PM0 R/W - FFH FF21H Port mode register 1 PM1 R/W - FFH FF22H Port mode register 2 PM2 R/W - FFH FF23H Port mode register 3 PM3 R/W - FFH FF24H Port mode register 4 PM4 R/W - FFH FF25H Port mode register 5 PM5 R/W - FFH FF26H Port mode register 6 PM6 R/W - FFH FF27H Port mode register 7 PM7 R/W - FFH FF28H A/D converter mode register ADM R/W - 00H FF11H FF12H FF13H FF14H FF15H FF29H Analog input channel specification register ADS R/W - 00H FF2CH Port mode register 12 PM12 R/W - FFH FF2EH Port mode register 14 PM14 R/W - FFH FF2FH A/D port configuration register ADPC R/W - 00H Preliminary User's Manual U17260EJ3V1UD 73 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol R/W 1 Bit Manipulatable Bit Unit 8 Bits 16 Bits After Reset FF30H Pull-up resistor option register 0 PU0 R/W - 00H FF31H Pull-up resistor option register 1 PU1 R/W - 00H FF33H Pull-up resistor option register 3 PU3 R/W - 00H FF34H Pull-up resistor option register 4 PU4 R/W - 00H FF35H Pull-up resistor option register 5 PU5 R/W - 00H FF37H Pull-up resistor option register 7 PU7 R/W - 00H FF3CH Pull-up resistor option register 12 PU12 R/W - 00H FF3EH Pull-up resistor option register 14 PU14 R/W - 00H FF40H Clock output selection register CKS R/W - 00H FF41H 8-bit timer compare register 51 CR51 R/W - - 00H FF43H 8-bit timer mode control register 51 TMC51 R/W - 00H FF48H External interrupt rising edge enable register EGP R/W - 00H FF49H External interrupt falling edge enable register EGN R/W - 00H R - - 00H FF4AH Serial I/O shift register 11 Note SIO11 FF4CH Transmit buffer register 11 SOTB11 R/W - - 00H FF4FH Input switch control register ISC R/W - 00H FF50H Asynchronous serial interface operation mode register 6 ASIM6 R/W - 01H FF53H Asynchronous serial interface reception error status register 6 ASIS6 R - - 00H FF55H Asynchronous serial interface transmission status register 6 ASIF6 R - - 00H FF56H Clock selection register 6 CKSR6 R/W - - 00H FF57H Baud rate generator control register 6 BRGC6 R/W - - FFH ASICL6 R/W - 16H R - 00H - R/W - - R/W - - - Note FF58H Asynchronous serial interface control register 6 FF60H Remainder data register 0 Note SDR0 SDR0L FF61H FF62H SDR0H Multiplication/division data register A0 Note MDA0L MDA0LL FF63H MDA0LH FF64H MDA0H MDA0HL FF65H FF66H MDA0HH Multiplication/division data register B0 Note MDB0 MDB0L R/W 00H 00H 00H 00H 00H 00H - DMUC0 R/W - 00H 8-bit timer H mode register 0 TMHMD0 R/W - 00H FF6AH Timer clock selection register 50 TCL50 R/W - 00H FF6BH 8-bit timer mode control register 50 TMC50 R/W - 00H FF6CH 8-bit timer H mode register 1 TMHMD1 R/W - 00H FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W - 00H FF6EH Key return mode register KRM R/W - 00H FF6FH Watch timer operation mode register WTM R/W - 00H FF67H MDB0H FF68H Multiplier/divider control register 0 FF69H Note Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 74 Preliminary User's Manual U17260EJ3V1UD 00H CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol R/W 1 Bit Manipulatable Bit Unit 8 Bits 16 Bits After Reset FF70H Asynchronous serial interface operation mode register 0 ASIM0 R/W - 01H FF71H Baud rate generator control register 0 BRGC0 R/W - - 1FH FF72H Receive buffer register 0 RXB0 R - - FFH FF73H Asynchronous serial interface reception error status register 0 ASIS0 R - - 00H FF74H Transmit shift register 0 TXS0 W - - FFH FF80H Serial operation mode register 10 CSIM10 R/W - 00H FF81H Serial clock selection register 10 CSIC10 R/W - 00H FF84H Transmit buffer register 10 SOTB10 R/W - - 00H CSIM11 R/W - 00H FF88H Serial operation mode register 11 Note 1 FF89H Serial clock selection register 11 CSIC11 R/W - 00H FF8CH Timer clock selection register 51 TCL51 R/W - 00H FF99H Watchdog timer enable register WDTE R/W - - FF9FH Clock operation mode select register OSCCTL R/W - FFA0H Internal oscillation mode register RCM R/W - FFA1H Main clock mode register MCM R/W - 00H FFA2H Main OSC control register MOC R/W - 80H FFA3H Oscillation stabilization time counter status register OSTC R - 00H Note 1 Note 2 1AH/9AH 00H Note 3 80H FFA4H Oscillation stabilization time select register OSTS R/W - - 05H FFA5H IIC shift register 0 IIC0 R/W - - 00H FFA6H IIC control register 0 IICC0 R/W - 00H FFA7H Slave address register 0 SVA0 R/W - - 00H FFA8H IIC clock selection register 0 IICCL0 R/W - 00H FFA9H IIC function expansion register 0 IICX0 R/W - 00H FFAAH IIC status register 0 IICS0 R - 00H FFABH IIC flag register 0 IICF0 R/W - FFACH Reset control flag register RESF R - - 00H FFB0H 16-bit timer counter 01 Note 1 TM01 R - - 0000H 00H Note 4 FFB1H FFB2H 16-bit timer capture/compare register 001 Note 1 CR001 R/W - - 0000H 16-bit timer capture/compare register 011 Note 1 CR011 R/W - - 0000H Note 1 TMC01 R/W - 00H PRM01 R/W - 00H Note 1 CRC01 R/W - 00H TOC01 R/W - 00H TMC00 R/W - 00H FFB3H FFB4H FFB5H FFB6H 16-bit timer mode control register 01 Note 1 FFB7H Prescaler mode register 01 FFB8H Capture/compare control register 01 Note 1 FFB9H 16-bit timer output control register 01 FFBAH 16-bit timer mode control register 00 Notes 1. Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 2. The reset value of WDTE is determined by setting of option byte. 3. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator has been stabilized. 4. The reset value of RESF varies depending on the reset source. Preliminary User's Manual U17260EJ3V1UD 75 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol R/W 1 Bit Manipulatable Bit Unit 8 Bits 16 Bits After Reset FFBBH Prescaler mode register 00 PRM00 R/W - 00H FFBCH Capture/compare control register 00 CRC00 R/W - 00H FFBDH 16-bit timer output control register 00 TOC00 R/W - FFBEH Low-voltage detection register LVIM R/W - 00H FFBFH Low-voltage detection level selection register LVIS R/W - 00H FFE0H Interrupt request flag register 0L IF0 IF0L R/W FFE1H Interrupt request flag register 0H IF0H R/W FFE2H Interrupt request flag register 1L IF1L R/W FFE3H Interrupt request flag register 1H IF1H R/W FFE4H Interrupt mask flag register 0L MK0 MK0L R/W FFE5H Interrupt mask flag register 0H MK0H R/W FFE6H Interrupt mask flag register 1L MK1 MK1L R/W FFE7H Interrupt mask flag register 1H MK1H R/W FFE8H Priority specification flag register 0L PR0 PR0L R/W PR0H R/W PR1 PR1L R/W PR1H R/W R/W - IF1 FFE9H Priority specification flag register 0H FFEAH Priority specification flag register 1L FFEBH Priority specification flag register 1H FFF0H Internal memory size switching register Note 2 IMS 00H Note 1 Note 1 00H 00H 00H 00H FFH FFH FFH FFH FFH FFH FFH FFH - CFH FFF3H Memory bank select register BANK R/W - - 00H FFF4H Internal expansion RAM size switching register IXS R/W - - 0CH FFFBH Processor clock control register PCC R/W - 01H Notes 1. The reset values of LVIM and LVIS vary depending on the reset source. Note 2 2. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE2 are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. Flash Memory Version IMS IXS (78K0/KE2) 76 ROM Internal High-Speed Internal Expansion Capacity RAM Capacity RAM Capacity PD78F0531 04H PD78F0532 C6H PD78F0533 C8H PD78F0534 CCH 0AH 48 KB 1 KB PD78F0535 CFH 08H 60 KB 2 KB 0CH 16 KB 768 bytes 24 KB 1 KB - 32 KB PD78F0536 CCH 04H 48 KB 4 KB PD78F0537, 78F0537D CCH 00H 48 KB 6 KB Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to PC and branched by the following addressing (for details of instructions, refer to the 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC indicates the start address of the instruction after the BR instruction. PC + 8 15 7 6 0 S jdisp8 15 0 PC When S = 0, all bits of are 0. When S = 1, all bits of are 1. Preliminary User's Manual U17260EJ3V1UD 77 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. However, before branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr. 15 8 7 0 PC In the case of CALLF !addr11 instruction 7 6 4 3 fa10-8 0 CALLF fa7-0 15 PC 78 0 11 10 0 0 0 8 7 1 Preliminary User's Manual U17260EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. However, before branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Illustration] 7 Operation code 6 1 5 1 1 ta4-0 1 15 Effective address 0 7 0 0 0 0 0 0 0 Memory (Table) 8 7 6 0 0 1 5 1 0 0 0 Low Addr. High Addr. Effective address+1 8 15 7 0 PC 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC Preliminary User's Manual U17260EJ3V1UD 79 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/KE2 instruction words, the following instructions employ implied addressing. Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets ROR4/ROL4 A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 80 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code Preliminary User's Manual U17260EJ3V1UD 81 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (lower) addr16 (upper) Memory 82 Preliminary User's Manual U17260EJ3V1UD CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See the [Illustration] shown below. [Operand format] Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] LB1 EQU 0FE30H ; Defines FE30H by LB1. : MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to that address Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 0 OP code saddr-offset Short direct memory 8 7 15 Effective address 1 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 Preliminary User's Manual U17260EJ3V1UD 83 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name sfrp 16-bit manipulatable special function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 84 1 8 7 1 1 1 1 1 1 1 Preliminary User's Manual U17260EJ3V1UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier Description - [DE], [HL] [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 8 7 D DE 0 E 7 Memory 0 The memory address specified with the register pair DE The contents of the memory addressed are transferred. 7 0 A Preliminary User's Manual U17260EJ3V1UD 85 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - Description [HL + byte] [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 8 7 H HL 0 L 7 Memory The contents of the memory addressed are transferred. 7 0 A 86 Preliminary User's Manual U17260EJ3V1UD 0 +10 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK. [Operand format] Identifier - Description [HL + B], [HL + C] [Description example] MOV A, [HL +B]; when selecting B register Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 8 HL 7 H 0 L + 7 0 B 7 Memory 0 The contents of the memory addressed are transferred. 7 0 A Preliminary User's Manual U17260EJ3V1UD 87 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] PUSH DE; when saving DE register Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP SP 88 FEE0H FEDEH Memory FEE0H FEDFH D FEDEH E Preliminary User's Manual U17260EJ3V1UD 0 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.1 Memory Bank The PD78F0536, 78F0537, and 78F0537D implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. The PD78F0536 has memory banks 0 to 3, and the PD78F0537 and 78F0537D have memory banks 0 to 5, as shown below. The memory banks are selected by using a memory bank select register (BANK). Figure 4-1. Internal ROM (Flash Memory) Configuration (a) PD78F0536 (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H 7FFFH Common area Flash memory 32768 x 8 bits 0000H (b) PD78F0537, 78F0537D (Memory bank 5) (Memory bank 4) (Memory bank 3) (Memory bank 2) (Memory bank 1) BFFFH Flash memory 16384 x 8 bits (memory bank 0) Bank area 8000H 7FFFH Common area Flash memory 32768 x 8 bits 0000H Preliminary User's Manual U17260EJ3V1UD 89 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.2 Memory Bank Select Register (BANK) The memory bank select register (BANK) is used to select a memory bank to be used. BANK can be set by an 8-bit memory manipulation instruction. Reset signal generation clears BANK to 00H. Figure 4-2. Format of Memory Bank Select Register (BANK) Address: FFF3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 BANK 0 0 0 0 0 BANK2 BANK1 BANK0 BANK2 BANK1 BANK0 Bank setting PD78F0536 PD78F0537, 78F0537D 0 0 0 Common area (32 K) + memory bank 0 (16 K) 0 0 1 Common area (32 K) + memory bank 1 (16 K) 0 1 0 Common area (32 K) + memory bank 2 (16 K) 0 1 1 Common area (32 K) + memory bank 3 (16 K) 1 0 0 Setting prohibited Common area (32 K) + memory bank 4 (16 K) 1 0 1 Common area (32 K) + memory bank 5 (16 K) Other than above Caution Setting prohibited Be sure to change the value of the BANK register in the common area (0000H to 7FFFH). If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent program loop occurs in the CPU. Therefore, never change the value of the BANK register in the bank area. 90 Preliminary User's Manual U17260EJ3V1UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register. The value of the BANK register must not be changed in the bank area (8000H to BFFFH). Therefore, to change the memory bank, branch an instruction to the common area (0000H to 7FFFH) and change the value of the BANK register in that area. Cautions 1. Instructions cannot be fetched between different memory banks. 2. Branching and accessing cannot be directly executed between different memory banks. Execute branching or accessing between different memory banks via the common area. 3. Allocate interrupt servicing in the common area. 4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0. 4.3.1 Referencing values between memory banks Values cannot be directly referenced from one memory bank to another. To access another memory bank from one memory bank, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then reference a value. Memory bank n Bank area Memory bank m Referencing value Common area Memory bank n Bank area Common area Memory bank m Referencing value Preliminary User's Manual U17260EJ3V1UD 91 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) * Software example (to store a value to be referenced in register A) RAMD R_BNKA: R_BNKN: R_BNKRN: DSEG DS DS DS SADDR 2 1 1 MOV MOVW CALL R_BNKN,#BANKNUM R_BNKA,#DATA1 !BNKRD : : CSEG AT PUSH MOV XCH HL A,R_BNKN A,BANK MOV MOVW XCHW MOV XCH MOV MOV POP R_BNKRN,A AX,R_BNKA HL,AX A,[HL] A,R_BNKRN BANK,A A,R_BNKRN HL ; Secures RAM for specifying an address at the reference destination. ; Secures RAM for specifying a memory bank number at the reference destination. ; Secures RAM for saving a memory bank number at the reference source. ; BNKC DATA DATA1: CSEG DB ; Stores the memory bank number at the reference destination. ; Stores the address at the reference destination. ; Calls a subroutine for referencing between memory banks. 7000H BNKRD: RET DATA1 ; Subroutine for referencing between memory banks. ; Saves the contents of register HL. ; ; Swaps the memory bank number at the reference source for that at the reference ; destination ; Saves the memory bank number at the reference source. ; ; Specifies the address at the reference destination. ; Reads the target value. ; Acquires the memory bank number at the reference source. ; Specifies the memory bank number at the reference source. ; ; Restores the contents of register HL. ; Return BANK3 0AAH END Remark 92 In the software example above, the X register is destructed. Preliminary User's Manual U17260EJ3V1UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again. Memory bank n Bank area Memory bank m Instruction branch Common area Memory bank n Bank area Memory bank m Instruction branch Common area Preliminary User's Manual U17260EJ3V1UD 93 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) * Software example RAMD R_BNKA: R_BNKN: BNKC BNKBR: BN3 TEST: DSEG DS DS SADDR 2 1 MOV MOVW BR : : R_BNKN,#BANKNUM R_BNKA,#TEST !BNKBR CSEG AT MOV MOV MOVW BR A,R_BNKN BANK,A AX,R_BNKA AX CSEG BANK3 ; Secures RAM for specifying a memory bank at the branch destination. ; Secures RAM for specifying a memory bank number at the branch destination. 7000H TEST ; Stores the memory bank number at the branch destination in RAM. ; Stores the address at the branch destination in RAM. ; Branches to inter-memory bank branch processing. ; ; ; Specifies the memory bank number at the branch destination. ; Specifies the address at the branch destination. ; Branch MOV : : END Remark 94 In the software example above, the AX register is destructed. Preliminary User's Manual U17260EJ3V1UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction. At this time, save the current value of the BANK register to RAM. Restore the value of the BANK register before executing the RET instruction. Memory bank n Bank area Memory bank m CALL instruction Common area Memory bank n Bank area Common area Memory bank m CALL instruction RET instruction BR instruction CALL instruction RET instruction Change BANK and save memory bank number at calling source. Preliminary User's Manual U17260EJ3V1UD 95 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) * Software example RAMD R_BNKA: R_BNKN: R_BNKRN: BNKC BNKCAL: DSEG DS DS DS SADDR 2 1 1 MOV MOVW CALL R_BNKN,#BANKNUM R_BNKA,#TEST !BNKCAL : : CSEG AT MOV XCH MOV CALL XCH MOV RET A,R_BNKN A,BANK R_BNKRN,A !BNKCALS A,R_BNKRN BANK,A ; Inter-memory bank calling processing routine ; Acquires the memory bank number at the calling destination. ; Changes the bank and acquires the memory bank number at the calling source. ; Saves the memory bank number at the calling source to RAM. ; Calls a subroutine to branch to the calling destination. ; ; Specifies the memory bank number at the calling source. ; Returns to the calling source. MOVW BR AX,R_BNKA AX ; Specifies the address at the calling destination. ; Branches to the calling destination. CSEG BANK3 ; Secures RAM for specifying an address at the calling destination. ; Secures RAM for specifying a memory bank number at the calling destination. ; Secures RAM for saving a memory bank number at the calling source. TEST ; Store the memory bank number at the calling destination in RAM. ; Stores the address at the calling destination in RAM. ; Branches to an inter-memory bank calling processing routine. 7000H BNKCALS: BN3 TEST: ; MOV : : RET END Remark 96 In the software example above, the AX register is destructed. Multiplexed processing is not supported. Preliminary User's Manual U17260EJ3V1UD CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs. Therefore, specify the branch destination address specified by the vector table in the common area (0000H to 7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and execute the CALL instruction. At this time, save the BANK register value before the change to RAM, and restore the value of the BANK register before executing the RETI instruction. Remark Allocate interrupt servicing that requires a quick response in the common area. Memory bank n Instruction branch Bank area Memory bank m Common area Vector table Save the original memory bank number. Specify the address and memory bank at the destination, and execute the call instruction. * Software example (when using interrupt request of 16-bit timer/event counter 00) VCTBL CSEG DW AT 0020H BNKITM000 ; Specifies an address at the timer interrupt destination. RAMD DSEG R_BNKRN: DS SADDR 1 ; Secures RAM for saving the memory bank number before the interrupt occurs. BNKC CSEG AT BNKITM000: PUSH AX 7000H ; Inter-memory bank interrupt servicing routine ; Saves the contents of the AX register. MOV MOV MOV CALL MOV MOV A,BANK R_BNKRN,A BANK,#BANKNUM TEST !TEST A,R_BNKRN BANK,A ; Saves the memory bank number before the interrupt to RAM. ; Specifies the memory bank number of the interrupt routine. ; Calls the interrupt routine. ; Restores the memory bank number before the interrupt. POP AX ; Restores the contents of the AX register. RETI BN3 TEST: CSEG BANK3 ; Interrupt servicing routine MOV : : RET END Preliminary User's Manual U17260EJ3V1UD 97 CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) Remark Note the following points to use the memory bank select function efficiently. * Allocate a routine that is used often in the common area. * If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. * If the reference destination and the branch destination of the routine placed in a memory bank are placed in the same memory bank, then the code size and processing are more efficient. * Allocate interrupt servicing that requires a quick response in the common area. 98 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions There are three types of pin I/O buffer power supplies: AVREF, EVDD, and VDD. The relationship between these power supplies and the pins is shown below. Table 5-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 and P121 to P124 VDD * P121 to P124 * Non-port pins 78K0/KE2 products are provided with the ports shown in Figure 5-1, which enable variety of control operations. The functions of each port are shown in Table 5-2. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. Figure 5-1. Port Types P50 P00 Port 5 P53 Port 0 P60 P06 Port 6 P63 P10 P70 Port 1 Port 7 P17 P77 P20 P120 Port 2 Port 12 P124 P27 Port 13 P130 Port 14 P140 P141 P30 Port 3 P33 P40 Port 4 P43 Preliminary User's Manual U17260EJ3V1UD 99 CHAPTER 5 PORT FUNCTIONS Table 5-2. Port Functions (1/2) Pin Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 SO11 Use of an on-chip pull-up resistor can be specified by a P03 TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Alternate Function SI11 software setting. Note1 Note1 P04 SCK11 P05 SSI11 P06 TI011 Note1 Note1 /TI001 Note1 P10 I/O Port 1. Input port 8-bit I/O port. P11 SCK10/TxD0 SO10 Use of an on-chip pull-up resistor can be specified by a P13 TxD6 software setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50 P20 to P27 I/O Note1 SI10/RxD0 Input/output can be specified in 1-bit units. P12 /TO01 Note1 Port 2. Analog input ANI0 to ANI7 Input port INTP1 8-bit I/O port. Input/output can be specified in 1-bit units. I/O P30 Port 3. 4-bit I/O port. P31 Input/output can be specified in 1-bit units. P32 Use of an on-chip pull-up resistor can be specified by a P33 I/O Port 4. Note2 INTP3/OCD1B Note2 INTP4/TI51/TO51 software setting. P40 to P43 INTP2/OCD1A Input port - Input port - 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P53 I/O Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O P60 Port 6. Input port 4-bit I/O port (N-ch open drain). P61 SDA0 Input/output can be specified in 1-bit units. P62 EXSCL0 - P63 P70 to P77 I/O Port 7. Input port 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Notes 1. Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 2. PD78F0537D only 100 SCL0 Preliminary User's Manual U17260EJ3V1UD KR0 to KR7 CHAPTER 5 PORT FUNCTIONS Table 5-2. Port Functions (2/2) Function Name I/O I/O P120 Function After Reset Port 12. Input port 5-bit I/O port. P121 Note Note X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 INTP0/EXLVI X1/OCD0A Input/output can be specified in 1-bit units. P122 Alternate Function XT1 specified by a software setting. P124 XT2/EXCLKS P130 Output Port 13. Output port - 1-bit output-only port. I/O P140 Port 14. Input port 2-bit I/O port. P141 PCL/INTP6 BUZ/INTP7 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Note PD78F0537D only 5.2 Port Configuration Ports include the following hardware. Table 5-3. Port Configuration Item Control registers Configuration Port mode register (PM0 to PM7, PM12, PM14) Port register (P0 to P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3 to PU7, PU12, PU14) A/D port configuration register (ADPC) Port Total: 55 (CMOS I/O: 50, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor Total: 38 Preliminary User's Manual U17260EJ3V1UD 101 CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O, serial interface data I/O, clock I/O, and chip select input. Reset signal generation sets port 0 to input mode. Figures 5-2 to 5-7 show block diagrams of port 0. Caution To use P02/SO11Note and P04/SCK11Note as general-purpose ports, set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H). Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. Figure 5-2. Block Diagram of P00 EVDD WRPU PU0 PU00 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00) P00/TI000 WRPM PM0 PM00 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal 102 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P01 EVDD WRPU PU0 PU01 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P01) P01/TI010/TO00 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 103 CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P02 EVDD WRPU PU0 PU02 P-ch Selector Internal bus RD WRPORT P0 Output latch (P02) P02/SO11Note WRPM PM0 PM02 Alternate functionNote P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 104 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P03 and P05 (a) PD78F0531, 78F0532, 78F0533 EVDD WRPU PU0 PU03, PU05 P-ch Selector Internal bus RD WRPORT P0 Output latch (P03, P05) P03, P05 WRPM PM0 PM03, PM05 (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D EVDD WRPU PU0 PU03, PU05 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P03, P05) P03/SI11, P05/SSI11/TI001 WRPM PM0 PM03, PM05 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 105 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P04 (a) PD78F0531, 78F0532, 78F0533 EVDD WRPU PU0 PU04 P-ch Selector Internal bus RD WRPORT P0 Output latch (P04) P04 WRPM PM0 PM04 (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D EVDD WRPU PU0 PU04 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P04) WRPM PM0 PM04 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal 106 Preliminary User's Manual U17260EJ3V1UD P04/SCK11 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P06 (a) PD78F0531, 78F0532, 78F0533 EVDD WRPU PU0 PU06 P-ch Internal bus Selector RD WRPORT P0 Output latch (P06) P06 WRPM PM0 PM06 (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D EVDD WRPU PU0 PU06 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P06) P06/TI011/TO01 WRPM PM0 PM06 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 107 CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. Reset signal generation sets port 1 to input mode. Figures 5-8 to 5-12 show block diagrams of port 1. Caution To use P10/SCK10/TxD0 and P12/SO10 as general-purpose ports, set serial operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default status (00H). Figure 5-8. Block Diagram of P10 EVDD WRPU PU1 PU10 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P10) P10/SCK10/TxD0 WRPM PM1 PM10 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 108 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P11, P14) P11/SI10/RxD0, P14/RxD6 WRPM PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 109 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P12 and P15 EVDD WRPU PU1 PU12, PU15 P-ch Internal bus Selector RD WRPORT P1 Output latch (P12, P15) P12/SO10 P15/TOH0 WRPM PM1 PM12, PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 110 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Figure 5-11. Block Diagram of P13 EVDD WRPU PU1 PU13 P-ch Selector Internal bus RD WRPORT P1 Output latch (P13) P13/TxD6 WRPM PM1 PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 111 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P16 and P17 EVDD WRPU PU1 PU16, PU17 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P16, P17) P16/TOH1/INTP5, P17/TI50/TO50 WRPM PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WRxx: Write signal 112 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit. To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using ADPC and in the output mode by using PM2. Table 5-4. Setting Functions of P20/ANI0 to P27/ANI7 Pins ADPC Digital I/O selection PM2 Input mode Output mode Analog input selection Input mode Output mode ADS P20/ANI0 to P27/ANI7 Pin Selects ANI. Setting prohibited Does not select ANI. Digital input Selects ANI. Setting prohibited Does not select ANI. Digital output Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated. Figure 5-13 shows a block diagram of port 2. Figure 5-13. Block Diagram of P20 to P27 Selector Internal bus RD WRPORT P2 Output latch (P20 to P27) P20/ANI0 to P27/ANI7 WRPM PM2 PM20 to PM27 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 113 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input and timer I/O. Reset signal generation sets port 3 to input mode. Figures 5-14 and 5-15 show block diagrams of port 3. Caution In the PD78F0537D, be sure to pull the P31 pin down before a reset release to prevent malfunction. Remark The P31 and P32 pins of the PD78F0537D can be used as on-chip debug mode setting pins (OCD1A, OCD1B) when the on-chip debug function is used. For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). Figure 5-14. Block Diagram of P30 to P32 EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P30 to P32) P30/INTP1, P31/INTP2/OCD1ANote, P32/INTP3/OCD1BNote WRPM PM3 PM30 to PM32 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal Note PD78F0537D only 114 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P33) P33/INTP4/TI51/TO51 WRPM PM3 PM33 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 115 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 Port 4 is a 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to input mode. Figure 5-16 shows a block diagram of port 4. Figure 5-16. Block Diagram of P40 to P43 EVDD WRPU PU4 PU40 to PU43 P-ch Internal bus RD Selector WRPORT P4 Output latch (P40 to P43) WRPM PM4 PM40 to PM43 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 116 Preliminary User's Manual U17260EJ3V1UD P40 to P43 CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 Port 5 is a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P53 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Reset signal generation sets port 5 to input mode. Figure 5-17 shows a block diagram of port 5. Figure 5-17. Block Diagram of P50 to P53 EVDD WRPU PU5 PU50 to PU53 P-ch Internal bus RD Selector WRPORT P5 Output latch (P50 to P53) WRPM P50 to P53 PM5 PM50 to PM53 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 117 CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O, clock I/O, and external clock input. Reset signal generation sets port 6 to input mode. Figures 5-18 to 5-20 show block diagrams of port 6. Remark When using P62/EXSCL0 as an external clock input pin of the serial interface, input a clock of 6.4 MHz to it. Figure 5-18. Block Diagram of P60 and P61 Alternate function Selector RD Internal bus WRPORT P6 Output latch (P60, P61) WRPM PM6 PM60, PM61 Alternate function P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal 118 Preliminary User's Manual U17260EJ3V1UD P60/SCL0, P61/SDA0 CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P62 Alternate function Internal bus Selector RD WRPORT P6 Output latch (P62) P62/EXSCL0 WRPM PM6 PM62 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Figure 5-20. Block Diagram of P63 Selector Internal bus RD WRPORT P6 Output latch (P63) P63 WRPM PM6 PM63 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 119 CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). This port can also be used for key return input. Reset signal generation sets port 7 to input mode. Figure 5-21 shows a block diagram of port 7. Figure 5-21. Block Diagram of P70 to P77 EVDD WRPU PU7 PU70 to PU77 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P70 to P77) P70/KR0 to P77/KR7 WRPM PM7 PM70 to PM77 P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal 120 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 12 Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Reset signal generation sets port 12 to input mode. Figures 5-22 and 5-23 show block diagrams of port 12. Caution When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary. Remark The X1 and X2 pins of the PD78F0537D can be used as on-chip debug mode setting pins (OCD0A, OCD0B) when the on-chip debug function is used. For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). Figure 5-22. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function Selector Internal bus RD WRPORT P12 Output latch (P120) P120/INTP0/EXLVI WRPM PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal Preliminary User's Manual U17260EJ3V1UD 121 CHAPTER 5 PORT FUNCTIONS Figure 5-23. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS Selector RD WRPORT P12 Output latch (P122/P124) P122/X2/EXCLK/OCD0BNote, P124/XT2/EXCLKS WRPM PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS Internal bus OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS Selector RD WRPORT P12 Output latch (P121/P123) P121/X1/OCD0ANote, P123/XT1 WRPM PM12 PM121/PM123 OSCCTL OSCSEL/ OSCSELS P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 OSCCTL: Clock operation mode select register RD: Read signal WRxx: Write signal Note PD78F0537D only 122 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 5-24 shows a block diagram of port 13. Figure 5-24. Block Diagram of P130 Internal bus RD WRPORT P13 Output latch (P130) P13: Port register 13 RD: Read signal P130 WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software Preliminary User's Manual U17260EJ3V1UD 123 CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). This port can also be used for external interrupt request input, buzzer output, clock output, serial interface data I/O, clock I/O, busy input, and strobe output. Reset signal generation sets port 14 to input mode. Figures 5-25 shows a block diagram of port 14. Figure 5-25. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P140, P141) P140/PCL/INTP6, P141/BUZ/INTP7 WRPM PM14 PM140, PM141 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal 124 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. * Port mode registers (PM0 to PM7, PM12, PM14) * Port registers (P0 to P7, P12 to P14) * Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) * A/D port configuration register (ADPC) (1) Port mode registers (PM0 to PM7, PM12, and PM14) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function. Preliminary User's Manual U17260EJ3V1UD 125 CHAPTER 5 PORT FUNCTIONS Figure 5-26. Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W PM6 1 1 1 1 PM63 PM62 PM61 PM60 FF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W PM14 1 1 1 1 1 1 PM141 PM140 FF2EH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 7, 12, 14; n = 0 to 7) 126 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 5-27. Format of Port Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 P06 P05 P04 P03 P02 P01 P00 FF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch) R/W P3 0 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W P4 0 0 0 0 P43 P42 P41 P40 FF04H 00H (output latch) R/W P5 0 0 0 0 P53 P52 P51 P50 FF05H 00H (output latch) R/W P6 0 0 0 0 P63 P62 P61 P60 FF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W P12 0 0 0 P124 P123 P122 P121 P120 FF0CH 00H (output latch) R/W P13 0 0 0 0 0 0 0 P130 FF0DH 00H (output latch) R/W P14 0 0 0 0 0 0 P141 P140 FF0EH 00H (output latch) R/W m = 0 to 7, 12 to 14; n = 0 to 7 Pmn Output data control (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Preliminary User's Manual U17260EJ3V1UD 127 CHAPTER 5 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, or P140 and P141 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU5, PU7, PU12, and PU14. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU5, PU7, PU12, and PU14. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 5-28. Format of Pull-up Resistor Option Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 FF30H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W PU4 0 0 0 0 PU43 PU42 PU41 PU40 FF34H 00H R/W PU5 0 0 0 0 PU53 PU52 PU51 PU50 FF35H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W PU14 0 0 0 0 0 0 PU141 PU140 FF3EH 00H R/W PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7, 12, 14; n = 0 to 7) 128 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-29. Format of A/D Port Configuration Register (ADPC) Address: FF2FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Digital I/O (D)/analog input (A) switching P27/ P26/ P25/ P24/ P23/ P22/ P21/ P20/ ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 0 0 0 0 A A A A A A A A 0 0 0 1 A A A A A A A D 0 0 1 0 A A A A A A D D 0 0 1 1 A A A A A D D D 0 1 0 0 A A A A D D D D 0 1 0 1 A A A D D D D D 0 1 1 0 A A D D D D D D 0 1 1 1 A D D D D D D D 1 0 0 0 D D D D D D D D Other than above Setting prohibited Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2 (PM2). 2. Do not set a pin to be used as a digital I/O pin with ADPC by using the analog input channel specification register (ADS). 3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. Preliminary User's Manual U17260EJ3V1UD 129 CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 5.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 5.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. The data of the output latch is cleared when a reset signal is generated. 130 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-5. Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name PMxx Pxx I/O P00 TI000 Input 1 x P01 TI010 Input 1 x P02 SO11 P03 SI11 TO00 Note P04 Note SCK11 P05 P10 0 0 0 0 Input 1 x Input 1 x Output 0 1 Input 1 x TI001 Note Input 1 x TI011 Note Input 1 x TO01 Note Output 0 0 Input 1 x Output 0 1 TxD0 Output 0 1 SSI11 P06 Note Output Output Note SCK10 SI10 Input 1 x RxD0 Input 1 x P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P11 P14 RxD6 Input 1 x P15 TOH0 Output 0 0 P16 TOH1 Output 0 0 INTP5 Input 1 x TI50 Input 1 x TO50 Output 0 0 P17 Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. Remark x: Don't care PMxx: Port mode register Pxx: Port output latch Preliminary User's Manual U17260EJ3V1UD 131 CHAPTER 5 PORT FUNCTIONS Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function PMxx Pxx Input 1 x Function Name P20 to P27 Note 1 ANI0 to ANI7 Note 1 I/O P30 to P32 INTP1 to INTP3 Input 1 x P33 INTP4 Input 1 x TI51 Input 1 x TO51 Output 0 0 P60 SCL0 I/O 0 0 P61 SDA0 I/O 0 0 P62 EXSCL0 Input 1 x P70 to P77 KR0 to KR7 Input 1 x P120 INTP0 Input 1 x EXLVI Input 1 x Note 2 - x x Note 2 - x x x x P121 X1 P122 X2 EXCLK Note 2 P123 XT1 Note 2 P124 XT2 Note 2 EXCLKS P140 P141 Input Note 2 PCL - x x - x x Input x x Output 0 0 INTP6 Input 1 x BUZ Output 0 0 INTP7 Input 1 x Remarks 1. x: Don't care PMxx: Port mode register Pxx: Port output latch 2. The X1, X2, P31, and P32 pins of the PD78F0537D can be used as on-chip debug mode setting pins (OCD0A, OCD0B, OCD1A, OCD1B) when the on-chip debug function is used. For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). (Notes 1 and 2 are listed on the next page.) 132 Preliminary User's Manual U17260EJ3V1UD CHAPTER 5 PORT FUNCTIONS Notes 1. The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), the analog input channel specification register (ADS), and PM2. Table 5-6. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC Analog input selection PM2 Input mode Output mode ADS ANI0/P20 to ANI7/P27 Pins Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Digital I/O selection Input mode Output mode 2. Selects ANI. Setting prohibited Does not select ANI. Digital input Selects ANI. Setting prohibited Does not select ANI. Digital output When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 are I/O port pins). At this time, setting of PM121 to PM124 and P121 to P124 is not necessary. Preliminary User's Manual U17260EJ3V1UD 133 CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC). <2> Internal high-speed oscillator This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a reset release, the CPU always starts operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP instruction or using the internal oscillation mode register (RCM). An external main system clock (fEXCLK = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or using RCM. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal highspeed oscillation clock can be selected by using the main clock mode register (MCM). (2) Subsystem clock * Subsystem clock oscillator This circuit oscillates at a frequency of fXT = 32.768 kHz by connecting a 32.768 kHz resonator across XT1 and XT2. Oscillation can be stopped by using the processor clock control register (PCC) and clock operation mode select register (OSCCTL). An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by setting PCC and OSCCTL. Remarks 1. fX: 2. fRH: X1 clock oscillation frequency Internal high-speed oscillation clock frequency 3. fEXCLK: External main system clock frequency 4. fXT: XT1 clock oscillation frequency 5. fEXCLKS: External subsystem clock frequency 134 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (3) Internal low-speed oscillation clock (clock for watchdog timer) * Internal low-speed oscillator This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when "internal low-speed oscillator can be stopped by software" is set by option byte. The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates with the internal low-speed oscillation clock. * Watchdog timer * TMH1 (when fRL, fRL/27, or fRL/29 is selected) Remark fRL: Internal low-speed oscillation clock frequency 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Oscillators X1 oscillator XT1 oscillator Internal high-speed oscillator Internal low-speed oscillator Preliminary User's Manual U17260EJ3V1UD 135 136 Figure 6-1. Block Diagram of Clock Generator Internal bus Clock operation mode select register (OSCCTL) Main OSC control register (MOC) AMPH EXCLK OSCSEL Main clock mode register (MCM) MCS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 Processor clock control register (PCC) XTSTART CLS XSEL MCM0 CSS PCC2 PCC1 PCC0 3 4 STOP X1 oscillation stabilization time counter To subsystem clock oscillator Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) X2/EXCLK/ P122 fXH Crystal/ceramic oscillation fX External input clock fEXCLK Controller Main system fXP clock switch Internal highfRH speed oscillator (8 MHz (TYP.)) Subsystem clock oscillator XT1/P123 Crystal oscillation XT2/EXCLKS/ P124 External input clock 1/2 fXT fSUB fXP 22 RSTS LSRSTOP RSTOP Internal oscillation mode register (RCM) Internal bus fXP 24 fSUB 2 fEXCLKS Clock operation mode select register (OSCCTL) fXP 23 Internal lowspeed oscillator fRL (240 kHz (TYP.)) Watch timer, clock output XTSTART EXCLKS OSCSELS Processor clock control register (PCC) Prescaler fXP 2 Option byte 1: Cannot be stopped 0: Can be stopped CPU clock (fCPU) Watchdog timer, 8-bit timer H1 CHAPTER 6 CLOCK GENERATOR Preliminary User's Manual U17260EJ3V1UD X1/P121 Peripheral hardware clock (fPRS) Peripheral hardware clock switch Selector High-speed system clock oscillator CHAPTER 6 CLOCK GENERATOR Remarks 1. fX: 2. fRH: X1 clock oscillation frequency Internal high-speed oscillation clock frequency 3. fEXCLK: External main system clock frequency 4. fXH: High-speed system clock oscillation frequency 5. fXP: Main system clock oscillation frequency 6. fPRS: Peripheral hardware clock oscillation frequency 7. fCPU: CPU clock oscillation frequency 8. fXT: XT1 clock oscillation frequency 9. fEXCLKS: External subsystem clock frequency 10. fSUB: Subsystem clock oscillation frequency 11. fRL: Internal low-speed oscillation clock frequency 6.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. * Clock operation mode select register (OSCCTL) * Processor clock control register (PCC) * Internal oscillation mode register (RCM) * Main OSC control register (MOC) * Main clock mode register (MCM) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the on-chip oscillator. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Preliminary User's Manual U17260EJ3V1UD 137 CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH Symbol OSCCTL After reset: 00H <7> <6> R/W <5> <4> Note Note 3 2 1 <0> 0 0 0 AMPH EXCLK OSCSEL EXCLKS EXCLK OSCSEL High-speed system clock pin operation mode 0 0 I/O port mode I/O port 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 I/O port mode I/O port 1 1 External clock input mode I/O port AMPH Note OSCSELS P121/X1 pin P122/X2/EXCLK pin External clock input Operating frequency control 0 1 MHz fXH 10 MHz 1 10 MHz < fXH 20 MHz EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor clock control register (PCC)). See (3) Setting of operation mode for subsystem clock pin. Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. 2. Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. The clock supply to the CPU is stopped for 5 s (MIN.) after AMPH has been set to 1. 3. If the STOP instruction is executed with AMPH set to 1 when the internal highspeed oscillation clock or external main system clock is used as the CPU clock, then the clock supply to the CPU is stopped for 5 s (MIN.) after the STOP mode has been released. If the X1 clock is used as the CPU clock, oscillation stabilization time is counted after the STOP mode has been released. 4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). Remark fXH: High-speed system clock oscillation frequency 138 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 6-3. Format of Processor Clock Control Register (PCC) Address: FFFBH Symbol PCC After reset: 01H 7 R/W 6 XTSTART 0 Note2 Note 1 <5> <4> 3 2 1 0 CLS CSS 0 PCC2 PCC1 PCC0 CLS CPU clock status 0 Main system clock 1 Subsystem clock CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 0 0 0 fSUB/2 0 0 1 0 1 0 0 1 1 1 0 0 1 Other than above CPU clock (fCPU) selection Setting prohibited Notes 1. Bit 5 is read-only. 2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the Clock operation mode select register (OSCCTL)). See (3) Setting of operation mode for subsystem clock pin. Caution Be sure to clear bits 3 and 7 to 0. Remarks 1. fXP: Main system clock oscillation frequency 2. fSUB: Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KE2. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2. Preliminary User's Manual U17260EJ3V1UD 139 CHAPTER 6 CLOCK GENERATOR Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Main System Clock High-Speed System Clock At 10 MHz Operation Note At 20 MHz Operation Subsystem Clock Internal High-Speed Note Oscillation Clock At 8 MHz (TYP.) Operation At 32.768 kHz Operation fXP 0.2 s 0.1 s 0.25 s (TYP.) - fXP/2 0.4 s 0.2 s 0.5 s (TYP.) - fXP/2 2 0.8 s 0.4 s 1.0 s (TYP.) - fXP/2 3 1.6 s 0.8 s 2.0 s (TYP.) - fXP/2 4 3.2 s 1.6 s 4.0 s (TYP.) - fSUB/2 - 122.1 s - Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (highspeed system clock/internal high-speed oscillation clock) (see Figure 6-6). (3) Setting of operation mode for subsystem clock pin The operation mode for the subsystem clock pin can be set by using bit 6 (XTSTART) of the processor clock control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register (OSCCTL) in combination. Table 6-3. Setting of Operation Mode for Subsystem Clock Pin PCC OSCCTL Subsystem Clock Pin Operation Mode P123/XT1 Pin P124/XT2/EXCLKS Pin Bit 6 Bit 5 Bit 4 XTSTART EXCLKS OSCSELS 0 0 0 I/O port mode I/O port 0 0 1 XT1 oscillation mode Crystal resonator connection 0 1 0 I/O port mode I/O port 0 1 1 External clock input mode I/O port 1 x x XT1 oscillation mode Crystal resonator connection Caution External clock input Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating with main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS. Remark 140 x: don't care Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80HNote 1. Figure 6-4. Format of Internal Oscillation Mode Register (RCM) Note 1 Address: FFA0H After reset: 80H R/W Note 2 Symbol <7> 6 5 4 3 2 <1> <0> RCM RSTS 0 0 0 0 0 LSRSTOP RSTOP RSTS Status of internal high-speed oscillator 0 Waiting for accuracy stabilization of internal high-speed oscillator 1 Stability operating of internal high-speed oscillator LSRSTOP Internal low-speed oscillator oscillating/stopped 0 Internal low-speed oscillator oscillating 1 Internal low-speed oscillator stopped RSTOP Internal high-speed oscillator oscillating/stopped 0 Internal high-speed oscillator oscillating 1 Internal high-speed oscillator stopped Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator has been stabilized. 2. Bit 7 is read-only. Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1. Preliminary User's Manual U17260EJ3V1UD 141 CHAPTER 6 CLOCK GENERATOR (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 6-5. Format of Main OSC Control Register (MOC) Address: FFA2H After reset: 80H R/W Symbol <7> 6 5 4 3 2 1 0 MOC MSTOP 0 0 0 0 0 0 0 Control of high-speed system clock operation MSTOP X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is enabled 1 X1 oscillator stopped External clock from EXCLK pin is disabled Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock other than the high-speed system clock. Specifically, set under either of the following conditions. * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) In addition, stop peripheral hardware that is operating on the high-speed system clock before setting MSTOP to 1. 2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select register (OSCCTL) is 0 (I/O port mode). 3. The peripheral hardware cannot operate when the peripheral hardware clock is stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. 142 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 6-6. Format of Main Clock Mode Register (MCM) Address: FFA1H After reset: 00H R/W Note Symbol 7 6 5 4 3 <2> <1> <0> MCM 0 0 0 0 0 XSEL MCS MCM0 XSEL MCM0 Selection of clock supplied to main system clock and peripheral hardware Main system clock (fXP) 0 0 Peripheral hardware clock (fPRS) 0 Internal high-speed oscillation clock Internal high-speed oscillation clock 1 (fRH) (fRH) 1 0 1 1 High-speed system clock (fXH) High-speed system clock (fXH) MCS Main system clock status 0 Operates with internal high-speed oscillation clock 1 Operates with high-speed system clock Note Bit 1 is read-only. Cautions 1. XSEL can be changed only once after a reset release. 2. A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0. * Watchdog timer (operates with internal low-speed oscillation clock) * When "fRL", "fRL/27", or "fRL/29" is selected as the count clock for 8-bit timer H1 (operates with internal low-speed oscillation clock) * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) Preliminary User's Manual U17260EJ3V1UD 143 CHAPTER 6 CLOCK GENERATOR (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 6-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 fX = 20 MHz 11 204.8 s min. 102.4 s min. 13 819.2 s min. 409.6 s min. 14 1.64 ms min. 819.2 s min. 15 3.27 ms min. 1.64 ms min. 16 6.55 ms min. 3.27 ms min. 2 /fX min. 2 /fX min. 2 /fX min. 1 1 1 1 0 2 /fX min. 1 1 1 1 1 2 /fX min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark 144 fX: X1 clock oscillation frequency Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 6-8. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 0 1 1 204.8 s 102.4 s 13 819.2 s 409.6 s 2 /fX 0 2 /fX 14 1.64 ms 819.2 s 15 3.27 ms 1.64 ms 16 6.55 ms 3.27 ms 0 1 1 2 /fX 1 0 0 2 /fX 1 0 1 2 /fX Other than above fX = 20 MHz 11 Setting prohibited Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency Preliminary User's Manual U17260EJ3V1UD 145 CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. Figure 6-9 shows an example of the external circuit of the X1 oscillator. Figure 6-9. Example of External Circuit of X1 Oscillator (Crystal or Ceramic Oscillation) VSS X1 X2 Crystal resonator or ceramic resonator Cautions are listed on the next page. 6.4.2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. Figure 6-10 shows an example of the external circuit of the XT1 oscillator. Figure 6-10. Example of External Circuit of XT1 Oscillator (Crystal Oscillation) VSS XT1 32.768 kHz XT2 Cautions are listed on the next page. 146 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-11 shows examples of incorrect resonator connection. Figure 6-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS Remark X1 X2 VSS X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Preliminary User's Manual U17260EJ3V1UD 147 CHAPTER 6 CLOCK GENERATOR Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS X1 A B X2 C High current (e) Signals are fetched VSS Remark X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. 148 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to VDD or VSS via a resistor. Output (PM123/PM124 = 0): Leave open. Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL) PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12) 6.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/KE2. Oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)). 6.4.5 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/KE2. The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock. "Can be stopped by software" or "Cannot be stopped" can be selected by the option byte. When "Can be stopped by software" is set, oscillation can be controlled by the internal oscillation mode register (RCM). After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte. 6.4.6 Prescaler The prescaler generates various clocks by dividing the main system clock when the main system clock is selected as the clock to be supplied to the CPU. Preliminary User's Manual U17260EJ3V1UD 149 CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6-1). * Main system clock fXP * High-speed system clock fXH X1 clock fX External main system clock fEXCLK * Internal high-speed oscillation clock fRH * Subsystem clock fSUB * XT1 clock fXT * External subsystem clock fEXCLKS * Internal low-speed oscillation clock fRL * CPU clock fCPU * Peripheral hardware clock fPRS The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the 78K0/KE2, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance can be improved. When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-12. 150 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR Figure 6-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply voltage (VDD) 1.8 V 1.59 V (TYP.) 0.5 V/ms (MAX.) 0V Internal reset signal <1> CPU clock Reset processing (20 s (TYP.)) <3> Waiting for voltage stabilization (3.24 ms (TYP.)) <5> Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected) Waiting for oscillation accuracy stabilization <4> X1 clock oscillation stabilization time: 11 2 /fX to 216/fXNote Starting X1 oscillation <4> is specified by software. Starting XT1 oscillation is specified by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> When the power supply voltage rises with a slope of 0.5 V/ms (MAX.), the CPU starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MAX.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE = 1) (see Figure 6-13). By doing so, the CPU operates with the same timing as <2> and thereafter in Figure 6-12 after reset release by the RESET pin. 2. It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Preliminary User's Manual U17260EJ3V1UD 151 CHAPTER 6 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock). Figure 6-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) 2.7 V (TYP.) Power supply voltage (VDD) 0V Internal reset signal <1> <3> Reset processing (20 s (TYP.)) <5> Internal high-speed oscillation clock CPU clock Switched by software High-speed system clock <5> Subsystem clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected) Waiting for oscillation accuracy stabilization <4> X1 clock oscillation stabilization time: 211/fX to 216/fXNote Starting X1 oscillation <4> is specified by software. Starting XT1 oscillation is specified by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit. <2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> After the reset is released and reset processing is performed, the CPU starts operation on the internal highspeed oscillation clock. <4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling highspeed system clock and (1) in 6.6.3 Example of controlling subsystem clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3 Example of controlling subsystem clock). Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation stabilization time select register (OSTS). Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. 152 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock). 6.6 Controlling Clock 6.6.1 Controlling high-speed system clock The following two types of high-speed system clocks are available. * X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. * External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins. Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating X1 clock (2) When using external main system clock (3) When using high-speed system clock as CPU clock and peripheral hardware clock (4) When stopping high-speed system clock (1) Example of setting procedure when oscillating the X1 clock <1> Setting frequency (OSCCTL register) Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used. Note AMPH Operating Frequency Control 0 1 MHz f XH 10 MHz 1 10 MHz < f XH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU is stopped for 5 s (MIN.). Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode. EXCLK OSCSEL Operation Mode of High- P121/X1 Pin P122/X2/EXCLK Pin Speed System Clock Pin 0 1 X1 oscillation mode Crystal/ceramic resonator connection <3> Controlling oscillation of X1 clock (MOC register) If MSTOP is cleared to 0, the X1 oscillator starts oscillating. Preliminary User's Manual U17260EJ3V1UD 153 CHAPTER 6 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock. Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. 2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)). (2) Example of setting procedure when using the external main system clock <1> Setting frequency (OSCCTL register) Using AMPH, set the frequency to be used. Note AMPH Operating Frequency Control 0 1 MHz f XH 10 MHz 1 10 MHz < f XH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU is stopped for 5 s (MIN.). Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode. EXCLK OSCSEL Operation Mode of High- P121/X1 Pin P122/X2/EXCLK Pin Speed System Clock Pin 1 1 External clock input mode I/O port External clock input <3> Controlling external main system clock input (MOC register) When MSTOP is cleared to 0, the input of the external main system clock is enabled. Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is operating. 2. Set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)). (3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral hardware clock <1> Setting high-speed system clock oscillationNote (See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. 154 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (f XP ) 1 1 Peripheral Hardware Clock (f PRS ) High-speed system clock (f XH ) High-speed system clock (f XH ) Caution If the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 Other than above CPU Clock (fCPU) Selection Setting prohibited (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. * Executing the STOP instruction to set the STOP mode * Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used) (a) To execute a STOP instruction <1> Setting to stop peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 21 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is stopped (the input of the external clock is disabled). Preliminary User's Manual U17260EJ3V1UD 155 CHAPTER 6 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to the subsystem clock or internal high-speed oscillation clock. CLS MCS CPU Clock Status 0 0 Internal high-speed oscillation clock 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the high-speed system clock (MOC register) When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled). Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop peripheral hardware that is operating on the high-speed system clock. 6.6.2 Example of controlling internal high-speed oscillation clock The following describes examples of clock setting procedures for the following cases. (1) When restarting oscillation of the internal high-speed oscillation clock (2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) When stopping the internal high-speed oscillation clock (1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1 <1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register) When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating. <2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register) Wait until RSTS is set to 1Note 2. Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. 156 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> * Restarting oscillation of the internal high-speed oscillation clockNote (See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock). * Oscillating the high-speed system clockNote (This setting is required when using the high-speed system clock as the peripheral hardware clock. See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when the internal high-speed oscillation clock or highspeed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (f XP ) 0 0 0 1 1 0 Peripheral Hardware Clock (f PRS ) Internal high-speed oscillation clock (f RH ) Internal high-speed oscillation clock (f RH ) High-speed system clock (f XH ) <3> Selecting the CPU clock division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS PCC2 PCC1 PCC0 0 0 0 0 fXP 0 0 1 fXP/2 (default) 0 1 0 fXP/2 2 0 1 1 fXP/2 3 1 0 0 fXP/2 4 Other than above CPU Clock (fCPU) Selection Setting prohibited (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. * Executing the STOP instruction to set the STOP mode * Setting RSTOP to 1 and stopping the internal high-speed oscillation clock (a) To execute a STOP instruction <1> Setting of peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 21 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and internal highspeed oscillation clock is stopped. Preliminary User's Manual U17260EJ3V1UD 157 CHAPTER 6 CLOCK GENERATOR (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock. When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change the CPU clock to the high-speed system clock or subsystem clock. CLS MCS CPU Clock Status 0 0 Internal high-speed oscillation clock 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the internal high-speed oscillation clock (RCM register) When RSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 6.6.3 Example of controlling subsystem clock The following two types of subsystem clocks are available. * XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. * External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating XT1 clock (2) When using external subsystem clock (3) When using subsystem clock as CPU clock (4) When stopping subsystem clock (1) Example of setting procedure when oscillating the XT1 clock <1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers) When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from port mode to XT1 oscillation mode. XTSTART EXCLKS OSCSELS Operation Mode of P123/XT1 Pin Subsystem Clock Pin 0 0 1 1 x x Remark XT1 oscillation mode P124/XT2/ EXCLKS Pin Crystal/ceramic resonator connection x: don't care <2> Waiting for the stabilization of the subsystem clock oscillation Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. 158 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins. XTSTART EXCLKS OSCSELS 0 1 1 Operation Mode of Subsystem Clock Pin External clock input mode P123/XT1 Pin I/O port P124/XT2/ EXCLKS Pin External clock input Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. (3) Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillationNote (See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. CSS PCC2 PCC1 PCC0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Other than above CPU Clock (fCPU) Selection fSUB/2 Setting prohibited (4) Example of setting procedure when stopping the subsystem clock <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock. When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal high-speed oscillation clock or high-speed system clock. CLS MCS CPU Clock Status 0 0 Internal high-speed oscillation clock 0 1 High-speed system clock 1 x Subsystem clock <2> Stopping the subsystem clock (OSCCTL register) When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled). Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. 2. The subsystem clock oscillation cannot be stopped using the STOP instruction. Preliminary User's Manual U17260EJ3V1UD 159 CHAPTER 6 CLOCK GENERATOR 6.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. * Watchdog timer * 8-bit timer H1 (if fRL is selected as the count clock) In addition, the following operation modes can be selected by the option byte. * Internal low-speed oscillator cannot be stopped * Internal low-speed oscillator can be stopped by software The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte. (1) Example of setting procedure when stopping the internal low-speed oscillation clock <1> Setting LSRSTOP to 1 (RCM register) When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped. (2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock <1> Clearing LSRSTOP to 0 (RCM register) When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted. Caution If "Internal low-speed oscillator cannot be stopped" is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. 6.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 6-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Supplied Clock Clock Supplied to CPU XSEL CSS MCM0 EXCLK Clock Supplied to Peripheral Hardware 0 0 x x X1 clock 1 0 0 0 External main system clock 1 0 0 1 X1 clock 1 0 1 0 External main system clock 1 0 1 1 Internal high-speed oscillation clock 0 1 x x X1 clock 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 Internal high-speed oscillation clock Internal high-speed oscillation clock Subsystem clock External main system clock Remarks 1. XSEL: Bit 2 of the main clock mode register (MCM) 2. CSS: Bit 4 of the processor clock control register (PCC) 3. MCM0: Bit 0 of MCM 4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL) 5. x: 160 don't care Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.6.6 CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Power ON VDD < 1.59 V (TYP.) (A) VDD 1.59 V (TYP.) Reset release Internal low-speed oscillation: Operating Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating (D) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU CPU: Operating with internal highspeed oscillation (H) CPU: Internal highspeed oscillation STOP CPU: Operating with XT1 oscillation or EXCLKS input (E) CPU: Internal highspeed oscillation HALT (C) (G) CPU: XT1 oscillation/EXCLKS input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operating VDD 1.8 V (MIN.) (B) CPU: Operating with X1 oscillation or EXCLK input Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operable (I) CPU: X1 oscillation/EXCLK input STOP (F) CPU: X1 oscillation/EXCLK input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Operable Remark Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Stops Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation: Stops In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (20 s (TYP.)). Preliminary User's Manual U17260EJ3V1UD 161 CHAPTER 6 CLOCK GENERATOR Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) (B) SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register AMPH EXCLK OSCSEL MSTOP OSTC XSEL MCM0 1 1 1 1 1 1 1 1 Register Status Transition (A) (B) (C) (X1 clock: 1 MHz fXH 0 0 1 0 10 MHz) Must be checked (A) (B) (C) (external main clock: 1 MHz 0 1 1 0 fXH 10 MHz) Must not be checked (A) (B) (C) (X1 clock: 10 MHz < fXH 1 0 1 0 20 MHz) Must be checked (A) (B) (C) (external main clock: 10 MHz < 1 1 1 0 fXH 20 MHz) Must not be checked Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)). (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS Waiting for OSCSELS CSS Oscillation Status Transition Stabilization (A) (B) (D) (XT1 clock) (A) (B) (D) (external subsystem clock) 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: 162 Don't care Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Note AMPH EXCLK OSCSEL OSTC MSTOP XSEL Note MCM0 Register Status Transition (B) (C) (X1 clock: 1 MHz fXH 10 MHz) 0 0 1 0 Must be 1 1 1 1 1 1 1 1 checked (B) (C) (external main clock: 1 MHz fXH 0 1 1 0 10 MHz) Must not be checked (B) (C) (X1 clock: 10 MHz < fXH 20 MHz) 1 0 1 0 Must be checked (B) (C) (external main clock: 10 MHz < fXH 1 1 1 0 20 MHz) Must not be checked Unnecessary if these registers Unnecessary if the are already set CPU is operating with the high-speed system clock Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)). (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS Waiting for OSCSELS CSS Oscillation Status Transition Stabilization (B) (D) (XT1 clock) (B) (D) (external subsystem clock) 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Unnecessary if the CPU is operating with the subsystem clock Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: Don't care Preliminary User's Manual U17260EJ3V1UD 163 CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 0 Confirm this flag is 1. 0 Status Transition (C) (B) Unnecessary if the CPU is operating with the internal high-speed oscillation clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register XTSTART EXCLKS Waiting for OSCSELS CSS Oscillation Status Transition Stabilization (C) (D) (XT1 clock) (C) (D) (external subsystem clock) 0 0 1 1 x x 0 1 1 Necessary 1 Unnecessary 1 Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 CSS 0 Confirm this flag 0 0 Status Transition (D) (B) is 1. Unnecessary if the CPU is operating Unnecessary if with the internal high-speed XSEL is 0 oscillation clock Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. MCM0: Bit 0 of the main clock mode register (MCM) EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL) 164 RSTS, RSTOP: Bits 7 and 0 of the internal oscillation mode register (RCM) XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC) x: Don't care Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Note Setting Flag of SFR Register AMPH EXCLK OSCSEL OSTC MSTOP XSEL Note MCM0 CSS 1 1 0 1 1 0 1 1 0 1 1 0 Register Status Transition (D) (C) (X1 clock: 1 MHz fXH 0 0 1 Must be 0 10 MHz) checked (D) (C) (external main clock: 1 MHz 0 1 1 0 Must not be fXH 10 MHz checked (D) (C) (X1 clock: 10 MHz < fXH 1 0 1 Must be 0 20 MHz) checked (D) (C) (external main clock: 10 MHz < 1 1 1 0 Must not be fXH 20 MHz) checked Unnecessary if these registers Unnecessary if the Unnecessary if this register are already set CPU is operating is already set with the high-speed system clock Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)). (10) * HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B) * HALT mode (F) set while CPU is operating with high-speed system clock (C) * HALT mode (G) set while CPU is operating with subsystem clock (D) Status Transition Setting (B) (E) Executing HALT instruction (C) (F) (D) (G) (11) * STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B) * STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition Setting (B) (H) Stopping peripheral functions that (C) (I) cannot operate in STOP mode Executing STOP instruction Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL) MSTOP: Bit 7 of the main OSC control register (MOC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) CSS: Bit 4 of the processor clock control register (PCC) Preliminary User's Manual U17260EJ3V1UD 165 CHAPTER 6 CLOCK GENERATOR 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-6. Changing CPU Clock CPU Clock Before Change Internal high- Condition Before Change Processing After Change After Change X1 clock Stabilization of X1 oscillation * Internal high-speed oscillator can be speed oscillation * MSTOP = 0, OSCSEL = 1, EXCLK = 0 clock * After elapse of oscillation stabilization time * Clock supply to CPU is stopped for 5 s External main Enabling input of external clock from EXCLK (MIN.) after AMPH has been set to 1. system clock pin stopped (RSTOP = 1). * MSTOP = 0, OSCSEL = 1, EXCLK = 1 X1 clock Internal high- Oscillation of internal high-speed oscillator X1 oscillation can be stopped (MSTOP = 1). External main speed oscillation * RSTOP = 0 External main system clock input can be system clock clock Internal high- XT1 clock speed oscillation clock disabled (MSTOP = 1). Stabilization of XT1 oscillation Operating current can be reduced by * XTSTART = 0, EXCLKS = 0, stopping internal high-speed oscillator OSCSELS = 1, or XTSTART = 1 * After elapse of oscillation stabilization time X1 clock (RSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main External main system clock input can be system clock disabled (MSTOP = 1). Internal high- External Enabling input of external clock from Operating current can be reduced by speed oscillation subsystem clock EXCLKS pin stopping internal high-speed oscillator * XTSTART = 0, EXCLKS = 1, (RSTOP = 1). clock OSCSELS = 1 X1 clock X1 oscillation can be stopped (MSTOP = 1). External main External main system clock input can be system clock disabled (MSTOP = 1). XT1 clock, Internal high- Oscillation of internal high-speed oscillator XT1 oscillation can be stopped or external external speed oscillation and selection of internal high-speed subsystem clock input can be disabled subsystem clock clock oscillation clock as main system clock (OSCSELS = 0). * RSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock subsystem clock input can be disabled (OSCSELS = 0). * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time * MCS = 1 External main Enabling input of external clock from EXCLK system clock pin and selection of high-speed system clock as main system clock * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * MCS = 1 166 * XT1 oscillation can be stopped or external Preliminary User's Manual U17260EJ3V1UD * Clock supply to CPU is stopped for 5 s (MIN.) after AMPH has been set to 1. CHAPTER 6 CLOCK GENERATOR 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the pre-switchover clock for several clocks (see Table 6-7). Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 5 (CLS) of the PCC register. Table 6-7. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor Set Value Before Set Value After Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 1 0 0 0 0 0 0 0 0 0 16 clocks 0 0 1 8 clocks 0 1 0 4 clocks 4 clocks 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 16 clocks 16 clocks 16 clocks 2fXP/fSUB clocks 8 clocks 8 clocks 8 clocks fXP/fSUB clocks 4 clocks 4 clocks fXP/2fSUB clocks 0 1 1 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 clock 1 clock 1 clock 2 clocks x x x 2 clocks 2 clocks 2 clocks 2 clocks fXP/4fSUB clocks fXP/8fSUB clocks 2 clocks Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remarks 1. The number of clocks listed in Table 6-7 is the number of CPU clocks before switchover. 2. When switching the CPU clock from the subsystem clock to the main system clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. Example When switching CPU clock from fSUB/2 to fXP/2 (@ oscillation with fSUB = 32.768 kHz, fXP = 10 MHz) fXP/fSUB = 10000/32.768 305.1 306 clocks By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the pre-switchover clock for several clocks (see Table 6-8). Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be ascertained using bit 1 (MCS) of MCM. Preliminary User's Manual U17260EJ3V1UD 167 CHAPTER 6 CLOCK GENERATOR Table 6-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 0 1 1 + 2fRH/fXH clock 1 1 + 2fXH/fRH clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Remarks 1. The number of clocks listed in Table 6-8 is the number of main system clocks before switchover. 2. Calculate the number of clocks in Table 6-8 by removing the decimal portion. Example When switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz) 1 + 2fRH/fXH = 1 + 2 x 8/10 = 1 + 2 x 0.8 = 1 + 1.6 = 2.6 2 clocks 6.6.9 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 6-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register Internal high-speed MCS = 1 or CLS = 1 oscillation clock (The CPU is operating on a clock other than the internal high-speed RSTOP = 1 oscillation clock) X1 clock MCS = 1 or CLS = 1 External main system clock (The CPU is operating on a clock other than the high-speed system clock) XT1 clock CLS = 0 External subsystem clock (The CPU is operating on a clock other than the subsystem clock) 168 MSTOP = 1 OSCSELS = 0 Preliminary User's Manual U17260EJ3V1UD CHAPTER 6 CLOCK GENERATOR 6.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/KE2. Table 6-10. Peripheral Hardware and Source Clocks Peripheral Hardware Clock (fPRS) Subsystem Clock (fSUB) Internal LowSpeed Oscillation Clock (fRL) TM50 Output 00 Y N N N Y (TI000 pin) 01 Y N N N Y (TI001 pin) Source Clock Peripheral Hardware 16-bit timer/ event counter External Clock from Peripheral Hardware Pins Note Note 8-bit timer/ event counter 50 Y N N N Y (TI50 pin) Note 51 Y N N N Y (TI51 pin) Note 8-Bit timer H0 Y N N Y H1 N Y N Y N N Watch timer Y Y N N N Watchdog timer N N Y N N Buzzer output Y N N N N Clock output Y Y N N N A/D converter Y N N N N UART0 Y N N Y N UART6 Y N N Y N CSI10 Y N N N Y (SCK10 pin) CSI11 Y N N N Y (SCK11 pin) IIC0 Y N N N Y (EXSCL0, Note SCL0 pin) Serial interface Note Note Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. Remark Y: Can be selected, N: Cannot be selected Preliminary User's Manual U17260EJ3V1UD 169 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The PD78F0531, 78F0532, and 78F0533 incorporate 16-bit timer/event counter 00, and the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D incorporate 16-bit timer/event counters 00 and 01. 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01Note have the following functions. (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (3) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (4) One-shot pulse output 16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. (5) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (6) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 170 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Time/counter 16-bit timer counter 0n (TM0n) Register 16-bit timer capture/compare registers 00n, 01n (CR00n, CR01n) Timer input TI00n, TI01n pins Timer output TO0n pin, output controller Control registers 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Figures 7-1 and 7-2 show the block diagrams. Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) Selector CRC002CRC001 CRC000 Noise eliminator TI010/TO00/P01 Selector To CR010 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00/TI010/ P01 Match 2 Output latch (P01) Noise eliminator TI000/P00 Clear PM01 16-bit timer capture/compare register 010 (CR010) Selector fPRS Selector fPRS fPRS/22 fPRS/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus Preliminary User's Manual U17260EJ3V1UD 171 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D) Internal bus Capture/compare control register 01 (CRC01) Selector CRC012CRC011 CRC010 Selector To CR011 Noise eliminator TI011/TO01/P06 16-bit timer capture/compare register 001 (CR001) INTTM001 Match Selector fPRS fPRS/24 fPRS/26 Noise eliminator fPRS 16-bit timer counter 01 (TM01) Output controller TO01/TI011/ P06 Match 2 Output latch (P06) Noise eliminator PM06 16-bit timer capture/compare register 011 (CR011) Selector TI001/P05/ SSI11 Clear INTTM011 CRC012 TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) PRM011 PRM010 Prescaler mode register 01 (PRM01) Internal bus (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, then input of the count clock is temporarily stopped, and the count value at that point is read. Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) After reset: 0000H FF11H (TM00), FFB1H (TM01) 15 14 13 12 11 10 9 FF10H (TM00), FFB0H (TM01) 8 7 6 5 TM0n (n = 0, 1) Remark 172 R PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 4 3 2 1 0 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when TMC0n3 and TMC0n2 = 00. The count value is reset to 0000H in the following cases. * At reset signal generation * If TMC0n3 and TMC0n2 are cleared to 00 * If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid edge to the TI00n pin * If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match * OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin Cautions 1. Even if TM0n is read, the value is not captured by CR01n. 2. When TM0n is read, input of the count clock is temporarily stopped and it is resumed after the timer has been read. Therefore, no clock miss occurs. (2) 16-bit timer capture/compare register 00n (CR00n)), 16-bit timer capture/compare register 01n (CR01n) CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by using CRC0n. Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00). The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see 7.5.1 Rewriting CR01n during TM0n operation. These registers can be read or written in 16-bit units. Reset signal generation sets these registers to 0000H. Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) FF13H (CR000), FFB3H (CR001) 15 14 13 12 11 10 9 After reset: 0000H R/W FF12H (CR000), FFB2H (CR001) 8 7 6 5 4 3 2 1 0 CR00n (n = 0, 1) Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (i) When CR00n is used as a compare register The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM00n) is generated if they match. The value is held until CR00n is rewritten. (ii) When CR00n is used as a capture register The count value of TM0n is captured to CR00n when a capture trigger is input. As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin can be selected by using CRC0n or PRM0n. Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) FF15H (CR010), FFB5H (CR011) 15 14 13 12 11 10 9 After reset: 0000H R/W FF14H (CR010), FFB4H (CR011) 8 7 6 5 4 3 2 1 0 CR01n (n = 0, 1) (i) When CR01n is used as a compare register The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM01n) is generated if they match. (ii) When CR01n is used as a capture register The count value of TM0n is captured to CR01n when a capture trigger is input. It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set by PRM0n. Cautions 1. To use this register as a compare register, set a value other than 0000H to CR00n and CR01n. 2. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. 3. If clearing of its 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined. 4. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has been once captured remains stored in CR00n unless the device is reset. If the mode has been changed to the comparison mode, be sure to set a comparison value. 5. CR00n/CR01n does not perform the capture operation when it is set in the comparison mode, even if a capture trigger is input to it. Remark 174 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. Capture Operation of CR00n and CR01n External Input Signal TI01n Pin Input TI00n Pin Input Capture Operation Capture operation of CRC0n1 = 1 Set values of ES0n1 and CRC0n1 bit = 0 Set values of ES1n1 and CR00n TI00n pin input ES0n0 TI01n pin input ES1n0 (reverse phase) Position of edge to be Position of edge to be captured captured 01: Rising 01: Rising 00: Falling 00: Falling 11: Both edges 11: Both edges (cannot be captured) INTTM00n signal is not Interrupt signal Capture operation of TI00n pin input CR01n Note Interrupt signal INTTM00n signal is generated even if value generated each time is captured. value is captured. Set values of ES0n1 and ES0n0 Position of edge to be captured 01: Rising 00: Falling 11: Both edges Interrupt signal INTTM01n signal is generated each time value is captured. Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit. Caution To capture the count value of the TM0n register to the CR00n register by using the phase reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated after the value has been captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM00n signal. Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n). ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n). 2. n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 Registers used to control 16-bit timer/event counters 00 and 01 are shown below. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) TMC0n is an 8-bit register that sets the 16-bit timer/event counter 0n operation mode, TM0n clear mode, and output timing, and detects an overflow. Rewriting TMC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). However, it can be changed when TMC0n3 and TMC0n2 are cleared to 00 (stopping operation) and when OVF0n is cleared to 0. TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets TMC0n to 00H. Caution 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3 are set to values other than 00 (operation stop mode), respectively. Set TMC0n2 and TMC0n3 to 00 to stop the operation. Remark 176 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 0 0 Operation enable of 16-bit timer/event counter 00 Disables TM00 operation. Stops supplying operating clock. Asynchronously resets the internal circuit. 0 1 Free-running timer mode 1 0 Clear & start mode entered by TI000 pin valid edge input 1 1 Clear & start mode entered upon a match between TM00 and CR000 Note TMC001 Condition to reverse timer output (TO00) 0 * Match between TM00 and CR000 or match between TM00 and CR010 1 * Match between TM00 and CR000 or match between TM00 and CR010 * Trigger input of TI000 pin valid edge OVF00 Clear (0) Set (1) TM00 overflow flag Clears OVF00 to 0 or TMC003 and TMC002 = 00 Overflow occurs. OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match between TM00 and CR000). It can also be set to 1 by writing 1 to OVF00. Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00). Preliminary User's Manual U17260EJ3V1UD 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC01 0 0 0 0 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 0 0 Operation enable of 16-bit timer/event counter 01 Disables TM01 operation. Stops supplying operating clock. Asynchronously resets the internal circuit. 0 1 Free-running timer mode 1 0 Clear & start mode entered by TI001 pin valid edge input 1 1 Clear & start mode entered upon a match between TM01 and CR001 Note TMC011 Condition to reverse timer output (TO01) 0 * Match between TM01 and CR001 or match between TM01 and CR011 1 * Match between TM01 and CR001 or match between TM01 and CR011 * Trigger input of TI001 pin valid edge OVF01 Clear (0) Set (1) TM01 overflow flag Clears OVF01 to 0 or TMC013 and TMC012 = 00 Overflow occurs. OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match between TM01 and CR001). It can also be set to 1 by writing 1 to OVF01. Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01). 178 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CRC0n to 00H. Remark PD78F0531, 78F0532, 78F0533 n = 0: n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC001 CR000 capture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00. If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot be detected. CRC000 CR000 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and CR000), be sure to set CRC000 to 0. Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). Preliminary User's Manual U17260EJ3V1UD 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock TM0n N-3 N-2 N-1 N N+1 TI00n Rising edge detection CR01n N INTTM01n Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Figure 7-10. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC01 0 0 0 0 0 CRC012 CRC011 CRC010 CRC012 CR011 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC011 CR001 capture trigger selection 0 Captures on valid edge of TI011 pin 1 Captures on valid edge of TI001 pin by reverse phase Note The valid edge of the TI011 and TI001 pin is set by PRM01. If ES011 and ES010 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI001 pin cannot be detected. CRC010 CR001 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and CR001), be sure to set CRC010 to 0. Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the INTTM001 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see Figure 7-9 Example of CR01n Capture Operation (When Rising Edge Is Specified). 180 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation. However, TOC0n4 can be rewritten during timer operation as a means to rewrite CR01n (see 7.5.1 Rewriting CR01n during TM0n operation). TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TOC0n to 00H. Caution Be sure to set TOC0n using the following procedure. <1> Set TOC0n4 and TOC0n1 to 1. <2> Set only TOE0n to 1. <3> Set either of LVS0n or LVR0n to 1. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software 0 - 1 One-shot pulse output The value of this bit is always "0" when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode. If it is set to 1, TM00 is cleared and started. OSPE00 One-shot pulse output operation control 0 Successive pulse output 1 One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI000 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and CR000. TOC004 TO00 pin output control on match between CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM010) is generated even when TOC004 = 0. LVS00 LVR00 Setting of TO00 pin output status 0 0 No change 0 1 Initial value of TO00 pin output is low level (TO00 pin output is cleared to 0). 1 0 Initial value of TO00 pin output is high level (TO00 pin output is set to 1). 1 1 Setting prohibited * LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin. If the initial value does not have to be set, leave LVS00 and LVR00 as 00. * Be sure to set LVS00 and LVR00 when TOE00 = 1. LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited. * LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO00 pin can be set. Even if these bits are cleared to 0, output of the TO00 pin is not affected. * The values of LVS00 and LVR00 are always 0 when they are read. * For how to set LVS00 and LVR00, see 7.5.2 Setting LVS0n and LVR0n. TOC001 TO00 pin output control on match between CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM000) is generated even when TOC001 = 0. TOE00 182 TO00 pin output control 0 Disables output (TO00 pin output fixed to low level) 1 Enables output Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC01 0 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger via software 0 - 1 One-shot pulse output The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot pulse output mode. If it is set to 1, TM01 is cleared and started. OSPE01 One-shot pulse output operation control 0 Successive pulse output 1 One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI001 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and CR001. TOC014 TO01 pin output control on match between CR011 and TM01 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM011) is generated even when TOC014 = 0. LVS01 LVR01 Setting of TO01 pin output status 0 0 No change 0 1 Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0). 1 0 Initial value of TO01 pin output is high level (TO01 pin output is set to 1). 1 1 Setting prohibited * LVS01 and LVR01 can be used to set the initial value of the output level of the TO01 pin. If the initial value does not have to be set, leave LVS01 and LVR01 as 00. * Be sure to set LVS01 and LVR01 when TOE01 = 1. LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited. * LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO01 pin can be set. Even if these bits are cleared to 0, output of the TO01 pin is not affected. * The values of LVS01 and LVR01 are always 0 when they are read. * For how to set LVS01 and LVR01, see 7.5.2 Setting LVS0n and LVR0n. TOC011 TO01 pin output control on match between CR001 and TM01 0 Disables inversion operation 1 Enables inversion operation The interrupt signal (INTTM001) is generated even when TOC011 = 0. TOE01 TO01 pin output control 0 Disables output (TO01 pin output is fixed to low level) 1 Enables output Preliminary User's Manual U17260EJ3V1UD 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PRM0n to 00H. Cautions 1. Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11 (to specify the valid edge of the TI00n pin as a count clock). * Clear & start mode entered by the TI00n pin valid edge * Setting the TI00n pin as a capture trigger 2. If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at the same time. Select either of the functions. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 184 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES101 ES100 ES001 ES000 0 0 PRM001 PRM000 ES101 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES001 ES000 TI010 pin valid edge selection TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 Count clock selection fPRS = 2 MHz 0 0 1 1 0 1 0 1 fPRS fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 2 MHz 5 MHz 10 MHz 20 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 8 7.81 kHz 19.53 kHz 39.06 kHz 78.12 kHz TI000 valid edge Note Note The external clock requires a pulse two cycles longer than internal clock (fPRS). Remark fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-14. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM01 ES111 ES110 ES011 ES010 0 0 PRM011 PRM010 ES111 ES110 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES011 ES010 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM011 PRM010 TI011 pin valid edge selection TI001 pin valid edge selection Count clock selection fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 fPRS/2 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz 1 0 fPRS/2 6 31.25 kHz 78.125 kHz 156.25 kHz 312.5 kHz 1 1 TI001 valid edge Note Note The external clock requires a pulse two cycles longer than internal clock (fPRS). Remark 186 fPRS = 20 MHz fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latches of P01 and P06 to 0. When using the P00/TI000, P01/TO00/TI010, P05/TI001/SSI11, and P06/TO01/TI011 pins for timer input, set PM00, PM01, PM05, and PM06 to 1. At this time, the output latches of P00, P01, P05, and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM0 to FFH. Figure 7-15. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH 6 5 4 R/W Symbol 7 3 2 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD 1 0 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal (INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 7-16. Block Diagram of Interval Timer Operation Clear Count clock 16-bit counter (TM0n) Match signal INTTM00n signal Operable bits TMC0n3, TMC0n2 CR00n register Figure 7-17. Basic Timing Example of Interval Timer Operation N N N N Interval (N + 1) Interval (N + 1) TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) N Compare match interrupt (INTTM00n) Interval (N + 1) Remark 188 Interval (N + 1) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Interval time = (M + 1) x Count clock cycle Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Example of Software Processing for Interval Timer Function N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 CR00n register N INTTM00n signal <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Remark 190 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 Square wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H. When TMC0n3 and TMC0n2 are set to 11 (count clear & start mode entered upon a match between TM0n and CR00n), the counting operation is started in synchronization with the count clock. When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H, an interrupt signal (INTTM00n) is generated, and output of the TO0n pin is inverted. This TO0n pin output that is inverted at fixed intervals enables TO0n to output a square wave. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 7-20. Block Diagram of Square Wave Output Operation Clear Count clock Output controller 16-bit counter (TM0n) Match signal TO0n pin INTTM00n signal Operable bits TMC0n3, TMC0n2 CR00n register Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Figure 7-21. Basic Timing Example of Square Wave Output Operation N N N N Interval (N + 1) Interval (N + 1) TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) N TO0n pin output Compare match interrupt (INTTM00n) Interval (N + 1) Remark Interval (N + 1) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 191 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-22. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 OVF0n 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 1 1 0 Enables TO0n pin output. Inverts TO0n pin output on match between TM0n and CR00n. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interval time is as follows. * Square wave frequency = 1 / [2 x (M + 1) x Count clock cycle] Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used for the square wave output function. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark 192 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Example of Software Processing for Square Wave Output Function N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 CR00n register N TO0n pin output INTTM00n signal TO0n output control bit (TOE0n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 External event counter operation When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM0n and CR00n (INTTM00n) is generated. To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an external event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and TMC0n2 = 10). The INTTM00n signal is generated with the following timing. * Timing of generation of INTTM00n signal (second time or later) = Number of times of detection of valid edge of external event x (Set value of CR00n + 1) However, the first match interrupt immediately after the timer/event counter has started operating is generated with the following timing. * Timing of generation of INTTM00n signal (first time only) = Number of times of detection of valid edge of external event input x (Set value of CR00n + 2) To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of fPRS. The valid edge is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 7-24. Block Diagram of External Event Counter Operation fPRS Clear TI00n pin Edge detection 16-bit counter (TM0n) Match signal Operable bits TMC0n3, TMC0n2 CR00n register Remark 194 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD Output controller INTTM00n signal TO0n pin CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-25. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 OVF0n 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0/1 0/1 0 0 PRM0n1 PRM0n0 1 1 Selects count clock (specifies valid edge of TI00n). 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) If M is set to CR00n, the interrupt signal (INTTM00n) is generated when the number of external events reaches (M + 1). Setting CR00n to 0000H is prohibited. (g) 16-bit capture/compare register 01n (CR01n) Usually, CR01n is not used in the external event counter mode. However, a compare match interrupt (INTTM01n) is generated when the set value of CR01n matches the value of TM0n. Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n). Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Example of Software Processing in External Event Counter Mode N N N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 11 Compare register (CR00n) N Compare match signal (INTTM00n) <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, CR00n register, port setting TMC0n3, TMC0n2 bits = 11 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 196 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear & start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected, TM0n overflows and continues counting. The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after the start of the operation. CR00n and CR01n are used as compare registers and capture registers. (a) When CR00n and CR01n are used as compare registers Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and CR01n. (b) When CR00n and CR01n are used as capture registers The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin). When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to 0000H. Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n is cleared. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. 3. n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 197 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: compare register) Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) TI00n pin Edge detection Clear Count clock Timer counter (TM0n) Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Output controller Match signal Compare register (CR01n) Remark 198 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD TO0n pin Interrupt signal (INTTM01n) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H M TM0n register N M N M N M N 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) M Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n pin output (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 0AH M TM0n register N M N M N M N 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) M Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n pin output (a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n (TMC0n). (a) The output level of the TO0n pin is inverted when TM0n matches a compare register. (b) The output level of the TO0n pin is inverted when TM0n matches a compare register or when the valid edge of the TI00n pin is detected. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: capture register) Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) TI00n pin Edge detector Clear Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Capture signal Remark 200 Output controller Capture register (CR01n) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD TO0n pin Interrupt signal (INTTM01n) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H M N P TM0n register Q S 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Capture & count clear input (TI00n pin input) Compare register (CR00n) 0001H Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n pin output This is an application example where the output level of the TO0n pin is inverted when the count value has been captured & cleared. The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated, and the output level of the TO0n pin is inverted. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H M N P TM0n register Q S 0003H 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Capture & count clear input (TI00n pin input) Compare register (CR00n) 0003H Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n pin output 4 4 4 4 This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to 0000H), and the output level of the TO0n pin is inverted when the valid edge of the TI00n pin is detected. When the count value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n) is generated and the output level of the TO0n pin is inverted. Remark 202 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Operation in clear & start mode by entered TI00n pin valid edge input (CR00n: capture register, CR01n: compare register) Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) TI00n pin Edge detection Clear Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM01n) Operable bits TMC0n3, TMC0n2 Compare register (CR01n) Capture signal Remark n = 0: Output controller Capture register (CR00n) TO0n pin Interrupt signal (INTTM00n) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H TM0n register M P N 0000H Operable bits (TMC0n3, TMC0n2) S 00 10 Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Compare register (CR01n) 0000H M N S P L 0001H Compare match interrupt (INTTM01n) TO0n pin output This is an application example where the output level of the TO0n pin is to be inverted when the count value has been captured & cleared. TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge detection of the TI00n pin. When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 204 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H TM0n register M 0003H 0000H Operable bits (TMC0n3, TMC0n2) S P N 00 10 Capture & count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n) Capture register (CR01n) 0000H M N S P L 0003H Capture interrupt (INTTM01n) TO0n pin output 4 4 4 4 This is an application example where the width set to CR01n (4 clocks in this example) is to be output from the TO0n pin when the count value has been captured & cleared. TM0n is cleared (to 0000H) at the rising edge detection of the TI00n pin and captured to CR00n at the falling edge detection of the TI00n pin. The output level of the TO0n pin is inverted when TM0n is cleared (to 0000H) because the rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a compare register (CR01n). When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is 1, the count value of TM0n is captured to CR00n in the phase reverse to that of the input signal of the TI00n pin, but the capture interrupt signal (INTTM00n) is not generated. However, the INTTM00n interrupt is generated when the valid edge of the TI01n pin is detected. Mask the INTTM00n signal when it is not used. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: capture register, CR01n: capture register) Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Clear Timer counter (TM0n) Count clock Capture signal Capture register (CR01n) Interrupt signal (INTTM01n) TI00n pin Edge detection Note Edge detection TI01n pin Selector Output controller Capture signal Capture register (CR00n) TO0n pinNote Interrupt signal (INTTM00n) Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Remark 206 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (1/3) (a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH L TM0n register N M O Q P R S T 0000H Operable bits (TMC0n3, TMC0n2) 00 10 Capture & count clear input (TI00n pin input) Capture register (CR00n) Capture interrupt (INTTM00n) Capture register (CR01n) 0000H L 0000H L M N O P Q R S T Capture interrupt (INTTM01n) TO0n pin output This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n pin output is inverted when the rising or falling edge of the TI00n pin is detected. When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n signal when it is not used. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (2/3) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH FFFFH N M 00 T Q S P 0000H Operable bits (TMC0n3, TMC0n2) R O L TM0n register 10 Capture trigger input (TI01n pin input) Capture register (CR00n) 0000H L M N O P Q R S T Capture interrupt (INTTM00n) Capture & count clear input (TI00n) L Capture register (CR01n) Capture interrupt (INTTM01n) 0000H L This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is captured to CR00n when the rising or falling edge of the TI01n pin is detected. Remark 208 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (3/3) (c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH O M TM0n register N L S Q W T R P 0000H Operable bits (TMC0n3, TMC0n2) 10 00 Capture & count clear input (TI00n pin input) Capture register (CR00n) 0000H Capture register (CR01n) L 0000H N M P O R Q T S W Capture interrupt (INTTM01n) Capture input (TI01n) Compare match interrupt (INTTM00n) L L This is an application example where the pulse width of the signal input to the TI00n pin is measured. By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the TI00n pin (i.e., rising edge) and to CR01n at the falling edge of the TI00n pin. The high- and low-level widths of the input pulse can be calculated by the following expressions. * High-level width = [CR01n value] - [CR00n value] x [Count clock cycle] * Low-level width = [CR00n value] x [Count clock cycle] If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the INTTM01n signal is generated. However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the pulse width of the TI00n pin, mask the INTTM00n signal when it is not used. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 0 OVF0n 0/1 0 0: Inverts TO0n output on match between CR00n and CR01n. 1: Inverts TO0n output on match between CR00n and CR01n and valid edge of TI00n pin. Clears and starts at valid edge input of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 0/1 0/1 0: Disables TO0n outputNote 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used. Remark 210 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pinNote input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. Note The timer output (TO0n) cannot be used when detection of the valid edge of the TI01n pin is used. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input M TM0n register M N M N M N N 0000H Operable bits (TMC0n3, TMC0n2) 10 00 00 Count clear input (TI00n pin input) Compare register (CR00n) M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n pin output <1> <2> <1> Count operation start flow <2> <2> <2> <3> <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, TMC0n.TMC0n1 bit, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 10. TMC0n3, TMC0n2 bits = 10 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP <2> TM0n register clear & start flow Edge input to TI00n pin Note When the valid edge is input to the TI00n pin, the value of the TM0n register is cleared. Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark 212 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Free-running timer operation When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (freerunning timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to 0000H) and continues counting. Clear OVF0n to 0 by executing the CLR instruction via software. The following three types of free-running timer operations are available. * Both CR00n and CR01n are used as compare registers. * One of CR00n or CR01n is used as a compare register and the other is used as a capture register. * Both CR00n and CR01n are used as capture registers. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. (1) Free-running timer mode operation (CR00n: compare register, CR01n: compare register) Figure 7-37. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Output controller Match signal TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 213 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) * TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H FFFFH N TM0n register 0000H Operable bits (TMC0n3, TMC0n2) 00 Compare register (CR00n) M N M N M N M 01 00 M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) TO0n pin output OVF0n bit 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where two compare registers are used in the free-running timer mode. The output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n or CR01n. When the count value matches the register value, the INTTM00n or INTTM01n signal is generated. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: (2) Free-running timer mode operation (CR00n: compare register, CR01n: capture register) Figure 7-39. Block Diagram of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) TI00n pin Remark n = 0: Edge detection Capture signal Capture register (CR01n) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 214 Preliminary User's Manual U17260EJ3V1UD Output controller TO0n pin Interrupt signal (INTTM01n) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-40. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) * TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H FFFFH M N TM0n register P S Q 0000H Operable bits (TMC0n3, TMC0n2) 00 01 Capture trigger input (TI00n) Compare register (CR00n) 0001H Compare match interrupt (INTTM00n) Compare register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) TO0n pin output Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where a compare register and a capture register are used at the same time in the free-running timer mode. In this example, the INTTM00n signal is generated and the output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n (compare register). In addition, the INTTM01n signal is generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is detected. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 215 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Free-running timer mode operation (CR00n: capture register, CR01n: capture register) Figure 7-41. Block Diagram of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock Capture register (CR01n) TI00n pin TI01n pin Edge detection Edge detection Selector Capture signal Capture signal Capture register (CR00n) Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the output level of the TO0n pin is not inverted. However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1) of 16-bit timer mode control register 0n (TMC0n) is set to 1. 2. n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 216 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 50H, CRC0n = 05H, TMC0n = 04H FFFFH M N TM0n register A 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C B Q D E 01 Capture trigger input (TI00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H A B C D E Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate capture registers in the free-running timer mode. The count value is captured to CR01n when the valid edge of the TI00n pin input is detected and to CR00n when the valid edge of the TI01n pin input is detected. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H FFFFH O L 00 T Q M 0000H Operable bits (TMC0n3, TMC0n2) R N TM0n register S P 01 Capture trigger input (TI01n) Capture register (CR00n) 0000H L M N O P Q R S T Capture interrupt (INTTM00n) Capture trigger input (TI00n) L Capture register (CR01n) Capture interrupt (INTTM01n) 0000H L This is an application example where both the edges of the TI01n pin are detected and the count value is captured to CR00n in the free-running timer mode. When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to be detected, the count value cannot be captured to CR01n. Remark 218 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0 1 0/1 OVF0n 0 0: Inverts TO0n pin output on match between CR00n and CR01n. 1: Inverts TO0n pin output on match between CR00n and CR01n and valid edge of TI00n pin. Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0/1 0/1 0/1 0: CR00n used as compare register 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 0: CR01n used as compare register 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0/1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 0/1 0/1 0: Disables TO0n output 1: Enables TO0n output Specifies initial value of TO0n output F/F 00: Does not invert TO0n output on match between TM0n and CR00n/CR01n. 01: Inverts TO0n output on match between TM0n and CR00n. 10: Inverts TO0n output on match between TM0n and CR01n. 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Count clock selection (setting TI00n valid edge is prohibited) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (setting prohibited when CRC0n1 = 1) 00: 01: 10: 11: Falling edge detection Rising edge detection Setting prohibited Both edges detection (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared. To use this register as a capture register, select either the TI00n or TI01n pin input as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) When this register is used as a compare register and when its value matches the count value of TM0n, an interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared. When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 220 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-44. Example of Software Processing in Free-Running Timer Mode FFFFH M M TM0n register 0000H Operable bits (TMC0n3, TMC0n2) N N 00 M N 01 Compare register (CR00n) N 00 M Compare match interrupt (INTTM00n) Compare register (CR01n) N Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output <1> <2> <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n/CR01n register, TMC0n.TMC0n1 bit, port setting TMC0n3, TMC0n2 bits = 0, 1 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 01. Starts count operation <2> Count operation stop flow TMC0n3, TMC0n2 bits = 0, 0 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 PPG output operation A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows. * Pulse cycle = (Set value of CR00n + 1) x Count clock cycle * Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1) Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during TM0n operation. Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 7-45. Block Diagram of PPG Output Operation Clear Count clock Timer counter (TM0n) Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Output controller Match signal Compare register (CR01n) Remark 222 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD TO0n pin Interrupt signal (INTTM01n) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-46. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 1 1 0 OVF0n 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n output Specifies initial value of TO0n output F/F 11: Inverts TO0n output on match between TM0n and CR00n/CR01n. 00: Disables one-shot pulse output (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is not cleared. (g) 16-bit capture/compare register 01n (CR01n) An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n. The count value of TM0n is not cleared. Caution Set values to CR00n and CR01n such that the condition 0000H < CR01n < CR00n FFFFH is satisfied. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-47. Example of Software Processing for PPG Output Operation M TM0n register M M N N N 0000H Operable bits (TMC0n3, TMC0n2) 00 00 11 Compare register (CR00n) N Compare match interrupt (INTTM00n) Compare register (CR01n) M Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output N+1 M+1 N+1 M+1 N+1 M+1 <2> <1> <2> Count operation stop flow <1> Count operation start flow TMC0n3, TMC0n2 bits = 00 START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. TMC0n3, TMC0n2 bits = 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remarks 1. PPG pulse cycle = (M + 1) x Count clock cycle PPG duty = (N + 1)/(M + 1) 2. n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 224 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register 0n (TMC0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI00n pin valid edge) and setting bit 5 (OSPE0n) of 16-bit timer output control register 0n (TOC0n) to 1. When bit 6 (OSPT0n) of TOC0n is set to 1 or when the valid edge is input to the TI00n pin during timer operation, clearing & starting of TM0n is triggered, and a pulse of the difference between the values of CR00n and CR01n is output only once from the TO0n pin. Cautions 1. Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. 2. To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do not change the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be unexpectedly output. Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 7-48. Block Diagram of One-Shot Pulse Output Operation TI00n edge detection OSPT0n bit Clear OSPE0n bit Timer counter (TM0n) Count clock Match signal Interrupt signal (INTTM00n) Operable bits TMC0n3, TMC0n2 Compare register (CR00n) Match signal Output controller TO0n pin Interrupt signal (INTTM01n) Compare register (CR01n) Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 0 0 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0/1 1 1 LVS0n LVR0n TOC0n1 TOE0n 0/1 0/1 1 1 Enables TO0n pin output Specifies initial value of TO0n pin output Inverts TO0n output on match between TM0n and CR00n/CR01n. Enables one-shot pulse output Software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0 0 0 0 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 226 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR00n, an interrupt signal (INTTM00n) is generated and the output level of the TO0n pin is inverted. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a compare register when a one-shot pulse is output. When the value of TM0n matches that of CR01n, an interrupt signal (INTTM01n) is generated and the output level of the TO0n pin is inverted. Caution Do not set identical values or 0000H for CR0n0 and CR0n1. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH N N M TM0n register N M M 0000H Operable bits (TMC0n3, TMC0n2) 00 01 or 10 00 One-shot pulse enable bit (OSPEn) One-shot pulse trigger bit (OSPTn) One-shot pulse trigger input (TI00n pin) Overflow plug (OVF0n) Compare register (CR00n) N Compare match interrupt (INTTM00n) Compare register (CR01n) M Compare match interrupt (INTTM01n) TO0n pin output M+1 TO0n output control bits (TOE0n, TOC0n4, TOC0n1) <1> <2> N-M M+1 N-M TO0n output level is not inverted because no oneshot trigger is input. <2> * Time from when the one-shot pulse trigger is input until the one-shot pulse is output = (M + 1) x Count clock cycle * One-shot pulse output active level width = (N - M) x Count clock cycle Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 228 Preliminary User's Manual U17260EJ3V1UD <3> CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, TOC0n registerNote, CR00n, CR01n registers, port setting TMC0n3, TMC0n2 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. Starts count operation <2> One-shot trigger input flow TOC0n.OSPT0n bit = 1 or edge input to TI00n pin Write the same value to the bits other than the OSTP0n bit. <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control register 0n (TOC0n). Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.8 Pulse width measurement operation TM0n can be used to measure the pulse width of the signal input to the TI00n and TI01n pins. Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI00n pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n). If it is set (to 1), clear it to 0 by software. Figure 7-51. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode) Operable bits TMC0n3, TMC0n2 Timer counter (TM0n) Count clock Capture register (CR01n) TI00n pin Edge detection TI01n pin Edge detection Remark Selector Capture signal Capture signal Capture register (CR00n) Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Figure 7-52. Block Diagram of Pulse Width Measurement (Clear & Start Mode Entered by TI00n Pin Valid Edge Input) Operable bits TMC0n3, TMC0n2 Clear Timer counter (TM0n) Count clock Capture register (CR01n) TI00n pin Edge detection TI01n pin Edge detection Remark n = 0: Selector Capture signal Capture signal Capture register (CR00n) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 230 Preliminary User's Manual U17260EJ3V1UD Interrupt signal (INTTM01n) Interrupt signal (INTTM00n) CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 A pulse width can be measured in the following three ways. * Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode) * Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 3. n = 0: (1) Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. When the valid edge of the TI01n pin is detected, the count value of TM0n is captured to CR00n. Specify detection of both the edges of the TI00n and TI01n pins. By this measurement method, the previous count value is subtracted from the count value captured by the edge of each input signal. Therefore, save the previously captured value to a separate register in advance. If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the current captured value and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Preliminary User's Manual U17260EJ3V1UD 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-53. Timing Example of Pulse Width Measurement (1) * TMC0n = 04H, PRM0n = F0H, CRC0n = 05H FFFFH M TM0n register N A B 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C Q D E 01 Capture trigger input (TI00n) Capture register (CR01n) 0000H M N S P Q Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H A B C D E Capture interrupt (INTTM00n) Overflow flag (OVF0n) 0 write clear Remark n = 0: 0 write clear PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 232 Preliminary User's Manual U17260EJ3V1UD 0 write clear 0 write clear CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measuring the pulse width by using one input signal of the TI00n pin (free-running mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge detected on the TI00n pin. When the valid edge of the TI00n pin is detected, the count value of TM0n is captured to CR01n. By this measurement method, values are stored in separate capture registers when a width from one edge to another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one capture register from that of another, a high-level width, low-level width, and cycle are calculated. If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-54. Timing Example of Pulse Width Measurement (2) * TMC0n = 04H, PRM0n = 10H, CRC0n = 07H FFFFH M TM0n register N A B 0000H Operable bits (TMC0n3, TMC0n2) 00 P S C Q D E 01 Capture trigger input (TI00n) Capture register (CR00n) 0000H Capture register (CR01n) 0000H A B M C N E D S P Q Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) L Compare match interrupt (INTTM00n) L Remark n = 0: 0 write clear 0 write clear 0 write clear PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore, a cycle is stored in CR01n if TM0n does not overflow. If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle. Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0. Figure 7-55. Timing Example of Pulse Width Measurement (3) * TMC0n = 08H, PRM0n = 10H, CRC0n = 07H FFFFH TM0n register N C D <1> <1> S A 0000H Operable bits 00 (TMC0n3, TMC0n2) Q P B M 10 00 <1> <1> Capture & count clear input (TI00n) <2> Capture register (CR00n) 0000H Capture register (CR01n) 0000H <3> <2> <3> A M <2> <3> B N <2> <3> C S D P Q Capture interrupt (INTTM01n) Overflow flag (OVF0n) 0 write clear Capture trigger input (TI01n) L Capture interrupt (INTTM00n) L (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR01n) x <1> Pulse cycle = <2> High-level pulse width = (10000H x Number of times OVF0n bit is set to 1 + Captured value of CR00n) x <3> Low-level pulse width = (Pulse cycle - High-level pulse width) Count clock cycle Count clock cycle Remark 234 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 0 0 0 0 0/1 0/1 0 OVF0n 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 0 0 0 0 0 1 0/1 1 1: CR00n used as capture register 0: TI01n pin is used as capture trigger of CR00n. 1: Reverse phase of TI00n pin is used as capture trigger of CR00n. 1: CR01n used as capture register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 0 0 0 0 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0 (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 3 2 0/1 0/1 0/1 0/1 0 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (setting valid edge of TI00n is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection (setting when CRC0n1 = 1 is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a capture register. Either the TI00n or TI01n pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM0n is stored in CR00n. (g) 16-bit capture/compare register 01n (CR01n) This register is used as a capture register. The signal input to the TI00n pin is used as a capture trigger. When the capture trigger is detected, the count value of TM0n is stored in CR01n. Remark 236 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH D10 TM0n register D11 D00 D13 D12 D01 D02 D03 D04 0000H Operable bits (TMC0n3, TMC0n2) 00 01 00 Capture trigger input (TI00n) Capture register (CR01n) D10 0000H D11 D12 D13 Capture interrupt (INTTM01n) Capture trigger input (TI01n) Capture register (CR00n) 0000H D00 D01 D02 D03 D04 Capture interrupt (INTTM00n) <1> <2> <2> <2> <2> <2> <2> <2> <2> <2><3> (b) Example of clear & start mode entered by TI00n pin valid edge FFFFH D3 D2 D5 D0 TM0n register D8 D6 D7 D4 D1 0000H Operable bits (TMC0n3, TMC0n2) 00 10 00 Capture & count clear input (TI00n) Capture register 0000H (CR00n) Capture interrupt (INTTM00n) D3 D1 D5 D7 L Capture register (CR01n) 0000H D2 D0 D4 D6 D8 Capture interrupt (INTTM01n) <1> Remark <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM0n register, CRC0n register, port setting TMC0n3, TMC0n2 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits. Starts count operation <2> Capture trigger input flow Edge detection of TI00n, TI01n pins Stores count value to CR00n, CR01n registers Generates capture interruptNote Calculated pulse width from capture value <3> Count operation stop flow TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00. STOP Note The capture interrupt signal (INTTM00n) is not generated when the reverse-phase edge of the TI00n pin input is selected to the valid edge of CR00n. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 238 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/KE2 when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00). However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if CR01n is used for PPG output and the duty factor is changed (change the value of CR01n immediately after its value matches the value of TM0n. If the value of CR01n is changed immediately before its value matches TM0n, an unexpected operation may be performed). Procedure for changing value of CR01n <1> Disable interrupt INTTM01n (TMMK01n = 1). <2> Disable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 0). <3> Change the value of CR01n. <4> Wait for one cycle of the count clock of TM0n. <5> Enable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 1). <6> Clear the interrupt flag of INTTM01n (TMIF01n = 0) to 0. <7> Enable interrupt INTTM01n (TMMK01n = 0). Remark For TMIF01n and TMMK01n, see CHAPTER 19 INTERRUPT FUNCTIONS. 7.5.2 Setting LVS0n and LVR0n (1) Usage of LVS0n and LVR0n LVS0n and LVR0n are used to set the default value of the TO0n pin output and to invert the timer output without enabling the timer operation (TMC0n3 and TMC0n2 = 00). Clear LVS0n and LVR0n to 00 (default value: lowlevel output) when software control is unnecessary. Remark n = 0: LVS0n LVR0n Timer Output Status 0 0 Not changed (low-level output) 0 1 Cleared (low-level output) 1 0 Set (high-level output) 1 1 Setting prohibited PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-58. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n bit Setting TOC0n.LVS0n, LVR0n bits Setting TMC0n.TMC0n3, TMC0n2 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Figure 7-59. Timing Example of LVR0n and LVS0n TOC0n.LVS0n bit TOC0n.LVR0n bit Operable bits (TMC0n3, TMC0n2) 00 01, 10, or 11 TO0n pin output INTTM00n signal <1> <2> <1> <3> <4> <4> <4> <1> The TO0n pin output goes high when LVS0n and LVR0n = 10. <2> The TO0n pin output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the high level even if LVS0n and LVR0n are cleared to 00). <3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and LVR0n were set to 10 before the operation was started, the TO0n pin output starts from the high level. After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00 (disabling the timer operation). <4> The output level of the TO0n pin is inverted each time an interrupt signal (INTTM00n) is generated. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 240 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-5 shows the restrictions for each channel. Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation Restriction - As interval timer As square wave output As external event counter TOC0n = 00H As clear & start mode entered by Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is TI00n pin valid edge input used. TOC0n = 00H - As free-running timer As PPG output Setting identical values or 0000H to CR00n and CP01n is prohibited. - As one-shot pulse output As pulse width measurement TOC0n = 00H (2) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. Figure 7-60. Start Timing of TM0n Count Count pulse TM0n count value 0000H 0001H 0002H 0003H 0004H Timer start (3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n) Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external event counter). Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n pin is detected). When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated. Figure 7-61. Timing of Holding Data by Capture Register Count pulse TM0n count value N N+1 N+2 M M+1 M+2 Edge input INTTM01n Capture read signal Value captured to CR01n X N+1 Capture operation Capture operation is performed but read value is not guaranteed. (b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops. (5) Setting valid edge Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1. (6) Re-triggering one-shot pulse Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 242 Preliminary User's Manual U17260EJ3V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H Figure 7-62. Operation Timing of OVF0n Flag Count pulse CR00n FFFFH TM0n FFFEH FFFFH 0000H 0001H OVF0n INTTM00n (b) Clearing OVF0n flag Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. (8) One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. Remark PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly. (b) Pulse width to accurately capture value by signals input to TI01n and TI00n pins To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 7-9). (c) Generation of interrupt signal The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9). (d) Note when CRC0n1 (bit 1 of capture/compare control register 0n (CRC0n)) is set to 1 When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal when the external interrupt is not used. (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. (b) Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge of TI00n is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM0n is used for sampling. When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9). (11) Timer operation The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. Remarks 1. fPRS: Peripheral hardware clock frequency PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 2. n = 0: 244 Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Timer register Configuration 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n) Timer input TI5n Timer output TO5n Control registers Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Preliminary User's Manual U17260EJ3V1UD 245 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Selector Match Selector INTTM50 Note 1 S Q INV 8-bit timer OVF counter 50 (TM50) To TMH0 To UART0 To UART6 Selector TI50/TO50/P17 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/28 fPRS/213 Mask circuit 8-bit timer compare register 50 (CR50) R TO50/TI50/ P17 Output latch (P17) Note 2 S 3 Invert level R Clear PM17 TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500 8-bit timer mode control register 50 (TMC50) Timer clock selection register 50 (TCL50) Internal bus Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Selector Match Selector INTTM51 Note 1 S Q INV 8-bit timer OVF counter 51 (TM51) R Selector TI51/TO51/ P33/INTP4 fPRS fPRS/2 fPRS/24 fPRS/26 fPRS/28 fPRS/212 Mask circuit 8-bit timer compare register 51 (CR51) Note 2 S 3 Clear TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) R Invert level TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. Timer output F/F 2. PWM output F/F 246 Preliminary User's Manual U17260EJ3V1UD TO51/TI51/ P33/INTP4 Output latch (P33) PM33 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) After reset: 00H R Symbol TM5n (n = 0, 1) In the following situations, the count value is cleared to 00H. <1> Reset signal generation <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In the PWM mode, the TO5n pin becomes inactive when the values of TM5n and CR5n match, but no interrupt is generated. The value of CR5n can be set within 00H to FFH. Reset signal generation sets CR5n to 00H. Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) After reset: 00H R/W Symbol CR5n (n = 0, 1) Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 247 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets TCL5n to 00H. Remark n = 0, 1 Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 Count clock selection fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz 0 0 0 TI50 pin falling edge 0 0 1 TI50 pin rising edge 0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz 1 0 0 fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/2 8 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz fPRS/2 13 0.24 kHz 0.61 kHz 1.22 kHz 2.44 kHz 1 1 1 0 1 1 1 0 1 Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to 0. Remark 248 fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL51 0 0 0 0 0 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz 0 0 0 TI51 pin falling edge 0 0 1 TI51 pin rising edge 0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz 1 0 0 fPRS/2 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS/2 8 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz fPRS/2 12 0.49 kHz 1.22 kHz 2.44 kHz 4.88 kHz 1 1 1 0 1 1 1 0 1 Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to clear bits 3 to 7 to 0. Remark fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD 249 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark n = 0, 1 Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH After reset: 00H R/W Note Symbol <7> 6 5 4 <3> <2> 1 <0> TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear & start occurs on a match between TM50 and CR50 1 PWM (free-running) mode LVS50 LVR50 0 0 No change 0 1 Timer output F/F clear (0) (default output value of TO50 pin: low level) 1 0 Timer output F/F set (1) (default output value of TO50 pin: high level) 1 1 Setting prohibited TMC501 Timer output F/F status setting In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE50 Timer output control 0 Output disabled (TM50 output is low level) 1 Output enabled Note Bits 2 and 3 are write-only. (Cautions and Remarks are listed on the next page.) 250 Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H R/W Note Symbol <7> 6 5 4 <3> <2> 1 <0> TMC51 TCE51 TMC516 0 0 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start TMC516 TM51 operating mode selection 0 Mode in which clear & start occurs on a match between TM51 and CR51 1 PWM (free-running) mode LVS51 LVR51 0 0 No change 0 1 Timer output F/F clear (0) (default output value of TO51 pin: low) 1 0 Timer output F/F set (1) (default output value of TO51 pin: high) 1 1 Setting prohibited TMC511 Timer output F/F status setting In other modes (TMC516 = 0) In PWM mode (TMC516 = 1) Timer F/F control Active level selection 0 Inversion operation disabled Active-high 1 Inversion operation enabled Active-low TOE51 Timer output control 0 Output disabled (TM51 output is low level) 1 Output enabled Note Bits 2 and 3 are write-only. Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: Operation mode setting <2> Set TOE5n to enable output: Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting <4> Set TCE5n 3. Stop operation before rewriting TMC5n6. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 251 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 8-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 8-10. Format of Port Mode Register 3 (PM3) Address: FF23H R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 PM33 PM32 PM31 PM30 PM3n 252 After reset: FFH P3n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Set TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. 2. n = 0, 1 Figure 8-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H Count start CR5n N N 00H 01H Clear N 00H 01H N Clear N N N TCE5n INTTM5n Interrupt acknowledged Interval time Remark Interrupt acknowledged Interval time Interval time = (N + 1) x t N = 01H to FFH n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 253 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H 00H 00H CR5n 00H 00H TCE5n INTTM5n Interval time (c) When CR5n = FFH t Count clock TM5n CR5n 01H FFH FEH FFH 00H FEH FFH FFH 00H FFH TCE5n INTTM5n Interrupt acknowledged Interval time Remark 254 n = 0, 1 Preliminary User's Manual U17260EJ3V1UD Interrupt acknowledged CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n pin input edge. TI5n pin falling edge TCL5n = 00H TI5n pin rising edge TCL5n = 01H * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 0000xx00B x = Don't care) <2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 8-bit timer/event counter 51: PM33 Remark For how to enable the INTTM5n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value 00H 01H 02H 03H 04H 05H N-1 CR5n N 00H 01H 02H 03H N INTTM5n Remark N = 00H to FFH n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 255 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. LVS5n LVR5n Timer Output F/F Status Setting 1 0 Timer output F/F clear (0) (default output value of TO50 pin: low level) 0 1 Timer output F/F set (1) (default output value of TO5n pin: high level) Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. * Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. 2. n = 0, 1 256 Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 8.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 257 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value * TMC5n: Stop the count operation, select PWM mode. The timer output F/F is not changed. TMC5n1 Active Level Selection 0 Active-high 1 Active-low Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation <1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 8-14 and 8-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark 258 n = 0, 1 Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n 00H 01H CR5n N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n <2> Active level <1> Inactive level <3> Inactive level <5> Inactive level <2> Active level (b) CR5n = 00H t Count clock TM5n 00H 01H CR5n 00H FFH 00H 01H 02H FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n L (Inactive level) (c) CR5n = FFH t TM5n 00H 01H CR5n FFH FFH 00H 01H 02H FFH 00H 01H 02H M 00H TCE5n INTTM5n TO5n <1> Inactive level <2> Active level <2> Active level <5> Inactive level <3> Inactive level Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) correspond to <1> to <3> and <5> in PWM output operation in 8.4.4 (1) PWM output basic operation. 2. n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 259 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n N N+1 N+2 CR5n N TCE5n INTTM5n FFH 00H 01H 02H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 M H TO5n <2> <1> CR5n change (N M) (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock TM5n N N+1 N+2 CR5n TCE5n INTTM5n N FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H N M M+1 M+2 M H TO5n <1> CR5n change (N M) <2> Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). 260 Preliminary User's Manual U17260EJ3V1UD CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 8-16. 8-Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H 01H 02H 03H 04H Timer start Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 261 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * Square-wave output * PWM output * Carrier generator (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 9-1. Configuration of 8-Bit Timers H0 and H1 Item Configuration Timer register 8-bit timer counter Hn Registers 8-bit timer H compare register 0n (CMP0n) Timer output TOHn, output controller Control registers 8-bit timer H mode register n (TMHMDn) 8-bit timer H compare register 1n (CMP1n) 8-bit timer H carrier control register 1 (TMCYC1) Port mode register 1 (PM1) Port register 1 (P1) Note 8-bit timer H1 only Remark n = 0, 1 Figures 9-1 and 9-2 show the block diagrams. 262 Preliminary User's Manual U17260EJ3V1UD Note Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 3 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) 2 Decoder TOH0/P15 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/210 8-bit timer/ event counter 50 output Selector Match Interrupt generator F/F R Output controller Level inversion Output latch (P15) 8-bit timer counter H0 Clear PWM mode signal Timer H enable signal 1 0 INTTMH0 PM15 CHAPTER 9 8-BIT TIMERS H0 AND H1 Preliminary User's Manual U17260EJ3V1UD Selector 263 264 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 0 1 (CMP01) 8-bit timer H compare register 1 1 (CMP11) 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) INTTM51 Reload/ interrupt control 2 TOH1/ INTP5/ P16 Decoder Selector Match fPRS fPRS/22 fPRS/24 fPRS/26 fPRS/212 fRL fRL/27 fRL/29 Interrupt generator F/F R Output controller Level inversion Output latch (P16) 8-bit timer counter H1 Carrier generator mode signal Clear PWM mode signal Timer H enable signal 1 0 INTTMH1 PM16 CHAPTER 9 8-BIT TIMERS H0 AND H1 Preliminary User's Manual U17260EJ3V1UD Selector CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn. Rewrite the value of CMP0n while the timer is stopped (TMHEn = 0). A reset signal generation sets this register to 00H. Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 5 6 After reset: 00H 4 3 R/W 2 1 0 (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request signal is generated. In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn). At the same time, the count value is cleared. CMP1n can be rewritten during timer count operation. If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the value of CMP1n is not changed. A reset signal generation sets this register to 00H. Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF19H (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 After reset: 00H 4 3 R/W 2 1 0 Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 265 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1)Note * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark n = 0, 1 266 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H TMHMD0 After reset: 00H R/W <7> 6 5 4 TMHE0 CKS02 CKS01 CKS00 TMHE0 3 2 <1> TMMD01 TMMD00 TOLEV0 <0> TOEN0 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) CKS02 CKS01 CKS00 Count clock selection 0 0 0 fPRS 0 0 1 fPRS/2 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 2 MHz 5 MHz 10 MHz 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 0 1 0 0 1 1 fPRS/2 1 0 0 fPRS/210 1.95 kHz 1 0 1 Other than above fPRS/2 9.77 kHz 19.54 kHz TM50 output Setting prohibited TMMD01 TMMD00 Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above 4.88 kHz Note Setting prohibited TOLEV0 Timer output level control (in default mode) 0 Low level 1 High level TOEN0 Timer output control 0 Disables output 1 Enables output Note Note the following points when selecting the TM50 output as the count clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of the 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of the 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Preliminary User's Manual U17260EJ3V1UD 267 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 268 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 3 2 <1> TMMD11 TMMD10 TOLEV1 <0> TOEN1 Timer operation enable 0 Stops timer count operation (counter is cleared to 0) 1 Enables timer count operation (count operation started by inputting clock) CKS12 0 0 CKS11 0 0 CKS10 0 1 Count clock selection fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 10 MHz 20 MHz 2 MHz 5 MHz 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz fPRS fPRS/2 0 1 0 0 1 1 fPRS/2 1 0 0 fPRS/212 0.49 kHz 1 0 1 fPRS/2 1.22 kHz 7 1.88 kHz (TYP.) 9 fRL/2 1 1 0 fRL/2 0.47 kHz (TYP.) 1 1 1 fRL 240 kHz (TYP.) TMMD11 TMMD10 4.88 kHz Timer operation mode 0 0 Interval timer mode 0 1 Carrier generator mode 1 0 PWM output mode 1 1 Setting prohibited TOLEV1 2.44 kHz Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Timer output control 0 Disables output 1 Enables output Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. Remarks 1. fPRS: Peripheral hardware clock frequency 2. fRL: Internal low-speed oscillation clock frequency Preliminary User's Manual U17260EJ3V1UD 269 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FF6DH After reset: 00H R/WNote <0> TMCYC1 0 0 0 0 0 RMC1 NRZB1 0 0 Low-level output 0 1 High-level output 1 0 Low-level output 1 1 Carrier pulse output RMC1 NRZB1 NRZ1 Remote control output NRZ1 Carrier pulse output status flag 0 Carrier output disabled status (low-level status) 1 Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) Note Bit 0 is read-only. (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 9-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 270 After reset: FFH P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. Setting <1> Set each register. Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) TMHMDn Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Default setting of timer output level Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting The interval time is as follows if N is set as a comparison value. * Interval time = (N +1)/fCNT <2> Count operation starts when TMHEn = 1. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and the 8-bit timer counter Hn is cleared to 00H. <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMHn signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. 3. n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 271 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H CMP0n FEH) Count clock Count start 00H 8-bit timer counter Hn 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP0n TMHEn INTTMHn Interval time TOHn <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at the rising edge of the count clock. <3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level is maintained. Remark n = 0, 1 01H N FEH 272 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 273 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. The TOHn output level is inverted and the 8-bit timer counter Hn is cleared to 0 when the 8-bit timer counter Hn and the CMP0n register match after the timer count is started. The TOHn output level is inverted when the 8-bit timer counter Hn and the CMP1n register match. Setting <1> Set each register. Figure 9-11. Register Setting in PWM Output Mode (i) TMHMDn Setting timer H mode register n (TMHMDn) TMHEn CKSn2 CKSn1 CKSn0 0 0/1 0/1 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 Timer output enabled Default setting of timer output level PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output is inverted. At the same time, the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. <4> When the 8-bit timer counter Hn and the CMP1n register match, TOHn output is inverted and the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. 274 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. * PWM pulse output cycle = (N + 1)/fCNT * Duty = (M + 1)/(N + 1) Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating. However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed until the value is transferred to the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). 3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. 3. n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 275 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H CMP0n A5H CMP1n 01H A5H 00H 01H 02H A5H 00H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <2> <3> <4> TOHn (TOLEVn = 1) <1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains the default. <2> When the values of the 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of the 8-bit timer counter Hn and the CMP1n register match, the TOHn output level is inverted. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal and TOHn output to the default. Remark n = 0, 1 276 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP0n FFH CMP1n 00H FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP0n FFH CMP1n FEH FEH FFH 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 277 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark 278 n = 0, 1 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H CMP11 02H (03H) <2> 03H <2>' TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains default. <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output level is inverted. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output default. Remark n = 0, 1 Preliminary User's Manual U17260EJ3V1UD 279 CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, the 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and the 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during the 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of the 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. 280 RMC1 Bit NRZB1 Bit Output 0 0 Low-level output 0 1 High-level output 1 0 Low-level output 1 1 Carrier pulse output Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 9-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 1 0 <2> NRZB1 1 0 1 <3> RMC1 <1> The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the INTTM5H1 signal. <2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. <3> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. Preliminary User's Manual U17260EJ3V1UD 281 CHAPTER 9 8-BIT TIMERS H0 AND H1 Setting <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode (i) TMHMD1 Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 TOEN1 1 1 0 0/1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... carrier output enable bit (v) TCL51 and TMC51 register setting * See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, the 8-bit timer H1 starts counting. <3> When TCE51 of the 8-bit timer mode control register 51 (TMC51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of the 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of the 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to count the next time to the CR51 register. <9> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. 282 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. * Carrier clock output cycle = (N + M + 2)/fCNT * Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. 3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 4. The set value of the CMP11 register can be changed while the timer counter is operating. However, it takes the duration of three operating clocks (signal selected by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11 register has been changed until the value is transferred to the register. 5. Be sure to set the RMC1 bit before the count operation is started. Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1). 2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS. Preliminary User's Manual U17260EJ3V1UD 283 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H N 00H N 00H N 00H CMP01 N CMP11 N N 00H N 00H N TMHE11 INTTMH1 <3> <4> <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value 00H 01H K 00H 01H L K CR51 00H 01H M 00H 01H L N 00H 01H N M TCE51 <5> INTTM5n1 INTTM5H1 NRZB1 0 1 0 1 0 <6> NRZ1 0 1 0 1 0 Carrier clock TOH11 <7> <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. 284 Preliminary User's Manual U17260EJ3V1UD CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H N 00H 01H M 00H N 00H 01H CMP01 N CMP11 M M 00H N 00H TMHE1 INTTMH1 <3> <4> <1><2> Carrier clock 8-bit timer 51 count clock TM51 count value 00H 01H K 00H 01H L 00H 01H K CR51 M 00H 01H N 00H 01H M L N TCE51 <5> INTTM51 INTTM5H1 NRZB1 NRZ1 0 1 0 0 1 1 0 0 1 0 Carrier clock <6> TOH1 <7> <1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock remains default. <3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1 is cleared to 00H. <4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). Preliminary User's Manual U17260EJ3V1UD 285 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>' M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default. <2> When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. <3> The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the CMP11 register is changed (<3>'). However, it takes three count clocks or more since the value of the CMP11 register has been changed until the value is transferred to the register. Even if a match signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. <5> The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). 286 Preliminary User's Manual U17260EJ3V1UD CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. 7 fPRS/2 11-bit prescaler fW fWX fWX/24 5-bit counter fWX/25 INTWT Clear fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Selector fSUB Selector Clear Selector Selector Figure 10-1. Block Diagram of Watch Timer WTM7 WTM6 WTM5 INTWTI WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) fWX: fW or fW/29 Preliminary User's Manual U17260EJ3V1UD 287 CHAPTER 10 WATCH TIMER (1) Watch timer When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at fSUB = 32.768 kHz fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 488 s 4 2 /fW 1.02 ms 410 s 205 s 102 s 5 977 s 2.05 ms 819 s 410 s 205 s 13 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 14 0.5 s 1.05 s 0.419 s 0.210 s 0.105 s 2 /fW 2 /fW 2 /fW Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) (2) Interval timer Interrupt request signals (INTWTI) are generated at preset time intervals. Table 10-2. Interval Timer Interval Time Interval Time When Operated at When Operated at When Operated at When Operated at When Operated at fSUB = 32.768 kHz fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 4 488 s 1.02 ms 410 s 205 s 102 s 5 977 s 2.05 ms 820 s 410 s 205 s 6 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 7 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 8 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 9 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 10 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 11 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) 10.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 10-3. Watch Timer Configuration Item 288 Configuration Counter 5 bits x 1 Prescaler 11 bits x 1 Control register Watch timer operation mode register (WTM) Preliminary User's Manual U17260EJ3V1UD CHAPTER 10 WATCH TIMER 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets WTM to 00H. Figure 10-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH Symbol WTM After reset: 00H R/W 7 6 5 4 3 2 <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (fW) fSUB = 32.768 kHz 0 fPRS/2 1 fSUB WTM6 - 7 fPRS = 2 MHz 15.625 kHz fPRS = 5 MHz 39.062 kHz fPRS = 20 MHz 78.125 kHz 156.25 kHz - 32.768 kHz WTM5 fPRS = 10 MHz WTM4 Prescaler interval time selection 4 0 0 0 2 /fW 0 0 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW 1 1 0 2 /fW 1 1 1 2 /fW WTM3 WTM2 5 6 7 8 9 10 11 Selection of watch timer interrupt time 14 0 0 2 /fW 0 1 2 /fW 1 0 2 /fW 1 1 2 /fW 13 5 4 WTM1 5-bit counter operation control 0 Clear after operation stop 1 Start WTM0 Watch timer operation enable 0 Operation stop (clear both prescaler and 5-bit counter) 1 Operation enable Preliminary User's Manual U17260EJ3V1UD 289 CHAPTER 10 WATCH TIMER Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fPRS/27 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 290 Preliminary User's Manual U17260EJ3V1UD CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 29 x 1/fW seconds occurs in the first overflow (INTWT) after zero-second start. The interrupt request is generated at the following time intervals. Table 10-4. Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at Selection fPRS = 20 MHz (WTM7 = 0) 0.210 s 0.105 s 13 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms 5 977 s 2.05 ms 819 s 410 s 205 s 4 488 s 1.02 ms 410 s 205 s 102 s 1 2 /fW Remarks 1. fW: (WTM7 = 0) 0.419 s 0 1 fPRS = 10 MHz (WTM7 = 0) 1.05 s 2 /fW 1 fPRS = 5 MHz (WTM7 = 0) 0.5 s 0 0 fPRS = 2 MHz (WTM7 = 1) 14 0 1 fSUB = 32.768 kHz 2 /fW 2 /fW 7 Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation stops. Table 10-5. Interval Timer Interval Time WTM6 WTM5 WTM4 Interval Time (WTM7 = 0) 5 977 s 2.05 ms 820 s 410 s 205 s 6 1.95 ms 4.10 ms 1.64 ms 820 s 410 s 7 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820 s 8 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms 9 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms 10 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms 11 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 2 /fW 2 /fW 1 1 0 2 /fW 1 1 1 2 /fW Remarks 1. fW: (WTM7 = 0) 102 s 0 1 (WTM7 = 0) 205 s 0 0 at fPRS = 5 MHz at fPRS = 10 MHz at fPRS = 20 MHz 410 s 2 /fW 1 (WTM7 = 0) 1.02 ms 0 0 at fPRS = 2 MHz 488 s 0 0 at fSUB = 32.768 kHz (WTM7 = 1) 4 0 1 When Operated When Operated When Operated When Operated When Operated 7 Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency Preliminary User's Manual U17260EJ3V1UD 291 CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Overflow Start Overflow Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Remark T fW: Watch timer clock frequency Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 10.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s INTWT 292 Preliminary User's Manual U17260EJ3V1UD 0.5 s CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If data is written to WDTE during a window close period * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while the CPU hangs up) * If the CPU accesses an area that is not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION. Preliminary User's Manual U17260EJ3V1UD 293 CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Option Byte (0080H) Window open period Bits 6 and 5 (WINDOW1, WINDOW0) Controlling counter operation of watchdog timer Bit 4 (WDTON) Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0) Remark For the option byte, see CHAPTER 25 OPTION BYTE. Figure 11-1. Block Diagram of Watchdog Timer CPU access error detector CPU access signal WDCS2 to WDCS0 of option byte (0080H) fRL/2 Clock input controller 17-bit counter 210/fRL to 217/fRL Selector Count clear signal WINDOW1 and WINDOW0 of option byte (0080H) WDTON of option byte (0080H) Overflow signal Window size determination signal Clear, reset control Watchdog timer enable register (WDTE) Internal bus 294 Preliminary User's Manual U17260EJ3V1UD Reset output controller Internal reset signal CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 11-2. Format of Watchdog Timer Enable Register (WDTE) Address: FF99H Symbol 7 After reset: 9AH/1AHNote 6 R/W 5 4 3 2 1 0 WDTE Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To operate watchdog timer, set WDTON to 1. WDTON Setting Value WDTE Reset Value 0 (watchdog timer count operation disabled) 1AH 1 (watchdog timer count operation enabled) 9AH Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). Preliminary User's Manual U17260EJ3V1UD 295 CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 25). WDTON Operation Control of Watchdog Timer Counter/Illegal Access Detection 0 Counter operation disabled (counting stopped after reset), illegal access detection operation disabled 1 Counter operation enabled (counting started after reset), illegal access detection operation enabled * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see 11.4.2 and CHAPTER 25). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for details, see 11.4.3 and CHAPTER 25). 2. After a reset release, the watchdog timer starts counting. 3. By writing "ACH" to WDTE after the watchdog timer starts counting and before the overflow time set by the 4. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE 5. If the overflow time expires without "ACH" written to WDTE, an internal reset signal is generated. option byte, the watchdog timer is cleared and starts counting again. is written during a window close period, an internal reset signal is generated. A internal reset signal is generated in the following cases. * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check during a CPU program loop) * If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing a read/write instruction (detection of an abnormal access during a CPU program loop) Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. If the watchdog timer is cleared by writing "ACH" to WDTE, the actual overflow time may be different from the overflow time set by the option byte by up to 2/fRL seconds. 3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH). 296 Preliminary User's Manual U17260EJ3V1UD CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. In HALT mode LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) Watchdog timer operation stops. Watchdog timer operation continues. In STOP mode If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is not cleared to 0 but starts counting from the value at which it was stopped. If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops operating. At this time, the counter is not cleared to 0. 5. The watchdog timer does not stop during self-programming of the flash memory and EEPROMTM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 11.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing "ACH" to WDTE during the window open period before the overflow time. The following overflow time is set. Table 11-3. Setting of Overflow Time of Watchdog Timer WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer 10 0 0 0 2 /fRL (3.88 ms) 0 0 1 2 /fRL (7.76 ms) 0 1 0 2 /fRL (15.52 ms) 0 1 1 2 /fRL (31.03 ms) 1 0 0 2 /fRL (62.06 ms) 1 0 1 2 /fRL (124.12 ms) 1 1 0 2 /fRL (248.24 ms) 1 1 1 2 /fRL (496.48 ms) 11 12 13 14 15 16 17 Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. The watchdog timer does not stop during self-programming of the flash memory and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. Remarks 1. fRL: Internal low-speed oscillation clock frequency 2. ( ): fRL = 264 kHz (MAX.) Preliminary User's Manual U17260EJ3V1UD 297 CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. * If "ACH" is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again. * Even if "ACH" is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated. Example: If the window open period is 25% Counting starts Overflow time Window close period (75%) Internal reset signal is generated if ACH is written to WDTE. Window open period (25%) Counting starts again when ACH is written to WDTE. Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. The window open period to be set is as follows. Table 11-4. Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Period of Watchdog Timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. The watchdog timer does not stop during self-programming of the flash memory and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 298 Preliminary User's Manual U17260EJ3V1UD CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows. Setting of Window Open Period 25% 50% 75% 100% Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None Window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms <When window open period is 25%> * Overflow time: 210/fRL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms * Window close time: 0 to 210/fRL (MIN.) x (1 - 0.25) = 0 to 210/216 kHz (MIN.) x 0.75 = 0 to 3.56 ms * Window open time: 210/fRL (MIN.) x (1 - 0.25) to 210/fRL (MAX.) = 210/216 kHz (MIN.) x 0.75 to 210/264 kHz (MAX.) = 3.56 to 3.88 ms Preliminary User's Manual U17260EJ3V1UD 299 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 12-1 shows the block diagram of clock output/buzzer output controller. Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller fPRS Prescaler 4 Selector 8 fPRS/210 to fPRS/213 BUZ/INTP7/P141 Output latch (P141) BZOE fSUB BCS0, BCS1 Selector fPRS to fPRS/27 Clock controller CLOE BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register (CKS) Internal bus 300 PM141 Preliminary User's Manual U17260EJ3V1UD PCL/INTP6/P140 Output latch (P140) PM140 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Clock output selection register (CKS) Control registers Port mode register 14 (PM14) Port register 14 (P14) 12.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 14 (PM14) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets CKS to 00H. Preliminary User's Manual U17260EJ3V1UD 301 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H R/W <7> 6 5 <4> 3 2 1 0 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification 0 Clock division circuit operation stopped. BUZ fixed to low level. 1 Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection fPRS = 10 MHz 0 0 1 1 0 1 0 1 fPRS/2 9.77 kHz 19.54 kHz fPRS/2 11 4.88 kHz 9.77 kHz fPRS/2 12 2.44 kHz 4.88 kHz fPRS/2 13 1.22 kHz 2.44 kHz CLOE PCL output enable/disable specification 0 Clock division circuit operation stopped. PCL fixed to low level. 1 Clock division circuit operation enabled. PCL output enabled. CCS3 0 fPRS = 20 MHz 10 CCS2 0 CCS1 0 CCS0 0 PCL output clock selection fPRS fSUB = fPRS = fPRS = 32.768 kHz 10 MHz 20 MHz - Note 1 Setting 10 MHz prohibited 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 5 MHz 10 MHz fPRS/2 2 2.5 MHz 5 MHz fPRS/2 3 1.25 MHz 2.5 MHz fPRS/2 4 625 kHz 1.25 MHz fPRS/2 5 312.5 kHz 625 kHz 156.25 kHz 312.5 kHz 78.125 kHz 156.25 kHz 0 1 1 0 fPRS/2 6 0 1 1 1 fPRS/2 7 1 0 0 0 fSUB Other than above Notes 1. fPRS/2 32.768 kHz - Setting prohibited If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V VDD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited. 2. The PCL output clock prohibits settings if they exceed 10 MHz. Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). 2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency 302 Note 2 Preliminary User's Manual U17260EJ3V1UD CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUZ pin for buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM14 to FFH. Figure 12-3. Format of Port Mode Register 14 (PM14) Address: FF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 1 1 1 1 1 1 PM141 PM140 PM14n P14n pin I/O mode selection (n = 0, 1) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 12.4 Operations of Clock Output/Buzzer Output Controller 12.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock. Figure 12-4. Remote Control Output Application Example CLOE * * Clock output 12.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. Preliminary User's Manual U17260EJ3V1UD 303 CHAPTER 13 A/D CONVERTER 13.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 13-1. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Voltage comparator AVSS Successive approximation register (SAR) Controller 3 ADS2 ADS1 ADS0 ADPC3 ADPC2 ADPC1 ADPC0 Analog input channel specification register (ADS) A/D conversion result register (ADCR) 5 4 ADCS FR2 FR1 FR0 LV1 LV0 Internal bus 304 ADCE A/D converter mode register (ADM) A/D port configuration register (ADPC) Preliminary User's Manual U17260EJ3V1UD Tap selector Selector Sample & hold circuit AVSS INTAD CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with the sampled voltage value. Figure 13-2. Circuit Configuration of Series Resistor String AVREF P-ch ADCS Series resistor string AVSS (4) Voltage comparator The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register converts the result of comparison by the voltage comparator, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). Preliminary User's Manual U17260EJ3V1UD 305 CHAPTER 13 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the VDD pin when port 2 is used as a digital port. The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and AVSS. (10) AVSS pin This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS pin even when the A/D converter is not used. (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. (13) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) Port mode register 2 (PM2) This register switches the ANI0/P20 to ANI7/P27 pins to input or output. 306 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * A/D port configuration register (ADPC) * Analog input channel specification register (ADS) * Port mode register 2 (PM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 13-3. Format of A/D Converter Mode Register (ADM) Address: FF28H Symbol ADM After reset: 00H <7> 6 ADCS 0 R/W 5 Note 1 FR2 ADCS 4 FR1 Note 1 FR0 2 1 Note 1 LV1 Note 1 LV0 <0> ADCE A/D conversion operation control 0 Stops conversion operation 1 Enables conversion operation Comparator operation controlNote 2 ADCE Notes 1. 3 Note 1 0 Stops comparator operation 1 Enables comparator operation (comparator: 1/2AVREF operation) For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time Selection. 2. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. Table 13-1. Settings of ADCS and ADCE ADCS ADCE 0 0 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (comparator: 1/2AVREF operation, only comparator consumes power) Note 1 0 Conversion mode (comparator operation stopped 1 1 Conversion mode (comparator: 1/2AVREF operation) ) Note Ignore data of the first conversion because it is not guaranteed range. Preliminary User's Manual U17260EJ3V1UD 307 CHAPTER 13 A/D CONVERTER Figure 13-4. Timing Chart When Comparator Is Used Comparator: 1/2AVREF operation ADCE Comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 s or longer. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other than the identical data. 2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. 308 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time Selection (1) 2.7 V AVREF 5.5 V A/D Converter Mode Register (ADM) FR2 FR1 FR0 LV1 Conversion Time Selection LV0 fPRS = 2 MHz Conversion fPRS = fPRS = Note 10 MHz 20 MHz Clock (fAD) Conversion Time Configuration SAR Clear Sampling Successive ADCR Conversion Transfer, Time INTAD Generation 0 0 0 0 0 264/fPRS Setting 26.4 s 13.2 s fPRS/12 Note 0 0 1 0 0 176/fPRS prohibited 17.6 s 8.8 s fPRS/8 0 1 0 0 0 132/fPRS 13.2 s 6.6 s fPRS/6 Note Note 0 1 1 0 0 88/fPRS 8.8 s Setting fPRS/4 1 0 0 0 0 66/fPRS 33.0 s 6.6 s prohibited fPRS/3 1 0 1 0 0 44/fPRS 22.0 s Setting Note Note 2/fAD 6/fAD 12/fAD 2/fAD fPRS/2 prohibited Other than above Setting prohibited Note This can be set only when 4.0 V AVREF 5.5 V. (2) 2.3 V AVREF < 2.7 V A/D Converter Mode Register (ADM) FR2 FR1 FR0 LV1 Conversion Time Selection LV0 fPRS = 2 MHz fPRS = 5 MHz Conversion Clock (fAD) Conversion Time Configuration SAR Clear Sampling Successive ADCR Conversion Transfer, Time INTAD Generation 0 0 0 0 1 480/fPRS 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 160/fPRS 1 0 0 0 1 120/fPRS 60.0 s 1 0 1 0 1 80/fPRS 40.0 s Other than above Setting prohibited Setting prohibited fPRS/12 320/fPRS 64.0 s fPRS/8 240/fPRS 48.0 s fPRS/6 32.0 s fPRS/4 Setting prohibited fPRS/3 Setting prohibited fPRS/2 2/fAD 24/fAD 12/fAD 2/fAD Setting prohibited Cautions 1. Set the conversion times with the following conditions. * 4.0 V AVREF 5.5 V: Sampling + successive conversion time = 5 to 30 s (fAD = 0.6 to 3.6 MHz) * 2.7 V AVREF < 4.0 V: Sampling + successive conversion time = 10 to 30 s (fAD = 0.6 to 1.8 MHz) * 2.3 V AVREF < 2.7 V: Sampling + successive conversion time = 25 to 62 s (fAD = 0.6 to 1.48 MHz) 2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. 3. Change LV1 and LV0 from the default value, when 2.3 V AVREF < 2.7 V. 4. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. Remark fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD 309 CHAPTER 13 A/D CONVERTER Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait periodNote SAR clear Sampling time Successive conversion time Sampling time Transfer SAR to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8 bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation sets this register to 0000H. Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF08H, FF09H Symbol After reset: 0000H R FF09H FF08H ADCR 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. 310 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 13-7. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF09H Symbol After reset: 00H 7 6 R 5 4 3 2 1 0 ADCRH Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. Preliminary User's Manual U17260EJ3V1UD 311 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 13-8. Format of Analog Input Channel Specification Register (ADS) Address: FF29H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 ADS2 ADS1 ADS0 ADS2 ADS1 ADS0 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 Analog input channel specification Cautions 1. Be sure to clear bits 3 to 7 to 0. 2 Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 3. Do not set a pin to be used as a digital I/O pin with ADPC with ADS. 4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. 312 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 13-9. Format of A/D Port Configuration Register (ADPC) Address: FF2FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/digital I/O (D) switching ANI7/ ANI6/ ANI5/ ANI4/ ANI3/ ANI2/ ANI1/ ANI0/ P27 P26 P25 P24 P23 P22 P21 P20 0 0 0 0 A A A A A A A A 0 0 0 1 A A A A A A A D 0 0 1 0 A A A A A A D D 0 0 1 1 A A A A A D D D 0 1 0 0 A A A A D D D D 0 1 0 1 A A A D D D D D 0 1 1 0 A A D D D D D D 0 1 1 1 A D D D D D D D 1 0 0 D D D D D D D D Other than above 0 Setting prohibited Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2 (PM2). 2. Do not set a pin to be used as a digital I/O pin with ADPC with ADS. 3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. Preliminary User's Manual U17260EJ3V1UD 313 CHAPTER 13 A/D CONVERTER (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of P20 to P27 at this time may be 0 or 1. If PM20 to PM27 are set to 0, they cannot be used as analog input port pins. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 13-10. Format of Port Mode Register 2 (PM2) Address: FF22H Symbol PM2 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2n P2n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of ADPC, ADS, and PM2. Table 13-3. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC Analog input selection PM2 Input mode Output mode ADS Selects ANI. ANI0/P20 to ANI7/P27 Pin Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Digital I/O selection Input mode Output mode 314 Selects ANI. Setting prohibited Does not select ANI. Digital input Selects ANI. Setting prohibited Does not select ANI. Digital output Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 2 (PM2). <3> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select one channel for A/D conversion using the analog input channel specification register (ADS). <5> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1. (<6> to <12> are operations performed by hardware.) <6> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <7> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <8> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <9> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <10> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <11> Comparison is continued in this way up to bit 0 of SAR. <12> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <13> Repeat steps <6> to <12>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <5>. To start A/D conversion again when ADCE = 0, set ADCE to 1, wait for 1 s or longer, and start <5>. To change a channel of A/D conversion, start from <4>. Caution Make sure the period of <1> to <5> is 1 s or more. Remark Two types of A/D conversion result registers are available. * ADCR (16 bits): Store 10-bit A/D conversion value * ADCRH (8 bits): Store 8-bit A/D conversion value Preliminary User's Manual U17260EJ3V1UD 315 CHAPTER 13 A/D CONVERTER Figure 13-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined Conversion result ADCR INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation sets the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. 316 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or ( ADCR 64 - 0.5) x where, INT( ): AVREF 1024 VAIN < ( ADCR 64 + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: A/D conversion result register (ADCR) value SAR: Successive approximation register Figure 13-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 13-12. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF Preliminary User's Manual U17260EJ3V1UD 317 CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been completed, the next A/D conversion operation is immediately started. If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result immediately before is retained. Figure 13-13. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result immediately before is retained ANIn ADCR, ADCRH ANIn INTAD Remarks 1. n = 0 to 7 2. m = 0 to 7 318 Preliminary User's Manual U17260EJ3V1UD Stopped Conversion result immediately before is retained ANIm CHAPTER 13 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2). <3> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select a channel to be used by using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS). <5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <6> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Change the channel> <8> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS to start A/D conversion. <9> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <10> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Complete A/D conversion> <11> Clear ADCS to 0. <12> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <5> is 1 s or more. 2. <1> may be done between <2> and <4>. 3. <1> can be omitted. However, ignore data of the first conversion after <5> in this case. 4. The period from <6> to <9> differs from the conversion time set using bits 5 to 1 (FR2 to FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time set using FR2 to FR0, LV1, and LV0. Preliminary User's Manual U17260EJ3V1UD 319 CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-14. Overall Error Figure 13-15. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 Analog input 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. 320 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-16. Zero-Scale Error Figure 13-17. Full-Scale Error Full-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 Ideal line 011 010 001 Zero-scale error 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 13-18. Integral Linearity Error Figure 13-19. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Differential linearity error Integral linearity error 0......0 0 Analog input 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time Preliminary User's Manual U17260EJ3V1UD 321 CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation. (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by instruction upon the end of conversion ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR or ADCRH. <2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 13-20 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion. 322 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER Figure 13-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI7 C = 100 to 1,000 pF AVSS VSS (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 1320). (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Preliminary User's Manual U17260EJ3V1UD 323 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-21. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ADCR ANIn ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF Remarks 1. n = 0 to 7 2. m = 0 to 7 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. 324 Preliminary User's Manual U17260EJ3V1UD CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF R1 C1 C2 4.0 V AVREF 5.5 V 8.1 k 8 pF 5 pF 2.7 V AVREF < 4.0 V 31 k 8 pF 5 pF 2.3 V AVREF < 2.7 V 381 k 8 pF 5 pF Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values. 2. n = 0 to 7 Preliminary User's Manual U17260EJ3V1UD 325 CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 14.4.2 Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate generator. * Maximum transfer rate: 312.5 kbps * Two-pin configuration TXD0: Transmit data output pin RXD0: Receive data input pin * Length of communication data can be selected from 7 or 8 bits. * Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full-duplex operation). * Fixed to LSB-first communication Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD0 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0. 2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start communication. 3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 326 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Registers Configuration Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0) Baud rate generator control register 0 (BRGC0) Port mode register 1 (PM1) Port register 1 (P1) Preliminary User's Manual U17260EJ3V1UD 327 328 Figure 14-1. Block Diagram of Serial Interface UART0 Filter RXD0/ SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial interface operation mode register 0 (ASIM0) fPRS/23 Baud rate generator Preliminary User's Manual U17260EJ3V1UD INTSR0 Reception control Receive buffer register 0 (RXB0) INTST0 Transmission control Transmit shift register 0 (TXS0) Reception unit Internal bus 8-bit timer/ event counter 50 output Baud rate generator control register 0 (BRGC0) 7 Baud rate generator 7 TXD0/ SCK10/P10 Output latch (P10) Registers Transmission unit PM10 CHAPTER 14 SERIAL INTERFACE UART0 fPRS/25 Asynchronous serial interface reception error status register 0 (ASIS0) Selector fPRS/2 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0. RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation and POWER0 = 0 set this register to FFH. (2) Receive shift register 0 (RXS0) This register converts the serial data input to the RXD0 pin into parallel data. RXS0 cannot be directly manipulated by a program. (3) Transmit shift register 0 (TXS0) This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is transmitted from the TXD0 pins. TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read. Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH. Cautions 1. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 2. Do not write the next transmit data to TXS0 before the transmission completion interrupt signal (INTST0) is generated. Preliminary User's Manual U17260EJ3V1UD 329 CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 0 (ASIM0) This 8-bit register controls the serial communication operations of serial interface UART0. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2) Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission. RXE0 2. . Enables operation of the internal operation clock. TXE0 Notes 1. Note 2 Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception. The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. 330 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL0 Reception operation Note Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL0 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission, clear TXE0 to 0, and then clear POWER0 to 0. 2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear RXE0 to 0, and then clear POWER0 to 0. 3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started. 4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1. 6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits. 7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with "number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit. 8. Be sure to set bit 0 to 1. Preliminary User's Manual U17260EJ3V1UD 331 CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0) to clear the error flag. Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) Address: FF73H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS0 0 0 0 0 0 PE0 FE0 OVE0 PE0 Status flag indicating parity error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If the parity of transmit data does not match the parity bit on completion of reception. FE0 Status flag indicating framing error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If the stop bit is not detected on completion of reception. OVE0 Status flag indicating overrun error 0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read. 1 If receive data is set to the RXB0 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0). 2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0) but discarded. 4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. 332 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH. Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FF71H After reset: 1FH R/W Symbol 7 6 5 4 3 2 1 0 BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00 TPS01 TPS00 Base clock (fXCLK0) selection fPRS = 2 MHz 0 0 TM50 output 0 1 fPRS/2 1 0 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz Note 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz 1 1 MDL04 MDL03 MDL02 MDL01 MDL00 k 0 0 x x x x Setting prohibited 0 1 0 0 0 8 fXCLK0/8 0 1 0 0 1 9 fXCLK0/9 0 1 0 1 0 10 fXCLK0/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 0 1 0 26 fXCLK0/26 1 1 0 1 1 27 fXCLK0/27 1 1 1 0 0 28 fXCLK0/28 1 1 1 0 1 29 fXCLK0/29 1 1 1 1 0 30 fXCLK0/30 1 1 1 1 1 31 fXCLK0/31 Selection of 5-bit counter output clock * * * * * Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Preliminary User's Manual U17260EJ3V1UD 333 CHAPTER 14 SERIAL INTERFACE UART0 Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fPRS: Peripheral hardware clock frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4. x: Don't care 5. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (4) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of P10 to 1. When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 14-5. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 334 After reset: FFH P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0). ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF70H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit TXE0 0 Notes 1. 2. . Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). RXE0 0 Note 2 Enables/disables reception Disables reception (synchronously resets the reception circuit). The input from the RXD0 pin is fixed to high level when POWER0 = 0. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and receive buffer register 0 (RXB0) are reset. Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode. To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1. Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 5 PORT FUNCTIONS. Preliminary User's Manual U17260EJ3V1UD 335 CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 0 (ASIM0) * Asynchronous serial interface reception error status register 0 (ASIS0) * Baud rate generator control register 0 (BRGC0) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the BRGC0 register (see Figure 14-4). <2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2). <3> Set bit 7 (POWER0) of the ASIM0 register to 1. <4> Set bit 6 (TXE0) of the ASIM0 register to 1. Transmission is enabled. Set bit 5 (RXE0) of the ASIM0 register to 1. Reception is enabled. <5> Write data to the TXS0 register. Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER0 0 1 TXE0 0 0 RXE0 PM10 P10 0 x x 1 x x Note Note Note PM11 x Note Note 1 0 0 1 1 1 0 1 P11 x Note x 1 x Note 1 UART0 Pin Function Operation TxD0/SCK10/P10 RxD0/SI10/P11 Stop SCK10/P10 SI10/P11 Reception SCK10/P10 RxD0 Note Transmission TxD0 SI10/P11 x Transmission/ TxD0 RxD0 x reception Note Can be set as port function or serial interface CSI10. Remark x: don't care POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) 336 TXE0: Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 PM1x: Port mode register P1x: Port output latch Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity bit D7 Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits (LSB first) * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (ASIM0). Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 Preliminary User's Manual U17260EJ3V1UD D6 D7 Stop 337 CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 338 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is generated. Transmission is stopped until the data to be transmitted next is written to TXS0. Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt occurs as soon as the last stop bit has been output. Caution After transmit data is written to TXS0, do not write the next transmit data before the transmission completion interrupt signal (INTST0) is generated. Figure 14-8. Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST0 2. Stop bit length: 2 TXD0 (output) Stop INTST0 Preliminary User's Manual U17260EJ3V1UD 339 CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs, however, the receive data is not written to RXB0. Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception. INTSR0 occurs upon completion of reception and in case of a reception error. Figure 14-9. Reception Completion Interrupt Request Timing RXD0 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR0 RXB0 Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 340 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt (INTSR0) servicing (see Figure 14-3). The contents of ASIS0 are cleared to 0 when ASIS0 is read. Table 14-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 0 (RXB0). (f) Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-10. Noise Filter Circuit Base clock RXD0/SI10/P11 In Q Internal signal A Match detector Preliminary User's Manual U17260EJ3V1UD In Q Internal signal B LD_EN 341 CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed to low level when POWER0 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when POWER0 = 1 and TXE0 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0). * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial interface operation mode register 0 (ASIM0) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Figure 14-11. Configuration of Baud Rate Generator POWER0 Baud rate generator fPRS/2 POWER0, TXE0 (or RXE0) fPRS/23 Selector 5-bit counter fXCLK0 fPRS/25 8-bit timer/ event counter 50 output Match detector BRGC0: TPS01, TPS00 Remark 342 1/2 Baud rate BRGC0: MDL04 to MDL00 POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0) TXE0: Bit 6 of ASIM0 RXE0: Bit 5 of ASIM0 BRGC0: Baud rate generator control register 0 Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit counter. Table 14-4. Set Value of TPS01 and TPS00 TPS01 TPS00 Base clock (fXCLK0) selection fPRS = 2 MHz 0 0 TM50 output 0 1 fPRS/2 1 0 1 1 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK0 2xk [bps] fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.5 M/(2 x 16) = 2,500,000/(2 x 16) = 78,125 [bps] Error = (78,125/76,800 - 1) x 100 = 1.725 [%] Preliminary User's Manual U17260EJ3V1UD 343 CHAPTER 14 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 14-5. Set Data of Baud Rate Generator Baud fPRS = 2.0 MHz Rate TPS01, [bps] TPS00 4800 2 9600 2 10400 k fPRS = 5.0 MHz Calculated ERR TPS01, Value [%] TPS00 26 4808 0.16 3 13 9615 0.16 3 2 12 10417 0.16 19200 1 26 19231 24000 1 21 31250 1 33660 38400 k fPRS = 10.0 MHz Calculated ERR TPS01, k fPRS = 20.0 MHz Calculated ERR TPS01, Calculated ERR [%] TPS00 16 4883 1.73 - - - - - - - - 8 9766 1.73 3 16 9766 1.73 - - - - 2 30 10417 0.16 3 15 10417 0.16 3 30 10417 0.16 0.16 2 16 19531 1.73 3 8 19531 1.73 3 16 19531 1.73 23810 -0.79 2 13 24038 0.16 2 26 24038 0.16 3 13 24038 0.16 16 31250 0 2 10 31250 0 2 20 31250 0 3 10 31250 0 1 15 33333 -0.79 2 9 34722 3.34 2 18 34722 3.34 3 9 34722 3.34 1 13 38462 0.16 2 8 39063 1.73 2 16 39063 1.73 3 8 39063 1.73 Value [%] k Value TPS00 Value [%] 56000 1 9 55556 -0.79 1 22 56818 1.46 2 11 56818 1.46 2 22 56818 1.46 62500 1 8 62500 0 1 20 62500 0 2 10 62500 0 2 20 62500 0 76800 - - - - 1 16 78125 1.73 2 8 78125 1.73 2 16 78125 1.73 115200 - - - - 1 11 113636 -1.36 1 22 113636 -1.36 2 11 113636 -1.36 153600 - - - - 1 8 156250 1 16 156250 2 8 156250 Remark 1.73 1.73 TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock (fXCLK0)) 344 1.73 k: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31) fPRS: Peripheral hardware clock frequency ERR: Baud rate error Preliminary User's Manual U17260EJ3V1UD CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-12. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART0 Start bit Bit 0 Bit 1 Bit 7 Stop bit Parity bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART0 k: Set value of BRGC0 FL: 1-bit data length Margin of latch timing: 2 clocks Preliminary User's Manual U17260EJ3V1UD 345 CHAPTER 14 SERIAL INTERFACE UART0 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 14-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 16 +4.14% -4.19% 24 +4.34% -4.38% 31 +4.44% -4.47% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC0 346 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 15.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 15.4.2 Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate generator. * Maximum transfer rate: 312.5 kbps * Two-pin configuration TXD6: Transmit data output pin RXD6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently (full duplex operation). * MSB- or LSB-first communication selectable * Inverted transmission operation * Sync break field transmission from 13 to 20 bits * More than 11 bits can be identified for sync break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start communication. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. Preliminary User's Manual U17260EJ3V1UD 347 CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-1 and 15-2 outline the transmission and reception operations of LIN. Figure 15-1. LIN Transmission Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field LIN Bus 8 bits Note 1 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 (output) INTST6Note 3 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 15.4.2 (2) (h) transmission). 3. Remark 348 INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. Preliminary User's Manual U17260EJ3V1UD SBF CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field 13-bit SBF reception SF reception ID reception Data reception Data reception LIN Bus <5> <2> RXD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows. <1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. <2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. <3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter 00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field (see 7.4.8 Pulse width measurement operation). Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. <4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). <5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. Figure 15-3 shows the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally. Preliminary User's Manual U17260EJ3V1UD 349 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0/EXLVI INTP0 input Port mode (PM120) Output latch (P120) Port input switch control (ISC0) <ISC0> 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector Selector P00/TI000 TI000 input Port mode (PM00) Output latch (P00) Remark Port input switch control (ISC1) <ISC1> 0: Select TI000 (P00) 1: Select RxD6 (P14) ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11) The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the sync field (SF) length and divides it by the number of bits. * Serial interface UART6 350 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Registers Configuration Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) Preliminary User's Manual U17260EJ3V1UD 351 352 Figure 15-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 Reception control INTSRE6 Selector Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) Transmission control Transmit shift register 6 (TXS6) Reception unit Internal bus Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) Baud rate generator 8 INTST6 TXD6/ P13 Registers Output latch (P13) Transmission unit Note Selectable with input switch control register (ISC). PM13 CHAPTER 15 SERIAL INTERFACE UART6 Preliminary User's Manual U17260EJ3V1UD fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output RXD6/ P14 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). 3. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. Preliminary User's Manual U17260EJ3V1UD 353 CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Note 2 . Enables operation of the internal operation clock TXE6 Enables/disables transmission 0 Disables transmission (synchronously resets the transmission circuit). 1 Enables transmission RXE6 Notes 1. Enables/disables reception 0 Disables reception (synchronously resets the reception circuit). 1 Enables reception The output of the TXD6 pin goes high level and the input from the RXD6 pin is fixed to the high level when POWER6 = 0 during transmission. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 354 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity. CL6 Note Specifies character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL6 Specifies number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 ISRM6 Reception operation Enables/disables occurrence of reception completion interrupt in case of error 0 "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). 1 "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission, clear TXE6 to 0, and then clear POWER6 to 0. 2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the base clock, the transmission circuit or reception circuit may not be initialized. 5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1. 6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 7. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 8. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. Preliminary User's Manual U17260EJ3V1UD 355 CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer register 6 (RXB6) to clear the error flag. Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF53H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If receive data is set to the RXB6 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. 356 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF55H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 TXBF6 Transmit buffer data flag 0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) 1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. Preliminary User's Manual U17260EJ3V1UD 357 CHAPTER 15 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection 0 0 0 0 fPRS 0 0 0 1 fPRS/2 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 fPRS = fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 20 MHz 2 MHz 5 MHz 10 MHz 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 4 125 kHz 312.5 kHz 625 kHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 1.25 MHz 0 1 1 0 fPRS/2 6 0 1 1 1 fPRS/2 7 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz fPRS/2 8 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz fPRS/2 9 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz fPRS/2 10 1.953 kHz 4.88 kHz 9.77 kHz 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 Other than above TM50 output 19.53 kHz Note Setting prohibited Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 358 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF57H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8-bit counter 0 0 0 0 0 x x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6/8 0 0 0 0 1 0 0 1 9 fXCLK6/9 0 0 0 0 1 0 1 0 10 fXCLK6/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 0 252 fXCLK6/252 1 1 1 1 1 1 0 1 253 fXCLK6/253 1 1 1 1 1 1 1 0 254 fXCLK6/254 1 1 1 1 1 1 1 1 255 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care Preliminary User's Manual U17260EJ3V1UD 359 CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)), because it may re-trigger SBF reception or SBF transmission. Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) Address: FF58H After reset: 16H R/W Note Symbol <7> <6> 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger - 0 1 SBF reception trigger SBTT6 SBF transmission trigger 0 - 1 SBF transmission trigger Note Bit 7 is read-only. 360 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length. 1 0 0 SBF is output with 20-bit length. DIR6 First-bit specification 0 MSB 1 LSB TXDLV6 Enables/disables inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF6 flag is held (1). 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. 6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during transmission. 7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. Preliminary User's Manual U17260EJ3V1UD 361 CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the P14/RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 15-11. Format of Input Switch Control Register (ISC) Address: FF4FH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 (P00) 1 RXD6 (P14) ISC0 INTP0 input source selection 0 INTP0 (P120) 1 RXD6 (P14) (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TXD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1. When using the P14/RXD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 15-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 362 After reset: FFH P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 TXE6 0 Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6 0 Notes 1. . Enables/disables reception Disables reception (synchronously resets the reception circuit). The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0 during transmission. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation. To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1. Remark To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 5 PORT FUNCTIONS. Preliminary User's Manual U17260EJ3V1UD 363 CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 15-8). <2> Set the BRGC6 register (see Figure 15-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 P13 0 0 0 x x 1 0 1 x x 1 0 0 1 1 1 0 1 Note Note Note PM14 x Note Note P14 x Note x 1 x Note 1 x UART6 Operation TXD6/P13 Pin Function Stop P13 P14 Reception P13 RXD6 Note Transmission TXD6 P14 x Transmission/ reception TXD6 RXD6 Note Can be set as port function. Remark x: don't care POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) 364 TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 PM1x: Port mode register P1x: Port output latch RXD6/P14 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. Preliminary User's Manual U17260EJ3V1UD 365 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start 366 D0 D1 D2 D3 D4 D5 Preliminary User's Manual U17260EJ3V1UD D6 D7 Stop Stop CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. Preliminary User's Manual U17260EJ3V1UD 367 CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the transmit data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 15-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) INTST6 368 Preliminary User's Manual U17260EJ3V1UD Stop CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 Transmission Status 0 Transmission is completed. 1 Transmission is in progress. Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, the next transmission may complete before execution of INTST6 interrupt servicing after transmission of one data frame. As a countermeasure, detection can be performed by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. Preliminary User's Manual U17260EJ3V1UD 369 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6. Transmission completion interrupt occurs? No Yes Transfer executed necessary number of times? Yes No Read ASIF6 TXSF6 = 0? Yes Yes of Completion transmission processing Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) 370 Preliminary User's Manual U17260EJ3V1UD No CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 Preliminary User's Manual U17260EJ3V1UD 371 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission TXD6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop INTST6 TXB6 Data (n - 1) Data (n) Data (n - 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) TXE6: 372 Bit 6 of asynchronous serial interface operation mode register (ASIM6) Preliminary User's Manual U17260EJ3V1UD FF CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 15-19. Reception Completion Interrupt Request Timing RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. Preliminary User's Manual U17260EJ3V1UD 373 CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt (INTSR6/INTSRE6) servicing (see Figure 15-6). The contents of ASIS6 are cleared to 0 when ASIS6 is read. Table 15-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 15-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception 374 (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 15-21. Noise Filter Circuit Base clock RXD6/P14 In Internal signal A Q In Internal signal B Q LD_EN Match detector (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 15-1 LIN Transmission Operation. When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered, and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6 (ASICL6) to 1. Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6), or until SBTT6 is set to 1. Figure 15-22. SBF Transmission 1 TXD6 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6 SBTT6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6) Preliminary User's Manual U17260EJ3V1UD 375 CHAPTER 15 SERIAL INTERFACE UART6 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 15-23. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 RXD6 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) 1 RXD6 2 3 4 5 6 7 8 9 SBRT6 /SBRF6 INTSR6 Remark RXD6: "0" RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request 376 Preliminary User's Manual U17260EJ3V1UD 10 CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Preliminary User's Manual U17260EJ3V1UD 377 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-24. Configuration of Baud Rate Generator POWER6 fPRS Baud rate generator fPRS/2 fPRS/22 POWER6, TXE6 (or RXE6) fPRS/23 fPRS/24 fPRS/25 Selector fPRS/26 8-bit counter fXCLK6 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Match detector CKSR6: TPS63 to TPS60 Remark Baud rate 1/2 BRGC6: MDL67 to MDL60 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 CKSR6: Clock selection register 6 BRGC6: Baud rate generator control register 6 (2) Generation of serial clock A serial clock to be generated can be specified by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). The clock to be input to the 8-bit counter can be set by bits 3 to 0 (TPS63 to TPS60) of CKSR6 and the division value (fXCLK6/8 to fXCLK6/255) of the 8-bit counter can be set by bits 7 to 0 (MDL67 to MDL60) of BRGC6. Table 15-4. Set Value of TPS63 to TPS60 TPS63 TPS62 TPS61 TPS60 Base Clock (fXCLK6) Selection fPRS = 2 MHz fPRS = 10 MHz fPRS = 20 MHz 0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz 0 0 1 0 fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 1.25 MHz 0 0 1 1 fPRS/2 3 250 kHz 625 kHz 0 1 0 0 fPRS/2 4 125 kHz 312.5 kHz 625 kHz 0 1 0 1 fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz 0 1 1 0 fPRS/2 6 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz 0 1 1 1 fPRS/2 7 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz 1 0 0 0 fPRS/2 8 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz 1.953 kHz 4.88 kHz 9.77 kHz 1 0 0 1 fPRS/2 9 1 0 1 0 fPRS/2 10 1 0 1 1 TM50 output Other than above 378 fPRS = 5 MHz Setting prohibited Preliminary User's Manual U17260EJ3V1UD 2.5 MHz 1.25 MHz 19.53 kHz CHAPTER 15 SERIAL INTERFACE UART6 (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] Preliminary User's Manual U17260EJ3V1UD 379 CHAPTER 15 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 15-5. Set Data of Baud Rate Generator Baud fPRS = 2.0 MHz Rate TPS63- [bps] TPS60 300 8H 600 7H 1200 k fPRS = 5.0 MHz Calculated ERR TPS63Value [%] TPS60 13 301 0.16 7H 13 601 0.16 6H 6H 13 1202 0.16 2400 5H 13 2404 4800 4H 13 9600 3H 19200 k fPRS = 10.0 MHz Calculated ERR TPS63Value [%] TPS60 65 301 0.16 8H 65 601 0.16 7H 5H 65 1202 0.16 0.16 4H 65 2404 4808 0.16 3H 65 13 9615 0.16 2H 2H 13 19231 0.16 24000 1H 21 23810 31250 1H 4 38400 1H 13 48000 0H 76800 k fPRS = 20.0 MHz Calculated ERR TPS63Value [%] TPS60 65 301 0.16 9H 65 601 0.16 8H 6H 65 1202 0.16 0.16 5H 65 2404 4808 0.16 4H 65 65 9615 0.16 3H 1H 65 19231 0.16 -0.79 3H 13 24038 31250 0 4H 5 38462 0.16 0H 65 21 47619 -0.79 2H 0H 13 76923 0.16 115200 0H 9 111111 -3.55 153600 - - - 312500 - - - Remark Calculated ERR Value [%] 65 301 0.16 65 601 0.16 7H 65 1202 0.16 0.16 6H 65 2404 0.16 4808 0.16 5H 65 4808 0.16 65 9615 0.16 4H 65 9615 0.16 2H 65 19231 0.16 3H 65 19231 0.16 0.16 4H 13 24038 0.16 5H 13 24038 0.16 31250 0 5H 5 31250 0 6H 5 31250 0 38462 0.16 1H 65 38462 0.16 2H 65 38462 0.16 13 48077 0.16 3H 13 48077 0.16 4H 13 48077 0.16 0H 33 75758 -1.36 0H 65 76923 0.16 1H 65 76923 0.16 1H 11 113636 -1.36 0H 43 116279 0.94 0H 87 114943 -0.22 - 1H 8 156250 1.73 0H 33 151515 -1.36 1H 33 151515 -1.36 - 0H 8 312500 0 1H 8 312500 2H 8 312500 0 0 TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) 380 k fPRS: Peripheral hardware clock frequency ERR: Baud rate error Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 15-25. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 Bit 1 Bit 7 Stop bit Parity bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 15-25, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: Set value of BRGC6 FL: 1-bit data length Margin of latch timing: 2 clocks Preliminary User's Manual U17260EJ3V1UD 381 CHAPTER 15 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 15-6. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 382 Preliminary User's Manual U17260EJ3V1UD CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 15-26. Data Frame Length During Continuous Transmission Start bit of second byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 Preliminary User's Manual U17260EJ3V1UD 383 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The PD78F0531, 78F0532, and 78F0533 incorporate serial interface CSI10, and the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D incorporate serial interfaces CSI10 and CSI11. 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data lines (SI1n and SO1n). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 16.4.2 3-wire serial I/O mode. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 384 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Transmit controller Controller Clock start/stop controller & clock phase controller Transmit buffer register 1n (SOTB1n) Registers Serial I/O shift register 1n (SIO1n) Serial operation mode register 1n (CSIM1n) Control registers Serial clock selection register 1n (CSIC1n) Port mode register 0 (PM0) or port mode register 1 (PM1) Port register 0 (P0) or port register 1 (P1) PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Figure 16-1. Block Diagram of Serial Interface CSI10 Internal bus (a) 8 8 Serial I/O shift register 10 (SIO10) SI10/P11/RXD0 Transmit buffer register 10 (SOTB10) Output selector SO10/P12 Output latch (P12) Output latch Transmit data controller PM12 Selector Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 SCK10/P10/TxD0 Clock start/stop controller & clock phase controller INTCSI10 Baud rate generator PM10 Remark Output latch (P10) (a): SO10 output Preliminary User's Manual U17260EJ3V1UD 385 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) Internal bus SI11/P03 (a) 8 8 Serial I/O shift register 11 (SIO11) Transmit buffer register 11 (SOTB11) Transmit data controller Output selector SO11/P02 Output latch (P02) Output latch SSI11 PM02 Selector Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 Clock start/stop controller & clock phase controller INTCSI11 SCK11/P04 SSI11 Baud rate generator PM04 Remark Output latch (P04) (a): SO11 output (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n). SOTB1n can be written or read by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a low level input to the SSI11 pin. For details on the transmission/reception operation, see 16.4.2 (2) Communication operation. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: 386 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n. Reset signal generation sets this register to 00H. Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication). 2. In the slave mode, reception is started when data is read from SIO11 with a low level input to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication operation. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Preliminary User's Manual U17260EJ3V1UD 387 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) (1) Serial operation mode register 1n (CSIM1n) CSIM1n is used to select the operation mode and enable or disable operation. CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD10 0 Note 5 1 DIR10 . Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode Note 6 First bit specification 0 MSB 1 LSB CSOT10 Notes 1. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. 2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status 3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. (00H). 4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). 5. The SO10 output (see (a) in Figure 16-1) is fixed to the low level when TRMD10 is 0. Reception is 6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). started when data is read from SIO10. Caution Be sure to clear bit 5 to 0. 388 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Address: FF88H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD11 0 Note 5 1 SSE11 Transmit/receive mode control Receive mode (transmission disabled). Notes 6, 7 SSI11 pin use selection 0 SSI11 pin is not used 1 SSI11 pin is used Note 8 First bit specification 0 MSB 1 LSB CSOT11 2. . Transmit/receive mode DIR11 Notes 1. Note 3 Communication status flag 0 Communication is stopped. 1 Communication is in progress. Bit 0 is a read-only bit. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). 3. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. 4. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication). 5. The SO11 output (see (a) in Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is started when data is read from SIO11. 6. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication). 7. Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1. 8. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication). Preliminary User's Manual U17260EJ3V1UD 389 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100 CKP10 DAP10 0 0 Specification of data transmission/reception timing 1 SCK10 SO10 Type D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 0 1 2 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 1 0 3 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing 1 1 4 SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 SI10 input timing CKS102 CKS101 0 0 0 0 0 1 CKS100 0 1 0 Mode CSI10 serial clock selection fPRS/2 fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 625 kHz 0 1 1 fPRS/2 4 125 kHz 312.5 kHz 1 0 0 fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz 1 0 1 fPRS/2 6 31.25 kHz 78.13 kHz 7 15.63 kHz 39.06 kHz 78.13 kHz 1 1 0 fPRS/2 1 1 1 External clock input to SCK10 Master mode 1.25 MHz 625 kHz 156.25 kHz 312.5 kHz 156.25 kHz Slave mode Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark 390 fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 0 0 Specification of data transmission/reception timing Type 1 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 0 1 2 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 1 0 3 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing 1 1 4 SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing CKS112 CKS111 CKS110 fPRS = 2 MHz 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Mode CSI11 serial clock selection fPRS/2 fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz fPRS/2 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz fPRS/2 5 62.5 kHz 156.25 kHz 312.5 kHz fPRS/2 6 31.25 kHz 78.13 kHz 7 15.63 kHz 39.06 kHz 78.13 kHz 1 1 0 fPRS/2 1 1 1 External clock input to SCK11 Master mode 625 kHz 156.25 kHz 312.5 kHz 156.25 kHz Slave mode Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status (00H). 3. The phase type of the data clock is type 1 after reset. Remark fPRS: Peripheral hardware clock frequency Preliminary User's Manual U17260EJ3V1UD 391 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. When using P10/SCK10 and P04/SCK11Note as the clock output pins of the serial interface, clear PM10 and PM04 to 0, and set the output latches of P10 and P04 to 1. When using P12/SO10 and P02/SO11Note as the data output pins of the serial interface, clear PM12, PM02, and the output latches of P12 and P02 to 0. When using P10/SCK10 and P04/SCK11Note as the clock input pins of the serial interface, P11/SI10/RXD0 and P03/SI11Note as the data input pins, and P05/SSI11 Note/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1. PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Figure 16-7. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH 6 5 4 R/W Symbol 7 3 2 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 6) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 1 0 Figure 16-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol 7 After reset: FFH 6 5 4 R/W 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n 392 P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11Note, P03/SI11Note, and P04/SCK11Note pins can be used as ordinary I/O port pins in this mode. Note Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D (1) Register used The operation stop mode is set by serial operation mode register 1n (CSIM1n). To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0. (a) Serial operation mode register 1n (CSIM1n) CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets CSIM1n to 00H. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: * Serial operation mode register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 . To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). 2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. * Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 . To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the default status (00H). 2. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset. Preliminary User's Manual U17260EJ3V1UD 393 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines. (1) Registers used * Serial operation mode register 1n (CSIM1n) * Serial clock selection register 1n (CSIC1n) * Port mode register 0 (PM0) or port mode register 1 (PM1) * Port register 0 (P0) or port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC1n register (see Figures 16-5 and 16-6). <2> Set bits 0 and 4 to 6 (CSOT1n, DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see Figures 16-3 and 16-4). <3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 1n (SOTB1n). Data transmission/reception is started. Read data from serial I/O shift register 1n (SIO1n). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: 394 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 CSI10 P10 Pin Function Operation SI10/RXD0/ SO10/P12 0 x Note 1 x x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop SCK10/ TXD0/P10 P11 RXD0/P11 P12 TXD0/ P10 1 0 x 1 x Note 1 x Note 1 1 x Slave reception 1 x Note 1 1 x Note 1 0 0 1 x SI10 P12 Note 3 Slave Note 3 RXD0/P11 SO10 Note 3 1 x 1 0 0 1 x Slave reception 1 0 x 1 x x Note 1 0 1 SCK10 Note 3 (input) SI10 SO10 SCK10 Note 3 transmission/ Note 1 SCK10 (input) transmission 1 Note 2 (input) Note 3 Master reception SI10 P12 SCK10 (output) 1 x Note 1 1 x Note 1 0 0 0 Master 1 RXD0/P11 SO10 transmission 1 1 1 x 0 0 0 Master 1 SCK10 (output) SI10 SO10 transmission/ SCK10 (output) reception Notes 1. Can be set as port function. 2. To use P10/SCK10/TXD0 as port pins, clear CKP10 to 0. 3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. Remark x: don't care CSIE10: Bit 7 of serial operation mode register 10 (CSIM10) TRMD10: Bit 6 of CSIM10 CKP10: Bit 4 of serial clock selection register 10 (CSIC10) CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 PM1x: Port mode register P1x: Port output latch Preliminary User's Manual U17260EJ3V1UD 395 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) (b) Serial interface CSI11 (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) CSI11 CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 Pin Function Operation 0 x x x Note 1 x Note 1 x x x x Note 1 Note 1 x Note 1 x Note 1 x x x x Note 1 Note 1 Stop SI11/ SO11/ SCK11/ SSI11/ P03 P02 P04 TI001/P05 P03 P02 P04 Note 2 TI001/ P05 1 0 0 x 1 Note 1 Note 1 1 x Note 1 Note 1 Slave reception SI11 P02 Note 3 SCK11 TI001/ (input) P05 Note 3 1 1 1 1 x Note 1 0 x Note 1 0 0 1 x x Note 1 x SSI11 x Note 1 Slave P03 SO11 Note 3 transmission SCK11 TI001/ (input) P05 Note 3 1 1 1 1 0 x 1 0 0 1 x x Note 1 x SSI11 x Note 1 Slave SI11 SO11 transmission/ 1 1 0 1 0 x 1 x Note 1 x Note 1 0 1 x Note 1 reception x x Note 1 Note 3 Master 1 1 x 0 x Note 1 0 0 0 1 x Note 1 x Note 1 Master 1 1 0 1 x 0 0 0 1 x x Note 1 Master SI11 P02 P03 SO11 SI11 SO11 transmission/ reception Notes 1. Can be set as port function. 2. To use P04/SCK11 as port pins, clear CKP11 to 0. 3. To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1. Remark x: don't care CSIE11: Bit 7 of serial operation mode register 11 (CSIM11) TRMD11: Bit 6 of CSIM11 CKP11: Bit 4 of serial clock selection register 11 (CSIC11) CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11 396 PM0x: Port mode register P0x: Port output latch Preliminary User's Manual U17260EJ3V1UD P05 SSI11 transmission Note 1 TI001/ (input) Note 3 reception Note 1 SCK11 SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 SCK11 TI001/ (output) P05 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition, data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. Reception is started when data is read from serial I/O shift register 1n (SIO1n). However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in the slave mode. <1> Low level input to the SSI11 pin Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read. <2> High level input to the SSI11 pin Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read, transmission/reception or reception will not be started. <3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low level is input to the SSI11 pin Transmission/reception or reception is started. <4> A high level is input to the SSI11 pin during transmission/reception or reception Transmission/reception or reception is suspended. After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared to 0. Then the next communication is enabled. Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial communication). 2. When using serial interface CSI11, wait for the duration of at least one clock before the clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise, malfunctioning may occur. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Preliminary User's Manual U17260EJ3V1UD 397 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) (a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 398 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) (b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) SO1n 55H is written to SOTB1n. Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave mode. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 399 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (c) Type 3: CKP1n = 1, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n (d) Type 4: CKP1n = 1, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n D7 D6 D5 D4 D3 D2 D1 D0 CSOT1n Remarks 1. n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 2. The above figure illustrates a communication operation where data is transmitted with the MSB first. 400 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11. Output Operation of First Bit (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch First bit SO1n 2nd bit (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 401 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-11. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin. The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling) edge of SCK1n, and the data is output from the SO1n pin. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D 402 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( Next request is issued.) Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch Last bit SO1n (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Remark n = 0: Last bit PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 403 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-12. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Last bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( Next request is issued.) SOTB1n SIO1n Output latch SO1n Last bit PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: 404 Preliminary User's Manual U17260EJ3V1UD CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (see (a) in Figures 16-1 and 16-2) The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3. SO1n Output Status TRMD1n TRMD1n = 0 DIR1n - - Outputs low level DAP1n = 0 - Value of SO1n latch Note 2 TRMD1n = 1 Note 1 DAP1n SO1n Output Note 2 (low-level output) DAP1n = 1 Notes 1. DIR1n = 0 Value of bit 7 of SOTB1n DIR1n = 1 Value of bit 0 of SOTB1n The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12 or PM02 and P02, as well as the SO1n output. 2. Status after reset Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Remark n = 0: Preliminary User's Manual U17260EJ3V1UD 405 CHAPTER 17 SERIAL INTERFACE IIC0 17.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial data bus (SDA0) line. This mode complies with the I2C bus format and the master device can generated "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received status and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial clock line and the serial data bus line. Figure 17-1 shows a block diagram of serial interface IIC0. 406 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Slave address register 0 (SVA0) SDA0/ P61 Noise eliminator IIC shift register 0 (IIC0) DFC0 PM61 Set D Q Stop condition generator SO latch CL01, CL00 Data hold time correction circuit TRC0 N-ch opendrain output Start condition generator Clear Match signal ACK generator Output control Output latch (P61) Wake-up controller ACK detector Start condition detector Stop condition detector SCL0/ P60 Noise eliminator DFC0 Interrupt request signal generator Serial clock counter Serial clock controller PM60 Output latch (P60) IICS0.MSTS0, EXC0, COI0 IIC shift register 0 (IIC0) Serial clock wait controller N-ch opendrain output INTIIC0 IICC0.STT0, SPT0 IICS0.MSTS0, EXC0, COI0 fPRS EXSCL0/ P62 Bus status detector Prescaler CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC clock selection register 0 (IICCL0) CLX0 STCF IIC function expansion register 0 (IICX0) IICBSY STCEN IICRSV IIC flag register 0 (IICF0) Internal bus Preliminary User's Manual U17260EJ3V1UD 407 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-2 shows a serial bus configuration example. Figure 17-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDA0 Slave CPU1 Address 0 SCL0 Serial data bus Serial clock SDA0 Slave CPU2 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 408 Preliminary User's Manual U17260EJ3V1UD Master CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N CHAPTER 17 SERIAL INTERFACE IIC0 17.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 17-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0) Port mode register 6 (PM6) Port register 6 (P6) (1) IIC shift register 0 (IIC0) IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. IIC0 can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing and reading operations to IIC0. Cancel the wait state and start data transfer by writing data to IIC0 during the wait period. IIC0 is set by an 8-bit memory manipulation instruction. Reset signal generation sets IIC0 to 00H. Figure 17-3. Format of IIC Shift Register 0 (IIC0) Address: FFA5H Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 IIC0 Cautions 1. Do not write data to IIC0 during data transfer. 2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state other than during the wait period is prohibited. When the device serves as the master, however, IIC0 can be written only once after the communication trigger bit (STT0) is set to 1. (2) Slave address register 0 (SVA0) This register stores local addresses when in slave mode. SVA0 is set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected). Reset signal generation sets SVA0 to 00H. Figure 17-4. Format of Slave Address Register 0 (SVA0) Address: FFA7H Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 0Note SVA0 Note Bit 0 is fixed to 0. Preliminary User's Manual U17260EJ3V1UD 409 CHAPTER 17 SERIAL INTERFACE IIC0 (3) SO latch The SO latch is used to retain the SDA0 pin's output level. (4) Wake-up controller This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC0). An I2C interrupt request is generated by the following two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by SPIE0 bit) Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0) SPIE0 bit: Bit 4 of IIC control register 0 (IICC0) (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1. (13) Stop condition generator This circuit generates a stop condition when the SPT0 bit is set to 1. 410 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit. Remark STT0 bit: Bit 1 of IIC control register 0 (IICC0) SPT0 bit: Bit 0 of IIC control register 0 (IICC0) IICRSV bit: Bit 0 of IIC flag register 0 IICBSY bit: Bit 6 of IIC flag register 0 STCF bit: Bit 7 of IIC flag register 0 STCEN bit: Bit 1 of IIC flag register 0 Preliminary User's Manual U17260EJ3V1UD 411 CHAPTER 17 SERIAL INTERFACE IIC0 17.3 Registers to Control Serial Interface IIC0 Serial interface IIC0 is controlled by the following seven registers. * IIC control register 0 (IICC0) * IIC flag register 0 (IICF0) * IIC status register 0 (IICS0) * IIC clock selection register 0 (IICCL0) * IIC function expansion register 0 (IICX0) * Port mode register 6 (PM6) * Port register 6 (P6) (1) IIC control register 0 (IICC0) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. IICC0 is set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from "0" to "1". Reset signal generation sets IICC0 to 00H. 412 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFA6H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable 0 Stop operation. Reset IIC status register 0 (IICS0) 1 Enable operation. Note 1 . Stop internal operation. Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level. Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1) * Cleared by instruction * Set by instruction * Reset LREL0 Note 2 Exit from communications 0 Normal operation 1 This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0 and SDA0 lines are set to high impedance. The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0. * STT0 * SPT0 * MSTS0 * EXC0 * COI0 * TRC0 * ACKD0 * STD0 The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1) * Automatically cleared after execution * Set by instruction * Reset WREL0 Note 2 Wait cancellation 0 Do not cancel wait 1 Cancel wait. This setting is automatically cleared after wait is canceled. When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the SDA0 line goes into the high impedance state (TRC0 = 0). Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the IICCL0 register are reset. 2. This flag's signal is invalid when IICE0 = 0. Caution The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1) while the SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I2C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction. Preliminary User's Manual U17260EJ3V1UD 413 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) * Cleared by instruction * Set by instruction * Reset Note 1 WTIM0 Control of wait and interrupt request generation 0 Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1, 2 ACKE0 0 1 Acknowledgment control Disable acknowledgment. Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However, ACK is invalid during address transfers and other than in expansion mode. Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1. This flag's signal is invalid when IICE0 = 0. 2. The set value is invalid during address transfer and if the code is not an extension code. When the device serves as a slave and the addresses match, an acknowledge is generated regardless of the set value. 414 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (3/4) STT0 Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in STOP mode): Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, SCL0 is changed to low level. When a third party is communicating: * When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSV = 1) STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as SPT0. * Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1) * Cleared by setting SST0 to 1 while communication * Set by instruction reservation is prohibited. * Cleared by loss in arbitration * Cleared after start condition is generated by master device * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Note This flag's signal is invalid when IICE0 = 0. Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting. 2. IICRSV: Bit 0 of IIC flag register (IICF0) STCF: Bit 7 of IIC flag register (IICF0) Preliminary User's Manual U17260EJ3V1UD 415 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device's transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop condition is generated. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as STT0. * SPT0 can be set to 1 only when in master mode Note . * When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output of the ninth clock. * Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited. Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. For details, see 17.5.15 Other cautions. Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance. Remark 416 Bit 0 (SPT0) becomes 0 when it is read after data setting. Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (2) IIC status register 0 (IICS0) This register indicates the status of I2C. IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation sets IICS0 to 00H. Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT. Figure 17-6. Format of IIC Status Register 0 (IICS0) (1/3) Address: FFAAH After reset: 00H R Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 MSTS0 Master device status 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1) * When a stop condition is detected * When ALD0 = 1 (arbitration loss) * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset * When a start condition is generated ALD0 Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". MSTS0 is cleared. Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1) Note * Automatically cleared after IICS0 is read * When IICE0 changes from 1 to 0 (operation stop) * Reset EXC0 * When the arbitration result is a "loss". Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other bits. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) Preliminary User's Manual U17260EJ3V1UD 417 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-6. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses 0 Addresses do not match. 1 Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) * When a start condition is detected * When the received address matches the local address * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) (slave address register 0 (SVA0)) (set at the rising edge of the eighth clock). * When IICE0 changes from 1 to 0 (operation stop) * Reset TRC0 Detection of transmit/receive status 0 Receive status (other than transmit status). The SDA0 line is set for high impedance. 1 Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the falling edge of the first byte's ninth clock). Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1) <Both master and slave> <Master> * When a stop condition is detected * When a start condition is generated * Cleared by LREL0 = 1 (exit from communications) * When "0" is output to the first byte's LSB (transfer * When IICE0 changes from 1 to 0 (operation stop) * Cleared by WREL0 = 1 Note (wait cancel) * When ALD0 changes from 0 to 1 (arbitration loss) * Reset direction specification bit) <Slave> * When "1" is input to the first byte's LSB (transfer direction specification bit) <Master> * When "1" is output to the first byte's LSB (transfer direction specification bit) <Slave> * When a start condition is detected * When "0" is input to the first byte's LSB (transfer direction specification bit) <When not used for communication> Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes into a high-impedance state. Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: 418 Bit 7 of IIC control register 0 (IICC0) Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-6. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) * When a stop condition is detected * After the SDA0 line is set to low level at the rising edge of * At the rising edge of the next byte's first clock SCL0's ninth clock * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset STD0 Detection of start condition 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect. Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LREL0 = 1 (exit from communications) * When IICE0 changes from 1 to 0 (operation stop) * Reset SPD0 Detection of stop condition 0 Stop condition was not detected. 1 Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When IICE0 changes from 1 to 0 (operation stop) * Reset Remark LREL0: Bit 6 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) (3) IIC flag register 0 (IICF0) This register sets the operation mode of I2C and indicates the status of the I2C bus. IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are readonly. The IICRSV bit can be used to enable/disable the communication reservation function (see 17.5.14 Communication reservation). STCEN can be used to set the initial value of the IICBSY bit (see 17.5.15 Other cautions). IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IIC control register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read. Reset signal generation sets IICF0 to 00H. Preliminary User's Manual U17260EJ3V1UD 419 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-7. Format of IIC Flag Register 0 (IICF0) Address: FFABH R/WNote After reset: 00H Symbol <7> <6> 5 4 3 2 <1> <0> IICF0 STCF IICBSY 0 0 0 0 STCEN IICRSV STCF STT0 clear flag 0 Generate start condition 1 Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF = 0) Condition for setting (STCF = 1) * Cleared by STT0 = 1 * When IICE0 = 0 (operation stop) * Reset * Generating start condition unsuccessful and STT0 cleared to 0 when communication reservation is disabled (IICRSV = 1). I2C bus status flag IICBSY 0 Bus release status (communication initial status when STCEN0 = 1) 1 Bus communication status (communication initial status when STCEN0 = 0) Condition for clearing (IICBSY = 0) Condition for setting (IICBSY = 1) * Detection of stop condition * When IICE0 = 0 (operation stop) * Reset * Detection of start condition * Setting of IICE0 when STCEN = 0 STCEN Initial start enable trigger 0 After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of a stop condition. 1 After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting a stop condition. Condition for clearing (STCEN = 0) Condition for setting (STCEN = 1) * Detection of stop condition * Reset * Set by instruction IICRSV Communication reservation function disable bit 0 Enable communication reservation 1 Disable communication reservation Condition for clearing (IICRSV = 0) Condition for setting (IICRSV = 1) * Cleared by instruction * Reset * Set by instruction Note Bits 6 and 7 are read-only. Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0). 2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to IICRSV only when the operation is stopped (IICE0 = 0). Remark STT0: Bit 1 of IIC control register 0 (IICC0) IICE0: Bit 7 of IIC control register 0 (IICC0) 420 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (4) IIC clock selection register 0 (IICCL0) This register is used to set the transfer clock for the I2C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are readonly. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion register 0 (IICX0) (see 17.3 (6) I2C transfer clock setting method). Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation sets IICCL0 to 00H. Figure 17-8. Format of IIC Clock Selection Register 0 (IICCL0) Address: FFA8H After reset: 00H R/W Note Symbol 7 6 <5> <4> <3> <2> 1 0 IICCL0 0 0 CLD0 DAD0 SMC0 DFC0 CL01 CL00 CLD0 Detection of SCL0 pin level (valid only when IICE0 = 1) 0 The SCL0 pin was detected at low level. 1 The SCL0 pin was detected at high level. Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1) * When the SCL0 pin is at low level * When the SCL0 pin is at high level * When IICE0 = 0 (operation stop) * Reset DAD0 Detection of SDA0 pin level (valid only when IICE0 = 1) 0 The SDA0 pin was detected at low level. 1 The SDA0 pin was detected at high level. Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1) * When the SDA0 pin is at low level * When the SDA0 pin is at high level * When IICE0 = 0 (operation stop) * Reset SMC0 Operation mode switching 0 Operates in standard mode. 1 Operates in high-speed mode. DFC0 Digital filter operation control 0 Digital filter off. 1 Digital filter on. Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0). The digital filter is used for noise elimination in high-speed mode. Note Bits 4 and 5 are read-only. Remark IICE0: Bit 7 of IIC control register 0 (IICC0) Preliminary User's Manual U17260EJ3V1UD 421 CHAPTER 17 SERIAL INTERFACE IIC0 (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I2C. IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 17.3 (6) I2C transfer clock setting method). Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0. Reset signal generation sets IICX0 to 00H. Figure 17-9. Format of IIC Function Expansion Register 0 (IICX0) Address: FFA9H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> IICX0 0 0 0 0 0 0 0 CLX0 (6) I2C transfer clock setting method The I2C transfer clock frequency (fSCL) is calculated using the following expression. fSCL = 1/(m x T + tR + tF) m = 12, 18, 24, 44, 66, 86 (see Table 17-2 Selection Clock Setting) 422 T: 1/fW tR: SCL0 rise time tF: SCL0 fall time Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(88 x 238.7 ns + 200 ns + 50 ns) 48.1 kHz m x T + tR + tF tF m/2 x T tR m/2 x T SCL0 SCL0 inversion SCL0 inversion SCL0 inversion The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0). Table 17-2. Selection Clock Setting IICX0 IICCL0 Selection Clock Transfer Clock Settable Selection Clock (fW) (fW/m) (fW) Range Operation Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 0 0 0 0 fPRS/2 fW/44 2.00 to 4.19 MHz Normal mode 0 0 0 1 fPRS/2 fW/86 4.19 to 8.38 MHz (SMC0 bit = 0) 0 0 1 0 fPRS/4 fW/86 0 0 1 1 fEXSCL0 fW/66 6.4 MHz 0 1 0 x fPRS/2 fW/24 4.00 to 8.38 MHz 0 1 1 0 fPRS/4 fW/24 0 1 1 1 fEXSCL0 fW/18 6.4 MHz 1 0 x x Setting prohibited 1 1 0 x fPRS/2 fW/12 4.00 to 4.19 MHz 1 1 1 0 fPRS/4 fW/12 1 1 1 1 Setting prohibited Caution High-speed mode (SMC0 bit = 1) High-speed mode (SMC0 bit = 1) Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0. Remarks 1. x: don't care 2. fPRS: Peripheral hardware clock frequency 3. fEXSCL0: External clock frequency from EXSCL0 pin Preliminary User's Manual U17260EJ3V1UD 423 CHAPTER 17 SERIAL INTERFACE IIC0 (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0 and P61/SDA0 pins output a low level (fixed) when IICE0 is 0. PM6 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM6 to FFH. Figure 17-10. Format of Port Mode Register 6 (PM6) Address: FF26H R/W Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 PM63 PM62 PM61 PM60 PM6n 424 After reset: FFH P6n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 17.4 I2C Bus Mode Functions 17.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0 ...... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDA0 ...... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 17-11. Pin Configuration Diagram Slave device VDD Master device SCL0 SCL0 Clock output (Clock output) VDD VSS VSS (Clock input) Clock input SDA0 SDA0 Data output Data output VSS VSS Data input Data input Preliminary User's Manual U17260EJ3V1UD 425 CHAPTER 17 SERIAL INTERFACE IIC0 17.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 17-12 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus. Figure 17-12. I2C Bus Serial Data Transfer Timing SCL0 1-7 8 9 1-8 9 1-8 9 ACK Data ACK SDA0 Start condition Address R/W ACK Data Stop condition The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0's low level period can be extended and a wait can be inserted. 17.5.1 Start conditions A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected. Figure 17-13. Start Conditions SCL0 H SDA0 A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of IICS0 is set (to 1). 426 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 17.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0 values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 17-14. Address SCL0 1 2 3 4 5 6 7 8 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Address Note INTIIC0 Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. The slave address and the eighth bit, which specifies the transfer direction as described in 17.5.3 Transfer direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received addresses are written to IIC0. The slave address is assigned to the higher 7 bits of IIC0. 17.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device. Figure 17-15. Transfer Direction Specification SCL0 1 2 3 4 5 6 7 8 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Transfer direction specification Note INTIIC0 Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device operation. Preliminary User's Manual U17260EJ3V1UD 427 CHAPTER 17 SERIAL INTERFACE IIC0 17.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows. <1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist. To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0) of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1 for reception (TRC0 = 0). If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). Figure 17-16. ACK SCL0 1 2 3 4 5 6 7 8 9 SDA0 A6 A5 A4 A3 A2 A1 A0 R/W ACK When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance. How ACK is generated when data is received differs as follows depending on the setting of the wait timing. * When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0): By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the SCL0 pin. * When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1): ACK is generated by setting ACKE0 to 1 in advance. 428 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 17.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 17-17. Stop Condition SCL0 H SDA0 A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4 (SPIE0) of IICC0 is set to 1. Preliminary User's Manual U17260EJ3V1UD 429 CHAPTER 17 SERIAL INTERFACE IIC0 17.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 17-18. Wait (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master returns to high impedance but slave is in wait state (low level). IIC0 Wait after output of ninth clock IIC0 data write (cancel wait) 6 SCL0 7 8 9 1 2 3 Slave Wait after output of eighth clock FFH is written to IIC0 or WREL0 is set to 1 IIC0 SCL0 ACKE0 H Transfer lines Wait from slave 430 SCL0 6 7 8 SDA0 D2 D1 D0 Wait from master 9 ACK Preliminary User's Manual U17260EJ3V1UD 1 2 3 D7 D6 D5 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-18. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IIC0 data write (cancel wait) IIC0 SCL0 6 7 8 9 1 2 3 Slave FFH is written to IIC0 or WREL0 is set to 1 IIC0 SCL0 ACKE0 H Wait from master and slave Transfer lines SCL0 6 7 8 9 SDA0 D2 D1 D0 ACK Wait from slave 1 D7 2 3 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0: Bit 2 of IIC control register 0 (IICC0) WREL0: Bit 5 of IIC control register 0 (IICC0) A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0). Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0. The master device can also cancel the wait state via either of the following methods. * By setting bit 1 (STT0) of IICC0 to 1 * By setting bit 0 (SPT0) of IICC0 to 1 Preliminary User's Manual U17260EJ3V1UD 431 CHAPTER 17 SERIAL INTERFACE IIC0 17.5.7 Canceling wait The I2C usually cancels a wait state by the following processing. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note Note Master only When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed. To cancel a wait state and transmit data (including addresses), write the data to IIC0. To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control register 0 (IICC0) to 1. To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1. To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1. Execute the canceling processing only once for one wait state. If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0. In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted, so that the wait state can be canceled. If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of IICC0, so that the wait state can be canceled. 17.5.8 Interrupt request (INTIIC0) generation timing and wait control The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated and the corresponding wait control, as shown in Table 17-3. Table 17-3. INTIIC0 Generation Timing and Wait Control WTIM0 During Slave Device Operation Address 0 1 9 Notes 1, 2 9 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 Notes 1. The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (SVA0). At this point, ACK is generated regardless of the value set to IICC0's bit 2 (ACKE0). For a slave device that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. If the received address does not match the contents of slave address register 0 (SVA0) and extension code is not received, neither INTIIC0 nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 432 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIM0 bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * Writing data to IIC shift register 0 (IIC0) * Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) * Setting bit 1 (STT0) of IIC0 register (generating start condition)Note * Setting bit 0 (SPT0) of IIC0 register (generating stop condition) Note Note Master only. When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be determined prior to wait cancellation. (5) Stop condition detection INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1). 17.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received. 17.5.10 Error detection In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0 (IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. Preliminary User's Manual U17260EJ3V1UD 433 CHAPTER 17 SERIAL INTERFACE IIC0 17.5.11 Extension code (1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected. (2) If "11110xx0" is set to SVA0 by a 10-bit address transfer and "11110xx0" is transferred from the master device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXC0 = 1 * Seven bits of data match: Remark COI0 = 1 EXC0: Bit 5 of IIC status register 0 (IICS0) COI0: Bit 4 of IIC status register 0 (IICS0) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next communication operation. Table 17-4. Extension Code Bit Definitions 434 Slave Address R/W Bit Description 0000 000 0 General call address 0000 000 1 Start byte 0000 001 x C-BUS address 0000 010 x Address that is reserved for different bus format 1111 0XX x 10-bit slave address specification Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 17.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0) is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. For details of interrupt request timing, see 17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence. Remark STD0: Bit 1 of IIC status register 0 (IICS0) STT0: Bit 1 of IIC control register 0 (IICC0) Figure 17-19. Arbitration Timing Example Master 1 Hi-Z SCL0 Hi-Z SDA0 Master 2 Master 1 loses arbitration SCL0 SDA0 Transfer lines SCL0 SDA0 Preliminary User's Manual U17260EJ3V1UD 435 CHAPTER 17 SERIAL INTERFACE IIC0 Table 17-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer During address transmission Note 1 Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data transmission When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1) When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transfer Note 1 condition When stop condition is detected while attempting to generate a Note 2 When stop condition is generated (when SPIE0 = 1) restart condition When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transfer Note 1 condition When SCL0 is at low level while attempting to generate a restart condition Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM0 = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation. Remark SPIE0: Bit 4 of IIC control register 0 (IICC0) 17.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. 436 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 17.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1). If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to IIC0 before the stop condition is detected is invalid. When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. * If the bus has been released .........................................a start condition is generated * If the bus has not been released (standby mode) .........communication reservation Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0 (IICS0)) after STT0 is set to 1 and the wait time elapses. The wait periods, which should be set via software, are listed in Table 17-6. Table 17-6. Wait Periods CLX0 SMC0 CL01 CL00 Wait Period 0 0 0 0 46 clocks 0 0 0 1 86 clocks 0 0 1 0 172 clocks 0 0 1 1 34 clocks 0 1 0 0 30 clocks 0 1 0 1 0 1 1 0 60 clocks 0 1 1 1 12 clocks 1 1 0 0 18 clocks 1 1 0 1 1 1 1 0 36 clocks Figure 17-20 shows the communication reservation timing. Preliminary User's Manual U17260EJ3V1UD 437 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-20. Communication Reservation Timing Program processing Write to IIC0 STT0 = 1 CommuniHardware processing cation reservation SCL0 1 2 3 4 Set SPD0 and INTIIC0 5 6 7 8 9 Set STD0 1 2 3 4 5 6 SDA0 Generate by master device with bus mastership Remark IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0) STD0: Bit 1 of IIC status register 0 (IICS0) SPD0: Bit 0 of IIC status register 0 (IICS0) Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0 (IICC0) to 1 before a stop condition is detected. Figure 17-21. Timing for Accepting Communication Reservations SCL0 SDA0 STD0 SPD0 Standby mode Figure 17-22 shows the communication reservation protocol. 438 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-22. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note Yes MSTS0 = 0? Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait period set by software (see Table 18-6). Confirmation of communication reservation No (Generate start condition) Cancel communication reservation MOV IIC0, #xxH Clear user flag IIC0 write operation EI Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop condition interrupt request occurs. Remark STT0: Bit 1 of IIC control register 0 (IICC0) MSTS0: Bit 7 of IIC status register 0 (IICS0) IIC0: IIC shift register 0 (2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1) When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when bit 6 (LREL0) of IICC0 was set to 1) To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0). The time shown in Table 17-7 is required until STCF is set to 1 after setting STT0 = 1. Therefore, secure the time by software. Preliminary User's Manual U17260EJ3V1UD 439 CHAPTER 17 SERIAL INTERFACE IIC0 Table 17-7. Wait Periods CL01 CL00 Wait Period 0 0 6 clocks 0 1 6 clocks 1 0 12 clocks 1 1 3 clocks 17.5.15 Other cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. <1> Set IIC clock selection register 0 (IICCL0). <2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1. <3> Set bit 0 (SPT0) of IICC0 to 1. (2) When STCEN = 1 Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this interferes with other I2C communications. To avoid this, start I2C in the following sequence. <1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the stop condition is detected. <2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C. <3> Wait for detection of the start condition. <4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly disable detection. (4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0 once. 440 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is prohibited. (6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software. Preliminary User's Manual U17260EJ3V1UD 441 CHAPTER 17 SERIAL INTERFACE IIC0 17.5.16 Communication operations (1) Master operation (single-master system) Figure 17-23. Master Operation Flowchart (Single-Master System) START Initializing I2C busNote Initial setting Setting port Sets each pin in the I2C mode (see 17.3 (7) Port mode register 6 (PM6)). IICX0 0XH IICCL0 XXH Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN, IICRSV = 0 Sets a start condition. IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 STCEN = 1? No SPT0 = 1 Yes STT0 = 1 Prepares for starting communication (generates a start condition). Writing IIC0 Starts communication (specifies an address and transfer direction). INTIIC0 interrupt occurs? No Waits for detection of acknowledge. INTIIC0 Interrupt occurs? Yes Prepares for starting communication (generates a stop condition). No Waits for detection of the stop condition. Yes No ACKD0 = 1? Communication processing Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Writing IIC0 INTIIC0 interrupt occurs? Starts transmission. No Waits for data transmission. WREL0 = 1 INTIIC0 interrupt occurs? Yes Yes ACKD0 = 1? No Starts reception. No Waits for data reception. Reading IIC0 Yes No End of transfer? No End of transfer? Yes Yes Restart? Yes ACKE0 = 0 WTIM0 = WREL0 = 1 No SPT0 = 1 INTIIC0 interrupt occurs? Yes No Waits for detection of acknowledge. END 2 Note Release (SCL0 and SDA0 pins = high level) the I C bus in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level. Remark 442 Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (2) Master operation (multi-master system) Figure 17-24. Master Operation Flowchart (Multi-Master System) (1/3) START Setting port Sets each pin in the I2C mode (see 17.3 (7) Port mode register 6 (PM6)). IICX0 0XH IICCL0 XXH Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN and IICRSV Sets a start condition. Initial setting IICC0 XXH ACKE0 = WTIM0 = SPIE0 = 1 IICE0 = 1 Checking bus statusNote Releases the bus for a specific period. Bus status is being checked. No No STCEN = 1? INTIIC0 interrupt occurs? Prepares for starting communication (generates a stop condition). SPT0 = 1 Yes Yes SPD0 = 1? INTIIC0 interrupt occurs? No Yes Yes Slave operation SPD0 = 1? No Waits for detection of the stop condition. No Yes 1 Waits for a communication Slave operation * Waiting to be specified as a slave by other master * Waiting for a communication start request (depends on user program) Master operation starts? No (No communication start request) Yes (Communication start request) SPIE0 = 0 INTIIC0 interrupt occurs? SPIE0 = 1 No Waits for a communication request. Yes IICRSV = 0? No Slave operation Yes A B Enables reserving Disables reserving communication. communication. Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and SDA0 pins = high level) in conformance with the specifications of the product that is communicating. Preliminary User's Manual U17260EJ3V1UD 443 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-24. Master Operation Flowchart (Multi-Master System) (2/3) A Enables reserving communication. STT0 = 1 Secure wait time by software (see Table 17-6). Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIIC0 interrupt occurs? Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function. EXC0 = 1 or COI0 =1? Yes C Slave operation B Disables reserving communication. IICBSY = 0? No Yes D Communication processing No Waits for bus release (communication being reserved). STT0 = 1 Wait STCF = 0? Yes Prepares for starting communication (generates a start condition). Secure wait time by software (see Table 18-7). No INTIIC0 interrupt occurs? No Waits for bus release Yes C EXC0 = 1 or COI0 =1? No Detects a stop condition. Yes Slave operation 444 Preliminary User's Manual U17260EJ3V1UD D CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-24. Master Operation Flowchart (Multi-Master System) (3/3) C Writing IIC0 INTIIC0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IIC0 Starts transmission. INTIIC0 interrupt occurs? INTIIC0 interrupt occurs? No Waits for data transmission. MSTS0 = 1? No No Yes Yes ACKD0 = 1? No Waits for data reception. Yes Yes MSTS0 = 1? Starts reception. 2 Reading IIC0 2 No Transfer end? No Yes Yes No WTIM0 = WREL0 = 1 ACKE0 = 0 Transfer end? Yes Restart? INTIIC0 interrupt occurs? No No Waits for detection of ACK. Yes SPT0 = 1 Yes MSTS0 = 1? STT0 = 1 END Yes No 2 Communication processing C 2 EXC0 = 1 or COI0 = 1? Yes Slave operation No 1 Does not participate in communication. Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIIC0 has occurred to check the arbitration result. 3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0 registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed next. Preliminary User's Manual U17260EJ3V1UD 445 CHAPTER 17 SERIAL INTERFACE IIC0 (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication. It is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. INTIIC0 Flag Interrupt servicing Setting Main processing IIC0 Data Setting Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIIC0. <1> Communication mode flag This flag indicates the following two communication statuses. * Clear mode: Status in which data communication is not performed * Communication mode: Status in which data communication is performed (from valid address detection to stop condition detection, no detection of ACK from master, address mismatch) <2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> Communication direction flag This flag indicates the direction of communication. Its value is the same as TRC0. 446 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way. Figure 17-25. Slave Operation Flowchart (1) START IICX0 0XH Selects a transfer clock. IICCL0 XXH SVA0 XXH Sets a local address. IICF0 0XH Setting IICRSV Sets a start condition. IICC0 XXH ACKE0 = WTIM0 = 1 SPIE0 = 0, IICE0 = 1 No Communication mode flag = 1? Yes No Communication direction flag = 1? Yes WREL0 = 1 Starts transmission. Writing IIC0 No Communication mode flag = 1? Communication mode flag = 1? No Yes Yes No Starts reception. Communication direction flag = 1? Communication direction flag = 1? No Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes Reading IIC0 Clearing ready flag Yes Clearing ready flag ACKD0 = 1? No Clearing communication mode flag WREL0 = 1 Remark Conform to the specifications of the product that is in communication, regarding the transmission and reception formats. Preliminary User's Manual U17260EJ3V1UD 447 CHAPTER 17 SERIAL INTERFACE IIC0 An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state. Remark <1> to <3> above correspond to <1> to <3> in Figure 17-26 Slave Operation Flowchart (2). Figure 17-26. Slave Operation Flowchart (2) INTIIC0 generated Yes <1> Yes <2> SPD0 = 1? No STD0 = 1? No No <3> COI0 = 1? Yes Set ready flag Communication direction flag TRC0 Set communication mode flag Clear ready flag Interrupt servicing completed 448 Preliminary User's Manual U17260EJ3V1UD Clear communication direction flag, ready flag, and communication mode flag CHAPTER 17 SERIAL INTERFACE IIC0 17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below. Remark ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition Preliminary User's Manual U17260EJ3V1UD 449 CHAPTER 17 SERIAL INTERFACE IIC0 (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B 3: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 4: IICS0 = 1000xx00B (Sets SPT0 to 1)Note 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK 2 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B 3: IICS0 = 1000xx00B (Sets SPT0 to 1) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 450 Don't care Preliminary User's Manual U17260EJ3V1UD SP 3 4 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 1 3: IICS0 = 1000xx00B (Clears WTIM0 to 0Note 2, sets STT0 to 1) 4: IICS0 = 1000x110B 5: IICS0 = 1000x000B (Sets WTIM0 to 1)Note 3 6: IICS0 = 1000xx00B (Sets SPT0 to 1) 7: IICS0 = 00000001B Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. 2. Clear WTIM0 to 0 to restore the original setting. 3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST SPT0 = 1 AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 1000x110B 4: IICS0 = 1000xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 451 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1010x110B 2: IICS0 = 1010x000B 3: IICS0 = 1010x000B (Sets WTIM0 to 1)Note 4: IICS0 = 1010xx00B (Sets SPT0 to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK 2 1: IICS0 = 1010x110B 2: IICS0 = 1010x100B 3: IICS0 = 1010xx00B (Sets SPT0 to 1) 4: IICS0 = 00001001B Remark : Always generated : Generated only when SPIE0 = 1 x: 452 Don't care Preliminary User's Manual U17260EJ3V1UD SP 3 4 CHAPTER 17 SERIAL INTERFACE IIC0 (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 453 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST AD6 to AD0 R/W ACK 2 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0001x110B 4: IICS0 = 0001xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 454 Don't care Preliminary User's Manual U17260EJ3V1UD D7 to D0 3 ACK SP 4 5 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 4 ACK SP 5 6 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0010x010B 4: IICS0 = 0010x110B 5: IICS0 = 0010xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 455 CHAPTER 17 SERIAL INTERFACE IIC0 (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST AD6 to AD0 R/W ACK 2 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 456 Don't care Preliminary User's Manual U17260EJ3V1UD D7 to D0 3 ACK SP 4 CHAPTER 17 SERIAL INTERFACE IIC0 (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 2 ACK D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 457 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0001x110B 5: IICS0 = 0001xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 458 Don't care Preliminary User's Manual U17260EJ3V1UD D7 to D0 4 ACK SP 5 6 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 4 D7 to D0 5 ACK SP 6 7 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0010x010B 5: IICS0 = 0010x110B 6: IICS0 = 0010xx00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 459 CHAPTER 17 SERIAL INTERFACE IIC0 (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 00100010B 2: IICS0 = 00100000B 3: IICS0 = 00000110B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST AD6 to AD0 R/W ACK 3 1: IICS0 = 00100010B 2: IICS0 = 00100110B 3: IICS0 = 00100x00B 4: IICS0 = 00000110B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 460 Don't care Preliminary User's Manual U17260EJ3V1UD D7 to D0 4 ACK SP 5 CHAPTER 17 SERIAL INTERFACE IIC0 (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 461 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 1: IICS0 = 0110x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 462 Don't care Preliminary User's Manual U17260EJ3V1UD SP 4 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0110x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1) ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK 1 SP 2 1: IICS0 = 01000110B 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 Preliminary User's Manual U17260EJ3V1UD 463 CHAPTER 17 SERIAL INTERFACE IIC0 (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICS0 = 0110x010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK 2 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 464 Preliminary User's Manual U17260EJ3V1UD SP 3 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 D7 to D0 2 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01000110B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 Preliminary User's Manual U17260EJ3V1UD 465 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 1: IICS0 = 1000x110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 466 Preliminary User's Manual U17260EJ3V1UD D7 to D0 ACK SP 3 CHAPTER 17 SERIAL INTERFACE IIC0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets STT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 467 CHAPTER 17 SERIAL INTERFACE IIC0 (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000xx00B (Sets STT0 to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets STT0 to 1) 3: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: 468 Don't care Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets WTIM0 to 1) 3: IICS0 = 1000x100B (Clears WTIM0 to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets SPT0 to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care Preliminary User's Manual U17260EJ3V1UD 469 CHAPTER 17 SERIAL INTERFACE IIC0 17.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figures 17-27 and 17-28 show timing charts of the data communication. IIC shift register 0 (IIC0)'s shift operation is synchronized with the falling edge of the serial clock (SCL0). The transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin. Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0. 470 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 address IIC0 IIC0 data ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 STT0 SPT0 L WREL0 L INTIIC0 TRC0 H Transmit Transfer lines 1 SCL0 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0 8 9 1 2 3 4 W ACK D7 D6 D5 D4 Start condition Processing by slave device IIC0 FFH Note IIC0 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Note WREL0 INTIIC0 (When EXC0 = 1) TRC0 L Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. Preliminary User's Manual U17260EJ3V1UD 471 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IIC0 data IIC0 IIC0 data ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 H STT0 L SPT0 L WREL0 L INTIIC0 TRC0 H Transmit Transfer lines SCL0 8 9 1 2 3 4 5 6 7 8 9 SDA0 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 D7 D6 D5 Processing by slave device IIC0 FFH Note IIC0 IIC0 FFH Note ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Note WREL0 Note INTIIC0 TRC0 L Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. 472 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IIC0 data IIC0 IIC0 address ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 STT0 SPT0 WREL0 L INTIIC0 (When SPIE0 = 1) TRC0 H Transmit Transfer lines SCL0 1 2 3 4 5 6 7 8 9 SDA0 D7 D6 D5 D4 D3 D2 D1 D0 ACK IIC0 FFH Note 2 AD6 AD5 Stop condition Processing by slave device IIC0 1 Start condition IIC0 FFH Note ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L Note WREL0 Note INTIIC0 (When SPIE0 = 1) TRC0 L Receive Note To cancel slave wait, write "FFH" to IIC0 or set WREL0. Preliminary User's Manual U17260EJ3V1UD 473 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device IIC0 address IIC0 IIC0 FFH Note ACKD0 STD0 SPD0 WTIM0 L ACKE0 H MSTS0 STT0 L SPT0 Note WREL0 INTIIC0 TRC0 Transfer lines 1 SCL0 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0 8 9 R ACK 1 D7 2 3 4 5 6 D6 D5 D4 D3 D2 Start condition Processing by slave device IIC0 data IIC0 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 L INTIIC0 TRC0 Note To cancel master wait, write "FFH" to IIC0 or set WREL0. 474 Preliminary User's Manual U17260EJ3V1UD CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IIC0 FFH Note IIC0 IIC0 FFH Note ACKD0 STD0 L SPD0 L WTIM0 L ACKE0 H MSTS0 H STT0 L SPT0 L Note WREL0 Note INTIIC0 L Receive TRC0 Transfer lines SCL0 8 9 SDA0 D0 ACK 1 D7 2 3 4 5 6 7 8 9 D6 D5 D4 D3 D2 D1 D0 ACK 1 D7 2 3 D6 D5 Processing by slave device IIC0 data IIC0 IIC0 data ACKD0 STD0 L SPD0 L WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 L INTIIC0 TRC0 H Transmit Note To cancel master wait, write "FFH" to IIC0 or set WREL0. Preliminary User's Manual U17260EJ3V1UD 475 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device IIC0 address IIC0 FFH Note IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 Note WREL0 INTIIC0 (When SPIE0 = 1) TRC0 Transfer lines SCL0 1 2 3 4 5 6 7 8 SDA0 D7 D6 D5 D4 D3 D2 D1 D0 9 1 AD6 NACK Stop condition Start condition Processing by slave device IIC0 data IIC0 ACKD0 STD0 SPD0 WTIM0 H ACKE0 H MSTS0 L STT0 L SPT0 L WREL0 INTIIC0 (When SPIE0 = 1) TRC0 Note To cancel master wait, write "FFH" to IIC0 or set WREL0. 476 Preliminary User's Manual U17260EJ3V1UD CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) Only for the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D, the multiplier/divider is provided. 18.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. * 16 bits x 16 bits = 32 bits (multiplication) * 32 bits / 16 bits = 32 bits, 16-bit remainder (division) 18.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 18-1. Configuration of Multiplier/Divider Item Registers Configuration Remainder data register 0 (SDR0) Multiplication/division data registers A0 (MDA0H, MDA0L) Multiplication/division data registers B0 (MDB0) Control register Multiplier/divider control register 0 (DMUC0) Figure 18-1 shows the block diagram of the multiplier/divider. Preliminary User's Manual U17260EJ3V1UD 477 478 Figure 18-1. Block Diagram of Multiplier/Divider Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 (MDB0 (MDB0H + MDB0L) Remainder data register 0 (SDR0 (SDR0H + SDR0L) Multiplication/division data register A0 (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) DMUSEL0 DMUE Start Preliminary User's Manual U17260EJ3V1UD MDA000 INTDMU Clear Controller Controller 17-bit adder Controller 6-bit counter CPU clock CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) Internal bus CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation sets SDR0 to 0000H. Figure 18-2. Format of Remainder Data Register 0 (SDR0) Address: FF60H, FF61H After reset: 0000H Symbol SDR0 R FF61H (SDR0H) FF60H (SDR0L) SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR SDR 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. 2. SDR0 is reset when the operation is started (when DMUE is set to 1). (2) Multiplication/division data register A0 (MDA0H, MDA0L) MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L). Figure 18-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) Address: FF62H, FF63H, FF64H, FF65H Symbol MDA0H R/W FF65H (MDA0HH) FF64H (MDA0HL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 031 030 Symbol MDA0L After reset: 0000H, 0000H 029 028 027 026 025 024 023 022 FF63H (MDA0LH) 021 020 019 018 017 016 FF62H (MDA0LL) MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA MDA 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when multiplier/divider control register 0 (DMUC0) is set to 81H). 2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed. Preliminary User's Manual U17260EJ3V1UD 479 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) The functions of MDA0 when an operation is executed are shown in the table below. Table 18-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result 0 Division mode Dividend Division result (quotient) 1 Multiplication mode Higher 16 bits: 0, Lower 16 bits: Multiplier A Multiplication result (product) The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDA0 (bits 15 to 0) x MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) * Register configuration during division <Dividend> <Divisor> <Quotient> <Remainder> MDA0 (bits 31 to 0) / MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) ... SDR0 (bits 15 to 0) MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is set to 1. MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears MDA0H and MDA0L to 0000H. (3) Multiplication/division data register B0 (MDB0) MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the division mode. MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation sets MDB0 to 0000H. Figure 18-4. Format of Multiplication/Division Data Register B0 (MDB0) Address: FF66H, FF67H After reset: 0000H Symbol MDB0 R/W FF67H (MDB0H) FF66H (MDB0L) MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB MDB 015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000 Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed, but the result is undefined. 2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored in MDA0 and SDR0. 480 Preliminary User's Manual U17260EJ3V1UD CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets DMUC0 to 00H. Figure 18-5. Format of Multiplier/Divider Control Register 0 (DMUC0) Address: FF68H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 DMUC0 DMUE 0 0 0 0 0 0 DMUSEL0 DMUENote Operation start/stop 0 Stops operation 1 Starts operation DMUSEL0 Operation mode (multiplication/division) selection 0 Division mode 1 Multiplication mode Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is complete. Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result is not guaranteed. If the operation is completed while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is changed, undefined operation results are stored in multiplication/division data register A0 (MDA0) and remainder data register 0 (SDR0). 3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation processing is stopped. To execute the operation again, set multiplication/division data register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the operation (by setting DMUE to 1). Preliminary User's Manual U17260EJ3V1UD 481 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.4 Operations of Multiplier/Divider 18.4.1 Multiplication operation * Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. * During operation 3. The operation will be completed when 16 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The operation result data is stored in the MDA0L and MDA0H registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. 482 Preliminary User's Manual U17260EJ3V1UD Figure 18-6. Timing Chart of Multiplication Operation (00DAH x 0093H) DMUE DMUSEL0 Preliminary User's Manual U17260EJ3V1UD Internal clock 0 Counter XXXX SDR0 MDA0 XXXX XXXX MDB0 XXXX INTDMU XXXX 00DA 0093 1 2 3 4 5 6 7 8 9 A B C D E F 10 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00DA 0000 0049 0024 005B 0077 003B 0067 007D 003E 001F 000F 0007 0003 0001 0000 0000 006D 8036 C01B E00D 7006 B803 5C01 2E00 9700 4B80 A5C0 D2E0 E970 F4B8 FA5C 7D2E 0 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) Operation clock 483 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.4.2 Division operation * Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start. * During operation 3. The operation will be completed when 32 internal clocks have been issued after the start of the operation (intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during operation, and therefore the read values of these registers are not guaranteed). * End of operation 4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers. 5. DMUE is cleared to 0 (end of operation). 6. After the operation, an interrupt request signal (INTDMU) is generated. * Next operation 7. To execute multiplication next, start from the initial setting in 18.4.1 Multiplication operation. 8. To execute division next, start from the initial setting in 18.4.2 Division operation. 484 Preliminary User's Manual U17260EJ3V1UD Figure 18-7. Timing Chart of Division Operation (DCBA2586H / 0018H) DMUE DMUSEL0 "0" Preliminary User's Manual U17260EJ3V1UD Internal clock 0 Counter XXXX SDR0 0000 MDA0 XXXX XXXX DCBA 2586 MDB0 XXXX 0018 INTDMU 1 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 4B0C 0C12 64D8 72E8 9618 E5D1 CBA2 2C30 5860 9744 B0C1 2E89 6182 5D12 C304 BA25 8609 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D 0932 6C3A 0 CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) Operation clock 485 CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored interrupt servicing. For the priority order, see Table 19-1. A standby release signal is generated and STOP and HALT modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. * PD78F0531, 78F0532, 78F0533 External: 9, internal: 16 * PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D External: 9, internal: 19 (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 19.2 Interrupt Sources and Configuration The PD78F0531, 78F0532, and 78F0533 have a total of 26 interrupt sources, and the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D have a total of 29 interrupt sources, including maskable interrupts and software interrupts. In addition, they also have up to four reset sources (see Table 19-1). 486 Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Note 1 Type Priority Name Trigger Internal/ Vector Basic External Table Configuration Address Maskable Note 3 Type Note 2 0 INTLVI Low-voltage detection Internal 0004H (A) 1 INTP0 Pin input edge detection External 0006H (B) 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTP4 000EH 6 INTP5 0010H 7 INTSRE6 UART6 reception error generation 8 INTSR6 End of UART6 reception 0014H Internal 0012H 9 INTST6 End of UART6 transmission 0016H 10 INTCSI10/ End of CSI10 communication/end of UART0 0018H INTST0 transmission INTTMH1 Match between TMH1 and CMP01 11 (A) 001AH (when compare register is specified) 12 INTTMH0 Match between TMH0 and CMP00 001CH (when compare register is specified) 13 INTTM50 Match between TM50 and CR50 001EH (when compare register is specified) 14 INTTM000 Match between TM00 and CR000 0020H (when compare register is specified), TI010 pin valid edge detection (when capture register is specified) 15 INTTM010 Match between TM00 and CR010 0022H (when compare register is specified), TI000 pin valid edge detection (when capture register is specified) 16 INTAD End of A/D conversion 0024H 17 INTSR0 End of UART0 reception or reception error 0026H generation 18 INTWTI Watch timer reference time interval signal 0028H 19 INTTM51 Match between TM51 and CR51 002AH (when compare register is specified) Notes 1. 20 INTKR Key interrupt detection External 002CH (C) 21 INTWT Watch timer overflow Internal 002EH (A) 22 INTP6 Pin input edge detection External 0030H (B) 23 INTP7 0032H The default priority determines the sequence of processing vectored interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 27 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. 3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0. Preliminary User's Manual U17260EJ3V1UD 487 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Note 1 Type Priority Name Trigger Internal/ Vector Basic External Table Configuration Address Maskable 24 End of IIC0 communication/end of INTIIC0/ Note 3 INTDMU Internal 0034H End of CSI11 communication 0036H Note 3 Match between TM01 and CR001 0038H INTCSI11 26 INTTM001 Note 2 (A) multiply/divide operation Note 3 25 Type (when compare register is specified), TI011 pin valid edge detection (when capture register is specified) 27 Note 3 INTTM011 Match between TM01 and CR011 003AH (when compare register is specified), TI001 pin valid edge detection (when capture register is specified) Software - BRK BRK instruction execution - 003EH (D) Reset - RESET Reset input - 0000H - POC Power-on clear LVI Low-voltage detection WDT WDT overflow Notes 1. Note 4 The default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 27 is the lowest. 2. 3. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1. The interrupt sources INTDMU, INTCSI11, INTTM001, and INTTM011 are available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 4. 488 When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1. Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Priority controller IF Vector table address generator Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Interrupt request Edge detector MK IF IE PR ISP Priority controller Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag Preliminary User's Manual U17260EJ3V1UD 489 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus MK Interrupt request Key interrupt detector IF IE PR ISP Priority controller Vector table address generator 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt request IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag Priority controller KRM: Key return mode register 490 Preliminary User's Manual U17260EJ3V1UD Vector table address generator CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) * Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) * Priority specification flag register (PR0L, PR0H, PR1L, PR1H) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Program status word (PSW) Table 19-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Preliminary User's Manual U17260EJ3V1UD 491 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Source Interrupt Mask Flag Register IF0L Priority Specification Flag Register INTLVI LVIIF INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTSRE6 SREIF6 SREMK6 SREPR6 INTSR6 SRIF6 INTST6 STIF6 IF0H INTCSI10 CSIIF10 LVIMK MK0L Register SRMK6 MK0H STMK6 DUALIF0 LVIPR PR0L SRPR6 PR0H STPR6 DUALMK0 CSIMK10 Note 1 DUALPR0 CSIPR10 Note 2 Note 2 INTST0 STIF0 STMK0 STPR0 INTTMH1 TMIFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 INTAD ADIF INTSR0 SRIF0 SRMK0 SRPR0 INTWTI WTIIF WTIMK WTIPR INTTM51 TMIF51 TMMK51 TMPR51 INTKR KRIF KRMK KRPR INTWT WTIF WTMK WTPR INTP6 PIF6 PMK6 PPR6 INTP7 PIF7 INTIIC0 IICIF0 Note 3 DMUIF Note 3 ADMK TMPR010 MK1L PMK7 IF1H Note 3 INTDMU INTCSI11 TMMK010 IF1L Note 3 CSIIF11 PR1L PPR7 IICMK0 DMUMK ADPR MK1H Note 3 CSIMK11 Note 3 IICPR0 PR1H Note 3 DMUPR CSIPR11 Note 3 INTTM001 Note 3 TMIF001 Note 3 TMMK001 Note 3 TMPR001 Note 3 INTTM011 Note 3 TMIF011 Note 3 TMMK011 Note 3 TMPR011 Note 3 Notes 1. 492 If either interrupt source INTCSI10 or INTST0 is generated, these flags are set (1). 2. Both interrupt sources INTCSI10 and INTST0 are supported. 3. PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 19-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) Address: FFE0H After reset: 00H R/W Symbol IF0L <7> <6> <5> <4> <3> <2> <1> <0> SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H Symbol IF0H After reset: 00H R/W <7> <6> <5> <4> <3> <2> <1> <0> TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 CSIIF10 STIF0 Address: FFE2H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF 5 4 <3> <2> <1> <0> Address: FFE3H Symbol IF1H After reset: 00H 7 0 6 0 R/W 0 0 TMIF011 Note TMIF001 Note Note CSIIF11 IICIF0 DMUIF XXIFX Note Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Cautions 1. Be sure to clear bits 1 to 7 of IF1H to 0 for the PD78F0531, 78F0532, and 78F0533. Be sure to clear bits 4 to 7 of IF1H to 0 for the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 2. When operating a timer, serial interface, or A/D converter after standby release, operate it once after clearing the interrupt request flag. An interrupt request flag may be set by noise. Preliminary User's Manual U17260EJ3V1UD 493 CHAPTER 19 INTERRUPT FUNCTIONS Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. 494 Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 19-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) Address: FFE4H Symbol MK0L After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 CSIMK0 STMK0 Address: FFE6H Symbol MK1L Address: FFE7H Symbol MK1H After reset: FFH R/W <7> <6> <5> <4> <3> <2> <1> <0> PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK 4 <3> <2> <1> <0> After reset: FFH 7 1 6 1 R/W 5 1 1 TMMK011 Note TMMK001 Note CSIMK11 Note IICMK0 DMUMK XXMKX Note Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Caution Be sure to set bits 1 to 7 of MK1H to 1 for the PD78F0531, 78F0532, and 78F0533. Be sure to set bits 4 to 7 of MK1H to 1 for the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. Preliminary User's Manual U17260EJ3V1UD 495 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 19-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) Address: FFE8H After reset: FFH Symbol PR0L <7> <6> <5> <4> <3> <2> <1> <0> SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H After reset: FFH Symbol PR0H R/W R/W <7> <6> <5> <4> <3> <2> <1> <0> TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 CSIPR10 STPR0 Address: FFEAH Symbol PR1L PR1H R/W <7> <6> <5> <4> <3> <2> <1> <0> PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR 4 <3> <2> <1> <0> Address: FFEBH Symbol After reset: FFH After reset: FFH 7 1 R/W 6 5 1 1 1 TMPR011 Note TMPR001 Note CSIPR11 Note IICPR0 Note DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Caution Be sure to set bits 1 to 7 of PR1H to 1 for the PD78F0531, 78F0532, and 78F0533. Be sure to set bits 4 to 7 of PR1H to 1 for the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 496 Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP) and External Interrupt Falling Edge Enable Register (EGN) Address: FF48H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 EGP R/W Address: FF49H After reset: 00H Symbol 7 6 5 4 3 2 1 0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges EGN R/W INTPn pin valid edge selection (n = 0 to 7) Table 19-3 shows the ports corresponding to EGPn and EGNn. Table 19-3. Ports Corresponding to EGPn and EGNn Detection Enable Register Edge Detection Port Interrupt Request Signal EGP0 EGN0 P120 INTP0 EGP1 EGN1 P30 INTP1 EGP2 EGN2 P31 INTP2 EGP3 EGN3 P32 INTP3 EGP4 EGN4 P33 INTP4 EGP5 EGN5 P16 INTP5 EGP6 EGN6 P140 INTP6 EGP7 EGN7 P141 INTP7 Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port function. Remark n = 0 to 7 Preliminary User's Manual U17260EJ3V1UD 497 CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 19-6. Format of Program Status Word PSW <7> <6> <5> <4> <3> 2 <1> 0 After reset IE Z RBS1 AC RBS0 0 ISP CY 02H Used when normal instruction is executed ISP 498 Priority of interrupt currently being serviced 0 High-priority interrupt servicing (low-priority interrupt disabled) 1 Interrupt request not acknowledged, or lowpriority interrupt servicing (all maskable interrupts enabled) IE Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 19-4 below. For the interrupt request acknowledgement timing, see Figures 19-8 and 19-9. Table 19-4. Time from Generation of Maskable Interrupt Until Servicing Minimum Time Note Maximum Time When xxPR = 0 7 clocks 32 clocks When xxPR = 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 19-7 shows the interrupt request acknowledgement algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. Preliminary User's Manual U17260EJ3V1UD 499 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Interrupt Request Acknowledgement Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending Any high-priority interrupt request among those simultaneously generated with xxPR = 0? No No IE = 1? Yes Interrupt request held pending No Vectored interrupt servicing Interrupt request held pending Any high-priority interrupt request among those simultaneously generated? No IE = 1? Yes ISP = 1? Yes Yes Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR: Priority specification flag IE: Flag that controls acknowledgement of maskable interrupt request (1 = Enable, 0 = Disable) ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) 500 Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 19-9. Interrupt Request Acknowledgement Timing (Maximum Time) CPU processing Instruction 25 clocks 6 clocks Divide instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) 19.4.2 Software interrupt request acknowledgement A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH, 003FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. Preliminary User's Manual U17260EJ3V1UD 501 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 19-10 shows multiple interrupt servicing examples. Table 19-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request PR = 0 IE = 1 IE = 0 IE = 1 IE = 0 ISP = 0 { x x x { ISP = 1 { x { x { { x { x { Software interrupt Remarks 1. Interrupt PR = 1 Request Interrupt Being Serviced Maskable interrupt Software Maskable Interrupt Request : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced. ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0: Interrupt request acknowledgement is disabled. IE = 1: Interrupt request acknowledgement is enabled. 4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H. PR = 0: Higher priority level PR = 1: Lower priority level 502 Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 RETI IE = 1 RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing IE = 0 EI EI INTxx (PR = 0) INTyy (PR = 1) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled Preliminary User's Manual U17260EJ3V1UD 503 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 EI INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0: Higher priority level IE = 0: 504 Interrupt request acknowledgement disabled Preliminary User's Manual U17260EJ3V1UD CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW. bit, CY * MOV1 CY, PSW. bit * AND1 CY, PSW. bit * OR1 CY, PSW. bit * XOR1 CY, PSW. bit * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW. bit, $addr16 * BF PSW. bit, $addr16 * BTCLR PSW. bit, $addr16 * EI * DI * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and PR1H registers. Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. Figure 19-11 shows the timing at which interrupt requests are held pending. Figure 19-11. Interrupt Request Hold CPU processing Instruction N Instruction M PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). Preliminary User's Manual U17260EJ3V1UD 505 CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 20-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0 Controls KR0 signal in 1-bit units. KRM1 Controls KR1 signal in 1-bit units. KRM2 Controls KR2 signal in 1-bit units. KRM3 Controls KR3 signal in 1-bit units. KRM4 Controls KR4 signal in 1-bit units. KRM5 Controls KR5 signal in 1-bit units. KRM6 Controls KR6 signal in 1-bit units. KRM7 Controls KR7 signal in 1-bit units. 20.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 20-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) Figure 20-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) 506 Preliminary User's Manual U17260EJ3V1UD CHAPTER 20 KEY INTERRUPT FUNCTION 20.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets KRM to 00H. Figure 20-2. Format of Key Return Mode Register (KRM) Address: FF6EH Symbol KRM After reset: 00H R/W 7 6 5 4 3 2 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRMn 0 KRM1 KRM0 Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the corresponding pull-up resistor register 7 (PU7) to 1. 2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and then change the KRM register. Clear the interrupt request flag and enable interrupts. 3. The bits not used in the key interrupt mode can be used as normal ports. Preliminary User's Manual U17260EJ3V1UD 507 CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with main system clock before executing STOP instruction. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. 21.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark 508 For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR. Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 21-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 fX = 20 MHz 11 204.8 s min. 102.4 s min. 13 819.2 s min. 409.6 s min. 14 1.64 ms min. 819.2 s min. 15 3.27 ms min. 1.64 ms min. 16 6.55 ms min. 3.27 ms min. 2 /fX min. 2 /fX min. 2 /fX min. 1 1 1 1 0 2 /fX min. 1 1 1 1 1 2 /fX min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency Preliminary User's Manual U17260EJ3V1UD 509 CHAPTER 21 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released. When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 0 1 1 204.8 s 102.4 s 13 819.2 s 409.6 s 14 1.64 ms 819.2 s 15 3.27 ms 1.64 ms 16 6.55 ms 3.27 ms 2 /fX 0 2 /fX 0 1 1 2 /fX 1 0 0 2 /fX 1 0 1 2 /fX Other than above fX = 20 MHz 11 Setting prohibited Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark 510 fX: X1 clock oscillation frequency Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock. The operating statuses in the HALT mode are shown below. Preliminary User's Manual U17260EJ3V1UD 511 CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) Item System clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Clock supply to the CPU is stopped Main system clock Subsystem clock fRH Operation continues (cannot be stopped) Status before HALT mode was set is retained fX Status before HALT mode was set is retained Operation continues (cannot be stopped) fEXCLK Operates or stops by external clock input fXT Status before HALT mode was set is retained fEXCLKS Operates or stops by external clock input fRL Status before HALT mode was set is retained Operation continues (cannot be stopped) Status before HALT mode was set is retained CPU Operation stopped Flash memory Operation stopped RAM Status before HALT mode was set is retained Port (latch) Status before HALT mode was set is retained Operable 16-bit timer/event counter 00 8-bit timer/event counter 50 8-bit timer H0 01 Note 51 H1 Watch timer Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 Note IIC0 Multiplier/divider Note Power-on-clear function Low-voltage detection function External interrupt Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Remark fRH: Internal high-speed oscillation clock fX: X1 clock fEXCLK: External main system clock fXT: XT1 clock fEXCLKS: External subsystem clock fRL: 512 Internal low-speed oscillation clock Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (fXT) When CPU Is Operating on External Subsystem Clock (fEXCLKS) Item System clock Clock supply to the CPU is stopped fRH Main system clock Status before HALT mode was set is retained fX Subsystem clock fEXCLK Operates or stops by external clock input fXT Operation continues (cannot be stopped) Status before HALT mode was set is retained fEXCLKS Operates or stops by external clock input Operation continues (cannot be stopped) fRL Status before HALT mode was set is retained CPU Operation stopped Flash memory Operation stopped RAM Status before HALT mode was set is retained Port (latch) Status before HALT mode was set is retained 00 Note1 counter 01 Note1. 2 8-bit timer/event 50 Note1 counter 51 Note1 8-bit timer H0 16-bit timer/event Operable H1 Watch timer Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable Buzzer output Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped. A/D converter Serial interface UART0 Operable UART6 CSI10 Note1 CSI11 Note1, 2 IIC0 Multiplier/divider Note1 Note2 Power-on-clear function Low-voltage detection function External interrupt Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of these functions on the external clock input from peripheral hardware pins. 2. PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Remark fRH: Internal high-speed oscillation clock fX: X1 clock fEXCLK: External main system clock fXT: XT1 clock fEXCLKS: External subsystem clock fRL: Internal low-speed oscillation clock Preliminary User's Manual U17260EJ3V1UD 513 CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 21-3. HALT Mode Release by Interrupt Request Generation HALT instruction Interrupt request Wait Standby release signal Status of CPU Operating mode HALT mode Wait Operating mode Oscillation High-speed system clock, internal high-speed oscillation clock, or subsystem clock Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 8 or 9 clocks * When vectored interrupt servicing is not carried out: 2 or 3 clocks 514 Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock HALT instruction Reset signal Status of CPU High-speed system clock (X1 oscillation) Normal operation (high-speed system clock) HALT mode Reset Reset processing period (20 s (TYP.)) Normal operation (internal high-speed oscillation clock) Oscillation Oscillation stopped stopped Oscillates Oscillates Oscillation stabilization time (211/fX to 216/fX) Starting X1 oscillation is specified by software. (2) When internal high-speed oscillation clock is used as CPU clock HALT instruction Reset signal Normal operation (internal high-speed oscillation clock) Status of CPU Internal high-speed oscillation clock HALT mode Oscillates Reset Reset processing period (20 s (TYP.)) Oscillation stopped Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization (3) When subsystem clock is used as CPU clock HALT instruction Reset signal Status of CPU Subsystem clock (XT1 oscillation) Normal operation (subsystem clock) HALT mode Oscillates Reset Normal operation mode Reset processing (internal high-speed period (20 s (TYP.)) oscillation clock) Oscillation Oscillation stopped stopped Oscillates Starting XT1 oscillation is specified by software. Remark fX: X1 clock oscillation frequency Preliminary User's Manual U17260EJ3V1UD 515 CHAPTER 21 STANDBY FUNCTION Table 21-2. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing Interrupt servicing execution execution Reset 1 x x x HALT mode held - - x x Reset processing x: don't care 21.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the main system clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. The operating statuses in the STOP mode are shown below. 516 Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION Table 21-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on Internal High-Speed Oscillation Clock (fRH) Item System clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEXCLK) Clock supply to the CPU is stopped fRH Main system clock Stopped fX fEXCLK Subsystem clock Input invalid fXT Status before STOP mode was set is retained fEXCLKS Operates or stops by external clock input fRL Status before STOP mode was set is retained CPU Operation stopped Flash memory Operation stopped RAM Status before STOP mode was set is retained Port (latch) Status before STOP mode was set is retained Operation stopped 16-bit timer/event counter 00 8-bit timer/event counter 50 Operable only when TI50 is selected as the count clock 51 Operable only when TI51 is selected as the count clock 8-bit timer H0 Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter 50 operation H1 Operable only when fRL, fRL/2 , fRL/2 is selected as the count clock 01 Note 7 9 Watch timer Operable only when subsystem clock is selected as the count clock Watchdog timer Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be stopped by software" is set by option byte. Clock output Operable only when subsystem clock is selected as the count clock Buzzer output Operation stopped A/D converter Serial interface UART6 Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter 50 operation CSI10 Operable only when external clock is selected as the serial clock UART0 CSI11 Note IIC0 Note2 Multiplier/divider Operation stopped Power-on-clear function Operable Low-voltage detection function External interrupt Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Remark fRH: Internal high-speed oscillation clock fX: X1 clock fEXCLK: External main system clock fXT: XT1 clock fEXCLKS: External subsystem clock fRL: Internal low-speed oscillation clock Preliminary User's Manual U17260EJ3V1UD 517 CHAPTER 21 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. Even if "internal low-speed oscillator can be stopped by software" is selected by the option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set. To stop the internal low-speed oscillator's oscillation in the STOP mode, stop it by software and then execute the STOP instruction. 3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal high-speed oscillation clock before the next execution of the STOP instruction. Before changing the CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). 4. If the STOP instruction is executed with AMPH set to 1 when the internal high-speed oscillation clock or external main system clock is used as the CPU clock, the internal high-speed oscillation clock or external main system clock is supplied to the CPU 5 s (MIN.) after the STOP mode has been released. (2) STOP mode release Figure 21-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode High-speed system clock (X1 oscillation) Internal high-speed oscillation clock High-speed system clock (X1 oscillation) is selected as CPU clock when STOP instruction is executed Internal high-speed oscillation clock is selected as CPU clock when STOP instruction is executed Wait for oscillation accuracy stabilization HALT status (oscillation stabilization time set by OSTS) High-speed system clock Automatic selection Internal high-speed oscillation clock 5 s (TYP.) High-speed system clock Note Clock switched by software Note When AMPH = 1 The STOP mode can be released by the following two sources. 518 Preliminary User's Manual U17260EJ3V1UD CHAPTER 21 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 21-6. STOP Mode Release by Interrupt Request Generation (1) When high-speed system clock is used as CPU clock Wait (set by OSTS) STOP instruction Standby release signal Status of CPU High-speed system clock (X1 oscillation) Operating mode (high-speed system clock) Oscillation stabilization wait (HALT mode status) STOP mode Oscillation stopped Oscillates Operating mode (high-speed system clock) Oscillates Oscillation stabilization time (set by OSTS) (2) When internal high-speed oscillation clock is used as CPU clock STOP instruction Standby release signal Status of CPU Internal high-speed oscillation clock Normal operation (internal high-speed oscillation clock) STOP mode Normal operation (internal high-speed oscillation clock) Oscillates Oscillation stopped Oscillates Wait for oscillation accuracy stabilization Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. Preliminary User's Manual U17260EJ3V1UD 519 CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-7. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Reset signal Status of CPU STOP mode Reset Reset processing period (20 s (TYP.)) Normal operation (internal high-speed oscillation clock) Oscillation stopped Oscillation Oscillation stopped stopped Oscillates Normal operation (high-speed system clock) High-speed system clock (X1 oscillation) Oscillates Oscillation stabilization time (211/fX to 216/fX) Starting X1 oscillation is specified by software. (2) When internal high-speed oscillation clock is used as CPU clock STOP instruction Reset signal Status of CPU Internal high-speed oscillation clock Normal operation (internal high-speed oscillation clock) Reset Reset processing period (20 s (TYP.)) STOP mode Oscillation Oscillation stopped stopped Oscillates Normal operation (internal high-speed oscillation clock) Oscillates Wait for oscillation accuracy stabilization Remark fX: X1 clock oscillation frequency Table 21-4. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt MKxx PRxx IE ISP 0 0 0 x request Operation Next address instruction execution 0 0 1 x Interrupt servicing execution 0 1 0 1 Next address 0 1 x 0 instruction execution 0 1 1 1 Interrupt servicing execution Reset 1 x x x STOP mode held - - x x Reset processing x: don't care 520 Preliminary User's Manual U17260EJ3V1UD CHAPTER 22 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Tables 22-1 and 22-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a reset release, except for P130, which is low-level output. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-speed oscillation clock (see Figures 22-2 to 22-4) after reset processing. Reset by POC and LVI circuit power supply detection is automatically released when VDD VPOC or VDD VLVI after the reset, and program execution starts using the internal high-speed oscillation clock (see CHAPTER 23 POWER-ON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR) after reset processing. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating. External main system clock input and external subsystem clock input become invalid. 3. When the STOP mode is released by a reset, the STOP mode contents are held during reset input. However, the port pins become high-impedance, except for P130, which is set to lowlevel output. Preliminary User's Manual U17260EJ3V1UD 521 522 Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Set LVIRF Set Watchdog timer reset signal Clear Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2. LVIS: Low-voltage detection level selection register Reset signal CHAPTER 22 RESET FUNCTION Preliminary User's Manual U17260EJ3V1UD RESET Clear CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Reset period (oscillation stop) Normal operation Reset processing (20 s (TYP.)) Normal operation (internal high-speed oscillation clock) RESET Internal reset signal Delay Delay (5 s (TYP.)) Port pin (except P130) Hi-Z Port pin (P130) Note Note Set P130 to high-level output by software. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow Wait for oscillation accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Normal operation Reset period (oscillation stop) Reset processing (20 s (TYP.)) Normal operation (internal high-speed oscillation clock) Watchdog timer overflow Internal reset signal Port pin (except P130) Hi-Z Port pin (P130) Note Note Set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Preliminary User's Manual U17260EJ3V1UD 523 CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Normal operation Stop status (oscillation stop) Reset period (oscillation stop) Reset processing Normal operation (internal high-speed oscillation clock) (20 s (TYP.)) RESET Internal reset signal Delay Port pin (except P130) Delay (5 s (TYP.)) Port pin (P130) Hi-Z Note Note Set P130 to high-level output by software. Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. 2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 23 POWER-ON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR. 524 Preliminary User's Manual U17260EJ3V1UD CHAPTER 22 RESET FUNCTION Table 22-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Subsystem clock fRH Operation stopped fX Operation stopped (pin is I/O port mode) fEXCLK Clock input invalid (pin is I/O port mode) fXT Operation stopped (pin is I/O port mode) fEXCLKS Clock input invalid (pin is I/O port mode) Operation stopped fRL CPU Flash memory RAM Port (latch) Operation stopped 16-bit timer/event 00 counter 01 8-bit timer/event 50 counter 51 8-bit timer H0 Note H1 Watch timer Watchdog timer Clock output Buzzer output A/D converter Serial interface UART0 UART6 CSI10 CSI11 Note IIC0 Multiplier/divider Note Power-on-clear function Operable Low-voltage detection function Operation stopped External interrupt Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Remark fRH: Internal high-speed oscillation clock fX: X1 oscillation clock fEXCLK: External main system clock fXT: XT1 oscillation clock fEXCLKS: External subsystem clock fRL: Internal low-speed oscillation clock Preliminary User's Manual U17260EJ3V1UD 525 CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined Note 2 General-purpose registers Undefined Note 2 Port registers (P0 to P7, P12 to P14) (output latches) 00H Port mode registers (PM0 to PM7, PM12, PM14) FFH Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) 00H Internal expansion RAM size switching register (IXS) 0CH Internal memory size switching register (IMS) CFH Memory bank select register (BANK) 00H Note 3 Note 3 Clock operation mode select register (OSCCTL) 00H Processor clock control register (PCC) 01H Internal oscillation mode register (RCM) 80H Main OSC control register (MOC) 80H Main clock mode register (MCM) 00H Oscillation stabilization time counter status register (OSTC) 00H Oscillation stabilization time select register (OSTS) 05H 16-bit timer/event Note 4 counters 00, 0 Timer counters 00, 01 (TM00, TM01) 0000H Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) 0000H Mode control registers 00, 01 (TMC00, TMC01) 00H Prescaler mode registers 00, 01 (PRM00, PRM01) 00H Capture/compare control registers 00, 01 (CRC00, CRC01) 00H Timer output control registers 00, 01 (TOC00, TOC01) 00H Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. When a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. The initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all the 78K0/KE2 products, regardless of the internal memory capacity. Therefore, after a reset is released, be sure to set the following values for each product. Flash Memory Version (78K0/KE2) 4. IMS 04H PD78F0532 C6H PD78F0533 C8H PD78F0534 CCH 0AH PD78F0535 CFH 08H PD78F0536 CCH 04H PD78F0537, 78F0537D CCH 00H 0CH 16-bit timer/event counter 01 is available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 526 IXS PD78F0531 Preliminary User's Manual U17260EJ3V1UD CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Acknowledgment 8-bit timer/event counters 50, 51 8-bit timers H0, H1 Timer counters 50, 51 (TM50, TM51) 00H Compare registers 50, 51 (CR50, CR51) 00H Timer clock selection registers 50, 51 (TCL50, TCL51) 00H Mode control registers 50, 51 (TMC50, TMC51) 00H Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H Mode registers (TMHMD0, TMHMD1) 00H Note 2 Carrier control register 1 (TMCYC1) 00H Watch timer Operation mode register (WTM) 00H Clock output/buzzer output controller Clock output selection register (CKS) 00H Watchdog timer Enable register (WDTE) 1AH/9AH A/D converter 10-bit A/D conversion result register (ADCR) 0000H 8-bit A/D conversion result register (ADCRH) 00H Mode register (ADM) 00H Analog input channel specification register (ADS) 00H A/D port configuration register (ADPC) 00H Serial interface Receive buffer register 0 (RXB0) FFH UART0 Transmit shift register 0 (TXS0) FFH Asynchronous serial interface operation mode register 0 (ASIM0) 01H Asynchronous serial interface reception error status register 0 (ASIS0) 00H Baud rate generator control register 0 (BRGC0) 1FH Serial interface Receive buffer register 6 (RXB6) FFH UART6 Transmit buffer register 6 (TXB6) FFH Asynchronous serial interface operation mode register 6 (ASIM6) 01H Asynchronous serial interface reception error status register 6 (ASIS6) 00H Asynchronous serial interface transmission status register 6 (ASIF6) 00H Clock selection register 6 (CKSR6) 00H Baud rate generator control register 6 (BRGC6) FFH Asynchronous serial interface control register 6 (ASICL6) 16H Input switch control register (ISC) 00H Transmit buffer registers 10, 11 (SOTB10, SOTB11) 00H Serial I/O shift registers 10, 11 (SIO10, SIO11) 00H Serial operation mode registers 10, 11 (CSIM10, CSIM11) 00H Serial clock selection registers 10, 11 (CSIC10, CSIC11) 00H Serial interfaces CSI10, CSI1 Notes 1. Note 1 Note 3 Note 4 During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. 8-bit timer H1 only. 3. The reset value of WDTE is determined by the option byte setting. 4. Serial interface CSI11 is available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. Preliminary User's Manual U17260EJ3V1UD 527 CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (3/3) Status After Reset Hardware Acknowledgment Serial interface IIC0 Shift register 0 (IIC0) 00H Control register 0 (IICC0) 00H Slave address register 0 (SVA0) 00H Clock selection register 0 (IICCL0) 00H Function expansion register 0 (IICX0) 00H Status register 0 (IICS0) 00H Flag register 0 (IICF0) 00H Remainder data register 0 (SDR0) 0000H Multiplication/division data register A0 (MDA0H, MDA0L) 0000H Multiplication/division data register B0 (MDB0) 0000H Multiplier/divider control register 0 (DMUC0) 00H Key interrupt Key return mode register (KRM) 00H Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level selection register (LVIS) 00H Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) 00H Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H) FFH Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, FFH Multiplier/divider Note 2 Interrupt Note 1 Note 3 Note 3 Note 3 PR1H) Notes 1. External interrupt rising edge enable register (EGP) 00H External interrupt falling edge enable register (EGN) 00H During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. Multiplier/divider is available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D. 3. These values vary depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register RESF WDTRF bit Cleared (0) Cleared (0) LVIRF bit LVIM Cleared (00H) Cleared (00H) Set (1) Held Held Set (1) Cleared (00H) Held LVIS 528 Preliminary User's Manual U17260EJ3V1UD CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KE2. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 22-5. Format of Reset Control Flag Register (RESF) Address: FFACH After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 22-3. Table 22-3. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Flag WDTRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Set (1) Preliminary User's Manual U17260EJ3V1UD 529 CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage (VDD) exceeds 1.59 V 0.15 V. In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply voltage (VDD) exceeds 2.7 V 0.2 V. * Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V), generates internal reset signal when VDD < VPOC, and releases reset when VDD VPOC. Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 22 RESET FUNCTION. 530 Preliminary User's Manual U17260EJ3V1UD CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 23-1. Figure 23-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Reference voltage source 23.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPOC = 1.59 V 0.15 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VPOC. (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VDDPOC = 2.7 V 0.2 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPOC = 1.59 V 0.15 V) are compared. When VDD < VPOC, the internal reset signal is generated. It is released when VDD VPOC. The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. Preliminary User's Manual U17260EJ3V1UD 531 CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset VLVI Supply voltage (VDD) 1.8 VNote 1 VPOC = 1.59 V (TYP.) 0.5 V/ms (MAX.) Note 2 0V Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Internal high-speed oscillation clock (fRH) Starting oscillation is specified by software. Starting oscillation is specified by software. High-speed system clock (fXH) (when X1 oscillation is selected) Operation CPU stops Wait for voltage stabilization (3.24 ms (TYP.)) Normal operation Reset period (internal high-speed (oscillation oscillation clock)Note 3 stop) Reset processing (20 s (TYP.)) Starting oscillation is specified by software. Normal operation Reset period Wait for voltage stabilization (internal high-speed (oscillation (3.24 ms (TYP.)) oscillation clock)Note 3 stop) Reset processing (20 s (TYP.)) Normal operation (internal high-speed oscillation clock)Note 3 Operation stops Reset processing (20 s (TYP.)) Internal reset signal Notes 1. The operation guaranteed range is 1.8 V VDD 5.5 V. To make the state at lower than 1.8 V reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin. 2. If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MAX.) on power application, input a low level to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1). 3. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-VOLTAGE DETECTOR). Remark VLVI: LVI detection voltage VPOC: POC detection voltage 532 Preliminary User's Manual U17260EJ3V1UD CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be used for reset Set LVI to be used for interrupt Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Set LVI to be used for reset VLVI Supply voltage 2.7 V (TYP.) (VDD) 1.8 VNote 1 VPOC = 1.59 V (TYP.) 0V Wait for oscillation accuracy stabilization Internal high-speed oscillation clock (fRH) Starting oscillation is specified by software. High-speed system clock (fXH) (when X1 oscillation is selected) CPU Normal operation Reset period (internal high-speed (oscillation stop) oscillation clock)Note 2 Operation stops Reset processing (20 s (TYP.)) Starting oscillation is specified by software. Starting oscillation is specified by software. Normal operation (internal high-speed oscillation clock)Note 2 Reset processing (20 s (TYP.)) Reset period (oscillation stop) Normal operation (internal high-speed oscillation clock)Note 2 Operation stops Reset processing (20 s (TYP.)) Internal reset signal Notes 1. The operation guaranteed range is 1.8 V VDD 5.5 V. To make the state at lower than 1.8 V reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin. 2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-VOLTAGE DETECTOR). Remark VLVI: LVI detection voltage VPOC: POC detection voltage Preliminary User's Manual U17260EJ3V1UD 533 CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 23-3. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset Initialization processing <1> ; Check the reset sourceNote 2 Initialize the port. Power-on-clear Setting 8-bit timer H1 (to measure 50 ms) ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Clearing WDT Note 1 No 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Notes 1. 2. 534 ; Setting of division ratio of system clock, such as setting of timer or A/D converter If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. Preliminary User's Manual U17260EJ3V1UD CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-3. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated Preliminary User's Manual U17260EJ3V1UD 535 CHAPTER 24 LOW-VOLTAGE DETECTOR 24.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. Detection levels (16 levels) of supply voltage can be changed by software. * Compares a voltage input from an external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.)), and generates an internal interrupt signal or internal reset signal when EXLVI < VEXLVI. * The supply voltage (VDD) or voltage input from an external input pin (EXLVI) can be selected by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, see CHAPTER 22 RESET FUNCTION. 24.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 24-1. Figure 24-1. Block Diagram of Low-Voltage Detector VDD N-ch Internal reset signal Selector EXLVI/P120/ INTP0 + Selector Low-voltage detection level selector VDD - INTLVI Reference voltage source 4 LVION LVISEL LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level selection register (LVIS) Low-voltage detection register (LVIM) Internal bus 536 LVIF Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR 24.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detection register (LVIM) * Low-voltage detection level selection register (LVIS) * Port mode register 12 (PM12) Preliminary User's Manual U17260EJ3V1UD 537 CHAPTER 24 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LVIM to 00H. Figure 24-2. Format of Low-Voltage Detection Register (LVIM) Address: FFBEH After reset: 00H R/WNote 1 Symbol <7> 6 5 4 3 <2> <1> <0> LVIM LVION 0 0 0 0 LVISEL LVIMD LVIF Notes 2, 3 LVION Enables low-voltage detection operation 0 Disables operation 1 Enables operation Note 2 LVISEL Voltage detection selection 0 Detects level of supply voltage (VDD) 1 Detects level of input voltage from external input pin (EXLVI) Note 2 LVIMD Low-voltage detection operation mode selection 0 * LVISEL = 0: Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI) * LVISEL = 1: Generates interrupt signal when input voltage from external input pin (EXLVI) < detection voltage (VEXLVI) 1 * LVISEL = 0: Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI) * LVISEL = 1: Generates internal reset signal when input voltage from external input pin (EXLVI) < detection voltage (VEXLVI) Note 4 LVIF Low-voltage detection flag 0 * LVISEL = 0: Supply voltage (VDD) detection voltage (VLVI), or when operation is disabled * LVISEL = 1: Input voltage from external input pin (EXLVI) detection voltage (VEXLVI), or when operation is disabled 1 * LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI) * LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI) Notes 1. 2. Bit 0 is read-only. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared to 0 in the case of an LVI reset. 3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for an operation stabilization time (10 s (MAX.)) when LVION is set to 1 until the voltage is confirmed at LVIF. 4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. 538 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets LVIS to 00H. Figure 24-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 0 0 0 0 VLVI0 (4.24 V 0.1 V) 0 0 0 1 VLVI1 (4.09 V 0.1 V) 0 0 1 0 VLVI2 (3.93 V 0.1 V) 0 0 1 1 VLVI3 (3.78 V 0.1 V) 0 1 0 0 VLVI4 (3.62 V 0.1 V) 0 1 0 1 VLVI5 (3.47 V 0.1 V) 0 1 1 0 VLVI6 (3.32 V 0.1 V) 0 1 1 1 VLVI7 (3.16 V 0.1 V) 1 0 0 0 VLVI8 (3.01 V 0.1 V) 1 0 0 1 VLVI9 (2.85 V 0.1 V) 1 0 1 0 VLVI10 (2.70 V 0.1 V) 1 0 1 1 VLVI11 (2.55 V 0.1 V) 1 1 0 0 VLVI12 (2.39 V 0.1 V) 1 1 0 1 VLVI13 (2.24 V 0.1 V) 1 1 1 0 VLVI14 (2.08 V 0.1 V) 1 1 1 1 VLVI15 (1.93 V 0.1 V) Detection level Cautions 1. Be sure to clear bits 4 to 7 to 0. 2. Do not change the value of LVIS during LVI operation. 3. When an input voltage from the external input pin (EXLVI) is detected, the detection voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary. Preliminary User's Manual U17260EJ3V1UD 539 CHAPTER 24 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH. Figure 24-4. Format of Port Mode Register 12 (PM12) Address: FF2CH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 PM12n P12n pin I/O mode selection (n = 0 to 4) 0 Output mode (output buffer on) 1 Input mode (output buffer off) 24.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD VLVI. * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)), generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI VEXLVI. (2) Used as interrupt * If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. * If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21 V (TYP.)), and generates an interrupt signal (INTLVI) when EXLVI < VEXLVI. Remark LVISEL: Bit 2 of low-voltage detection register (LVIM) 540 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR 24.4.1 When used as reset (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MAX.)). <6> Wait until it is checked that (supply voltage (VDD) detection voltage (VLVI)) by bit 0 (LVIF) of LVIM. <7> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 24-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <7> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <4>. 2. If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. Preliminary User's Manual U17260EJ3V1UD 541 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) H <1> LVISEL flag (set by software) L LVION flag (set by software) <3> <2> Not cleared Not cleared <4> Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Clear Note 2 Not cleared Not cleared <7> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET FUNCTION. Remark <1> to <7> in Figure 24-5 above correspond to <1> to <7> in the description of "When starting operation" in 24.4.1 (1) When detecting level of supply voltage (VDD). 542 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V (TYP.) VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) HNote 1 LVISEL flag (set by software) L LVION flag (set by software) <1> <3> <2> Not cleared Not cleared <4> Clear <5> Wait time LVIF flag <6> LVIMD flag (set by software) Clear Note 2 Not cleared Not cleared <7> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. 2. 3. The LVIMK flag is set to "1" by reset signal generation. The LVIF flag may be set (1). LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET FUNCTION. Remark <1> to <7> in Figure 24-5 above correspond to <1> to <7> in the description of "When starting operation" in 24.4.1 (1) When detecting level of supply voltage (VDD). Preliminary User's Manual U17260EJ3V1UD 543 CHAPTER 24 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MAX.)Note). <5> Wait until it is checked that (input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.))) by bit 0 (LVIF) of LVIM. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when input voltage from external input pin (EXLVI) < detection voltage (VEXLVI = 1.21 V (TYP.))). Figure 24-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)) when LVIMD is set to 1, an internal reset signal is not generated. 3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and then LVION to 0. 544 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage (VEXLVI) Time LVIMK flag (set by software) LVISEL flag (set by software) HNote 1 <1> Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared Not cleared <2> LVION flag (set by software) <3> <4> Wait time LVIF flag <5> LVIMD flag (set by software) Note 2 Not cleared <6> LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET FUNCTION. Remark <1> to <6> in Figure 24-6 above correspond to <1> to <6> in the description of "When starting operation" in 24.4.1 (2) When detecting level of input voltage from external input pin (EXLVI). Preliminary User's Manual U17260EJ3V1UD 545 CHAPTER 24 LOW-VOLTAGE DETECTOR 24.4.2 When used as interrupt (1) When detecting level of supply voltage (VDD) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <5> Use software to wait for an operation stabilization time (10 s (MAX.)). <6> Confirm that "supply voltage (VDD) detection voltage (VLVI)" at bit 0 (LVIF) of LVIM. <7> Clear the interrupt request flag of LVI (LVIIF) to 0. <8> Release the interrupt mask flag of LVI (LVIMK). <9> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)) (default value). <10> Execute the EI instruction (when vector interrupts are used). Figure 24-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <9> above. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 546 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) <1> Note 1 LVISEL flag (set by software) <8> Cleared by software <3> L LVION flag (set by software) <2> <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <7> Cleared by software <9> Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 24-7 above correspond to <1> to <9> in the description of "When starting operation" in 24.4.2 (1) When detecting level of supply voltage (VDD). Preliminary User's Manual U17260EJ3V1UD 547 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V(TYP.) VPOC = 1.59 V (TYP.) Time LVIMK flag (set by software) <1> Note 1 LVISEL flag (set by software) <8> Cleared by software <3> L <2> LVION flag (set by software) <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag LVIMD flag (set by software) Note 2 <7> Cleared by software L <9> Internal reset signal Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <9> in Figure 24-7 above correspond to <1> to <9> in the description of "When starting operation" in 24.4.2 (1) When detecting level of supply voltage (VDD). 548 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 s (MAX.)). <5> Confirm that "input voltage from external input pin (EXLVI) detection voltage (VEXLVI = 1.21 V (TYP.)" at bit 0 (LVIF) of LVIM. <6> Clear the interrupt request flag of LVI (LVIIF) to 0. <7> Release the interrupt mask flag of LVI (LVIMK). <8> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)) (default value). <9> Execute the EI instruction (when vector interrupts are used). Figure 24-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this timing chart correspond to <1> to <8> above. Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. Preliminary User's Manual U17260EJ3V1UD 549 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) VEXLVI Time LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVISEL flag (set by software) LVION flag (set by software) <2> <3> <4> Wait time LVIF flag <5> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) L <6> Cleared by software <8> Notes 1. 2. Remark The LVIMK flag is set to "1" by reset signal generation. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1). <1> to <8> in Figure 24-8 above correspond to <1> to <8> in the description of "When starting operation" in 24.4.2 (1) When detecting level of supply voltage (VDD). 550 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR 24.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. In this system, take the following actions. <Action> (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see Figure 24-9). (2) When used as interrupt (a) Check that "supply voltage (VDD) detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L) to 0. (b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) detection voltage (VLVI)" using the LVIF flag, and clear the LVIIF flag to 0. Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to "1", the meanings of the above words change as follows. * Supply voltage (VDD) Input voltage from external input pin (EXLVI) Note * Detection voltage (VLVI) Detection voltage (VEXLVI = 1.21 V ) Preliminary User's Manual U17260EJ3V1UD 551 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-9. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check the reset sourceNote Initialize the port. Initialization processing <1> LVI reset ; Setting of detection level by LVIS The low-voltage detector operates (LVION = 1). Setting LVI ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, Where comparison value = 102: 50 ms Timer starts (TMHE1 = 1). Setting 8-bit timer H1 (to measure 50 ms) Clearing WDT Detection voltage or higher (LVIF = 0?) Yes No ; The low-voltage detection flag is cleared. LVIF = 0 Restarting timer H1 (TMHE1 = 0 TMHE1 = 1) No ; The timer counter is cleared and the timer is started. 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> ; Setting of division ratio of system clock, such as setting of timer or A/D converter Note A flowchart is shown on the next page. 552 Preliminary User's Manual U17260EJ3V1UD CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-9. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector Preliminary User's Manual U17260EJ3V1UD 553 CHAPTER 25 OPTION BYTE 25.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/KE2 is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes. When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H. Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance. (1) 0080H/1080H { Internal low-speed oscillator operation * Can be stopped by software * Cannot be stopped { Watchdog timer interval time setting { Watchdog timer counter operation * Enabled counter operation * Disabled counter operation { Watchdog timer window open period setting (2) 0081H/1081H { Selecting POC mode * During 2.7 V/1.59 V POC mode operation (POCMODE = 1) The device is in the reset state upon power application and until the supply voltage reaches 2.7 V (TYP.). It is released from the reset state when the voltage exceeds 2.7 V (TYP.). After that, POC is not detected at 2.7 V but is detected at 1.59 V (TYP.). If the supply voltage rises to 1.8 V after power application at a pace slower than 0.5 V/ms (MAX.), use of the 2.7 V/1.59 V POC mode is recommended. * During 1.59 V POC mode operation (POCMODE = 0) The device is in the reset state upon power application and until the supply voltage reaches 1.59 V (TYP.). It is released from the reset state when the voltage exceeds 1.59 V (TYP.). After that, POC is detected at 1.59 V (TYP.), in the same manner as on power application. (3) 0084H/1084H { On-chip debug operation control * Disabling on-chip debug operation * Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the onchip debug security ID fails * Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped with the on-chip debug function (PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535, 78F0536, and 78F0537). Also set 00H to 1084H because 0084H and 1084H are switched at boot swapping. 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F0537D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched at boot swapping. Caution Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap function is used). 554 Preliminary User's Manual U17260EJ3V1UD CHAPTER 25 OPTION BYTE 25.2 Format of Option Byte The format of the option byte is shown below. Figure 25-1. Format of Option Byte (1/2) Note Address: 0080H/1080H 7 6 5 4 3 2 1 0 0 WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 0 0 25% 0 1 50% 1 0 75% 1 1 100% WDTON Watchdog timer window open period Operation control of watchdog timer counter/illegal access detection 0 Counter operation disabled (counting stopped after reset), illegal access detection operation disabled 1 Counter operation enabled (counting started after reset), illegal access detection operation enabled WDCS2 WDCS1 WDCS0 Watchdog timer overflow time 10 0 0 0 2 /fRL (3.88 ms) 0 0 1 2 /fRL (7.76 ms) 0 1 0 2 /fRL (15.52 ms) 0 1 1 2 /fRL (31.03 ms) 1 0 0 2 /fRL (62.06 ms) 1 0 1 2 /fRL (124.12 ms) 1 1 0 2 /fRL (248.24 ms) 1 1 1 2 /fRL (496.48 ms) LSROSC 11 12 13 14 15 16 17 Internal low-speed oscillator operation 0 Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register) 1 Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit) Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation. Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 2. The watchdog timer does not stop during self-programming of the flash memory and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. 3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is supplied to 8-bit timer H1 even in the HALT/STOP mode. 4. Be sure to clear bit 7 to 0. Remarks 1. 2. fRL: Internal low-speed oscillation clock frequency ( ): fRL = 264 kHz (MAX.) Preliminary User's Manual U17260EJ3V1UD 555 CHAPTER 25 OPTION BYTE Figure 25-1. Format of Option Byte (2/2) Notes 1, 2 Address: 0081H/1081H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POCMODE POCMODE Notes 1. POC mode selection 0 1.59 V POC mode (default) 1 2.7 V/1.59 V POC mode POCMODE can only be written by using a dedicated flash programmer. It cannot be set during selfprogramming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function is used. 2. To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip erasure) of the flash memory. The setting cannot be changed after the memory of the specified block is erased. Caution Be sure to clear bits 7 to 1 to 0. Note Address: 0082H/1082H, 0083H/1083H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082 and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is used. Notes1, 2 Address: 0084H/1084H Notes 1. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 OCDEN1 OCDEN0 OCDEN1 OCDEN0 0 0 Operation disabled 0 1 Setting prohibited 1 0 Operation enabled. Does not erase data of the flash memory in case authentication of the on-chip debug security ID fails. 1 1 Operation enabled. Erases data of the flash memory in case authentication of the on-chip debug security ID fails. On-chip debug operation control Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the onchip debug function (PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535, 78F0536, and 78F0537). Also set 00H to 1084H because 0084H and 1084H are switched at boot swapping. 2. To use the on-chip debug function with a product equipped with the on-chip debug function (PD78F0537D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched at boot swapping. Remark For the on-chip debug security ID, see CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY). 556 Preliminary User's Manual U17260EJ3V1UD CHAPTER 25 OPTION BYTE Here is an example of description of the software for setting the option bytes. OPT CSEG OPTION: DB AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 210/fRL, ; Internal low-speed oscillator can be stopped by software. Remark DB 00H ; 1.59 V POC mode DB 00H ; Reserved area DB 00H ; Reserved area DB 00H ; On-chip debug operation disabled Referencing of the option byte is performed during reset processing. For the reset processing timing, see CHAPTER 22 RESET FUNCTION. Preliminary User's Manual U17260EJ3V1UD 557 CHAPTER 26 FLASH MEMORY The 78K0/KE2 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 26.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH. Caution Be sure to set each product to the values shown in Table 26-1 after a reset release. Figure 26-1. Format of Internal Memory Size Switching Register (IMS) Address: FFF0H After reset: CFH Symbol 7 6 5 4 3 2 1 0 RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 0 0 0 768 bytes 1 1 0 1024 bytes IMS R/W Other than above Internal high-speed RAM capacity selection Setting prohibited ROM3 ROM2 ROM1 ROM0 0 1 0 0 16 KB 0 1 1 0 24 KB 1 0 0 0 32 KB 1 1 0 0 48 KB 1 1 1 1 Other than above Internal ROM capacity selection 60 KB Setting prohibited Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and internal expansion RAM areas do not overlap. 558 Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY Table 26-1. Internal Memory Size Switching Register Settings Flash Memory Versions (78K0/KE2) IMS Setting PD78F0531 04H PD78F0532 C6H PD78F0533 C8H PD78F0534 CCH PD78F0535 CFH PD78F0536 CCH PD78F0537, 78F0537D CCH Note Note Note The PD78F0536, PD78F0537, and 78F0537D have internal ROMs of 96 KB and 128 KB, respectively. However, the set values for the IMS of these devices is the same as those for the 48 KB product because memory banks are used. For how to set the memory banks, see Figure 4-2 Format of Memory Bank Select Register (BANK). Preliminary User's Manual U17260EJ3V1UD 559 CHAPTER 26 FLASH MEMORY 26.2 Internal Expansion RAM Size Switching Register The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register (IXS). IXS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IXS to 0CH. Caution Be sure to set each product to the values shown in Table 26-2 after a reset release. Figure 26-2. Format of Internal Expansion RAM Size Switching Register (IXS) Address: FFF4H After reset: 0CH R/W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 1 1 0 0 0 byte 0 1 0 1 0 1024 bytes 0 1 0 0 0 2048 bytes 0 0 1 0 0 4096 bytes 0 0 0 0 0 6144 bytes Other than above Internal expansion RAM capacity selection Setting prohibited Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and internal expansion RAM area do not overlap. Table 26-2. Internal Expansion RAM Size Switching Register Settings Flash Memory Versions (78K0/KE2) PD78F0531 IXS Setting 0CH PD78F0532 PD78F0533 560 PD78F0534 0AH PD78F0535 08H PD78F0536 04H PD78F0537, 78F0537D 00H Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY 26.3 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/KE2 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/KE2 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 26-3. Wiring Between 78K0/KE2 and Dedicated Flash Programmer Pin Configuration of Dedicated Flash Programmer Signal Name I/O With CSI10 Pin Function Pin Name With UART6 Pin No. Pin Name Pin No. SI/RxD Input Receive signal SO10/P12 44 TxD6/P13 43 SO/TxD Output Transmit signal SI10/RxD0/P11 45 RxD6/P14 42 SCK Output Transfer clock SCK10/TxD0/P10 46 RESET 6 RESET 6 Mode signal FLMD0 9 FLMD0 9 VDD voltage generation/ VDD 15 VDD 15 Clock to 78K0/KE2 /RESET Output Reset signal FLMD0 Output VDD I/O power monitoring - Notes 1. 2. - EXCLK/X2/P122 Output GND - - - CLK Ground Note 1 Note 2 10 EVDD 16 EVDD 16 AVREF 47 AVREF 47 VSS 13 VSS 13 EVSS 14 EVSS 14 AVSS 48 AVSS 48 Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When using the clock out of the flash programmer, connect CLK and EXCLK of the programmer. Preliminary User's Manual U17260EJ3V1UD 561 CHAPTER 26 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 26-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode VDD (2.7 to 5.5 V) GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDD VDD2 SI SO SCK CLK /RESET FLMD0 WRITER INTERFACE 562 Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY Figure 26-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.5 V) GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDD VDD2 SI SO SCK CLK /RESET FLMD0 WRITER INTERFACE Preliminary User's Manual U17260EJ3V1UD 563 CHAPTER 26 FLASH MEMORY 26.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/KE2 is illustrated below. Figure 26-5. Environment for Writing Program to Flash Memory FLMD0 VDD XXXXXX XXXX Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) VSS XXXXX XXXX YYYY Axxxx XXX YYY RS-232C USB RESET Dedicated flash programmer CSI10/UART6 78K0/KE2 Host machine A host machine that controls the dedicated flash programmer is necessary. To interface between the dedicated flash programmer and the 78K0/KE2, CSI10 or UART6 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 26.5 Communication Mode Communication between the dedicated flash programmer and the 78K0/KE2 is established by serial communication via CSI10 or UART6 of the 78K0/KE2. (1) CSI10 Transfer rate: 2.4 kHz to 2.5 MHz Figure 26-6. Communication with Dedicated Flash Programmer (CSI10) FLMD0 VDD GND STATVE PG-FP4 (Flash Pro4) Dedicated flash programmer 564 VDD/EVDD/AVREF VSS/EVSS/AVSS XXXXXX XXXX Bxxxxx Cxxxxxx XXXXX XXX YYY XXXX YYYY Axxxx FLMD0 /RESET RESET SI/RxD SO10 SO/TxD SI10 SCK SCK10 Preliminary User's Manual U17260EJ3V1UD 78K0/KE2 CHAPTER 26 FLASH MEMORY (2) UART6 Transfer rate: 115200 bps Figure 26-7. Communication with Dedicated Flash Programmer (UART6) FLMD0 VDD GND VDD/EVDD/AVREF VSS/EVSS/AVSS XXXXXX /RESET XXXX Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx FLMD0 Dedicated flash programmer RESET SI/RxD TxD6 SO/TxD RxD6 CLK 78K0/KE2 EXCLK If FlashPro4 is used as the dedicated flash programmer, FlashPro4 generates the following signal for the 78K0/KE2. For details, refer to the FlashPro4 manual. Table 26-4. Pin Connection FlashPro4 Signal Name I/O 78K0/KE2 Pin Function Pin Name FLMD0 Output Mode signal FLMD0 VDD I/O VDD voltage generation/power monitoring VDD, EVDD, AVREF - GND Ground VSS, EVSS, AVSS CLK Output Clock output to 78K0/KE2 EXCLK /RESET Output Reset signal RESET SI/RxD Input Receive signal SO10/TxD6 SO/TxD Output Transmit signal SI10/RxD6 SCK Output Transfer clock SCK10 Notes 1. 2. Connection CSI10 x Note 1 UART6 { Note 2 x Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When using the clock out of the flash programmer, connect CLK and EXCLK of the programmer. Remark : Be sure to connect the pin. {: The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. Preliminary User's Manual U17260EJ3V1UD 565 CHAPTER 26 FLASH MEMORY 26.6 Handling of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 26.6.1 FLMD0 pin In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below. Figure 26-8. FLMD0 Pin Connection Example 78K0/KE2 Dedicated flash programmer connection pin FLMD0 26.6.2 Serial interface pins The pins used by each serial interface are listed below. Table 26-5. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 UART6 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. 566 Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY (1) Signal collision If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 26-9. Signal Collision (Input Pin of Serial Interface) 78K0/KE2 Signal collision Input pin Dedicated flash programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. Therefore, isolate the signal of the other device. (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 26-10. Malfunction of Other Device 78K0/KE2 Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the 78K0/KE2 in the flash memory programming mode affects the other device, isolate the signal of the other device. 78K0/KE2 Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the dedicated flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. Preliminary User's Manual U17260EJ3V1UD 567 CHAPTER 26 FLASH MEMORY 26.6.3 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash programmer. Figure 26-11. Signal Collision (RESET Pin) 78K0/KE2 Signal collision RESET Dedicated flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 26.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 26.6.5 REGC pin Connect the REGC pin to GND via a capacitor (0.47 F: target) in the same manner as during normal operation. 26.6.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the programmer, however, connect the clock out of the programmer to EXCLK. Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used. 2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. 26.6.7 Power supply To use the supply voltage output of the flash programmer, connect the VDD pin to VDD of the flash programmer, and the VSS pin to GND of the flash programmer. However, be sure to connect the VDD and VSS pins to VDD and GND of the flash programmer to use the power monitor function with the flash programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. Supply the same other power supplies (EVDD, EVSS, AVREF, and AVSS) as those in the normal operation mode. 568 Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY 26.7 Programming Method 26.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 26-12. Flash Memory Manipulation Procedure Start FLMD0 pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory No End? Yes End 26.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/KE2 in the flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 26-13. Flash Memory Programming Mode VDD 5.5 V 0V VDD RESET 0V FLMD0 pulse VDD FLMD0 0V Flash memory programming mode Table 26-6. Relationship Between FLMD0 Pin and Operation Mode After Reset Release FLMD0 0 VDD Operation Mode Normal operation mode Flash memory programming mode Preliminary User's Manual U17260EJ3V1UD 569 CHAPTER 26 FLASH MEMORY 26.7.3 Selecting communication mode In the 78K0/KE2, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. Table 26-7. Communication Modes Communication Mode Standard Setting Port Speed Note 1 On Target Note 3 UART (UART6) UART-ch0 115200 bps 3-wire serial I/O (CSI10) SIO-ch0 2.4 kHz to 2.5 MHz Optional Pins Used Frequency Multiply Rate 1 to 20 Note 2 MHz 1.0 Peripheral Number of Clock FLMD0 Pulses TxD6, RxD6 fX 0 fEXCLK 3 SO10, SI10, SCK10 fRH 8 Notes 1. Selection items for Standard settings on FlashPro4. 2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical specifications. 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the FLMD0 pulse has been received. Remark fX: X1 clock fEXCLK: External main system clock fRH: 570 Internal high-speed oscillation clock Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY 26.7.4 Communication commands The 78K0/KE2 communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the 78K0/KE2 are called commands, and the signals sent from the 78K0/KE2 to the dedicated flash programmer are called response. XXXX XXXXXX Axxxx Bxxxxx Cxxxxxx STATVE XXXXX XXX YYY XXXX YYYY Figure 26-14. Communication Commands PG-FP4 (Flash Pro4) Command Response 78K0/KE2 Dedicated flash programmer The flash memory control commands of the 78K0/KE2 are listed in the table below. All these commands are issued from the programmer and the 78K0/KE2 perform processing corresponding to the respective commands. Table 26-8. Flash Memory Control Commands Classification Command Name Verify Function Compares the contents of the entire memory Batch verify command with the input data. Erase Batch erase command Erases the contents of the entire memory. Blank check Batch blank check command Checks the erasure status of the entire memory. Data write High-speed write command Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Writes data from the address following that of Successive write command the high-speed write command executed immediately before, and executes a verify check. System setting, control Status read command Obtains the operation status Oscillation frequency setting command Sets the oscillation frequency Erase time setting command Sets the erase time for batch erase Write time setting command Sets the write time for writing data Baud rate setting command Sets the baud rate when UART is used Silicon signature command Reads the silicon signature information Reset command Escapes from each status The 78K0/KE2 return a response for the command issued by the dedicated flash programmer. The response names sent from the 78K0/KE2 are listed below. Table 26-9. Response Names Response Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. Preliminary User's Manual U17260EJ3V1UD 571 CHAPTER 26 FLASH MEMORY 26.8 Security Settings The operations shown below can be performed using the security setting command. The security setting is valid when the programming mode is set next. * Disabling batch erase (chip erase) Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited by this setting. Once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings can no longer be cancelled. Caution After the security setting for the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written, because the erase command is disabled. * Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited by this setting. This prohibition setting can be cancelled using the batch erase (chip erase) command. * Disabling write Execution of the write and block erase commands for entire blocks in the flash memory is prohibited by this setting. This prohibition setting can be cancelled using the batch erase (chip erase) command. * Disabling rewriting boot cluster 0 Execution of the batch erase (chip erase) command, block erase command, and write command on boot cluster 0 (0000H to 0FFFH) in the flash memory is prohibited by this setting. Caution If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device will not be rewritten. The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. The above security settings are only possible for on-board/off-board programming. Each security setting can be used in combination. Table 26-10 shows the relationship between the erase and write commands when the 78K0/KE2 security function is enabled. Table 26-10. Relationship Between Commands When Security Function Is Enabled Command Security Setting Batch Erase (Chip Block Erase Erase) Command Command Disabling batch erase (chip erase) Invalid Disabling block erase Valid Invalid Disabling write Write Command Valid Note Valid Invalid Disabling rewriting boot cluster 0 Invalid Note Since the erase command is disabled, data different from that which has already been written to the flash memory cannot be written. 572 Preliminary User's Manual U17260EJ3V1UD CHAPTER 26 FLASH MEMORY Table 26-11 shows the relationship between the security setting and the operation in each programming mode. Table 26-11. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode Security Setting On-Board/Off-Board Programming Security Setting Disabling batch erase (chip erase) Enabled Self Programming Security Operation Note 1 Valid Security Setting Security Operation Note 2 Disabled Invalid Enabled Valid Disabling block erase Disabling write Disabling rewriting boot cluster 0 Notes 1. Execution of each command is prohibited by the security setting. 2. Execution of self programming command is possible regardless of the security setting. Preliminary User's Manual U17260EJ3V1UD 573 CHAPTER 26 FLASH MEMORY 26.9 Flash Memory Programming by Self-Programming The 78K0/KE2 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/KE2 self- programming library, it can be used to upgrade the program in the field. If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt servicing can be executed. To execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute the EI instruction. After the self-programming mode is later restored, self- programming can be resumed. Remark For details of the self-programming function and the 78K0/KE2 self-programming library, refer to a separate document to be published (document name: 78K0/Kx2 Application Note, release schedule: Pending). Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2. Input a high level to the FLMD0 pin during self-programming. 3. Be sure to execute the DI instruction before starting self-programming. The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H). If an interrupt request is generated, self-programming is stopped. 4. Self-programming is also stopped by an interrupt request that is not masked even in the DI status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L, MK0H, MK1L, and MK1H). 5. Self-programming is executed with the internal high-speed oscillation clock. If the CPU operates with the X1 clock or external main system clock, the oscillation stabilization wait time of the internal high-speed oscillation clock elapses during self-programming. 6. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH. Figure 26-15. Operation Mode and Memory Map for Self-Programming (PD78F0537) FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH Reserved Buffer RAM Reserved Memory bank 4 Memory bank 2 Internal expansion RAM E000H DFFFH C000H BFFFH FFFFH FF00H FEFFH FB00H FA F F H FA 2 0 H FA 1 F H FA 0 0 H F9FFH F800H F7FFH SFR Internal highspeed RAM Reserved Flash memory control firmware ROM Flash memory (memory bank 0) Disable accessing 8000H 7FFFH Memory bank 5 SFR Internal highspeed RAM Reserved Buffer RAM Reserved Memory bank 2 Internal expansion RAM E000H DFFFH C000H BFFFH Reserved Flash memory control firmware ROM Disable accessing Enable accessing 8000H 7FFFH Memory bank 5 Memory bank 3 Flash memory (common area) Memory bank 1 0000H Normal mode 574 Memory bank 4 Instructions can be fetched from common area and selected memory bank. 0000H Flash memory (common area) Memory bank 3 Memory bank 1 Self-programming mode Preliminary User's Manual U17260EJ3V1UD Instructions can be fetched from common area and firmware ROM. CHAPTER 26 FLASH MEMORY The procedure of self-programming is illustrated below. Figure 26-16. Self-Programming Procedure Start self-programming Secure entry RAM area Set parameters to entry RAM Entry program (user program) FLMD0 pin = High level Execute DI instruction Execute library and access flash memory according to library contents Library Interrupt request Execute EI instruction Interrupt servicing No interrupt request Entry program (user program) Confirm library return value Self-programming being suspended FLMD0 pin = Low level End of self-programming Preliminary User's Manual U17260EJ3V1UD 575 CHAPTER 26 FLASH MEMORY 26.9.1 Boot swap function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78K0/KE2, so that boot cluster 1 is used as a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. If the program has been correctly written to boot cluster 0, restore the original boot area by using the set information function of the firmware of the 78K0/KE2. Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function. Boot cluster 0 (0000H to 0FFFH): Original boot program area Boot cluster 1 (1000H to 1FFFH): Area subject to boot swap function Figure 26-17. Boot Swap Function XXXXH User program Self-programming to boot cluster 1 User program Execution of boot swap by firmware User program 2000H Boot User program New boot program (boot cluster 1) Boot program (boot cluster 0) Boot program (boot cluster 0) 1000H 0000H New boot program (boot cluster 1) Boot Boot program (boot cluster 0) Boot XXXXH Self-programming to boot cluster 0 User program Execution of boot swap by firmware User program 2000H 1000H 0000H 576 New boot program (boot cluster 1) New boot program (boot cluster 1) Boot New boot program (boot cluster 0) Preliminary User's Manual U17260EJ3V1UD New boot program (boot cluster 0) Boot CHAPTER 26 FLASH MEMORY Figure 26-18. Example of Executing Boot Swapping Block number Boot cluster 1 Boot cluster 0 7 6 5 4 3 2 1 0 Program Program Program Program Boot program Boot program Boot program Boot program 1000H 0000H Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Program Program Program Boot program Boot program Boot program Boot program Program Program Boot program Boot program Boot program Boot program Program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Boot program Booted by boot cluster 0 Writing blocks 5 to 7 7 New boot program 6 New boot program 5 New boot program 4 New boot program 3 Boot program 2 Boot program 1 Boot program 0 Boot program Boot swap 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program Boot program 0000H 1000H Erasing block 0 Erasing block 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program Boot program Boot program New boot program New boot program New boot program New boot program Boot program Boot program Booted by boot cluster 1 Erasing block 2 Erasing block 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Boot program New boot program New boot program New boot program New boot program Writing blocks 0 to 3 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program New boot program New boot program New boot program New boot program Boot swap canceled 7 New boot program 6 New boot program 5 New boot program 4 New boot program 1 0 0 0 H 3 New boot program 2 New boot program 1 New boot program 0 New boot program 0 0 0 0 H Booted by boot cluster 0 Preliminary User's Manual U17260EJ3V1UD 577 CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY) The PD78F0537D uses the VDD, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Whether OCD0A/X1 and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected. Caution The PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the issue of the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Figure 27-1. Connection Example of QB-78K0MINI and PD78F0537D (When OCD0A/X1 and OCD0B/X2 Are Used) PD78F0537D QB-78K0MINI target connector FLMD0 FLMD0 Note Target reset RESET_IN RESET RESET_OUT X1 OCD0A/X1 X2 OCD0B/X2 GND GND VDD VDD P31 Note Note Make pull-down resistor 470 or more. Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging. 2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin or by using an external circuit using the P130 pin (that outputs a low level when the device is reset). 578 Preliminary User's Manual U17260EJ3V1UD CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY) Figure 27-2. Connection Example of QB-78K0MINI and PD78F0537D (When OCD1A and OCD1B Are Used) PD78F0537D QB-78K0MINI target connector FLMD0 FLMD0 Note Target reset RESET_IN RESET RESET_OUT X1 OCD1A/P31 Note X2 OCD1B/P32 GND GND VDD VDD X1 X2 Note Make pull-down resistor 470 or more. 27.1 On-Chip Debug Security ID The PD78F0537D has an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 25 OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH. When the boot swap function is used, also set a value that is the same as that of 1084H and 1085H to 108EH in advance, because 0084H, 0085H to 008EH and 1084H, and 1085H to 108EH are switched. For details on the on-chip debug security ID, refer to the QB-78K0MINI User's Manual (U17029E). Table 27-1. On-Chip Debug Security ID Address 0085H to 008EH On-Chip Debug Security ID Any ID code of 10 bytes 1085H to 108EH Preliminary User's Manual U17260EJ3V1UD 579 CHAPTER 28 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KE2 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E). 28.1 Conventions Used in Operation List 28.1.1 Operand identifiers and specification methods Operands are written in the "Operand" column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to write the #, !, $, and [ ] symbols. For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for specification. Table 28-1. Operand Identifiers and Specification Methods Identifier Specification Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special function register symbol sfrp Special function register symbol (16-bit manipulatable register even addresses only) saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even address only) addr16 0000H to FFFFH Immediate data or labels Note Note (Only even addresses for 16-bit data transfer instructions) addr11 0800H to 0FFFH Immediate data or labels addr5 0040H to 007FH Immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label RBn RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark 580 For special function register symbols, see Table 3-6 Special Function Register List. Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag RBS: Register bank select flag IE: Interrupt request enable flag ( ): Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 28.1.3 Description of flag operation column (Blank): Not affected 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored Preliminary User's Manual U17260EJ3V1UD 581 CHAPTER 28 INSTRUCTION SET 28.2 Operation List Instruction Group 8-bit data Mnemonic MOV transfer XCH Notes 1. Operands Clocks Bytes Note 1 Note 2 Z AC CY r, #byte 2 4 - r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 - 7 sfr byte A, r Note 3 1 2 - Ar r, A Note 3 1 2 - rA A, saddr 2 4 5 A (saddr) saddr, A 2 4 5 (saddr) A A, sfr 2 - 5 A sfr sfr, A 2 - 5 sfr A A, !addr16 3 8 9 A (addr16) !addr16, A 3 8 9 (addr16) A PSW, #byte 3 - 7 PSW byte A, PSW 2 - 5 A PSW PSW, A 2 - 5 PSW A A, [DE] 1 4 5 A (DE) [DE], A 1 4 5 (DE) A A, [HL] 1 4 5 A (HL) [HL], A 1 4 5 (HL) A A, [HL + byte] 2 8 9 A (HL + byte) [HL + byte], A 2 8 9 (HL + byte) A A, [HL + B] 1 6 7 A (HL + B) [HL + B], A 1 6 7 (HL + B) A A, [HL + C] 1 6 7 A (HL + C) [HL + C], A 1 6 7 (HL + C) A 1 2 - Ar A, r Note 3 Flag Operation A, saddr 2 4 6 A (saddr) A, sfr 2 - 6 A (sfr) A, !addr16 3 8 10 A (addr16) A, [DE] 1 4 6 A (DE) A, [HL] 1 4 6 A (HL) A, [HL + byte] 2 8 10 A (HL + byte) A, [HL + B] 2 8 10 A (HL + B) A, [HL + C] 2 8 10 A (HL + C) x x x x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 582 Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 16-bit data MOVW transfer 3 6 - rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 - 10 sfrp word AX, saddrp 2 6 8 AX (saddrp) saddrp, AX 2 6 8 (saddrp) AX AX, sfrp 2 - 8 AX sfrp sfrp, AX 2 - 8 sfrp AX 4 - AX rp AX, rp Note 3 1 rp, AX Note 3 1 4 - rp AX 3 10 12 AX (addr16) 3 10 12 (addr16) AX 1 4 - AX rp 2 4 - A, CY A + byte x x x 3 6 8 (saddr), CY (saddr) + byte x x x 2 4 - A, CY A + r x x x 2 4 - r, CY r + A x x x !addr16, AX XCHW AX, rp ADD A, #byte operation Note 3 saddr, #byte A, r Note 4 r, A ADDC A, saddr 2 4 5 A, CY A + (saddr) x x x A, !addr16 3 8 9 A, CY A + (addr16) x x x A, [HL] 1 4 5 A, CY A + (HL) x x x A, [HL + byte] 2 8 9 A, CY A + (HL + byte) x x x A, [HL + B] 2 8 9 A, CY A + (HL + B) x x x A, [HL + C] 2 8 9 A, CY A + (HL + C) x x x A, #byte 2 4 - A, CY A + byte + CY x x x 3 6 8 (saddr), CY (saddr) + byte + CY x x x 2 4 - A, CY A + r + CY x x x 2 4 - r, CY r + A + CY x x x saddr, #byte A, r Note 4 r, A Notes 1. Z AC CY Note 2 rp, #word AX, !addr16 8-bit Flag Operation A, saddr 2 4 5 A, CY A + (saddr) + CY x x x A, !addr16 3 8 9 A, CY A + (addr16) + C x x x A, [HL] 1 4 5 A, CY A + (HL) + CY x x x A, [HL + byte] 2 8 9 A, CY A + (HL + byte) + CY x x x A, [HL + B] 2 8 9 A, CY A + (HL + B) + CY x x x A, [HL + C] 2 8 9 A, CY A + (HL + C) + CY x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. Preliminary User's Manual U17260EJ3V1UD 583 CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 8-bit SUB operation 2 4 - A, CY A - byte x x x saddr, #byte 3 6 8 (saddr), CY (saddr) - byte x x x 2 4 - A, CY A - r x x x r, A 2 4 - r, CY r - A x x x A, saddr 2 4 5 A, CY A - (saddr) x x x Note 3 A, !addr16 3 8 9 A, CY A - (addr16) x x x A, [HL] 1 4 5 A, CY A - (HL) x x x A, [HL + byte] 2 8 9 A, CY A - (HL + byte) x x x A, [HL + B] 2 8 9 A, CY A - (HL + B) x x x A, [HL + C] 2 8 9 A, CY A - (HL + C) x x x A, #byte 2 4 - A, CY A - byte - CY x x x saddr, #byte 3 6 8 (saddr), CY (saddr) - byte - CY x x x 2 4 - A, CY A - r - CY x x x r, A 2 4 - r, CY r - A - CY x x x A, saddr 2 4 5 A, CY A - (saddr) - CY x x x A, !addr16 3 8 9 A, CY A - (addr16) - CY x x x A, [HL] 1 4 5 A, CY A - (HL) - CY x x x A, [HL + byte] 2 8 9 A, CY A - (HL + byte) - CY x x x A, r AND Note 3 A, [HL + B] 2 8 9 A, CY A - (HL + B) - CY x x x A, [HL + C] 2 8 9 A, CY A - (HL + C) - CY x x x A, #byte 2 4 - A A byte x 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x 2 4 - rrA x saddr, #byte A, r r, A Notes 1. Z AC CY Note 2 A, #byte A, r SUBC Flag Operation Note 3 A, saddr 2 4 5 A A (saddr) x A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 584 Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 8-bit OR operation 2 4 - A A byte x saddr, #byte 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x r, A 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x Note 3 A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x A, #byte 2 4 - A A byte x saddr, #byte 3 6 8 (saddr) (saddr) byte x 2 4 - AAr x r, A 2 4 - rrA x A, saddr 2 4 5 A A (saddr) x A, !addr16 3 8 9 A A (addr16) x A, [HL] 1 4 5 A A (HL) x A, [HL + byte] 2 8 9 A A (HL + byte) x A, r CMP Note 3 A, [HL + B] 2 8 9 A A (HL + B) x A, [HL + C] 2 8 9 A A (HL + C) x A, #byte 2 4 - A - byte x x x 3 6 8 (saddr) - byte x x x 2 4 - A-r x x x 2 4 - r-A x x x saddr, #byte A, r r, A Notes 1. Z AC CY Note 2 A, #byte A, r XOR Flag Operation Note 3 A, saddr 2 4 5 A - (saddr) x x x A, !addr16 3 8 9 A - (addr16) x x x A, [HL] 1 4 5 A - (HL) x x x A, [HL + byte] 2 8 9 A - (HL + byte) x x x A, [HL + B] 2 8 9 A - (HL + B) x x x A, [HL + C] 2 8 9 A - (HL + C) x x x When the internal high-speed RAM area is accessed or for an instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. Preliminary User's Manual U17260EJ3V1UD 585 CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 Note 2 Flag Operation Z AC CY 16-bit ADDW AX, #word 3 6 - AX, CY AX + word x x x operation SUBW AX, #word 3 6 - AX, CY AX - word x x x CMPW AX, #word 3 6 - AX - word x x x Multiply/ MULU X 2 16 - AX A x X divide DIVUW C 2 25 - AX (Quotient), C (Remainder) AX / C Increment/ INC decrement DEC INCW Rotate r 1 2 - rr+1 x x saddr 2 4 6 (saddr) (saddr) + 1 x x r 1 2 - rr-1 x x saddr 2 4 6 (saddr) (saddr) - 1 x x rp 1 4 - rp rp + 1 DECW rp 1 4 - rp rp - 1 ROR A, 1 1 2 - (CY, A7 A0, Am - 1 Am) x 1 time x ROL A, 1 1 2 - (CY, A0 A7, Am + 1 Am) x 1 time x RORC A, 1 1 2 - (CY A0, A7 CY, Am - 1 Am) x 1 time x ROLC A, 1 1 2 - (CY A7, A0 CY, Am + 1 Am) x 1 time x ROR4 [HL] 2 10 12 A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 ROL4 [HL] 2 10 12 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 BCD ADJBA adjustment ADJBS Bit MOV1 manipulate Notes 1. 2. 2 4 - Decimal Adjust Accumulator after Addition x x x x x 2 4 - Decimal Adjust Accumulator after Subtract CY, saddr.bit 3 6 7 CY (saddr.bit) x CY, sfr.bit 3 - 7 CY sfr.bit x CY, A.bit 2 4 - CY A.bit x CY, PSW.bit 3 - 7 CY PSW.bit x CY, [HL].bit 2 6 7 CY (HL).bit x saddr.bit, CY 3 6 8 (saddr.bit) CY sfr.bit, CY 3 - 8 sfr.bit CY A.bit, CY 2 4 - A.bit CY PSW.bit, CY 3 - 8 PSW.bit CY [HL].bit, CY 2 6 8 (HL).bit CY x x x When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 586 Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 Bit AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Flag Operation Z AC CY Note 2 CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW.bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x CY, saddr.bit 3 6 7 CY CY (saddr.bit) x CY, sfr.bit 3 - 7 CY CY sfr.bit x CY, A.bit 2 4 - CY CY A.bit x CY, PSW. bit 3 - 7 CY CY PSW.bit x CY, [HL].bit 2 6 7 CY CY (HL).bit x saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 - 8 sfr.bit 1 A.bit 2 4 - A.bit 1 PSW.bit 2 - 6 PSW.bit 1 [HL].bit 2 6 8 (HL).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 - 8 sfr.bit 0 A.bit 2 4 - A.bit 0 PSW.bit 2 - 6 PSW.bit 0 x x x x x x [HL].bit 2 6 8 (HL).bit 0 SET1 CY 1 2 - CY 1 1 CLR1 CY 1 2 - CY 0 0 NOT1 CY 1 2 - CY CY x When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. Preliminary User's Manual U17260EJ3V1UD 587 CHAPTER 28 INSTRUCTION SET Instruction Group Call/return Mnemonic CALL Operands !addr16 Clocks Bytes 3 Note 1 Note 2 7 - Operation Flag Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLF !addr11 2 5 - (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 CALLT [addr5] 1 6 - (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 BRK 1 6 - (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 RET 1 6 - PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 6 - PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 RETB 1 6 - PCH (SP + 1), PCL (SP), R R R PSW (SP + 2), SP SP + 3 Stack PUSH manipulate PSW rp 1 1 2 - 4 - (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 POP PSW 1 2 - PSW (SP), SP SP + 1 rp 1 4 - rpH (SP + 1), rpL (SP), SP, #word 4 - 10 SP word SP, AX 2 - 8 SP AX R R R SP SP + 2 MOVW AX, SP 2 - 8 AX SP Unconditional BR !addr16 3 6 - PC addr16 branch $addr16 2 6 - PC PC + 2 + jdisp8 - PCH A, PCL X AX 2 8 Conditional BC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 1 branch BNC $addr16 2 6 - PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 - PC PC + 2 + jdisp8 if Z = 0 Notes 1. 2. When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 588 Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET Instruction Group Mnemonic Operands Clocks Bytes Note 1 Z AC CY Note 2 Conditional BT saddr.bit, $addr16 3 8 9 PC PC + 3 + jdisp8 if (saddr.bit) = 1 branch sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 - 9 PC PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 0 BF BTCLR Flag Operation PSW.bit, $addr16 4 - 11 PC PC + 4 + jdisp8 if PSW. bit = 0 [HL].bit, $addr16 3 10 11 PC PC + 3 + jdisp8 if (HL).bit = 0 saddr.bit, $addr16 4 10 12 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 - 12 PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr16 3 8 - PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PSW.bit, $addr16 4 - 12 PC PC + 4 + jdisp8 if PSW.bit = 1 x x x then reset PSW.bit [HL].bit, $addr16 3 10 12 PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit DBNZ B, $addr16 2 6 - B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 - C C -1, then saddr, $addr16 3 8 10 (saddr) (saddr) - 1, then PC PC + 2 + jdisp8 if C 0 PC PC + 3 + jdisp8 if (saddr) 0 CPU SEL 2 4 - RBS1, 0 n control NOP 1 2 - No Operation EI 2 - 6 IE 1 (Enable Interrupt) DI 2 - 6 IE 0 (Disable Interrupt) HALT 2 6 - Set HALT Mode STOP 2 6 - Set STOP Mode Notes 1. 2. RBn When the internal high-speed RAM area is accessed or for an instruction with no data access When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. Preliminary User's Manual U17260EJ3V1UD 589 CHAPTER 28 INSTRUCTION SET 28.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None [HL + B] First Operand A r [HL + C] ADD MOV MOV MOV MOV ADDC XCH XCH XCH XCH SUB ADD ADD ADD SUBC ADDC ADDC ADDC ADDC ADDC AND SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD RORC SUB ROLC SUB MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ ADD INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV PUSH MOV POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note Except "r = A" 590 Preliminary User's Manual U17260EJ3V1UD CHAPTER 28 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None First Operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1 BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 Preliminary User's Manual U17260EJ3V1UD 591 CHAPTER 28 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 592 Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Cautions 1. These specifications show target values of (T) (S), and (R) products, which may change after device evaluation. 2. The PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the issue of the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol Conditions VDD Unit -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 -0.5 to VDD + 0.3 AVREF VI1 V Note -0.5 to +0.3 AVSS Input voltage Ratings P00 to P06, P10 to P17, P20 to P27, P30 -0.3 to VDD + 0.3 V V Note V to P33, P40 to P43, P50 to P53, P70 to P77, P120 to P124, P140, P141, X1, X2, XT1, XT2, RESET VI2 Output voltage Analog input voltage P60 to P63 (N-ch open drain) -0.3 to +6.5 V VO -0.3 to VDD + 0.3 VAN -0.3 to AVREF + 0.3 ANI0 to ANI7 Note Note V V and -0.3 to VDD + 0.3 Note Output current, high IOH Per pin Total of all pins P00 to P04, P40 to P43, -80 mA -10 mA -25 mA -55 mA P120, P130, P140, P141 P05, P06, P10 to P17, P30 to P33, P50 to P53, P70 to P77 Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17260EJ3V1UD 593 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions Per pin Total of all pins P00 to P04, P40 to P43, 200 mA Ratings Unit 30 mA 60 mA 140 mA -40 to +85 C -40 to +150 C P120, P130, P140, P141 P05, P06, P10 to P17, P30 to P33, P50 to P53, P60 to P63, P70 to P77 Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 594 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) X1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit X1 clock Ceramic resonator Parameter VSS X1 X2 Conditions MIN. TYP. MAX. Unit MHz 4.0 V VDD 5.5 V 1.0 20.0 2.7 V VDD < 4.0 V 1.0 10.0 1.8 V VDD < 2.7 V 1.0 5.0 4.0 V VDD 5.5 V 1.0 20.0 2.7 V VDD < 4.0 V 1.0 10.0 1.8 V VDD < 2.7 V 1.0 5.0 oscillation Note frequency (fX) C1 C2 X1 clock Crystal resonator VSS X1 X2 MHz oscillation Note frequency (fX) C1 C2 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Preliminary User's Manual U17260EJ3V1UD 595 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Internal Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Parameter 8 MHz internal oscillator Conditions Internal high-speed oscillation Note 1 240 kHz internal oscillator 2.7 V VDD 5.5 V MIN. Note 2 7.6 TYP. 8.0 Note 2 8.0 Note 2 MAX. 8.4 Note 2 Unit MHz clock frequency (fRH) 1.8 V VDD < 2.7 V Internal low-speed oscillation 2.7 V VDD 5.5 V 216 240 264 kHz clock frequency (fRL) 1.8 V VDD < 2.7 V 120 240 264 kHz Note 2 7.6 10.4 Note 2 MHz Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. This is the frequency when RSTS (bit 7 of the internal oscillation mode register (RCM)) = 1. It is 5.6 MHz (TYP.) when RSTS = 0. XT1 Oscillator Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, VSS = EVSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 Conditions XT1 clock oscillation MIN. TYP. MAX. Unit 32 32.768 35 kHz Note frequency (fXT) Rd C4 Parameter C3 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 596 Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (1/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 MAX. Unit Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, P130, P140, P141 Conditions 4.0 V VDD 5.5 V -3.0 mA 2.7 V VDD < 4.0 V -2.5 mA 1.8 V VDD < 2.7 V -1.0 mA Total of P00 to P04, P40 to P43, Note 3 P120, P130, P140, P141 4.0 V VDD 5.5 V -20.0 mA 2.7 V VDD < 4.0 V -10.0 mA 1.8 V VDD < 2.7 V -5.0 mA 4.0 V VDD 5.5 V -30.0 mA 2.7 V VDD < 4.0 V -19.0 mA 1.8 V VDD < 2.7 V -10.0 mA 4.0 V VDD 5.5 V -50.0 mA 2.7 V VDD < 4.0 V -29.0 mA 1.8 V VDD < 2.7 V -15.0 mA AVREF = VDD -0.1 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P53, P70 to Note 3 P77 Total Note 3 of all pins MIN. TYP. IOH2 Per pin for P20 to P27 -0.1 mA IOL1 Per pin for P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, P130, P140, P141 4.0 V VDD 5.5 V 8.5 mA 2.7 V VDD < 4.0 V 5.0 mA 1.8 V VDD < 2.7 V 2.0 mA Per pin for P60 to P63 4.0 V VDD 5.5 V 15.0 mA 2.7 V VDD < 4.0 V 5.0 mA Per pin for P121 to P124 Output current, low Note 2 1.8 V VDD < 2.7 V 2.0 mA Total of P00 to P04, P40 to P43, Note 3 P120, P130, P140, P141 4.0 V VDD 5.5 V 20.0 mA 2.7 V VDD < 4.0 V 15.0 mA 1.8 V VDD < 2.7 V 9.0 mA Total of P05, P06, P10 to P17, P30 to P33, P50 to P53, P60 to Note 3 P63, P70 to P77 4.0 V VDD 5.5 V 45.0 mA 2.7 V VDD < 4.0 V 35.0 mA Note 3 Total of all pins IOL2 Per pin for P20 to P27 1.8 V VDD < 2.7 V 20.0 mA 4.0 V VDD 5.5 V 65.0 mA 2.7 V VDD < 4.0 V 50.0 mA 1.8 V VDD < 2.7 V 29.0 mA AVREF = VDD Per pin for P121 to P124 0.4 mA 0.4 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output pin. 2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to GND. 3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 x t and time for which current is not output is 0.3 x t, where t is a specific time). The total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. * Where the duty factor of IOH is n%: Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where the duty factor is 50%, IOH = 20.0 mA Total output current of pins = (20.0 x 0.7)/(50 x 0.01) = 28.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17260EJ3V1UD 597 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (2/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) MAX. Unit Input voltage, high (PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) Parameter VIH1 P02, P12, P13, P15, P40 to P43, P50 to P53, P63, P121 to P124 0.7VDD VDD V VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P60 to P62, P70 to P77, P120, P140, P141, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V Input voltage, high (PD78F0531, 78F0532, 78F0533) VIH1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P63, P121 to P124 0.7VDD VDD V VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P60 to P62, P70 to P77, P120, P140, P141, RESET 0.8VDD VDD V VIH3 P20 to P27 0.7AVREF AVREF V Input voltage, low (PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) VIL1 P02, P12, P13, P15, P40 to P43, P50 to P53, P63, P121 to P124 0 0.3VDD V VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17, P30 to P33, P60 to P62, P70 to P77, P120, P140, P141, RESET 0 0.2VDD V VIL3 P20 to P27 0 0.3AVREF V Input voltage, low (PD78F0531, 78F0532, 78F0533) VIL1 P02 to P06, P12, P13, P15, P40 to P43, P50 to P53, P63, P121 to P124 0 0.3VDD V VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33, P60 to P62, P70 to P77, P120, P140, P141, RESET 0 0.2VDD V VIL3 P20 to P27 AVREF = VDD 0 0.3AVREF V VOH1 P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, P130, P140, P141 4.0 V VDD 5.5 V, IOH1 = -3.0 mA VDD - 0.7 V 2.7 V VDD < 4.0 V, IOH1 = -2.5 mA VDD - 0.5 V 1.8 V VDD < 2.7 V, IOH1 = -1.0 mA VDD - 0.5 V P20 to P27 AVREF = VDD, IOH2 = -100 A VDD - 0.5 V P121 to P124 IOH2 = -100 A VDD - 0.5 V Output voltage, high Symbol VOH2 Remark 598 Conditions AVREF = VDD AVREF = VDD AVREF = VDD MIN. TYP. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (3/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Output voltage, low Symbol VOL1 VOL2 VOL3 Input leakage current, high ILIH1 Conditions MAX. Unit 4.0 V VDD 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V VDD < 4.0 V, IOL1 = 5.0 mA 0.7 V 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA 0.5 V 1.8 V VDD < 2.7 V, IOL1 = 0.5 mA 0.4 P20 to P27 AVREF = VDD, IOL2 = 0.4 mA 0.4 P121 to P124 IOL2 = 0.4 mA 0.4 V P60 to P63 4.0 V VDD 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V VDD 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V VDD < 4.0 V, IOL1 = 3.0 mA 0.4 V 1.8 V VDD < 2.7 V, IOL1 = 2.0 mA 0.4 V VI = VDD 1 A P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, P130, P140, P141 P00 to P06, MIN. TYP. V P10 to P17, P30 to P33, P40 to P43, P50 to P53, P60 to P63, P70 to P77, P120, P130, P140, P141 Input leakage current, low ILIH2 P20 to P27 VI = AVREF = VDD 1 A ILIH3 P121 to 124 VI = VDD I/O port mode 1 A X1, X2, XT1, XT2 VI = VDD OSC mode 20 A P00 to P06, VI = VSS -1 A VI = VSS, AVREF = VDD -1 A ILIL1 P10 to P17, P30 to P33, P40 to P43, P50 to P53, P60 to P63, P70 to P77, P120, P130, P140, P141 ILIL2 ILIL3 P20 to P27 P121 to 124 VI = VSS I/O port mode -1 A X1, X2, XT1, XT2 VI = VSS OSC mode -20 A 100 k Pull-up resistor RU VI = VDD 10 FLMD0 supply voltage VIL In normal operation mode 0 0.2VDD V VIH In self-programming mode 0.8VDD VDD V Remark 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U17260EJ3V1UD 599 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (4/4) (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 IDD1 Conditions Operating mode MIN. TYP. MAX. Unit Note 2 fXH = 20 MHz 4.7 5.8 mA Notes 2, 3 , VDD = 5.0 V 2.5 3.5 mA Notes 2, 3 fXH = 10 MHz , VDD = 5.0 V fXH = 10 MHz 2.1 3.1 mA Notes 2, 3 , VDD = 3.0 V 1.5 2.2 mA Notes 2, 3 1.2 1.8 mA 1.9 2.7 mA 17 30 A 2.2 2.6 mA 1.0 1.2 mA 0.55 0.65 mA 0.6 0.65 mA 3.5 20 A 1 20 A 0.86 1.9 mA 5 10 A 9 35 A fXH = 5 MHz , VDD = 3.0 V fXH = 5 MHz , VDD = 2.0 V fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz Note 5 IDD2 HALT mode Notes 2, 4 , VDD = 5.0 V Note 2 fXH = 20 MHz , VDD = 5.0 V Notes 2, 3 fXH = 10 MHz , VDD = 5.0 V Notes 2, 3 fXH = 5 MHz , VDD = 3.0 V fRH = 8 MHz, VDD = 5.0 V fSUB = 32.768 kHz Note 5 STOP mode Note 6 During conversion at maximum speed IDD3 A/D converter IADC IWDT Note 7 operating current LVI operating current Notes 1. 2. , VDD = 5.0 V VDD = 5.0 V 2.3 V AVREF VDD operating current Watchdog timer Notes 2, 4 During 240 kHz internal low-speed oscillation clock operation Note 8 ILVI Total current flowing into the internal power supply (VDD), including the peripheral operation current (however, the current flowing into the pull-up resistors of the port, and A/D converter is not included). Square-wave input 3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0. 4. When main system clock is stopped 5. Total current flowing into the internal power supply (VDD), including the peripheral operating current (however, the current flowing into the pull-up resistor of the port, A/D converter, watchdog timer, and LVI circuit is not included) 6. Current flowing only to the A/D converter. The current value of the 78K0/KE2 is the sum of IDD1 or IDD2 7. Current flowing only to the watchdog timer. The current value of the 78K0/KE2 is the sum of IDD2 or IDD3 and IADC when the A/D converter operates in an operation mode or the HALT mode. and IWDT when the watchdog timer operates in the HALT or STOP mode. 8. Current flowing only to the LVI circuit. The current value of the 78K0/KE2 is the sum of IDD2 or IDD3 and ILVI when the LVI circuit operates in the HALT or STOP mode. Remarks 1. fXH: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fRH: Internal high-speed oscillation clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock frequency) 600 Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics (1) Basic operation (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Instruction cycle (minimum TCY instruction execution time) Conditions fEXCLK frequency TYP. MAX. Unit Main system clock (fXP) 4.0 V VDD 5.5 V 0.1 32 s operation 2.7 V VDD < 4.0 V 0.2 32 s 32 s 125 s MHz 1.8 V VDD < 2.7 V External main system clock MIN. 0.4 Note 1 Subsystem clock (fSUB) operation 114 4.0 V VDD 5.5 V 1.0 20.0 2.7 V VDD < 4.0 V 1.0 10.0 MHz 1.8 V VDD < 2.7 V 1.0 5.0 MHz External main system clock input tEXCLKH, (1/fEXCLK high-level width, low-level width tEXCLKL x 1/2) - 1 External subsystem clock fEXCLKS 32 122 ns 32.768 35 kHz frequency External subsystem clock input tEXCLKSH, (1/fEXCLKS high-level width, low-level width tEXCLKSL x 1/2) - 5 TI000, TI010, TI001 Note 2 Note 2 , TI011 input high-level width, low-level tTIH0, 4.0 V VDD 5.5 V tTIL0 width fTI5 Note 3 s 2/fsam + 0.2 TI50, TI51 input frequency s 2/fsam + 0.1 2.7 V VDD < 4.0 V ns Note 3 4.0 V VDD 5.5 V 10 MHz 2.7 V VDD < 4.0 V 10 MHz 1.8 V VDD < 2.7 V 5 MHz TI50, TI51 input high-level width, tTIH5, 4.0 V VDD 5.5 V 50 ns low-level width tTIL5 2.7 V VDD < 4.0 V 50 ns 1.8 V VDD < 2.7 V 100 ns 1 s Key interrupt input low-level width tKR 250 ns RESET low-level width 10 s Interrupt input high-level width, tINTH, low-level width tINTL Notes 1. tRSL 0.38 s when operating with the 8 MHz internal oscillator. 2. PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. 3. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS. Preliminary User's Manual U17260EJ3V1UD 601 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) TCY vs. VDD (Main System Clock Operation) 100 32 10 Cycle time TCY [ s] 5.0 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 1.8 3.0 5.0 5.5 6.0 4.0 2.7 Supply voltage VDD [V] AC Timing Test Points (Excluding External Main System Clock and External Subsystem Clock) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLK 1/fEXCLKS tEXCLKSL tEXCLKSH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLKS 602 Preliminary User's Manual U17260EJ3V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) TI Timing tTIL0 tTIH0 TI000, TI010, TI001Note, TI011Note 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET Note PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only. Preliminary User's Manual U17260EJ3V1UD 603 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) (2) Serial interface (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 312.5 kbps MAX. Unit 312.5 kbps High-Speed Mode Unit Transfer rate (b) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (c) IIC0 Parameter Symbol SCL0 clock frequency Standard Mode MIN. MAX. MAX. 0 100 0 400 kHz tSU:STA 4.8 - 0.7 - s Hold time tHD:STA 4.1 - 0.7 - (s Hold time when SCL0 = "L" tLOW 5.0 - 1.25 - (s Hold time when SCL0 = "H" tHIGH 5.0 - 1.25 - (s Data setup time (reception) tSU:DAT 0 - 0 - (s Data hold time (transmission)Note 2 tHD:DAT 0.47 4.0 0.23 1.00 (s Setup time of start/restart condition fSCL MIN. Note 1 Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. * The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK 2. (acknowledge) timing. (d) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 Conditions SI1n hold time (from SCK1n) tKSI1 Delay time from SCK1n to tKSO1 2. Remark 604 Unit 100 ns 200 ns 1.8 V VDD < 2.7 V 400 ns tKCY1/2 - ns Note 1 10 Note 2 C = 50 pF SO1n output Notes 1. MAX. 2.7 V VDD < 4.0 V tKH1, tSIK1 TYP. 4.0 V VDD 5.5 V tKL1 SI1n setup time (to SCK1n) MIN. This value is when high-speed system clock (fXH) is used. C is the load capacitance of the SCK1n and SO1n output lines. PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: Preliminary User's Manual U17260EJ3V1UD 30 ns 30 ns 40 ns CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) (e) CSI1n (slave mode, SCK1n... external clock input) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol Conditions MIN. TYP. MAX. Unit tKCY2 400 ns tKH2, tKCY2/2 ns 80 ns 50 ns tKL2 SI1n setup time (to SCK1n) tSIK2 SI1n hold time (from SCK1n) tKSI2 Delay time from SCK1n to tKSO2 Note C = 50 pF 120 ns SO1n output Note C is the load capacitance of the SO1n output line. Remark n = 0: PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Preliminary User's Manual U17260EJ3V1UD 605 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Serial Transfer Timing IIC0: tLOW SCL0 tHD:DAT tHIGH tHD:STA tSU:STA tHD:STA tSU:DAT SDA0 Stop condition Start condition Restart condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 PD78F0531, 78F0532, 78F0533 n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D n = 0: 606 Preliminary User's Manual U17260EJ3V1UD Stop condition CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) A/D Converter Characteristics (TA = -40 to +85C, 1.8 V VDD = EVDD 5.5 V, 2.3 V AVREF VDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Resolution Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 EFS Note 1 Integral non-linearity error Differential non-linearity error Analog input voltage 2. MIN. TYP. MAX. Unit 10 bit 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 1.2 %FSR 36.7 s RES Notes 1, 2 Notes 1. Conditions ILE Note 1 DLE 4.0 V AVREF 5.5 V 6.1 2.7 V AVREF < 4.0 V 12.2 36.7 s 2.3 V AVREF < 2.7 V 27 66.6 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 2.3 V AVREF < 2.7 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 2.3 V AVREF < 2.7 V 6.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB 2.3 V AVREF < 2.7 V 2.0 %FSR AVREF V VAIN AVSS Excludes quantization error (1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value. 1.59 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Symbol Detection voltage VPOC Power voltage rise inclination tPTH Minimum pulse width tPW Conditions MIN. TYP. MAX. Unit 1.44 1.59 1.74 V 0.5 V/ms VDD: 0 V change inclination of VPOC s 200 POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH Time Preliminary User's Manual U17260EJ3V1UD 607 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Supply Voltage Rise Time (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Maximum time to rise to 1.8 V (VDD (MIN.)) Symbol tPUP1 (VDD: 0 V 1.8 V) Maximum time to rise to 1.8 V (VDD (MIN.)) Conditions MIN. TYP. POCMODE (option byte) = 0, MAX. Unit 3.6 ms 1.9 ms when RESET input is not used tPUP2 (releasing RESET input VDD: 1.8 V) POCMODE (option byte) = 0, when RESET input is used Supply Voltage Rise Time Timing * When RESET pin input is not used * When RESET pin input is used Supply voltage (VDD) Supply voltage (VDD) 1.8 V 1.8 V VPOC Time Time tPUP1 RESET pin tPUP2 2.7 V POC Circuit Characteristics (TA = -40 to +85C, VSS = EVSS = 0 V) Parameter Detection voltage on application of supply Symbol VDDPOC Conditions POCMODE (option bye) = 1 voltage 608 Preliminary User's Manual U17260EJ3V1UD MIN. TYP. MAX. Unit 2.50 2.70 2.90 V CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) LVI Circuit Characteristics (TA = -40 to +85C, VPOC VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = 0 V) Parameter Detection Symbol Supply voltage level voltage External input pin Note 1 Minimum pulse width MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.26 V VLVI8 2.91 3.01 3.11 V VLVI9 2.75 2.85 2.95 V VLVI10 2.60 2.70 2.80 V VLVI11 2.45 2.55 2.65 V VLVI12 2.29 2.39 2.49 V VLVI13 2.14 2.24 2.34 V VLVI14 1.98 2.08 2.18 V VLVI15 1.83 1.93 2.03 V EXLVI Conditions EXLVI < VDD, 1.8 V VDD 5.5 V 1.21 tLW Operation stabilization wait time Note 2 V s 200 tLWAIT 10 s Notes 1. The EXLVI/P120/INTP0 pin is used. 2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation stabilization Remark VLVI(n - 1) > VLVIn: n = 1 to 15 LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION 1 Preliminary User's Manual U17260EJ3V1UD Time 609 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.44 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected. STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 610 Preliminary User's Manual U17260EJ3V1UD Operation mode CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD = EVDD 5.5 V, AVREF VDD, VSS = EVSS = AVSS = 0 V) (1) Basic characteristics Parameter VDD supply current Note 1 Erase time Symbol IDD Conditions MIN. fXP = 10 MHz (TYP.), 20 MHz (MAX.) TYP. MAX. Unit 4.5 11.0 mA All block Teraca 20 200 ms Block unit Terasa 20 200 ms Write time Twrwa TBD TBD s Number of rewrites per chip Cerwr Retention: 10 years 100 Times Note 2 1 erase + 1 write after erase = 1 rewrite Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one 2. rewrite. Remark fXP: Main system clock oscillation frequency (2) Serial write operation characteristics Parameter Time from RESET to FLMD0 Symbol Conditions MIN. TYP. MAX. Unit TRFCF 4.1 17.1 ms Count execution time TCOUNT 10.8 13.2 ms FLMD0 counter high-/low-level TCH/TCL TC x 0.45 s 12.5 s count start width FLMD0 counter rise/fall time Remark TR/TF These values may change after evaluation. Serial Write Operation RESET VDD 0V TCOUNT TCH FLMD0 VDD 0V TF TRFCF TCL TR TC Preliminary User's Manual U17260EJ3V1UD 611 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) HD D detail of lead end 48 33 49 A3 32 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S A ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c S y A1 S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. 612 Preliminary User's Manual U17260EJ3V1UD L 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 P64GB-50-UEU-1 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP(14x14) HD D detail of lead end 48 49 A3 33 32 c E L Lp HE L1 64 17 16 1 (UNIT:mm) ZE e ZD b x M S A A2 A1 S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 S y ITEM D 0.37 +0.08 -0.07 c 0.17 +0.03 -0.06 L 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE Preliminary User's Manual U17260EJ3V1UD 0.25 b 1.00 P64GC-80-UBS 613 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP(12x12) HD D detail of lead end 48 33 49 32 A3 c E L Lp HE L1 (UNIT:mm) ITEM D 17 64 1 16 ZE e ZD b x M S A A2 S y A1 S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. 614 Preliminary User's Manual U17260EJ3V1UD DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 0.25 b 0.32 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 +5 3 -3 e 0.65 x 0.13 y 0.10 ZD ZE 1.125 1.125 P64GK-65-UET-1 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC TQFP(FINE PITCH)(7x7) HD D detail of lead end 33 32 48 49 A3 c E L HE Lp L1 64 17 16 1 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.20 MAX. A1 0.100.05 A2 1.000.05 A3 b S c L y A1 S NOTE Each lead centerline is located within 0.07 mm of its true position at maximum material condition. Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.40 x 0.07 y 0.08 ZD 0.50 ZE Preliminary User's Manual U17260EJ3V1UD 0.25 0.180.05 0.145 +0.055 -0.045 0.50 0.50 P64GA-40-9EV-1 615 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC FLGA(5x5) x 60x b M S AB A ZE w S A D e ZD 8 7 6 5 3.90 4 3 2 1 B E C D H G F E D C B A y1 S E 3.90 w S B INDEX MARK A S y DETAIL OF C PART S DETAIL OF D PART DETAIL OF E PART R0.170.05 0.700.05 0.550.05 R0.120.05 0.75 0.55 R0.170.05 0.700.05 R0.120.05 0.550.05 0.75 0.55 b (Land pad) 0.340.05 (Aperture of solder resist) 616 0.55 0.75 0.550.05 0.700.05 0.55 0.75 0.550.05 0.700.05 Preliminary User's Manual U17260EJ3V1UD R0.2750.05 R0.350.05 (UNIT:mm) ITEM D DIMENSIONS 5.000.10 E 5.000.10 w 0.20 e 0.50 A 0.910.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 P64FC-50-AA1-1 CHAPTER 31 CAUTIONS FOR WAIT 31.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware. When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes processing, until the correct data is passed. As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Tables 31-1). This must be noted when real-time processing is performed. Preliminary User's Manual U17260EJ3V1UD 617 CHAPTER 31 CAUTIONS FOR WAIT 31.2 Peripheral Hardware That Generates Wait Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Register Access Number of Wait Clocks Hardware Serial interface ASIS0 Read 1 clock (fixed) ASIS6 Read 1 clock (fixed) IICS0 Read 1 clock (fixed) ADM Write 1 to 5 clocks (when fAD = fPRS/2 is selected) ADS Write 1 to 7 clocks (when fAD = fPRS/3 is selected) ADPC Write ADCR Read UART0 Serial interface UART6 Serial interface IIC0 A/D converter 1 to 9 clocks (when fAD = fPRS/4 is selected) 2 to 13 clocks (when fAD = fPRS/6 is selected) 2 to 17 clocks (when fAD = fPRS/8 is selected) 2 to 25 clocks (when fAD = fPRS/12 is selected) The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait clocks can be calculated by the following expression and under the following conditions. <Calculating number of wait clocks> * Number of wait clocks = {(1/fAD) x 2/(1/fCPU)} + 1 * Fraction is truncated if the number of wait clocks 0.5 and rounded up if the number of wait clocks > 0.5. fAD: A/D conversion clock frequency (fPRS/2 to fPRS/12) fCPU: CPU clock frequency fPRS: Peripheral hardware clock frequency fXP: Main system clock frequency <Conditions for maximum/minimum number of wait clocks> * Maximum number of times: Maximum speed of CPU (fXP), lowest speed of A/D conversion clock (fPRS/12) * Minimum number of times: Minimum speed of CPU (fSUB/2), highest speed of A/D conversion clock (fPRS/2) Caution When the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped, do not access the registers listed above using an access method in which a wait request is issued. Remark The clock is the CPU clock (fCPU). 618 Preliminary User's Manual U17260EJ3V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/KE2. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 98 * Windows NTTM * Windows 2000 * Windows XP Preliminary User's Manual U17260EJ3V1UD 619 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator QB-78K0KX2 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debugger * C compiler package * System simulator * Device file * C library source fileNote 1 Control software * Project manager (Windows only)Note 2 Host machine (PC or EWS) USB interface cable Power supply unit In-circuit emulatorNote 3 Flash memory write environment Flash programmer Emulation probe Flash memory write adapter Flash memory Target system Notes 1. 2. The C library source file is not included in the software package. The project manager PM+ is included in the assembler package. The PM+ is only used for Windows. 3. In-circuit emulator QB-78K0KX2 is supplied with integrated debugger ID78K0-QB, simple flash memory programmer PG-FPL3, power supply unit, and USB interface cable. Any other products are sold separately. 620 Preliminary User's Manual U17260EJ3V1UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the on-chip debug emulator QB-78K0MINI Software package * Software package Debugging software Language processing software * Assembler package * Integrated debugger * C compiler package * System simulator * Device file * C library source fileNote 1 Control software * Project manager (Windows only)Note 2 Host machine (PC or EWS) USB interface cable On-chip debug emulatorNote 3 Flash memory write environment Flash programmer Connection cable Flash memory write adapter Flash memory Target connector Target system Notes 1. The C library source file is not included in the software package. 2. The project manager PM+ is included in the assembler package. The PM+ is only used for Windows. 3. The on-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB interface cable, and connection cable. Any other products are sold separately. Preliminary User's Manual U17260EJ3V1UD 621 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package Part number: SxxxxSP78K0 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP78K0 xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780547) (sold separately). <Precaution when using RA78K0 in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxRA78K0 CC78K0 This compiler converts programs written in C language into object codes executable with C compiler package a microcontroller. This compiler should be used in combination with an assembler package and device file (both sold separately). <Precaution when using CC78K0 in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) on Windows. Part number: SxxxxCC78K0 Note 1 DF780547 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (RA78K0, CC78K0, SM+ for 78K0/KX2, and ID78K0-QB) (all sold separately). The corresponding OS and host machine differ depending on the tool to be used. Part number: SxxxxDF780547 CC78K0-L Note 2 This is a source file of the functions that configure the object library included in the C C library source file compiler package. This file is required to match the object library included in the C compiler package to the user's specifications. Part number: SxxxxCC78K0-L Notes 1. The DF780547 can be used in common with the RA78K0, CC78K0, SM+ for 78K0/KX2, and ID78K0QB. 2. 622 The CC78K0-L is not included in the software package (SP78K0). Preliminary User's Manual U17260EJ3V1UD APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxRA78K0 SxxxxCC78K0 SxxxxCC78K0-L xxxx Host Machine AB17 PC-9800 series, BB17 IBM PC/AT compatibles 3P17 HP9000 series 700 3K17 Windows (Japanese version) TM SPARCstation OS TM Supply Medium CD-ROM Windows (English version) HP-UX TM SunOS TM TM Solaris (Rel. 10.10) (Rel. 4.1.4) (Rel. 2.5.1) SxxxxDF780547 xxxx Host Machine OS AB13 PC-9800 series, Windows (Japanese version) BB13 IBM PC/AT compatibles Windows (English version) Supply Medium 3.5-inch 2HD FD A.3 Control Software PM+ This is control software designed to enable efficient user program development in the Project manager Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. <Caution> The project manager is included in the assembler package (RA78K0). It can only be used in Windows. A.4 Flash Memory Writing Tools FlashPro4 Flash memory programmer dedicated to microcontrollers with on-chip flash memory. (part number: FL-PR4, PG-FP4) Flash memory programmer FlashPro4 Simple flash memory programmer dedicated to microcontrollers with on-chip flash (part number: PG-FPL3) memory. Simple flash memory programmer FA-64GB-8EU-A Flash memory writing adapter used connected to the FlashPro4. FA-64GC-8BS-A * FA-64GB-8EU-A: For 64-pin plastic LQFP (GB-UEU type) FA-78F0537GK-UET-MX * FA-64GC-8BS-A: For 64-pin plastic LQFP (GC-UBS type) FA-78F0537GA-9EV-MX * FA-78F0537GK-UET-MX: For 64-pin plastic LQFP (GK-UET type) FA-78F0537FC-AA1-MX * FA-78F0537GA-9EV-MX: For 64-pin plastic TQFP (GA-9EV type) Flash memory writing adapter * FA-78F0537FC-AA1-MX: For 64-pin plastic FLGA (FC-AA1 type) Remark FL-PR4, FA-64GA-8EU-A, FA-64GC-8BS-A, FA-78F0537GK-UET-MX, FA-78F0537GA-9EV-MX, and FA-78F0537FC-AA1-MX are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. Preliminary User's Manual U17260EJ3V1UD 623 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB-78K0KX2 Note 1 QB-78K0KX2 In-circuit emulator This in-circuit emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2. It supports to the integrated debugger (ID78K0-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. QB-144-CA-01 Check pin adapter This check pin adapter is used in waveform monitoring using the oscilloscope, etc. QB-80-EP-01T Emulation probe This emulation probe is flexible type and used to connect the in-circuit emulator and target system. QB-64GB-EA-04T, QB-64GC-EA-03T, QB-64GK-EA-04T, QB-64GA-EA-01T, QB-64FC-EA-01T Exchange adapter This exchange adapter is used to perform pin conversion from the in-circuit emulator to target connector. * QB-64GB-EA-04T: 64-pin plastic LQFP (GB-UEU type) * QB-64GC-EA-03T: 64-pin plastic LQFP (GC-UBS type) * QB-64GK-EA-04T: 64-pin plastic LQFP (GK-UET type) * QB-64GA-EA-01T: 64-pin plastic TQFP (GA-9EV type) * QB-64FC-EA-01T: 64-pin plastic FLGA (FC-AA1 type) QB-64GB-YS-01T, QB-64GC-YS-01T, QB-64GK-YS-01T, QB-64GA-YS-01T Space adapter This space adapter is used to adjust the height between the target system and in-circuit emulator. * QB-64GB-YS-01T: 64-pin plastic LQFP (GB-UEU type) * QB-64GC-YS-01T: 64-pin plastic LQFP (GC-UBS type) * QB-64GK-YS-01T: 64-pin plastic LQFP (GK-UET type) * QB-64GA-YS-01T: 64-pin plastic TQFP (GA-9EV type) QB-64GB-YQ-01T, QB-64GC-YQ-01T, QB-64GK-YQ-01T, QB-64GA-YQ-01T YQ connector This YQ connector is used to connect the target connector and exchange adapter. * QB-64GB-YQ-01T: 64-pin plastic LQFP (GB-UEU type) * QB-64GC-YQ-01T: 64-pin plastic LQFP (GC-UBS type) * QB-64GK-YQ-01T: 64-pin plastic LQFP (GK-UET type) * QB-64GA-YQ-01T: 64-pin plastic TQFP (GA-9EV type) QB-64GB-HQ-01T, QB-64GC-HQ-01T, QB-64GK-HQ-01T, QB-64GA-HQ-01T Mount adapter This mount adapter is used to mount the target device with socket. * QB-64GB-HQ-01T: 64-pin plastic LQFP (GB-UEU type) * QB-64GC-HQ-01T: 64-pin plastic LQFP (GC-UBS type) * QB-64GK-HQ-01T: 64-pin plastic LQFP (GK-UET type) * QB-64GA-HQ-01T: 64-pin plastic TQFP (GA-9EV type) QB-64GB-NQ-01T, QB-64GC-NQ-01T, QB-64GK-NQ-01T, QB-64GA-NQ-01T, QB-64FC-NQ-01T Target connector This target connector is used to mount on the target system. * QB-64GB-NQ-01T: 64-pin plastic LQFP (GB-UEU type) * QB-64GC-NQ-01T: 64-pin plastic LQFP (GC-UBS type) * QB-64GK-NQ-01T: 64-pin plastic LQFP (GK-UET type) * QB-64GA-NQ-01T: 64-pin plastic TQFP (GA-9EV type) * QB-64FC-NQ-01T: 64-pin plastic LQFP (FC-AA1 type) Note The QB-78K0KX2 is supplied with a power supply unit and USB interface cable. As control software, the integrated debugger ID78K0-QB and simple flash memory programmer PG-FPL3 are supplied. 624 Preliminary User's Manual U17260EJ3V1UD APPENDIX A DEVELOPMENT TOOLS Remark The packed contents differ depending on the part number, as follows. Packed Contents In-Circuit Emulator Emulation Probe Exchange Adapter YQ Connector Target Connector QB-64GB-EA-04T QB-64GB-YQ-01T QB-64GB-NQ-01T QB-78K0KX2-T64GC QB-64GC-EA-03T QB-64GC-YQ-01T QB-64GC-NQ-01T QB-78K0KX2-T64GK QB-64GK-EA-04T QB-64GK-YQ-01T QB-64GK-NQ-01T QB-78K0KX2-T64GA QB-64GA-EA-01T QB-64GA-YQ-01T QB-64GA-NQ-01T QB-78K0KX2-T64FC QB-64FC-EA-01T None QB-64FC-NQ-01T Part Number QB-78K0KX2 QB-78K0KX2-ZZZ None QB-80-EP-01T QB-78K0KX2-T64GB A.5.2 When using on-chip debug emulator QB-78K0MINI Note QB-78K0MINI On-chip debug emulator This on-chip debug emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2. It supports the integrated debugger (ID78K0-QB). This emulator should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. Target connector specifications 10-pin general-purpose connector (2.54 mm pitch) Note The QB-78K0MINI is supplied with a USB interface cable and a connection cable. As control software, the integrated debugger ID78K0-QB is supplied. A.6 Debugging Tools (Software) SM+ for 78K0/KX2 The SM+ for 78K0/KX2 is Windows-based software. System simulator It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM+ for 78K0/KX2 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM+ for 78K0/KX2 should be used in combination with the device file (DF780547) (sold separately). Part number: SM780547-B ID78K0-QB This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-QB is Integrated debugger Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part number: SxxxxID78K0-QB Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM780547-B SxxxxID78K0-QB xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Preliminary User's Manual U17260EJ3V1UD Supply Medium CD-ROM 625 APPENDIX B NOTES ON TARGET SYSTEM DESIGN This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0KX2 is used. 15 10.5 10 10 15 13.375 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mounted Note 626 10.5 Figure B-1. For 64-Pin GB Package Note Height can be adjusted by using space adapters (each adds 2.4 mm) Preliminary User's Manual U17260EJ3V1UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN 15 10 15 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note 10 11.85 11.85 Figure B-2. For 64-Pin GC Package Height can be adjusted by using space adapters (each adds 2.4 mm) 15 10.5 10 10.5 10 Figure B-3. For 64-Pin GK Package 15 13.375 17.375 : Exchange adapter area: Components up to 17.45 mm in height can be mountedNote : Emulation probe tip area: Components up to 24.45 mm in height can be mountedNote Note Height can be adjusted by using space adapters (each adds 2.4 mm) Preliminary User's Manual U17260EJ3V1UD 627 APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D converter mode register (ADM) ............................................................................................................................307 A/D port configuration register (ADPC) .......................................................................................................................313 Analog input channel specification register (ADS) ......................................................................................................312 Asynchronous serial interface control register 6 (ASICL6) ..........................................................................................360 Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................330 Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................354 Asynchronous serial interface reception error status register 0 (ASIS0) .....................................................................332 Asynchronous serial interface reception error status register 6 (ASIS6) .....................................................................356 Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................357 [B] Baud rate generator control register 0 (BRGC0) .........................................................................................................333 Baud rate generator control register 6 (BRGC6) .........................................................................................................359 [C] Capture/compare control register 00 (CRC00)............................................................................................................179 Capture/compare control register 01 (CRC01)............................................................................................................179 Clock operation mode select register (OSCCTL) ........................................................................................................137 Clock output selection register (CKS) .........................................................................................................................301 Clock selection register 6 (CKSR6).............................................................................................................................358 [E] 8-bit A/D conversion result register (ADCRH) .............................................................................................................311 8-bit timer compare register 50 (CR50) .......................................................................................................................247 8-bit timer compare register 51 (CR51) .......................................................................................................................247 8-bit timer counter 50 (TM50)......................................................................................................................................247 8-bit timer counter 51 (TM51)......................................................................................................................................247 8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................270 8-bit timer H compare register 00 (CMP00).................................................................................................................265 8-bit timer H compare register 01 (CMP01).................................................................................................................265 8-bit timer H compare register 10 (CMP10).................................................................................................................265 8-bit timer H compare register 11 (CMP11).................................................................................................................265 8-bit timer H mode register 0 (TMHMD0) ....................................................................................................................266 8-bit timer H mode register 1 (TMHMD1) ....................................................................................................................266 8-bit timer mode control register 50 (TMC50)..............................................................................................................250 8-bit timer mode control register 51 (TMC51)..............................................................................................................250 External interrupt falling edge enable register (EGN)..................................................................................................497 External interrupt rising edge enable register (EGP)...................................................................................................497 [I] IIC clock selection register 0 (IICCL0) .........................................................................................................................421 IIC control register 0 (IICC0) .......................................................................................................................................412 628 Preliminary User's Manual U17260EJ3V1UD APPENDIX C REGISTER INDEX IIC flag register 0 (IICF0) ............................................................................................................................................419 IIC function expansion register 0 (IICX0) ....................................................................................................................422 IIC shift register 0 (IIC0)..............................................................................................................................................409 IIC status register 0 (IICS0) ........................................................................................................................................417 Input switch control register (ISC) ...............................................................................................................................362 Internal expansion RAM size switching register (IXS).................................................................................................560 Internal memory size switching register (IMS) ............................................................................................................558 Internal oscillation mode register (RCM).....................................................................................................................141 Interrupt mask flag register 0H (MK0H) ......................................................................................................................495 Interrupt mask flag register 0L (MK0L)........................................................................................................................495 Interrupt mask flag register 1H (MK1H) ......................................................................................................................495 Interrupt mask flag register 1L (MK1L)........................................................................................................................495 Interrupt request flag register 0H (IF0H) .....................................................................................................................493 Interrupt request flag register 0L (IF0L) ......................................................................................................................493 Interrupt request flag register 1H (IF1H) .....................................................................................................................493 Interrupt request flag register 1L (IF1L) ......................................................................................................................493 [K] Key return mode register (KRM) .................................................................................................................................507 [L] Low-voltage detection level selection register (LVIS)..................................................................................................538 Low-voltage detection register (LVIM) ........................................................................................................................539 [M] Main clock mode register (MCM) ................................................................................................................................143 Main OSC control register (MOC) ...............................................................................................................................142 Memory bank select register (BANK)............................................................................................................................90 Multiplication/division data register A0 (MDA0H, MDA0L) ..........................................................................................479 Multiplication/division data register B0 (MDB0)...........................................................................................................481 Multiplier/divider control register 0 (DMUC0) ..............................................................................................................481 [O] Oscillation stabilization time counter status register (OSTC) ..............................................................................144, 509 Oscillation stabilization time select register (OSTS)............................................................................................145, 510 [P] Port mode register 0 (PM0)......................................................................................................................... 125, 187, 392 Port mode register 1 (PM1)................................................................................................. 125, 252, 270, 334, 362, 392 Port mode register 2 (PM2).................................................................................................................................125, 314 Port mode register 3 (PM3).................................................................................................................................125, 252 Port mode register 4 (PM4).........................................................................................................................................125 Port mode register 5 (PM5).........................................................................................................................................125 Port mode register 6 (PM6).................................................................................................................................125, 424 Port mode register 7 (PM7).........................................................................................................................................125 Port mode register 12 (PM12).............................................................................................................................125, 540 Port mode register 14 (PM14).............................................................................................................................125, 303 Port register 0 (P0)......................................................................................................................................................127 Preliminary User's Manual U17260EJ3V1UD 629 APPENDIX C REGISTER INDEX Port register 1 (P1)......................................................................................................................................................127 Port register 2 (P2)......................................................................................................................................................127 Port register 3 (P3)......................................................................................................................................................127 Port register 4 (P4)......................................................................................................................................................127 Port register 5 (P5)......................................................................................................................................................127 Port register 6 (P6)......................................................................................................................................................127 Port register 7 (P7)......................................................................................................................................................127 Port register 12 (P12) ..................................................................................................................................................127 Port register 13 (P13) ..................................................................................................................................................127 Port register 14 (P14) ..................................................................................................................................................127 Prescaler mode register 00 (PRM00) ..........................................................................................................................184 Prescaler mode register 01 (PRM01) ..........................................................................................................................184 Priority specification flag register 0H (PR0H) ..............................................................................................................496 Priority specification flag register 0L (PR0L) ...............................................................................................................496 Priority specification flag register 1H (PR1H) ..............................................................................................................496 Priority specification flag register 1L (PR1L) ...............................................................................................................496 Processor clock control register (PCC) .......................................................................................................................139 Pull-up resistor option register 0 (PU0) .......................................................................................................................128 Pull-up resistor option register 1 (PU1) .......................................................................................................................128 Pull-up resistor option register 3 (PU3) .......................................................................................................................128 Pull-up resistor option register 4 (PU4) .......................................................................................................................128 Pull-up resistor option register 5 (PU5) .......................................................................................................................128 Pull-up resistor option register 6 (PU6) .......................................................................................................................128 Pull-up resistor option register 7 (PU7) .......................................................................................................................128 Pull-up resistor option register 12 (PU12) ...................................................................................................................128 Pull-up resistor option register 14 (PU14) ...................................................................................................................128 [R] Receive buffer register 0 (RXB0) ................................................................................................................................329 Receive buffer register 6 (RXB6) ................................................................................................................................353 Remainder data register 0 (SDR0)..............................................................................................................................479 Reset control flag register (RESF) ..............................................................................................................................529 [S] Serial clock selection register 10 (CSIC10) .................................................................................................................390 Serial clock selection register 11 (CSIC11) .................................................................................................................390 Serial I/O shift register 10 (SIO10) ..............................................................................................................................387 Serial I/O shift register 11 (SIO11) ..............................................................................................................................387 Serial operation mode register 10 (CSIM10) ...............................................................................................................388 Serial operation mode register 11 (CSIM11) ...............................................................................................................388 16-bit timer capture/compare register 000 (CR000) ....................................................................................................173 16-bit timer capture/compare register 001 (CR001) ....................................................................................................173 16-bit timer capture/compare register 010 (CR010) ....................................................................................................173 16-bit timer capture/compare register 011 (CR011) ....................................................................................................173 16-bit timer counter 00 (TM00)....................................................................................................................................172 16-bit timer counter 01 (TM00)....................................................................................................................................172 630 Preliminary User's Manual U17260EJ3V1UD APPENDIX C REGISTER INDEX 16-bit timer mode control register 00 (TMC00) ...........................................................................................................176 16-bit timer mode control register 01 (TMC01) ...........................................................................................................176 16-bit timer output control register 00 (TOC00)...........................................................................................................181 16-bit timer output control register 01 (TOC01)...........................................................................................................181 Slave address register 0 (SVA0).................................................................................................................................409 [T] Timer clock selection register 50 (TCL50) ..................................................................................................................248 Timer clock selection register 51 (TCL51) ..................................................................................................................248 10-bit A/D conversion result register (ADCR)..............................................................................................................310 Transmit buffer register 10 (SOTB10).........................................................................................................................386 Transmit buffer register 11 (SOTB11).........................................................................................................................386 Transmit buffer register 6 (TXB6)................................................................................................................................353 Transmit shift register 0 (TXS0) ..................................................................................................................................329 [W] Watch timer operation mode register (WTM) ..............................................................................................................289 Watchdog timer enable register (WDTE) ....................................................................................................................295 Preliminary User's Manual U17260EJ3V1UD 631 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: 10-bit A/D conversion result register........................................................................................................310 ADCRH: 8-bit A/D conversion result register..........................................................................................................311 ADM: A/D converter mode register....................................................................................................................307 ADPC: A/D port configuration register .................................................................................................................313 ADS: Analog input channel specification register .............................................................................................312 ASICL6: Asynchronous serial interface control register 6......................................................................................360 ASIF6: Asynchronous serial interface transmission status register 6 ..................................................................357 ASIM0: Asynchronous serial interface operation mode register 0........................................................................330 ASIM6: Asynchronous serial interface operation mode register 6........................................................................354 ASIS0: Asynchronous serial interface reception error status register 0...............................................................332 ASIS6: Asynchronous serial interface reception error status register 6...............................................................356 [B] BANK: Memory bank select register .................................................................................................................... 90 BRGC0: Baud rate generator control register 0 .....................................................................................................333 BRGC6: Baud rate generator control register 6 .....................................................................................................359 [C] CKS: Clock output selection register ................................................................................................................301 CKSR6: Clock selection register 6 ........................................................................................................................358 CMP00: 8-bit timer H compare register 00 ............................................................................................................265 CMP01: 8-bit timer H compare register 01 ............................................................................................................265 CMP10: 8-bit timer H compare register 10 ............................................................................................................265 CMP11: 8-bit timer H compare register 11 ............................................................................................................265 CR000: 16-bit timer capture/compare register 000...............................................................................................173 CR001: 16-bit timer capture/compare register 000...............................................................................................173 CR010: 16-bit timer capture/compare register 010...............................................................................................173 CR011: 16-bit timer capture/compare register 011...............................................................................................173 CR50: 8-bit timer compare register 50................................................................................................................247 CR51: 8-bit timer compare register 51................................................................................................................247 CRC00: Capture/compare control register 00 .......................................................................................................179 CRC01: Capture/compare control register 01 .......................................................................................................179 CSIC10: Serial clock selection register 10 .............................................................................................................390 CSIC11: Serial clock selection register 11 .............................................................................................................390 CSIM10: Serial operation mode register 10............................................................................................................388 CSIM11: Serial operation mode register 11............................................................................................................388 [D] DMUC0: Multiplier/divider control register 0 ...........................................................................................................481 [E] EGN: External interrupt falling edge enable register .........................................................................................497 EGP: External interrupt rising edge enable register ..........................................................................................497 632 Preliminary User's Manual U17260EJ3V1UD APPENDIX C REGISTER INDEX [I] IF0H: Interrupt request flag register 0H.............................................................................................................493 IF0L: Interrupt request flag register 0L .............................................................................................................493 IF1H: Interrupt request flag register 1H.............................................................................................................493 IF1L: Interrupt request flag register 1L .............................................................................................................493 IIC0: IIC shift register 0 ....................................................................................................................................409 IICC0: IIC control register 0 ................................................................................................................................412 IICCL0: IIC clock selection register 0 ...................................................................................................................421 IICF0: IIC flag register 0.....................................................................................................................................419 IICS0: IIC status register 0 .................................................................................................................................417 IICX0: IIC function expansion register 0.............................................................................................................422 IMS: Internal memory size switching register ..................................................................................................558 ISC: Input switch control register.....................................................................................................................362 IXS: Internal expansion RAM size switching register ......................................................................................560 [K] KRM: Key return mode register.........................................................................................................................507 [L] LVIM: Low-voltage detection register ................................................................................................................538 LVIS: Low-voltage detection level selection register .........................................................................................539 [M] MCM: Main clock mode register ........................................................................................................................143 MDA0H: Multiplication/division data register A0 ....................................................................................................479 MDA0L: Multiplication/division data register A0 ....................................................................................................479 MDB0: Multiplication/division data register B0 ....................................................................................................480 MK0H: Interrupt mask flag register 0H ................................................................................................................495 MK0L: Interrupt mask flag register 0L.................................................................................................................495 MK1H: Interrupt mask flag register 1H ................................................................................................................495 MK1L: Interrupt mask flag register 1L.................................................................................................................495 MOC: Main OSC control register .......................................................................................................................142 [O] OSCCTL: Clock operation mode select register ......................................................................................................137 OSTC: Oscillation stabilization time counter status register ........................................................................144, 509 OSTS: Oscillation stabilization time select register .....................................................................................145, 510 [P] P0: Port register 0..........................................................................................................................................127 P1: Port register 1..........................................................................................................................................127 P2: Port register 2..........................................................................................................................................127 P3: Port register 3..........................................................................................................................................127 P4: Port register 4..........................................................................................................................................127 P5: Port register 5..........................................................................................................................................127 P6: Port register 6..........................................................................................................................................127 P7: Port register 7..........................................................................................................................................127 P12: Port register 12........................................................................................................................................127 Preliminary User's Manual U17260EJ3V1UD 633 APPENDIX C REGISTER INDEX P13: Port register 13 ........................................................................................................................................127 P14: Port register 14 ........................................................................................................................................127 PCC: Processor clock control register...............................................................................................................139 PM0: Port mode register 0 ................................................................................................................125, 187, 392 PM1: Port mode register 1 ........................................................................................125, 252, 270, 334, 362, 392 PM2: Port mode register 2 ........................................................................................................................125, 314 PM3: Port mode register 3 ........................................................................................................................125, 252 PM4: Port mode register 4 ................................................................................................................................125 PM5: Port mode register 5 ................................................................................................................................125 PM6: Port mode register 6 ........................................................................................................................125, 424 PM7: Port mode register 7 ................................................................................................................................125 PM12: Port mode register 12 ......................................................................................................................125, 540 PM14: Port mode register 14 ......................................................................................................................125, 303 PR0H: Priority specification flag register 0H .......................................................................................................496 PR0L: Priority specification flag register 0L ........................................................................................................496 PR1H: Priority specification flag register 1H .......................................................................................................496 PR1L: Priority specification flag register 1L ........................................................................................................496 PRM00: Prescaler mode register 00 .....................................................................................................................184 PRM01: Prescaler mode register 01 .....................................................................................................................184 PU0: Pull-up resistor option register 0 ..............................................................................................................128 PU1: Pull-up resistor option register 1 ..............................................................................................................128 PU3: Pull-up resistor option register 3 ..............................................................................................................128 PU4: Pull-up resistor option register 4 ..............................................................................................................128 PU5: Pull-up resistor option register 5 ..............................................................................................................128 PU7: Pull-up resistor option register 7 ..............................................................................................................128 PU12: Pull-up resistor option register 12 ............................................................................................................128 PU14: Pull-up resistor option register 14 ............................................................................................................128 [R] RCM: Internal oscillation mode register .............................................................................................................141 RESF: Reset control flag register........................................................................................................................529 RXB0: Receive buffer register 0 .........................................................................................................................329 RXB6: Receive buffer register 6 .........................................................................................................................353 [S] SDR0: Remainder data register 0 .......................................................................................................................479 SIO10: Serial I/O shift register 10 ........................................................................................................................387 SIO11: Serial I/O shift register 11 ........................................................................................................................387 SOTB10: Transmit buffer register 10 ......................................................................................................................386 SOTB11: Transmit buffer register 11 ......................................................................................................................386 SVA0: Slave address register 0..........................................................................................................................409 [T] TCL50: Timer clock selection register 50 .............................................................................................................248 TCL51: Timer clock selection register 51 .............................................................................................................248 TM00: 16-bit timer counter 00.............................................................................................................................172 TM01: 16-bit timer counter 01.............................................................................................................................172 634 Preliminary User's Manual U17260EJ3V1UD APPENDIX C REGISTER INDEX TM50: 8-bit timer counter 50 ..............................................................................................................................247 TM51: 8-bit timer counter 51 ..............................................................................................................................247 TMC00: 16-bit timer mode control register 00.......................................................................................................176 TMC01: 16-bit timer mode control register 01.......................................................................................................176 TMC50: 8-bit timer mode control register 50.........................................................................................................250 TMC51: 8-bit timer mode control register 51.........................................................................................................250 TMCYC1: 8-bit timer H carrier control register 1 ......................................................................................................270 TMHMD0: 8-bit timer H mode register 0...................................................................................................................266 TMHMD1: 8-bit timer H mode register 1...................................................................................................................266 TOC00: 16-bit timer output control register 00......................................................................................................181 TOC01: 16-bit timer output control register 01......................................................................................................181 TXB6: Transmit buffer register 6 ........................................................................................................................353 TXS0: Transmit shift register 0...........................................................................................................................329 [W] WDTE: Watchdog timer enable register ..............................................................................................................295 WTM: Watch timer operation mode register ......................................................................................................289 Preliminary User's Manual U17260EJ3V1UD 635 APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/7) Page Description CHAPTER 1 OUTLINE pp. 17, 18 Addition of Note on a product with on-chip debug function to and modification of operating ambient temperature in 1.1 Features p. 18 Addition of special grade products supporting automotive equipment to 1.2 Applications p. 19 Modification of 1.3 Ordering Information p. 23, 24 Addition of 64-pin plastic TQFP (7x7), 64-pin plastic FLGA (5x5), Note to and modification of Caution 1 in 1.4 Pin Configuration (Top View) pp. 27, 28 Modification of the following items on the function list in 1.5 78K0/Kx2 Series Lineup * Supply voltage range of internal low-speed oscillation clock * Detection voltage of POC * Operating ambient temperature p. 29 Addition of pin to "On-chip debug" in 1.6 Block Diagram pp. 30, 31 Modification of the following items in 1.7 Outline of Functions * Oscillation frequency range of high-speed system clock * Supply voltage range of internal low-speed oscillation clock * Operating ambient temperature * Package p. 31 Modification of outline of timer in 1.7 Outline of Functions CHAPTER 2 PIN FUNCTIONS p. 32 Modification of Table 2-1 Pin I/O Buffer Power Supplies pp. 32 to 35 Addition of Note to 2.1 Pin Function List p. 41 Modification of descriptions in 2.2.12 AVREF p. 41 Addition of Caution to 2.2.15 REGC p. 42 Modification of descriptions in 2.2.16 VDD and EVDD, and 2.2.17 VSS and EVSS p. 44 Modification of recommended connection of unused pins of P121/X1, P122/X2/EXCLK, P123/XT1, and P124/XT2/EXCLKS in Table 2-2 Pin I/O Circuit Types CHAPTER 3 CPU ARCHITECTURE p. 47 Addition of Caution 2 to 3.1 Memory Space p. 47 Modification of Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) pp. 48 to 55 Modification of Figure 3-1 Memory Map (PD78F0531) to Figure 3-8 Memory Map (PD78F0537D) p. 57 Modification of description in (3) Option byte area and (5) On-chip debug security ID setting area (PD78F0537D only) in 3.1.1 p. 58 Modification of description in 3.1.2 Memory bank (PD78F0536, 78F0537, and 78F0537D only) pp. 65, 66 Addition of Note to Figure 3-14 Correspondence Between Data Memory and Addressing (PD78F0536) and Figure 3-15 Correspondence Between Data Memory and Addressing (PD78F0537, 78F0537D) p. 77 Addition to description in 3.3 Instruction Address Addressing p. 78 Addition to description in 3.3.2 Immediate addressing p. 79 Addition to description in 3.3.3 Table indirect addressing p. 82 Addition to description in 3.4.3 Direct addressing p. 83 Modification of [Description example] in 3.4.4 Short direct addressing 636 Preliminary User's Manual U17260EJ3V1UD APPENDIX D REVISION HISTORY (2/7) Page Description p. 85 Addition to description in 3.4.6 Register indirect addressing p. 86 Addition to description in 3.4.7 Based addressing p. 87 Addition to description in 3.4.8 Based indexed addressing CHAPTER 4 MEMORY BANK SELECT FUNCTION (PD78F0536, 78F0537, AND 78F0537D ONLY) p. 89 Addition of chapter CHAPTER 5 PORT FUNCTIONS p. 99 Modification of Table 5-1 Pin I/O Buffer Power Supplies p. 102 Addition of Caution to 5.2.1 Port 0 p. 102 Modification of Figure 5-2 Block Diagram of P00 p. 103 Modification of Figure 5-3 Block Diagram of P01 p. 104 Modification of Figure 5-4 Block Diagram of P02 p. 105 Modification of Figure 5-5 Block Diagram of P03, P05 p. 106 Modification of Figure 5-6 Block Diagram of P04 p. 107 Modification of Figure 5-7 Block Diagram of P06 p. 108 Addition of Caution to 5.2.2 Port 1 p. 113 Addition of description to 5.2.3 Port 2 and addition of Table 5-4 Setting Functions of P20/ANI0 to P27/ANI7 Pins p. 121 Addition of Remark to and modification of Caution in 5.2.9 Port 12 p. 121 Modification of Figure 5-22 Block Diagram of P120 p. 122 Modification of Figure 5-23 Block Diagram of P121 to P124 p. 123 Addition of a figure to Remark in 5.2.10 Port 13 p. 129 Addition of (4) A/D port configuration register (ADPC) to 5.3 Registers Controlling Port Function pp. 132, 133 Addition of Remark 2 and Notes 1 and 2 to Table 5-5 Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) CHAPTER 6 CLOCK GENERATOR p. 134 Modification of oscillation frequency range X1 oscillator and external main system clock in 6.1 (1) Main system clock p. 135 Addition to description in 6.1 (3) Internal low-speed oscillation clock p. 136 Modification of Figure 6-1 Block Diagram of Clock Generator p. 139 Modification of Figure 6-3 Format of Processor Clock Control Register (PCC) p. 140 Addition of 6.3 (3) Setting of operation mode for subsystem clock pin p. 145 Modification of description in 6.3 (8) Oscillation stabilization time select register (OSTS) p. 146 Modification of oscillation frequency range in 6.4.1 X1 oscillator p. 149 Modification of description in 6.4.3 When subsystem clock is not used p. 151 Addition of Figure 6-12 Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) p. 152 Addition of Figure 6-13 Clock Generator Operation When Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1)) p. 153 Modification of 6.6.1 Controlling high-speed system clock p. 156 Modification of 6.6.2 Example of controlling internal high-speed oscillation clock p. 158 Modification of 6.6.3 Example of controlling subsystem clock p. 160 Modification of description in Table 6-4 Clocks Supplied to CPU and Peripheral Hardware, and Register Setting Preliminary User's Manual U17260EJ3V1UD 637 APPENDIX D REVISION HISTORY (3/7) Page Description p. 161 Addition of Remark to Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) pp. 162 to 165 Modification of the following items in Table 6-5 CPU Clock Transition and SFR Register Setting Examples (3) CPU operating with subsystem clock (D) after reset release (A) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) p. 166 Modification of Table 6-6 Changing CPU Clock p. 167 Addition of 6.6.8 Time required for switchover of CPU clock and main system clock p. 168 Addition of 6.6.9 Conditions before clock oscillation is stopped p. 169 Addition of 6.6.10 Peripheral Hardware and Source Clocks CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 p. 170 Revision of chapter CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 p. 247 Modification of description in 8.2 (2) 8-bit timer compare register 5n (CR5n) CHAPTER 9 8-BIT TIMERS H0 AND H1 p. 264 Modification of Figure 9-2 Block Diagram of 8-Bit Timer H1 p. 265 Modification of description in (1) 8-bit timer H compare register 0n (CMP0n) and (2) 8-bit time r H compare register 1n (CMP1n) in 9.2 p. 269 Modification of Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1) p. 279 Modification of Figure 9-12 (e) Operation by changing CMP1n (CMP1n = 02H 03H, CMP0n = A5H) p. 280 Modification of description in 9.4.3 Carrier generator operation (8-bit timer H1 only) p. 281 Addition of <3> to Figure 9-13 Transfer Timing p. 282 Addition of <8> to Setting in 9.4.3 pp. 284, 285 Modification of (a) Operation when CMP01 = N, CMP11 = N and (b) Operation when CMP01 = N, CMP11 = M in Figure 9-15 p. 286 Modification of description in Figure 9-15 (c) Operation when CMP11 is changed CHAPTER 11 WATCHDOG TIMER p. 293 Modification of description in 11.1 Functions of Watchdog Timer pp. 296, 297 Addition to description in and addition of Caution 4 to 11.4.1 Controlling operation of watchdog timer CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER p. 302 Addition of Note 1 and Cautions 1 and 2 to Figure 12-2 Format of Clock Output Selection Register (CKS) CHAPTER 13 A/D CONVERTER pp. 305, 306 Modification of the following items in 13.2 Configuration of A/D Converter (2) Sample & hold circuit (3) Series resistor string (5) Successive approximation register (SAR) (9) AVREF pin p. 309 Addition to Caution 1 in and addition of Caution 4 to Table 13-2 A/D Conversion Time Selection p. 312 Modification of Cautions 2 and 3 in Figure 13-8 Format of Analog Input Channel Specification Register (ADS) p. 313 Modification of description in 13.3 (5) A/D port configuration register (ADPC) p. 313 Modification of Cautions 1 and 2 in Figure 13-9 Format of A/D Port Configuration Register (ADPC) 638 Preliminary User's Manual U17260EJ3V1UD APPENDIX D REVISION HISTORY (4/7) Page Description p. 314 Modification of Table 13-3 Setting Functions of ANI0/P20 to ANI7/P27 Pins p. 315 Modification of 13.4.1 Basic operations of A/D converter p. 316 Modification of description in Figure 13-11 Basic Operation of A/D Converter p. 317 Modification of expression in 13.4.2 Input voltage and conversion results pp. 318, 319 Modification of description in 13.4.3 A/D converter operation mode pp. 322, 323, 325 Modification of the description of the following items in 13.6 Cautions for A/D Converter (1) Operating current in STOP mode (4) Noise countermeasures (6) Input impedance of ANI0 to ANI7 pins (11) Internal equivalent circuit CHAPTER 14 SERIAL INTERFACE UART0 p. 326 Addition of maximum transfer rate and Caution 4 to 14.1 (2) Asynchronous serial interface (UART) mode p. 329 Addition of Caution 1 to 14.2 (3) Transmit shift register 0 (TXS0) p. 331 Addition of Caution 5 to Figure 14-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) p. 332 Modification of description in 14.3 (2) Asynchronous serial interface reception error status register 0 (ASIS0) p. 340 Modification of Caution 1 in Figure 14-9 Reception Completion Interrupt Request Timing p. 343 Addition of Table 14-4 Set Value of TPS01 and TPS00 CHAPTER 15 SERIAL INTERFACE UART6 p. 347 Addition of maximum transfer rate and Cautions 4 and 5 to 15.1 (2) Asynchronous serial interface (UART) mode p. 348 Modification of Figure 15-1 LIN Transmission Operation p. 349 Modification of Figure 15-2 LIN Reception Operation p. 353 Addition of Caution 3 to 15.2 (3) Transmit buffer register 6 (TXB6) p. 355 Addition of Cautions 4 and 5 to Figure 15-5 Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) p. 356 Modification of description in 15.3 (2) Asynchronous serial interface reception error status register 6 (ASIS6) p. 361 Addition of Caution 6 to Figure 15-10 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) p. 362 Modification of description in 15.3 (7) Input switch control register (ISC) p. 373 Modification of Caution 1 in 15.4.2 (2) (e) Normal reception CHAPTER 16 SERIAL INTERFACE CSI10, CSI11 p. 385 Modification of Figure 16-1 Block Diagram of Serial Interface CSI10 p. 386 Modification of Figure 16-2 Block Diagram of Serial Interface CSI11 p. 386 Modification of Caution 2 in 16.2 (1) Transmit buffer register 1n (SOTB1n) p. 387 Modification of Caution 2 in 16.2 (2) Serial I/O shift register 1n (SIO1n) p. 388 Modification of Note 2 in Figure 16-3 Format of Serial Operation Mode Register 10 (CSIM10) p. 389 Modification of Note 2 in Figure 16-4 Format of Serial Operation Mode Register 11 (CSIM11) p. 390 Modification of Caution 2 in Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10) p. 391 Modification of Caution 2 in Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11) p. 393 Modification of Note 1 of CSIM10 and CSIM11 in 16.4.1 (1) Register used Preliminary User's Manual U17260EJ3V1UD 639 APPENDIX D REVISION HISTORY (5/7) Page pp. 401, 402 Description Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 to Figure 16-11 Output Operation of First Bit pp. 403, 404 Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n = 1 in Figure 16-12 Output Value of SO1n Pin (Last Bit) CHAPTER 17 SERIAL INTERFACE IIC0 p. 407 p. 409 Modification of Figure 17-1 Block Diagram of Serial Interface IIC0 Addition of Caution 2 to 17.2 (1) IIC shift register 0 (IIC0) and addition to description in (2) Slave address register 0 (SVA0) p. 410 Addition of 17.2 (13) Stop condition generator p. 413 Addition of description to IICE0 and addition of Caution to Figure 17-5 Format of IIC Control Register 0 (IICC0) (1/4) p. 414 Addition of Note 2 to Figure 17-5 Format of IIC Control Register 0 (IICC0) (2/4) p. 415 Addition of description to STT0 in Figure 17-5 Format of IIC Control Register 0 (IICC0) (3/4) p. 420 Addition of clearing condition to STCF and IICBSY in Figure 17-7 Format of IIC Flag Register 0 (IICF0) p. 421 Modification of description in 17.3 (4) IIC clock selection register 0 (IICCL0) pp. 422, 423 Modification of description in 17.3 (6) I C transfer clock setting method p. 423 Modification of Table 17-2 Selection Clock Setting p. 428 Addition of cause that ACK is not returned to 17.5.4 Acknowledge (ACK) p. 432 Addition of 17.5.7 Canceling wait p. 437 Modification of Table 17-6 Wait Periods and Figure 17-20 Communication Reservation Timing p. 440 Modification of Table 17-7 Wait Periods pp. 440, 441 Addition of (4) to (6) to 17.5.15 Other cautions pp. 442, 443 2 Modification of 17.5.16 (1) Master operation (single-master system) and (2) Master operation (multimaster system) pp. 447, 448 Modification of Figure 17-25 Slave Operation Flowchart (1) and Figure 17-26 Slave Operation Flowchart (2) p. 450 Addition of Note to (a) (i) When WTIM0 = 0 to and modification of (ii) When WTIM0 = 1 in 17.5.17 (1) Master device operation p. 451 Addition of Notes 1 to 3 to (b) (i) When WTIM0 = 0 in 17.5.17 (1) Master device operation p. 452 Addition of Note to (c) (i) When WTIM0 = 0 in 17.5.17 (1) Master device operation pp. 456, 460, 466, Modification of the value of the following items of IICS0 register in 17.5.17 469 (2) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) (2) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code)) (3) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not extension code)) (3) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not extension code)) (6) (d) (ii) Extension code (6) (e) When loss occurs due to stop condition during data transfer (6) (h) (ii) When WTIM0 = 1 pp. 461, 463 Addition of description to 17.5.17 (5) Arbitration loss operation (operation as slave after arbitration loss) and (6) Operation when arbitration loss occurs (no communication after arbitration loss) 640 Preliminary User's Manual U17260EJ3V1UD APPENDIX D REVISION HISTORY (6/7) Page pp. 467 to 469 Description Addition of description when (i) When WTIM0 = 0 to the following items in 17.5.17 (6) Operation when arbitration loss occurs (no communication after arbitration loss) (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition pp. 471 to 476 Modification of Figure 17-27 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) and Figure 17-28 Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) CHAPTER 18 MULTIPLIER/DIVIDER (PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) p. 485 Modification of Figure 18-7. Timing Chart of Division Operation (DCBA2586H / 0018H) CHAPTER 21 STANDBY FUNCTION p. 508 Modification of Caution 3 in 21.1.1 Standby function p. 510 Modification of description in 21.1.2 (2) Oscillation stabilization time select register (OSTS) pp. 512, 513 Addition of clock output and buzzer output to items in and addition of Note to Table 21-1 Operating Statuses in HALT Mode p. 515 p. 517 Modification of Figure 21-4 HALT Mode Release by Reset Addition of clock output and buzzer output to items in and addition of Note to Table 21-3 Operating Statuses in STOP Mode p. 518 Modification of Figure 21-5 Operation Timing When STOP Mode Is Released p. 520 Modification of Figure 21-7 STOP Mode Release by Reset CHAPTER 22 RESET FUNCTION p. 523 Modification of Figure 22-2 Timing of Reset by RESET Input p. 523 Modification of Figure 22-3 Timing of Reset Due to Watchdog Timer Overflow p. 524 Modification of Figure 22-4 Timing of Reset in STOP Mode by RESET Input p. 525 Addition of clock output and buzzer output to items in Table 22-1 Operation Statuses During Reset Period p. 528 Modification of table in Note of Table 22-2 Hardware Statuses After Reset Acknowledgment (3/3) CHAPTER 23 POWER-ON-CLEAR CIRCUIT p. 530 Addition of description of 2.7 V/1.59 V POC mode to 23.1 Functions of Power-on-Clear Circuit p. 531 Modification of 23.3 Operation of Power-on-Clear Circuit p. 534 Modification of Figure 23-3 Example of Software Processing After Reset Release (1/2) CHAPTER 24 LOW-VOLTAGE DETECTOR p. 536 Modification of Figure 24-1 Block Diagram of Low-Voltage Detector p. 539 Modification of Figure 24-3 Format of Low-Voltage Detection Level Selection Register (LVIS) p. 543 Addition of (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 24-5 Timing of LowVoltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) pp. 547, 548 Modification of (1) In 1.59 V POC mode (option byte: POCMODE = 0) in and addition of (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 24-7 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) p. 550 Modification of Figure 24-8 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) p. 552 Modification of Figure 24-9 Example of Software Processing After Reset Release (1/2) Preliminary User's Manual U17260EJ3V1UD 641 APPENDIX D REVISION HISTORY (7/7) Page Description CHAPTER 25 OPTION BYTE p. 554 pp. 555, 556 Modification of description in 25.1 Functions of Option Bytes Modification of Note in and addition of setting of area 0081H/1081H to 0084H/1084H to Figure 25-1 Format of Option Byte p. 557 Modification of description example of software for setting the option bytes CHAPTER 26 FLASH MEMORY p. 558 Addition of Caution to Figure 26-1 Format of Internal Memory Size Switching Register (IMS) p. 560 Addition of Caution to Figure 26-2 Format of Internal Expansion RAM Size Switching Register (IXS) p. 562 Modification of value of VDD in Figure 26-3 Example of Wiring Adapter for Flash Memory Writing in 3Wire Serial I/O (CSI10) Mode p. 563 Modification of value of VDD in Figure 26-4 Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode pp. 564, 565 Modification of transfer rate in (1) CSI10 and (2) UART6 in 26.5 p. 570 Modification of transfer rate in Speed column of Table 26-7 Communication Modes p. 572 Addition of 26.8 Security Settings p. 576 Modification of 26.9.1 Boot swap function p. 577 Modification of Figure 26-18 Boot Swap Function CHAPTER 27 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY) p. 578 Revision of chapter CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) p. 593 Revision of chapter CHAPTER 30 PACKAGE DRAWINGS pp. 612 to 616 Addition of package drawing CHAPTER 31 CAUTIONS FOR WAIT p. 618 Modification of <Conditions for maximum/minimum number of wait clocks> of A/D converter in Table 31-1 Registers That Generate Wait and Number of CPU Wait Clocks APPENDIX A DEVELOPMENT TOOLS p. 621 Addition of (2) When using the on-chip debug emulator QB-78K0MINI to Figure A-1 Development Tool Configuration p. 625 Addition of A.5.2 When using on-chip debug emulator QB-78K0MINI APPENDIX B NOTES ON TARGET SYSTEM DESIGN p. 626 Addition of chapter APPENDIX D REVISION HISTORY p. 636 642 Addition of chapter Preliminary User's Manual U17260EJ3V1UD APPENDIX D REVISION HISTORY D.2 Revision History up to Previous Edition Revisions up to the previous edition are shown below. The "Applied to:" column indicates the chapter in each edition to which the revision was applied. (1/2) Edition 2nd edition Description Applied to Addition of only PD78F0537D as on-chip debug function model Throughout Addition of Caution 3 to 1.4 Pin Configuration (Top View) CHAPTER 1 OUTLINE Addition of description of EXSCL0 to (2) Non-port pins in 2.1 Pin Function List CHAPTER 2 PIN Addition of Caution to (2) Control mode in 2.2.3 P20 to P27 (port 2) FUNCTIONS Addition of description to (c) EXSCL0 of (2) Control mode in 2.2.7 P60 to P63 (port 6) Addition of Note 2 to Table 2-2 Pin I/O Circuit Types Addition of Cautions 1, 2, and 3 to 3.1.2 Bank area (PD78F0536, 78F0537, and CHAPTER 3 CPU 78F0537D only) ARCHITECTURE Deletion of descriptions of the FLPMC, PFCMD, and PFS registers Addition of Remark to 4.2.7 Port 6 Modification of output latch setting of P60 and P61 in Table 4-4 Settings of Port CHAPTER 4 PORT FUNCTIONS Mode Register and Output Latch When Using Alternate Function Addition of Cautions 2 and 3 to Figure 5-6 Format of Clock Operation Mode CHAPTER 5 CLOCK Select Register (OSCCTL) GENERATOR 6.4.6 One-shot pulse output operation CHAPTER 6 16-BIT * Modification of Caution 1 in (1) One-shot pulse output with software trigger * Modification of Caution in (2) One-shot pulse output with external trigger TIMER/EVENT COUNTERS 00 AND 01 Modification of (a) One-shot pulse output by software and (b) One-shot pulse output with external trigger of (5) Re-triggering one-shot pulse in 6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 Modification of Caution in (6) Asynchronous serial interface control register 6 CHAPTER 14 SERIAL (ASICL6) of 14.3 Registers Controlling Serial Interface UART6 INTERFACE UART6 Modification of Cautions 1, 2, and 4 in Figure 14-10 Format of Asynchronous Serial Interface Control Register 6 (ASICL6) Modification of description in (7) Port mode register 6 (PM6) of 16.3 Registers to CHAPTER 16 SERIAL Control Serial Interface IIC0 INTERFACE IIC0 Addition of "WREL0 = WTIM0 = 1" to "ACKE0 = 0" in Figure 16-23 Master Operation Flowchart (1) and Figure 16-24 Master Operation Flowchart (2) Modification of 20.2.1 HALT mode Addition of Caution 4 to Table 20-3 Operating Statuses in STOP Mode CHAPTER 20 STANDBY FUNCTION Addition of Note to Figure 22-2 Timing of Internal Reset Signal Generation in CHAPTER 22 POWER- Power-on-Clear Circuit ON-CLEAR CIRCUIT Change of value of operation stabilization time in CHAPTER 23 LOW-VOLTAGE CHAPTER 23 LOW- DETECTOR to 10 s (TYP.) and addition of Note "This value may change after evaluation." VOLTAGE DETECTOR Modification of transfer rate in 25.6 (2) UART6 CHAPTER 25 FLASH Modification of transfer rate and deletion of Notes 2 in Speed column of UART in MEMORY Table 25-7. Communication Modes Modification of description in 25.9 Flash Memory Programming by Self-Writing Preliminary User's Manual U17260EJ3V1UD 643 APPENDIX D REVISION HISTORY (2/2) Edition 2nd edition Description Total revision of CHAPTER 26 ON-CHIP DEBUG FUNCTION (PD78F0537D ONLY) Applied to CHAPTER 26 ONCHIP DEBUG FUNCTION (PD78F0537D ONLY) Total revision of CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET) CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET) Total revision of APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS 644 Preliminary User's Manual U17260EJ3V1UD