Rev.3.00 Dec 27, 2006 page 1 of 6
2SK2569
Silicon N Channel MOS FET REJ03G1018-0300
Rev.3.00
Dec 27, 2006
Application
High speed power switching
Features
• Low on-resistance.
• RDS(on) = 2.6 Ω max. (at VGS = 4 V, ID = 100 mA)
• 2.5 V gate drive devi ce.
• Small package (MPAK).
Outline
RENESAS Package code: PLSP0003ZB-A
(Package name: MPAK)
1. Source
2. Gate
3. Drain
S
D
G
2
1
3
Note: Marking is "ZN–"
2SK2569
Rev.3.00 Dec 27, 2006 page 2 of 6
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 50 V
Gate to source voltage VGSS ±20 V
Drain current ID 0.2 A
Drain peak current ID(pulse)*1 0.4 A
Channel dissipation Pch*2 150 mW
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW ≤ 10 µs, duty cycle ≤ 1 %
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 50 — — V ID = 100 µA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0
Zero gate voltage drain current IDSS — — 1.0 µA VDS = 40 V, VGS = 0
Gate to source leak current IGSS — — ±2.0 µA VGS = ±16 V, VDS = 0
Gate to source cutoff voltage VGS(off) 0.5 — 1.5 V ID = 10 µA, VDS = 5 V
Static drain to source on state
resistance RDS(on)1 — 2.0 2.6 Ω I
D = 100 mA, VGS = 4 V*2
Static drain to source on state
resistance RDS(on)2 — 3.1 5.0 Ω I
D = 40 mA, VGS = 2.5 V*2
Forward transfer admittance |yfs| 0.13 0.23 — S ID = 100 mA, VDS = 10 V
Input capacitance Ciss — 14.0 — pF
Output capacitance Coss — 17.2 — pF
Reverse transfer capacitance Crss — 1.73 — pF
VDS = 10 V, VGS = 0,
f = 1 MHz
Turn-on delay time td(on) — 40 — ns
Rise time tr — 86 — ns
Turn-off delay time td(off) — 1120 — ns
Fall time tf — 430 — ns
VGS = 10 V, ID = 100 mA,
RL = 300 Ω
Note: 2. Pulse test
2SK2569
Rev.3.00 Dec 27, 2006 page 3 of 6
Main Characteristics
Drain to Source Voltage V
DS
(V)
Drain Current I
D
(A)
Maximum Safe Operation Area
Drain to Source Voltage V
DS
(V)
Typical Output Characteristics
Drain Current I
D
(A)
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
Typical Transfer Characteristics
Gate to Source Voltage V
GS
(V)
Drain to Source Saturation Voltage V
DS (on)
(V)
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
Drain Current I
D
(A)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
Static Drain to Source on State
Resistance vs. Drain Current
1
0.3
0.1
0.03
0.01
0.003
0.001
0.1 0.3 1 3 10 30 100
Ta = 25°C
1 ms
PW = 10 ms
DC Operation
Operation in
this area is
limited by R
DS(on)
0.20
0.16
0.12
0.08
0.04
0246810
10 V 4 V
2.5 V 2.3 V
2 V
V
GS
= 1.5 V
Pulse Test
0.20
0.16
0.12
0.08
0.04
0
Tc = 75°C
25°C
–25°C
12345
V
DS
= 5 V
Pulse Test
0.5
0.4
0.3
0.2
0.1
0246810
I
D
= 0.2 A
0.1 A
0.05 A
Pulse Test
20
10
2
5
1
0.2
0.5
0.01 0.02 0.05 0.1 0.2 0.5 1
V
GS
= 2.5 V
4 V
Pulse Test
200
150
100
50
050 100 150 200
Case Temperature Tc (°C)
Channel Dissipation Pch (mW)
Power vs. Temperature Derating
2SK2569
Rev.3.00 Dec 27, 2006 page 4 of 6
Case Temperature T
C
(°C)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
Static Drain to Source on State
Resistance vs. Temperature
Drain Current I
D
(A)
Forward Transfer Admittance yfs (S)
Forward Transfer Admittance
vs. Drain Current
10
8
6
4
2
–40 0 40 80 120 160
0
I
D
= 0.2 A
0.1 A
0.05 A
V
GS
= 2.5 V
4 V
0.05, 0.1 A
Pulse Test
0.2 A
0.5
0.2
0.1
0.02
0.05
0.01
0.005
0.001 0.003 0.01 0.03 0.1 0.3 1
25°C
Tc = –25°C
75°C
V
DS
= 10 V
Pulse Test
0 10 20304050
100
30
10
3
1
0.3
0.1
Ciss
Coss
Crss
V
GS
= 0
f = 1 MHz
Capacitance C (pF)
Drain to Source Voltage V
DS
(V)
Typical Capacitance vs.
Drain to Source Voltage
tf
tr
td(on)
td(off)
0.01 0.02 0.05 0.1 0.2 0.5 1
V
GS
= 10 V
V
DD
= 30 V
PW = 5 µs
duty < 1 %
2
1
0.2
0.5
0.1
0.02
0.05
Drain Current I
D
(A)
Switching Time t (µs)
Switching Characteristics
0.20
0.16
0.12
0.08
0.04
00.2 0.4 0.6 0.8 1.0
V
GS
= 0
–5 V
Pulse Test
Source to Drain Voltage V
SD
(V)
Reverse Drain Current I
DR
(A)
Reverse Drain Current vs.
Source to Drain Voltage
2SK2569
Rev.3.00 Dec 27, 2006 page 5 of 6
Vin Monitor
D.U.T.
Vin
10 V
R
L
V
DD
= 30 V
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
50 Ω
90%
10%
tf
WaveformSwitching Test Circuit
2SK2569
Rev.3.00 Dec 27, 2006 page 6 of 6
Package Dimensions
D
eA
AA
b
xSA
M
EH
E
A
A
2
A
1
S
b
A-A Section
c
Qc
LL
1
L
P
A
3
Pattern of terminal position areas
I
1
b
2
e
e
1
A
A
1
A
2
A
3
b
c
D
E
e
H
E
L
L
1
L
P
x
b
2
e
1
I
1
Q
1.0
0
1.0
0.35
0.1
2.7
1.35
2.2
0.35
0.15
0.25
Min Nom
Dimension in Millimeters
Reference
Symbol
Max
1.1
0.25
0.4
0.16
1.5
0.95
2.8
1.95
0.3
1.3
0.1
1.2
0.5
0.26
3.1
1.65
3.0
0.75
0.55
0.65
0.05
0.55
1.05
SC-59A PLSP0003ZB-A MPAK(T) / MPAK(T)V 0.011g
MASS[Typ.]RENESAS CodeJEITA Package Code Previous Code
Package Name
MPAK
Ordering Information
Part Name Quantity Shipping Container
2SK2569ZN-TL-E 3000 pcs Taping
2SK2569ZN-TR-E 3000 pcs Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
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