DG441
DG441
Dual-In-Line and SOIC
IN1IN2
D1D2
S1S2
V– V+
GND NC
S4S3
D4D3
IN4IN3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
Top View
9
S1
NC
S2
IN3
V–
D3
V+
D4
NC
IN4
NC
NC
GND
IN2
NC
D2
S4
D1
S3
IN1
Key
Top View
LCC
910111213
4
5
6
7
8
1231920
14
15
16
17
18
TRUTH TABLE
Logic DG441 DG442
0
1
ON
OFF
OFF
ON
Logic “0” v 0.8 V
Logic “1” w 2.4 V
DG441/442
Vishay Siliconix
Document Number: 70053
S-20147—Rev. H, 11-Mar-02 www.vishay.com
1
Quad SPST CMOS Analog Switches
FEATURES BENEFITS APPLICATIONS
DLow On-Resistance: 50
DLow Leakage: 80 pA
DLow Power Consumption: 0.2 mW
DFast Switching Action—tON: 150
ns
DLow Charge Injection—Q: –1 pC
DDG201A/DG202 Upgrades
DTTL/CMOS-Compatible Logic
DSingle Supply Capability
DLess Signal Errors and Distortion
DReduced Power Supply
Requirements
DFaster Throughput
DImproved Reliability
DReduced Pedestal Errors
DSimplifies Retrofit
DSimple Interfacing
DAudio Switching
DBattery Powered Systems
DData Acquisition
DHi-Rel Systems
DSample-and-Hold Circuits
DCommunication Systems
DAutomatic Test Equipment
DMedical Instruments
DESCRIPTION
The DG441/442 monolithic quad analog switches are
designed to provide high speed, low error switching of analog
and audio signals. The DG441 has a normally closed function.
The DG442 has a normally open function. Combining low
on-resistance (50 , typ.) with high speed (tON 150 ns, typ.),
the DG441/442 are ideally suited for upgrading DG201A/202
sockets. Charge injection has been minimized on the drain for
use in sample-and-hold circuits.
To achieve high voltage ratings and superior switching
performance, the DG441/442 are built on Vishay Siliconix’s
high-voltage silicon-gate process. An epitaxial layer prevents
latchup.
Each switch conducts equally well in both directions when on,
and blocks input voltages to the supply levels when off.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG441/442
Vishay Siliconix
www.vishay.com
2Document Number: 70053
S-20147—Rev. H, 11-Mar-02
ORDERING INFORMATION
Temp Range Package Part Number
DG441DJ
_
16-Pin Plastic DIP DG442DJ
–40 to 85_CDG441DY
16-Pin Narrow SOIC DG442DY
DG441AK
DG441AK/883
5962-9204101MEA
_
16-Pin CerDIP DG442AK
–55 to 125_CDG442AK/883
5962-9204102MEA
5962-9204101M2A
LCC-20 5962-9204102M2A
ABSOLUTE MAXIMUM RATINGS
V+ to V–44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND to V–25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa VS, VD(V–) –2 V to (V+) +2 V. . . . . . . . . . . . . . . . . . . . . . . . . .
or 30 mA, whichever occurs first
Continuous Current (Any Terminal) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current, S or D (Pulsed 1 ms, 10% duty cycle) 100 mA. . . . . . . . . . . . . . . . . .
Storage Temperature (AK Suffix) –65 to 150_C. . . . . . . . . . . . . . . . . .
(DJ, DY Suffix) –65 to 125_C. . . . . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIPc450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin CerDIPd900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Narrow Body SOICd900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-20d1200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 75_C
d. Derate 12 mW/_C above 25_C
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
FIGURE 1.
INX
5 V Reg
Level
Shift/
Drive
V+
GND
V–
V–
V+
DG441/442
Vishay Siliconix
Document Number: 70053
S-20147—Rev. H, 11-Mar-02 www.vishay.com
3
SPECIFICATIONSa FOR DUAL SUPPLIES
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source
On-Resistance rDS(on) IS = –10 mA, VD = "8.5 V
V+ = 13.5 V, V– = –13.5 V Room
Full 50 85
100 85
100
On-Resistance Match Be-
tween ChannelserDS(on) IS = –10 mA, VD = "10 V
V+ = 15 V, V– = –15 V Room
Full 4
54
5
Switch Off IS(off) V+ = 16.5, V– = –16.5 V Room
Full "0.01 –0.5
–20 0.5
20 –0.5
–50.5
5
Switch Off
Leakage Current ID(off)
V+ = 16.5, V– = –16.5 V
VD = "15.5 V, VS = #15.5 V Room
Full "0.01 –0.5
–20 0.5
20 –0.5
–50.5
5nA
Channel On
Leakage Current ID(on) V+ = 16.5 V, V– = –16.5 V
VS = VD = "15.5 V Room
Full "0.08 –0.5
–40 0.5
40 –0.5
–10 0.5
10
Digital Control
Input Current VIN Low IIL VIN under test = 0.8 V, All Other = 2.4 V Full –0.01 –500 500 –500 500
Input Current VIN High IIH VIN under test = 2.4 V, All Other = 0.8 V Full 0.01 –500 500 –500 500 nA
Dynamic Characteristics
Turn-On Time tON
Room 150 250 250
DG441 RL = 1 k , CL = 35 pF
V = "10 V, See Figure 2 Room 90 120 120 ns
Turn-Off Time DG442 tOFF VS =
"
10 V, See Figure 2 Room 110 210 210
Charge InjectioneQCL = 1 nF, VS = 0 V
Vgen = 0 V, Rgen = 0 Room –1 pC
Off IsolationeOIRR
Room 60
Crosstalke
(Channel-to-Channel) XTALK
RL = 50 , CL = 5 pF
f = 1 MHz Room 100 dB
Source Off CapacitanceeCS(off) Room 4
Drain Off CapacitanceeCD(off) f = 1 MHz Room 4 pF
Channel On CapacitanceeCD(on) VANALOG = 0 V Room 16
Power Supplies
Positive Supply Current I+ Full 15 100 100
Negative Supply Current I–V+ = 16.5 V, V– = –16.5 V
VIN = 0 or 5 V Room
Full –0.000
1–1
–5–1
–5A
Ground Current IGND Full –15 –100 –100
DG441/442
Vishay Siliconix
www.vishay.com
4Document Number: 70053
S-20147—Rev. H, 11-Mar-02
SPECIFICATIONSa FOR SINGLE SUPPLY
Test Conditions
Otherwise Unless Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 12 V, V– = 0 V, VIN = 2.4 V,
0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance rDS(on) IS = –10 mA, VD = 3 V, 8 V
V+ = 10.8 V Room
Full 100 160
200 160
200
Dynamic Characteristics
Turn-On Time tON RL = 1 k , CL = 35 pF Room 300 450 450
Turn-Off Time tOFF
RL = 1 k
, CL = 35 pF
VS = 8 V, See Figure 2 Room 60 200 200 ns
Charge Injection QCL = 1 nF Vgen = 6 V, Rgen = 0 Room 2 pC
Power Supplies
Positive Supply Current I+ Full 15 100 100
Negative Supply Current I–V+ = 13.2 V, V– = 0 V
VIN = 0 or 5 V Room
Full –0.0001 –1
–100 –1
–100 A
Ground Current IGND
IN Full –15 –100 –100
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
DG441/442
Vishay Siliconix
Document Number: 70053
S-20147—Rev. H, 11-Mar-02 www.vishay.com
5
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
200–20
0
20
60
40
80
100
"15 V
"20 V
"5 V
"8 V
"10 V
–15 –10 –5 5 10 15
rDS(on) vs. VD and Power Supply Voltage rDS(on) vs. VD and Temperature
150–15
0
20
50
30
70
80
40
60
10
125_C
25_C
85_C
–40_C
V+ = 15 V
V– = –15 V
–10 –5510
rDS(on)
– Drain-Source On-Resistance (
VD – Drain Voltage (V) VD – Drain Voltage (V)
rDS(on)
– Drain-Source On-Resistance (
"12 V
–55_C
0_C
)
)
rDS(on) vs. VD and Temperature
(Single 12-V Supply)
rDS(on) vs. VD and Unipolar
Power Supply Voltage
1260
0
20
40
80
100
60
120
140
200
0
50
150
200
100
250
300
V+ = 5 V
8 V 10 V 12 V 15 V
20 V V+ = 12 V
V– = 0 V
V– = 0 V
125_C
25_C
–55_C
85_C
24 8104 8 12 16
rDS(on)
– Drain-Source On-Resistance (
VD – Drain Voltage (V) VD – Drain Voltage (V)
rDS(on)
– Drain-Source On-Resistance (
–40_C
0_C
)
)
Crosstalk and Off Isolation vs. Frequency Charge Injection vs. Source Voltage
(–dB)
Q (pC)
0
20
40
80
100
60
120
140
100–10
–30
–10
20
0
40
50
10
30
–20
–55
1 k 10 k 100 k 1 M 10 M100
V+ = 15 V
V– = –15 V
Ref. 10 dBm
Off Isolation
Crosstalk
V+ = 15 V
V– = –15 V
V+ = 12 V
V– = 0 V
CL = 1 nF
VS – Source Voltage (V)f – Frequency (Hz)
DG441/442
Vishay Siliconix
www.vishay.com
6Document Number: 70053
S-20147—Rev. H, 11-Mar-02
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Source/Drain Leakage CurrentsSwitching Threshold vs. Supply Voltage
150–15
–100
–80
–40
–20
–60
0
20
–10 –5510
V+ = 15 V
V– = –15 V
For I(off), VD = –VS
IS(off) , ID(off)
ID(on)
0
1.6
0.8
2.4
0"5"10 "15 "20
V+, V– Positive and Negative Supplies (V) VD or VS – Drain or Source Voltage (V)
(V)
IN
V
(pA)I , I
SD
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
Source/Drain Leakage Currents
(Single 12-V Supply) Operating Voltage
V+ (V)
1260
–40
–30
–10
–20
0
10
–50–200
0
10
30
40
50
20
–40–30–10
44
3
V–
V+
V+ = 12 V
V– = 0 V
For ID, VS = 0
For IS, VD = 0
IS(off) , ID(off)
IS(on) + ID(on)
D
IN
S
24 810
VD or VS – Drain or Source Voltage (V) V– – Negative Supply (V)
(pA)I , I
SD
CMOS
Compatible
Switching Time vs. Power Supply Voltage
Supply Voltage (V)
t (ns)
"10 "12 "14 "16 "18 "20 "22
160
140
120
20
80
60
40
100
tOFF
tON
Switching Time vs. Power Supply Voltage
t (ns)
500
400
0822
200
100
300
10 12 14 16 18 20
tOFF
tON
V– = 0 V
VS – Source Voltage (V)
5 V – CMOS
Compatible
TTL Compatible
VIN = 0.8 V, 2.4 V
DG441/442
Vishay Siliconix
Document Number: 70053
S-20147—Rev. H, 11-Mar-02 www.vishay.com
7
TEST CIRCUITS
FIGURE 2. Switching Time
0 V
Logic
Input
Switch
Input
Switch
Output
3 V
50%
0 V
VO
VS
tr <20 ns
tf <20 ns
tOFF
tON
Note: Logic input waveform is inverted for DG442.
50%
80% 80%
"10 V
CL (includes fixture and stray capacitance)
V–
V+
IN
SD
3 V RL
1
k
CL
35 pF
VO
–15 V
GND
+15 V
FIGURE 3. Charge Injection
OFFONOFF
OFFONOFF
VO
V
O
INX
INX
Q = VO x CL
(DG441)
(DG442)
CL
1 nF
IN
DVO
V–
V+
S
3 V
Rg
–15 V
GND
+15 V
FIGURE 4. Crosstalk FIGURE 5. Off Isolation
FIGURE 6. Source/Drain Capacitances
C = 1 mF tantalum in parallel with 0.01 mF ceramic
50
D1
VO
Rg = 50
S1
+15 V
–15 V
D2
GND
V+
V–
NC
C
C
S2
RL
IN1
XTALK Isolation = 20 log VS
VO
0V, 2.4 V
0V, 2.4 V
VS
IN2
C = RF bypass
S
IN RL
D
Rg = 50
VSVO
0V, 2.4 V
Off Isolation = 20 log VS
VO
V+
–15 V
GND V–C
C
+15 V
S
D
IN
+15 V
–15 V
GND
V+
V–C
C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
DG441/442
Vishay Siliconix
www.vishay.com
8Document Number: 70053
S-20147—Rev. H, 11-Mar-02
APPLICATIONS
FIGURE 7. Power MOSFET Driver
+15 V
+15 V
GND V–
V+
0 = Load Off
1 = Load On
+24 V
I = 3A
VN0300L, M
DG442
+15 V
10 k
150
RL
FIGURE 8. Open Loop Sample-and-Hold
H = Sample
L = Hold
–15 V
+15 V
VIN
VOUT
CH
SD
IN
1/4 DG442
+
–
+
–
IN
+15 V
–15 V
V+
V–GND
DG441 or DG442
+
–
VIN VOUT
Gain error is determined only by the resistor
tolerance. Op amp offset and CMRR will limit ac-
curacy of circuit.
GAIN1
AV = 1
GAIN2
AV = 10
GAIN3
AV = 20
GAIN4
AV = 100
R1
90 k
R2
5 k
R3
4 k
R4
1 k
VOUT
VIN =R1 + R2 + R3 + R4
R4= 100
With SW4 Closed
FIGURE 9. Precision-Weighted Resistor Programmable-Gain Amplifier
Legal Disclaimer Notice
Vishay
Document Number: 91000 www.vishay.com
Revision: 08-Apr-05 1
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
