HD74LV393AFP-E - Renesas Electronics

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The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

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April 1, 2003

To all our customers

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HD74LV393A

Dual 4-bit Binary Counters

ADE-205-276A (Z)

2nd. Edition

Jul. 2001

Description

The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single

divide-by-256 counter.

The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and

each has an independent clear input. When clear is set high all four bits of each counter are set to a low

level. This enables count trucation and allows the implementation of divide-by-N counter configurations.

Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook

computers), and the low-power consumption extends the battery life.

Features

• VCC = 2.0 V to 5.5 V operation

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

HD74LV393A

Rev.1, Jul. 2001, page 2 of 2

Function Table

Inputs

CLK

CLKCLK

CLK CLR Output

X H L

H L No change

L L No change

↑ L No change

↓ L Count up

Note: H: High level

L: Low level

X: Immaterial

↑: Low to high transition

↓: High to low transition

Pin Arrangement

2CLR

2QA

2QB

2QC

1CLR

1QA

1QB

1QC

1QD

GND 2QD

(Top view)

HD74LV393A

Rev.1, Jul. 2001, page 3 of 3

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage range VCC –0.5 to 7.0 V

Input voltage range*1 V

I –0.5 to 7.0 V

Output voltage range*1, 2 V

O –0.5 to VCC + 0.5 V Output: H or L

–0.5 to 7.0 VCC: OFF

Input clamp current IIK –20 mA VI < 0

Output clamp current IOK ±50 mA VO < 0 or VO > VCC

Continuous output current IO ±25 mA VO = 0 to VCC

Continuous current through

VCC or GND

ICC or IGND ±50 mA

Maximum power dissipation

at Ta = 25°C (in still air)*3

PT 785 mW SOP

500 TSSOP

Storage temperature Tstg –65 to 150 °C

Notes: The absolute maximum ratings are values which must not individually be exceeded, and

furthermore, no two of which may be realized at the same time.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current

ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The maximum package power dissipation was calculated using a junction temperature of 150°C.

HD74LV393A

Rev.1, Jul. 2001, page 4 of 4

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage range VCC 2.0 5.5 V

Input voltage range VI 0 5.5 V

Output voltage range VO 0 VCC V H or L

Output current IOH — –50 µA VCC = 2.0 V

— –2 mA VCC = 2.3 to 2.7 V

— –6 VCC = 3.0 to 3.6 V

— –12 VCC = 4.5 to 5.5 V

OL — 50 µA VCC = 2.0 V

— 2 mA VCC = 2.3 to 2.7 V

— 6 VCC = 3.0 to 3.6 V

— 12 VCC = 4.5 to 5.5 V

Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V

0 100 VCC = 3.0 to 3.6 V

0 20 VCC = 4.5 to 5.5 V

Operating free-air temperature Ta –40 85 °C

Note: Unused or floating inputs must be held high or low.

Logic Diagram

CLR

HD74LV393A

Rev.1, Jul. 2001, page 5 of 5

Timing Diagram

CLR

HD74LV393A

Rev.1, Jul. 2001, page 6 of 6

DC Electrical Characteristics

Ta = –40 to 85°C

Item Symbol VCC (V)* Min Typ Max Unit Test Conditions

Input voltage VIH 2.0 1.5 — — V

2.3 to 2.7 VCC × 0.7 — —

3.0 to 3.6 VCC × 0.7 — —

4.5 to 5.5 VCC × 0.7 — —

IL 2.0 — — 0.5

2.3 to 2.7 — — V

CC × 0.3

3.0 to 3.6 — — V

CC × 0.3

4.5 to 5.5 — — V

CC × 0.3

Output voltage VOH Min to

Max

VCC – 0.1 — — V IOL = –50 µA

2.3 2.0 — — I

OL = –2 mA

3.0 2.48 — — I

OL = –6 mA

4.5 3.8 — — I

OL = –12 mA

OL Min to

Max

— — 0.1 V IOL = 50 µA

2.3 — — 0.4 IOL = 2 mA

3.0 — — 0.44 IOL = 6 mA

4.5 — — 0.55 IOL = 12 mA

Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND

Quiescent

supply current

ICC 5.5 — — 20 µA VIN = VCC or GND, IO = 0

Output leakage

current

IOFF 0 — — 5 µA VI or VO = 0 V to 5.5 V

Input

capacitance

CIN 3.3 — 1.7 — pF VI = VCC or GND

Note: For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

HD74LV393A

Rev.1, Jul. 2001, page 7 of 7

Switching Characteristics

VCC = 2.5 ± 0.2 V

Ta = 25°C Ta = –40 to 85°C

Item

Symbol

Min

Typ

Max

Min

Max

Unit

Test Conditions

FROM

(Input)

(Output)

Maximum

clock

frequency

fmax 50 90 — 40 — MHz CL = 15 pF

30 60 — 25 — C

L = 50 pF

Propa-

gation

delay time

tPLH/./tPHL — 11.8 17.7 1.0 20.5 ns CL = 15 pF CLK Q

— 15.1 21.3 1.0 24.5 CL = 50 pF

— 13.4 20.3 1.0 23.5 CL = 15 pF QB

— 16.7 23.9 1.0 27.5 CL = 50 pF

— 14.9 22.5 1.0 26.0 CL = 15 pF QC

— 18.2 26.1 1.0 30.0 CL = 50 pF

— 16.2 24.2 1.0 28.0 CL = 15 pF QD

— 19.5 27.8 1.0 32.0 CL = 50 pF

PHL — 10.8 14.8 1.0 17.0 CL = 15 pF CLR Qn

— 14.2 17.4 1.0 20.0 CL = 50 pF

Setup time tsu 6.0 — — 6.0 — ns CLR L before CLK ↓

Pulse

width

tw 5.0 — — 5.0 — ns CLR H

5.0 — — 5.0 — CLK H or L

HD74LV393A

Rev.1, Jul. 2001, page 8 of 8

Switching Characteristics (cont)

VCC = 3.3 ± 0.3 V

Ta = 25°C Ta = –40 to 85°C

Item

Symbol

Min

Typ

Max

Min

Max

Unit

Test Conditions

FROM

(Input)

(Output)

Maximum

clock

frequency

fmax 75 120 — 65 — MHz CL = 15 pF

45 65 — 35 — C

L = 50 pF

Propa-

gation

delay time

tPLH/./tPHL — 8.6 13.2 1.0 15.5 ns CL = 15 pF CLK Q

— 11.1 16.7 1.0 19.0 CL = 50 pF

— 10.2 15.8 1.0 18.5 CL = 15 pF QB

— 12.7 19.3 1.0 22.0 CL = 50 pF

— 11.7 18.0 1.0 21.0 CL = 15 pF QC

— 14.2 21.5 1.0 24.5 CL = 50 pF

— 13.0 19.7 1.0 23.0 CL = 15 pF QD

— 15.5 23.2 1.0 26.5 CL = 50 pF

PHL — 7.9 12.3 1.0 14.5 CL = 15 pF CLR Qn

— 10.4 15.8 1.0 18.0 CL = 50 pF

Setup time tsu 5.0 — — 5.0 — ns CLR L before CLK ↓

Pulse

width

tw 5.0 — — 5.0 — ns CLR H

5.0 — — 5.0 — CLK H or L

HD74LV393A

Rev.1, Jul. 2001, page 9 of 9

Switching Characteristics (cont)

VCC = 5.0 ± 0.5 V

Ta = 25°C Ta = –40 to 85°C

Item

Symbol

Min

Typ

Max

Min

Max

Unit

Test Conditions

FROM

(Input)

(Output)

Maximum

clock

frequency

fmax 125 170 — 105 — MHz CL = 15 pF

85 115 — 75 — C

L = 50 pF

Propa-

gation

delay time

tPLH/./tPHL — 5.8 8.5 1.0 10.0 ns CL = 15 pF CLK Q

— 7.3 10.5 1.0 12.0 CL = 50 pF

— 6.8 9.8 1.0 11.5 CL = 15 pF QB

— 8.3 11.8 1.0 13.5 CL = 50 pF

— 7.7 11.2 1.0 13.0 CL = 15 pF QC

— 9.2 13.2 1.0 15.0 CL = 50 pF

— 8.5 12.5 1.0 14.5 CL = 15 pF QD

— 10.0 14.5 1.0 16.5 CL = 50 pF

PHL — 5.4 8.1 1.0 9.5 CL = 15 pF CLR Qn

— 6.9 10.1 1.0 11.5 CL = 50 pF

Setup time tsu 4.0 — — 4.0 — ns CLR L before CLK ↓

Pulse

width

tw 5.0 — — 5.0 — ns CLR H

5.0 — — 5.0 — CLK H or L

Operating Characteristics

CL = 50 pF

Ta = 25°C

Item Symbol VCC (V) Min Typ Max Unit Test Conditions

Power

dissipation

capacitance

CPD 3.3 — 12.0 — pF f = 10 MHz

5.0 — 15.0 —

HD74LV393A

Rev.1, Jul. 2001, page 10 of 10

Noise Characteristics

CL = 50 pF

Ta = 25°C

Item Symbol VCC = (V) Min Typ Max Unit Test Conditions

Quiet output,

maximum

dynamic VOL

VOL (P) 3.3 — 0.4 0.8 V

Quiet output,

minimum

dynamic VOL

VOL (V) 3.3 — –0.4 –0.8

Quiet output,

minimum

dynamic VOH

VOH (V) 3.3 — 3.2 —

High-level

dynamic

input voltage

VIH (D) 3.3 2.31 — —

Low-level

dynamic

input voltage

VIL (D) 3.3 — — 0.99

Test Circuit

Note: C includes the probe and jig capacitance.

Measurement point

HD74LV393A

Rev.1, Jul. 2001, page 11 of 11

PHL

0 V

PHL

PLH

10 %

90 %

50 % V

10 %

90 %

CLR

0 V

50 % V

CLR

10 %

50 % V

10 %

PHL

PLH

50 % V

10 %

90 %

90 % 90 %

•

Waveforms

−

•

Waveforms

−

1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns

2. The output are measured one at a time with one transition per measurement.

Notes:

HD74LV393A

Rev.1, Jul. 2001, page 12 of 12

Package Dimensions

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

FP-14DAV

—

Conforms

0.23 g

*Pd plating

*0.20 ± 0.05

*0.40 ± 0.06

0.70 ± 0.20

0.12

0.15

0˚ – 8˚

0.10 ± 0.10

2.20 Max

5.5

10.06

1.42 Max

14 8

10.5 Max

+ 0.20

– 0.30

7.80

1.15

1.27

As of July, 2001

Unit: mm

HD74LV393A

Rev.1, Jul. 2001, page 13 of 13

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

FP-14DNV

Conforms

0.13 g

– 8

1.27

14 8

0.15

0.25

1.75 Max 3.95

*0.20 ± 0.05

8.65

9.05 Max

*0.40 ± 0.06

0.14

+ 0.11

– 0.04

0.635 Max

6.10

+ 0.10

– 0.30

0.60

+ 0.67

– 0.20

1.08

*Pd plating

As of July, 2001

Unit: mm

Hitachi Code

JEDEC

JEITA

Mass

(reference value)

TTP-14D

—

0.05 g

*Dimension including the plating thickness

Base material dimension

0.50 ± 0.10

0˚ – 8˚

*0.17 ± 0.05

6.40 ± 0.20

0.10

1.10 Max

0.13 M

0.65

14 8

4.40

5.00

5.30 Max

0.83 Max

*0.22+0.08

–0.07

0.07+0.03

–0.04

0.20 ± 0.06

0.15 ± 0.04

1.0

As of July, 2001

Unit: mm

HD74LV393A

Rev.1, Jul. 2001, page 14 of 14

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safe

devices, so that the equipment incorporating the Hitachi product does not cause bodily injury, fire or

other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Sales Offices

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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

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URL NorthAmerica : http://semiconductor.hitachi.com/

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Fax : <886>-(2)-2718-8180

Telex : 23222 HAS-TP

URL : http://www.hitachi.com.tw

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Hong Kong

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Fax : <852>-(2)-730-0281

URL : http://www.hitachi.com.hk

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Tel: <44> (1628) 585000

Fax: <44> (1628) 585160

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Electronic Components Group

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D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

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(America) Inc.

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San Jose,CA 95134

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Fax: <1>(408) 433-0223

For further information write to:

Colophon 2.0