250 MHz Dual Integrated DCL with Level
Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE305
Rev. 0
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FEATURES
Driver
3-level driver with high-Z mode and built-in clamps
Precision trimmed output resistance
Low leakage mode (typically <10 nA)
Voltage range: up to −2.0 V to +6.0 V
1.6 ns minimum pulse width, 2 V terminated
2.1 ns minimum pulse width, 3 V terminated
Comparator
Window and differential comparator
500 MHz input equivalent bandwidth
Load
±12 mA maximum current capability
Per pin PMU
Force voltage range: up to −2.0 V to +6.0 V
5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA
Levels
14-bit DAC for DCL levels
Typically < ±5 mV INL (calibrated)
16-bit DAC for PMU levels
Typically < ±1.5 mV INL (calibrated) linearity in FV mode
HVOUT output buffer
0 V to 13.5 V output range
100-lead, 14 mm × 14 mm, TQFP_EP package
900 mW per channel with no load
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE305 is a complete, single-chip solution that performs
the pin electronic functions of the driver, the comparator, and
the active load (DCL), per pin PMU, and dc levels for ATE appli-
cations. The device also contains an HVOUT driver with a VHH
buffer capable of generating up to 13.5 V.
The driver features three active states: data high mode, data low
mode, and term mode, as well as an inhibit state. The inhibit
state, in conjunction with the integrated dynamic clamp, facili-
tates the implementation of a high speed active termination.
The ADATE305 supports two output voltage ranges: −2.0 V
to +6.0 V and −1.5 V to +6.0 V by adjusting the positive and
negative supply voltages.
The ADATE305 can be used as either a dual single-ended drive/
receive channel or a single differential drive/receive channel.
Each channel of the ADATE305 features a high speed window
comparator per pin for functional testing, as well as a per pin
PMU with FV, or FI and MV, or MI functions. All necessary dc
levels for DCL functions are generated by on-chip 14-bit DACs.
The per pin PMU features an on-chip 16-bit DAC for high
accuracy and contains integrated range resistors to minimize
external component counts.
The ADATE305 uses a serial bus to program all functional blocks
and has an on-board temperature sensor for monitoring the
device temperature.
ADATE305
Rev. 0 | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Total Function ............................................................................... 4
Driver ............................................................................................. 5
Reflection Clamp .......................................................................... 7
Normal Window Comparator .................................................... 7
Differential Comparator .............................................................. 9
Active Load .................................................................................. 11
PMU ............................................................................................. 12
External Sense (PMUS_CHx) ................................................... 16
DUTGND Input ......................................................................... 16
Serial Peripheral Interface ......................................................... 17
HVOUT Driver ........................................................................... 17
Overvoltage Detector (OVD) ................................................... 18
16-Bit DAC Monitor MUX ....................................................... 18
Absolute Maximum Ratings ......................................................... 19
Thermal Resistance .................................................................... 19
Explanation of Test Levels ......................................................... 19
ESD Caution................................................................................ 19
Pin Configuration and Function Descriptions ........................... 20
Typical Performance Characteristics ........................................... 23
SPI Details ....................................................................................... 34
Definition of SPI Word .............................................................. 35
Write Operation.......................................................................... 36
Read Operation........................................................................... 37
Reset Operation .......................................................................... 38
Register Map ................................................................................... 39
Details of Registers ......................................................................... 40
User Information ............................................................................ 42
Details of DACs vs. Levels ......................................................... 43
Recommended PMU Mode Switching Sequences ................. 46
Block Diagrams ............................................................................... 49
Outline Dimensions ....................................................................... 53
Ordering Guide .......................................................................... 53
REVISION HISTORY
8/08—Revision 0: Initial Version
ADATE305
Rev. 0 | Page 3 of 56
FUNCTIONAL BLOCK DIAGRAM
16-BIT DAC PMU
PMU_FLAG
MUX
*
MUX
*
WINDOW
DIFF.
C
*
VHH
DRV
14-BIT DAC
OVD
TEMPERATURE
SENSOR
*
VOL
VOH
C
C
OTHER CHANNEL
DUT1
FORCE
SENSE
ROUT
(TRIMMED)
VCLAMPH VCLAMPL
VCLAMPH
VCLAMPL
IOL
IOH
VCOM
SPI
*
50
100
100
VH
VT
VL
CH1
CH1
DAC16_MON
MEASOUT01
PMUS_CH0
DATA0P
DATA0N
RCV0P
RCV0N
COMP_QH0P
COMP_VTT0
COMP_QH0N
COMP_QL0P
TEMPSENSE
HVOUT
DUT0
OVD_CH0
COMP_QL0N
SDIN
RST
SCLK
CS
SDOUT
ADATE305
07280-001
G
*
MUX
*ONE PER DEVICE.
*
Figure 1. One of Two Channels Is Shown
ADATE305
Rev. 0 | Page 4 of 56
SPECIFICATIONS
Characterization and production tests performed using Power Supply Range 1 (see Table 36 ). VDD = +10.0 V, VCC = +3.3 V, VSS = −5.25 V,
VPLUS = +16.75 V, VCOMP_VTT = +3.3 V, VREF = +5.0 V, VREF_GND = 0.0 V. All default test conditions are as defined in Table 3 8. All specified
values are at TJ = 70°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are
measured at TJ = 70°C ± 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench
evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.
TOTAL FUNCTION
Table 1.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
TOTAL FUNCTION
Output Leakage Current
PE Disable Range E −20.0 5.3 +20.0 nA P −1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range E, VCH = 7.0 V, VCL = −2.5 V
PE Disable Range A, B, C, D 5.3 nA CT −1.5 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU
Range A, PMU Range B, PMU Range C, and PMU Range D,
VCH = +7.0 V, VCL = −2.5 V
High-Z Mode −400 5.4 +400 nA P −1.5 V < VDUTx < +6.0 V; PMU disabled and PE enabled via SPI;
RCV active, VCH = +7.0 V, VCL = −2.5 V
Output Capacitance 4 pF S VTERM mode operation
DUT Pin Range −1.5 +6.0 V D
POWER SUPPLIES
Total Supply Range, VPLUS to VSS 22.5 23.25 V D Defines PSRR conditions
VPLUS Supply, VPLUS 16.25 16.75 17.25 V D Defines PSRR conditions
Positive Supply, VDD 9.5 10.0 10.5 V D Defines PSRR conditions
Negative Supply, VSS −5.50 −5.25 −5.00 V D Defines PSRR conditions
Logic Supply, VCC 3.1 3.3 3.5 V D Defines PSRR conditions
Comparator Termination, VCOMP_VTT 3.3 5.0 V D
VPLUS Supply Current, IPLUS −1.0 +1.3 +3.0 mA P HVOUT disabled
VPLUS Supply Current, IPLUS 4.0 12.7 17.0 mA P HVOUT enabled, RCV active, no load, VHH = 12 V
Logic Supply Current, ICC 1.0 2.7 10.0 mA P Quiescent (SPI is static)
Comparator Termination Current,
ICOMP_VTT
10.0 17 26.0 mA P
Positive Supply Current, IDD 72 92 105 mA P Load power down (IOH = IOL = 0 mA)
Negative Supply Current, ISS 100 119 135 mA P Load power down (IOH = IOL = 0 mA)
Total Power Dissipation 1.0 1.7 1.9 W P Load power down (IOH = IOL = 0 mA)
Positive Supply Current, IDD 102 133 154 mA P Load active off (IOH = IOL = 12 mA)
Negative Supply Current, ISS 130 158 183 mA P Load active off (IOH = IOL = 12 mA)
Total Power Dissipation 1.8 2.2 2.5 W P Load active off (IOH = IOL = 12 mA)
TEMPERATURE MONITORS
Temperature Sensor Gain 10 mV/K CT
Temperature Sensor Accuracy
Without Calibration over
25°C to 100°C
6 °C CT Temperature voltage available on Pin 3 at all times and Pin 28
when selected (see Table 24 and Table 36)
VREF INPUT
Reference Input Voltage Range for
DACs (VREF Pin)
4.95 5 5.05 V D Referenced to VREF_GND; not referenced to VDUTGND
Input Bias Current 0.1 100 A P Tested with 5 V applied
ADATE305
Rev. 0 | Page 5 of 56
DRIVER
VH − VL ≥ 200 mV (to meet dc/ac specifications).
Table 2.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC SPECIFICATIONS
High-Speed Differential Logic
Input Characteristics (DATA, RCV)
Input Termination Resistance 92 100 108 Ω P Push 6 mA into xP pins, force 1.3 V on xN pins; measure voltage
from xP to xN, calculate resistance (∆V/∆I)1
Input Voltage Differential 0.2 1.0 V PF
Common-Mode Voltage 0.85 2.35 V PF
Input Bias Current −20.0 +2.2 +20.0 A P Each pin tested at 2.85 V and 0.35 V, while the other high speed
pin remains open
Pin Output Characteristics
Output High Range, VH −1.4 +6.0 V D
Output Low Range, VL −1.5 +5.9 V D
Output Term Range, VT −1.5 +6.0 V D
Functional Amplitude (VH − VL) 0.0 7.5 V D Amplitude can be programmed to VH = VL, accuracy specs
apply when VH − VL ≥ 200 mV
DC Output Current Limit
Source
75 100 120 mA P Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure current
DC Output Current Limit Sink −120 −100 −75 mA P Driver low, VL = −1.5 V, short DUTx pin to 6.0 V, measure current
Output Resistance, ±50 mA 45.0 47.0 49.0 Ω P Source: driver high, VH = 3.0 V, IDUTx = 1 mA and 50 mA;
sink: driver low, VL = 0.0 V, IDUTx = −1 mA and −50 mA; ∆VDUT/∆IDUT
ABSOLUTE ACCURACY VH tests done with VL = −2.5 V and VT= −2.5 V;
VL tests done with VH = 7.5 V and VT = 7.5 V;
VT tests done with VL = −2.5 V and VH = +7.5 V; unless otherwise
specified
VH, VL, VT Uncalibrated Accuracy −250 ±75 +250 mV P Error measured at calibration points of 0 V and 5 V
VH, VL, VT Offset Tempco ±450 V/°C CT Measured at calibration points
VH, VL, VT DNL ±1 mV CT After two-point gain/offset calibration
VH, VL, VT INL −10 ±2.5 +10 mV P After two-point gain/offset calibration; measured over driver
output ranges
VH, VL, VT Resolution 0.6 +1 mV PF After two-point gain/offset calibration; range/number of DAC
bits as measured at calibration points of 0 V and 5 V
DUTGND Voltage Accuracy −7 ±1.3 +7 mV P Over ±0.1 V range; measured at end points of VH, VL, and VT
functional range
VH, VL, VT Crosstalk ±2 mV CT VL = −1.5 V: VH = −1.4 V → 6.0 V, VT = −1.5 V → 6.0 V;
VH = 6.0 V: VL = −1.5 V → 5.9 V, VT = −1.5 V → 6.0 V;
VT = 1.5 V: VL = −1.5 V → 5.9 V, VH = −1.4 V → 6.0 V; dc crosstalk
on VL, VH, VT output level when other driver DACs are varied
Overall Voltage Accuracy ±10 mV CT Sum of INL, crosstalk, DUTGND, and tempco over ±5°C, after
gain/offset calibration
VH, VL, VT DC PSRR ±15 mV/V CT Measured at calibration points
AC SPECIFICATIONS
Rise/Fall Times Toggle DATAxx
0.2 V Programmed Swing 1000 ps CB VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%
1.0 V Programmed Swing 800 ps CB VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%
2.0 V Programmed Swing 950 ps CB VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%
3.0 V Programmed Swing 1000 1175 1500 ps P/CB VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%
3.0 V Programmed Swing 1650 ps CB VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%
5.0 V Programmed Swing 2350 ps CB VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90%
Rise to Fall Matching 30 ps CB VH = 3.0 V, VL = 0.0 V, terminated; rise to fall within one channel
ADATE305
Rev. 0 | Page 6 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Minimum Pulse Width Toggle DATAxx
1.0 V Programmed Swing 1.4 ns CB VH = 1.0 V, VL = 0.0 V, terminated; timing error ±75 ps
1.6 ns CB VH = 1.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
2.0 V Programmed Swing 1.6 ns CB VH = 2.0 V, VL = 0.0 V, terminated; timing error ±75 ps
1.8 ns CB VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
3.0 V Programmed Swing 2.1 ns CB VH = 3.0 V, VL = 0.0 V, terminated; timing error ±75 ps
2.3 ns CB VH = 3.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
Maximum Toggle Rate
2.0 V Programmed Swing 250 MHz CB VH = 2.0 V, VH = 0.0 V, terminated, 10% amplitude degradation
3.0 V Programmed Swing 200 MHz CB VH = 3.0 V, VH = 0.0 V, terminated, 10% amplitude degradation
Dynamic Performance, Drive
(VH to VL and VL to VH)
Toggle DATAxx
Propagation Delay Time 3.0 ns CB VH = 3.0 V, VL = 0.0 V, terminated
Propagation Delay Tempco 3.0 ps/°C CT VH = 3.0 V, VL = 0.0 V, terminated
Delay Matching VH = 3.0 V, VL = 0.0 V, terminated
Edge to Edge 115 ps CB Rising vs. falling
Channel to Channel 30 ps CB Rising vs. rising, falling vs. falling
Delay Change vs. Duty Cycle 30 ps CB VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz
Overshoot and Undershoot 20 mV CB VH = 3.0 V, VL = 0.0 V, terminated
Settling Time (VH to VL) Toggle DATAxx
To Within 3% of Final Value 5 ns CB VH = 3.0 V, VL = 0.0 V, terminated
To Within 1% of Final Value 35 ns CB VH = 3.0 V, VL = 0.0 V, terminated
Dynamic Performance, VT
(VH or VL to VT and VT to VH
or VL)
Toggle RCVx
Propagation Delay Time 3.3 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
Delay Matching, Edge to Edge 100 ps CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling
Propagation Delay Tempco 4.0 ps/°C CT VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
Transition Time, Active to VT
and VT to Active
0.85 ns CB VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%
Dynamic Performance,
Inhibit (VH or VL to/from
Inhibit)
Toggle RCVx
Propagation Delay Time VH = +1.0 V, VL = −1.0 V, terminated
Active to Inhibit 4.5 ns CB
Inhibit to Active 6.9 ns CB
Transition Time VH =+1.0 V, VL = −1.0 V, terminated; 20% to 80%
Active to Inhibit 2.6 ns CB
Inhibit to Active 0.75 ns CB
I/O Spike 190 mV CB VH = 0.0 V, VL = 0.0 V, terminated
1 The xP pins include DATA0P, DATA1P, RCV0P, and RCV1P; the xN pins include DATA0N, DATA1N, RCV0N, and RCV1N. For example, push 6 mA into the DATA0P pin,
force 1.3 V into DATA0N, and measure the voltage from DATA0P to DATA0N.
ADATE305
Rev. 0 | Page 7 of 56
REFLECTION CLAMP
Clamp accuracy specifications apply when VCH > VCL.
Table 3.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
VCH
Range −1.0 +6.0 V D
Uncalibrated Accuracy −200 ±50 +200 mV P Driver high-Z, sinking 1 mA; VCH error measured at the
calibration points of 0.0 V and 5.0 V
Resolution 0.6 0.75 mV PF Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
DNL ±1 mV CT Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration
INL −40 ±2 +40 mV P Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; measured over VCH range of −1.0 V to +6.0 V
Tempco −0.3 mV/°C CT Measured at calibration points
VCL
Range −1.5 +5.0 V D
Uncalibrated Accuracy −200 ±50 +200 mV P Driver high-Z, sourcing 1 mA; VCL error measured at the
calibration points of 0.0 V and 5.0 V
Resolution 0.6 0.75 mV PF Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
DNL ±1 mV CT Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration
INL −40 ±2 +40 mV P Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; measured over VCL range of −1.5 V to +5 V
Tempco 0.5 mV/°C CT Measured at calibration points
DC CLAMP CURRENT LIMIT
VCH −120 −85 −60 mA P Driver high-Z, VCH = 0 V, VCL = −1.5 V, VDUTx = +5 V
VCL 60 85 120 mA P Driver high-Z, VCH = 6.0 V, VCL = 5.0 V, VDUTx = 0.0 V
DUTGND VOLTAGE ACCURACY −7 ±1 +7 mV P Over ±0.1 V range; measured at the end points of VCH
and VCL functional range
NORMAL WINDOW COMPARATOR
VOH tests done with VOL = −1.5 V; VOL tests done with VOH = 6.0 V, unless otherwise specified.
Table 4.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC SPECIFICATIONS
Input Voltage Range −1.5 +6.0 V D
Differential Voltage Range ±0.1 ±7.5 V D
Comparator Input Offset Vol-
tage Accuracy, Uncalibrated
−150 ±30 +150 mV P Offset measured at the calibration
points of 0.0 V and 5.0 V
Comparator Threshold
Resolution
0.6 1 mV PF After two-point gain/offset calibration;
range/number of DAC bits as measured
at the calibration points of 0 V and 5 V
Comparator Threshold DNL ±1 mV CT After two-point gain/offset calibration
Comparator Threshold INL −7 ±1.3 +7 mV P After two-point gain/offset calibration;
measured over VOH, VOL range of
−1.5 V to +6.0 V
Comparator Input Offset
Voltage Tempco
±100 µV/°C CT Measured at calibration points
DUTGND Voltage Accuracy −7 ±0.5 +7 mV P Over ±0.1 V range; measured at end
points of VOH and VOL functional range
ADATE305
Rev. 0 | Page 8 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Comparator Uncertainty Range 6.0 mV CB V
DUTx = 0 V, sweep comparator
threshold to determine uncertainty
region
DC Hysteresis 0.5 mV CB V
DUTx = 0 V
DC PSRR ±5 mV/V CT Measured at calibration points
Digital Output Characteristics
Internal Pull-Up Resistance
to Comparator, COMP_VTT
Pin
40 50 60 Ω P Pull 1 mA and 10 mA from Logic 1 leg
and measure ∆V to calculate resis-
tance; measured ∆V/9 mA; done for
both comparator logic states
VCOMP_VTT Range 3.3 5.0 V D
Common-Mode Voltage VCOMP_VTT − 1.88 V CT Measured with 100 Ω differential
termination
V
COMP_VTT − 2.075 VCOMP_VTT − 1.675 V P Measured with no external termination
Differential Voltage 250 mV CT Measured with 100 Ω differential
termination
400 500 600 mV P Measured with no external termination
Rise/Fall Time, 20% to 80% 450 ps CB Measured with each comparator leg
terminated 50 Ω to GND
AC SPECIFICATIONS Input transition time = 800 ps, 10% to
90%; measured with each comparator
leg terminated 50 Ω to GND; unless
otherwise specified
Propagation Delay, Input to
Output
1.75 ns CB V
DUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
Propagation Delay Tempco 5 ps/°C CT V
DUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
Propagation Delay Matching VDUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
High Transition to Low
Transition
200 ps CB
High to Low Comparator 50 ps CB
Propagation Delay Change
(with Respect To)
Slew Rate, 800 ps, 1 ns, 1.2 ns,
and 2.2 ns (10% to 90%)
50 ps CB V
DUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
Overdrive, 250 mV and 1.5 V 75 ps CB For 250 mV: VDUTx = 0 V to 0.5 V swing;
for 1.5 V: VDUTx = 0 V to 1.75 V swing;
Driver VTERM mode, VT = 0.0 V; high-
side measurement: VOH = 0.25 V,
VOL = −1.5 V; low-side measurement:
VOH = 6.0 V, VOL = 0.25 V
Pulse Width, Sweep 1.6 ns to
10 ns
75 ps CB V
DUTx = 0 V to 1.5 V swing @ 32.0 MHz,
Driver VTERM mode, VT = 0.0 V; high-
side measurement: VOH = 0.5 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.5 V
ADATE305
Rev. 0 | Page 9 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Duty Cycle, 5% to 95% 50 ps CB V
DUTx = 0 V to 1.5 V swing @ 1.0 MHz,
Driver VTERM mode, VT =0.0 V; high-
side measurement: VOH = 0.75 V, VOL =
−1.5 V; low-side measurement: VOH =
6.0 V, VOL = 0.75 V
Minimum Pulse Width 2.0 ns CB V
DUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; less than
12% amplitude degradation measured
by shmoo
Input Equivalent Bandwidth,
Terminated
500 MHz CB V
DUTx = 0 V to 1.5 V swing, Driver
VTERM mode, VT = 0.0 V; as measured
by shmoo
ERT High-Z Mode, 3 V, 20%
to 80%
2.5 ns CB V
DUTx = 0 V to 3.0 V swing, driver high-Z;
as measured by shmoo; input transition
time of ~2000 ps, 10% to 90%
DIFFERENTIAL COMPARATOR
VOH tests done with VOL = −1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified.
Table 5.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC SPECIFICATIONS
Input Voltage Range −1.25 +4.5 V D
Operational Differential Voltage
Range
±0.05 ±1.1 V D
Maximum Differential Voltage Range ±8 V D
Comparator Input Offset Voltage
Accuracy, Uncalibrated
−150 ±35 +150 mV P/CT Offset measured at differential calibration points +1.0 V
and −1.0 V, with common mode = 0.0 V
VOH, VOL Resolution 0.6 1 mV PF After two-point gain/offset calibration; range/number of
DAC bits as measured at differential calibration points
+1.0 V and −1.0 V, with common mode = 0.0 V
VOH, VOL DNL ±1 mV CT After two-point gain/offset calibration; common
mode = 0.0 V
VOH, VOL INL −15 ±2.0 +15 mV P After two-point gain/offset calibration; measured over VOH,
VOL range of −1.1 V to +1.1 V, common mode = 0.0 V
VOH, VOL Offset Voltage Tempco ±200 µV/°C CT Measured at calibration points
Comparator Uncertainty Range 18 mV CB V
DUTx = 0 V, sweep comparator threshold to determine
uncertainty region
DC Hysteresis 0.5 mV CB V
DUTx = 0 V
CMRR 0.15 1 mV/V P Offset measured at common-mode voltage points of
−1.5 V and +4.5 V, with differential voltage = 0.0 V
DC PSRR ±1.5 mV/V CT Measured at calibration points
AC SPECIFICATIONS Input transition time = 800 ps, 10% to 90%, measured
with each comparator leg terminated 50 Ω to GND
Propagation Delay, Input to Output 1.7 ns CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Propagation Delay Tempco 5 ps/°C CT V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
Propagation Delay Matching VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
High Transition to Low Transition 100 ps CB
High-to-Low Comparator 50 ps CB
ADATE305
Rev. 0 | Page 10 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Propagation Delay Change (with
Respect To)
V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
Slew Rate, 800 ps, 1ns, 1.2ns, and
2.2 ns (10% to 90%)
60 ps CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; repeat for other DUT channel
Overdrive, 250 mV and 750 mV 100 ps CB V
DUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for
750 mV: VDUT1 = 0 V to 1.0 V swing, Driver VTERM mode,
VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel
with comparator threshold = +0.25 V
Pulse Width, Sweep from 1.6 ns to
10 ns
75 ps CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Duty Cycle, 5% to 95% 60 ps CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 1 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Minimum Pulse Width 2.5 ns CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; less than 10% amplitude degradation measured by
shmoo; repeat for other DUT channel
Input Equivalent Bandwidth,
Terminated
400 MHz CB V
DUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =
0.0 V; less than 22% amplitude degradation measured by
shmoo; repeat for other DUT channel
ADATE305
Rev. 0 | Page 11 of 56
ACTIVE LOAD
See Table 29 for load control information.
Table 6.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC SPECIFICATIONS Load active on, RCV active, unless otherwise noted
Input Characteristics
VCOM Voltage Range −1.25 +5.75 V D
VDUT Range −1.5 +6.0 V D
VCOM Accuracy, Uncalibrated −200 ±30 +200 mV P IOH = IOL = 6 mA, VCOM error measured at the calibration
points of 0.0 V and 5.0 V
VCOM Resolution 0.6 1 mV PF IOH = IOL = 6 mA, after two-point gain/offset calibration;
range/number of DAC bits as measured at the calibration
points of 0.0 V and 5.0 V
VCOM DNL ±1 mV CT IOH = IOL = 6 mA, after two-point gain/offset calibration
VCOM INL −7 ±2 +7 mV P IOH = IOL = 6 mA, after two-point gain/offset calibration;
measured over VCOM range of −1.25 V to +5.75 V
DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of VCOM functional
range
Output Characteristics
IOL
Maximum Source Current 12 mA D
Uncalibrated Offset −600.0 ±100 +600.0 µA P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated
from the calibration points of 1 mA and 11 mA
Uncalibrated Gain −12 ±4 +12 % P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from
the calibration points of 1 mA and 11 mA
Resolution 1.5 2 µA PF IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; range/number of DAC bits as measured at the
calibration points of 1 mA and 11 mA
DNL ±3.0 µA CT IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point
gain/offset calibration
INL −80 ±20 +80 µA P IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; measured over IOL range of 0 mA to 12 mA
90% Commutation Voltage 0.25 V P IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at
VDUTx = −1.0 V, measure IOL current at VDUTx = 1.75 V, ensure > 90%
of reference current
IOH
Maximum Sink Current 12 mA D
Uncalibrated Offset −600.0 ±100 +600.0 µA P IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated
from the calibration points of 1 mA and 11 mA
Uncalibrated Gain −12 ±4 +12 % P IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from
the calibration points of 1 mA and 11 mA
Resolution 1.5 2 µA PF IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration; range/number of DAC bits as measured
at the calibration points of 1 mA and 11 mA
DNL ±3.0 µA CT IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration
INL −80 ±20 +80 µA P IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/
offset calibration; measured over IOH range of 0 mA to 12 mA
90% Commutation Voltage 0.25 V P IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at
VDUTx = 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure >
90% of reference current
Output Current Tempco ±1.5 µA/°C CT Measured at calibration points
ADATE305
Rev. 0 | Page 12 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
AC SPECIFICATIONS Load active on, unless otherwise noted
Dynamic Performance
Propagation Delay, Load Active
On to Load Active Off;
50%, 90%
7.3 ns CB Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point
of final output, repeat for drive low and high
Propagation Delay, Load Active
Off to Load Active On;
50%, 90%
10.3 ns CB Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point
of final output, repeat for drive low and high
Propagation Delay Matching 3.0 ns CB Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; active on vs. active off, repeat for drive low and high
Load Spike 190 mV CB Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; repeat for drive low and high
Settling Time to 90% 1.9 ns CB Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured at 90% of final value
PMU
FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing.
Table 7.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
FORCE VOL TAGE (FV)
Current Range A ±32 mA D
Current Range B ±2 mA D
Current Range C ±200 µA D
Current Range D ±20 µA D
Current Range E ±2 µA D
Force Input Voltage Range at
Output for All Ranges
−1.5 +6.0 V D
Force Voltage Uncalibrated
Accuracy for Range C
−100 ±25 +100 mV P PMU enabled, FV, Range C, PE disabled, error measured at
calibration points of 0.0 V and 5.0 V
Force Voltage Uncalibrated
Accuracy for All Ranges
±25 mV CT PMU enabled, FV, PE disabled, error measured at calibration
points of 0.0 V and 5.0 V; repeat for each PMU current range
Force Voltage Offset Tempco
for All Ranges
±25 µV/°C CT Measured at calibration points for each PMU current range
Force Voltage Gain Tempco
for All Ranges
±10 ppm/°C CT Measured at calibration points for each PMU current range
Forced Voltage INL −7 ±2 +7 mV P PMU enabled, FV, Range C, PE disabled, after two-point gain/offset
calibration; measured over output range of −1.5 V to +6.0 V
Force Voltage Compliance vs.
Current Load
PMU enabled, FV, PE disabled, force −1.5 V, measure voltage
while PMU sinking zero and full-scale current; measure V;
force 6.0 V, measure voltage while PMU sourcing zero and full-
scale current; measure V; repeat for each PMU current range
Range A ±4 mV CT
Range B to Range E ±1 mV CT
ADATE305
Rev. 0 | Page 13 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Current Limit, Source, and Sink
Range A 108 140 180 %FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx
to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS =
32 mA, 108% FS = 35 mA, 180% FS = 58 mA
Range B to Range E 120 145 180 %FS P PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to
6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each
PMU current range; example: Range B FS = 2 mA, 120 % FS =
2.4 mA, 180% FS = 3.6 mA
DUTGND Voltage Accuracy −7 ±1 +7 mV P Over ±0.1 V range; measured at end points of FV functional
range
MEASURE CURRENT (MI) VDUTx externally forced to 0.0V, unless otherwise specified, ideal
MEASOUT transfer functions: VMEASOUT01 [V] = (IMEASOUT01 × 5/FSR) +
2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 − VDUTGND − 2.5) × FSR/5
Measure Current, Pin DUTx
Voltage Range for All Ranges
−1.5 +6.0 V D
Measure Current Uncalibrated
Accuracy
Range A ±500 µA CT PMU enabled, FIMI, Range A, PE disabled, error at calibration
points −25 mA and +25 mA, error = (I(VMEASOUT01) − IDUTx)
Range B −400 ±3.0 +400 µA P PMU enabled, FIMI, Range B, PE disabled, error at calibration
points −1.6 mA and +1.6 mA, error = (I(VMEASOUT01) − IDUTx)
Range C ± 2.00 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01)1 − IDUTx)
Range D ±0.30 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
Range E ±0.08 µA CT PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
Measure Current Offset Tempco
Range A ±2 µA/°C CT Measured at calibration points
Range B ±25 nA/°C CT Measured at calibration points
Range C ±5 nA/°C CT Measured at calibration points
Range D and Range E ±1 nA/°C CT Measured at calibration points
Measure Current Gain Error,
Nominal Gain = 1
Range A ±2.5 % CT PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
Range B −20 ±2 +20 % P PMU enabled, FIMI, Range B, PE disabled, gain error from
calibration points ±1.6 mA
Range C to Range E ±4 % CT PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
Measure Current Gain Tempco Measured at calibration points
Range A ±300 ppm/°C CT
Range B to Range E ±50 ppm/°C CT
Measure Current INL
Range A ±0.05 %FSR CT PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration, measured over FSR output of −32 mA
to +32 mA
Range B −0.02 +0.02 %FSR P PMU enabled, FIM,I Range B, PE disabled, after two-point gain/
offset calibration measured over FSR output of −2 mA to +2 mA
Range B to Range E ±0.01 %FSR CT PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
FVMI DUT Pin Voltage Rejection −0.01 +0.01 %FSR/V P PMU enabled, FVMI, Range B, PE disabled, force −1 V and +5 V
into load of 1 mA; measure I reported at MEASOUT01
DUTGND Voltage Accuracy ±2.5 mV CT Over ±0.1 V range; measured at end points of MI functional range
ADATE305
Rev. 0 | Page 14 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
FORCE CURRENT (FI) VDUTx externally forced to 0.0V, unless otherwise specified, ideal
force current transfer function: IFORCE = (PMUDAC − 2.5) × (FSR/5)
Force Current, DUTx Pin Voltage
Range for All Ranges
−1.5 +6.0 V D
Force Current Uncalibrated
Accuracy
Range A −5.0 ±0.5 +5.0 mA P PMU enabled, FIMI, Range A, PE disabled, error at calibration
points of −25 mA and +25 mA
Range B −400 ±40 +400 µA P PMU enabled, FIMI, Range B, PE disabled, error at calibration
points of −1.6 mA and 1.6 mA
Range C −40 ±4 +40 µA P PMU enabled, FIMI, Range C, PE disabled, error at calibration
points of ±80% FS
Range D −4 ±0.4 +4 µA P PMU enabled, FIMI, Range D, PE disabled, error at calibration
points of ±80% FS
Range E −400 ±75 +400 nA P PMU enabled, FIMI, Range E, PE disabled, error at calibration
points of ±80% FS
Force Current Offset Tempco
Range A ±1 µA/°C CT Measured at calibration points
Range B ±80 nA/°C CT Measured at calibration points
Range C to Range E ±4 nA/°C CT Measured at calibration points
Forced Current Gain Error,
Nominal Gain = 1
−20 ±4 +20 % P PMU enabled, FIMI, PE disabled, gain error from calibration
points of ±80% FS
Forced Current Gain Tempco Measured at calibration points
Range A −500 ppm/°C CT
Range B to Range E ±75 ppm/°C CT
Force Current INL
Range A −0.3 ±0.05 +0.3 %FSR P PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration; measured over FSR output of −32 mA
to +32 mA
Range B to Range E −0.2 ±0.015 +0.2 %FSR P PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
Force Current Compliance vs.
Voltage Load
PMU enabled, FIMV, PE disabled; force positive full-scale
current driving −1.5 V and +6.0 V, measure I @ DUTx pin;
force negative full-scale current driving −1.5 V and +6.0 V,
measure I @ DUTx pin
Range A to Range D −0.6 ±0.06 +0.6 %FSR P
Range E −1.0 ±0.1 +1.0 %FSR P
MEASURE VOLTAGE
Measure Voltage Range −1.5 +6.0 V D
Measure Voltage Uncalibrated
Accuracy
−25 ±2.0 +25 mV P PMU enabled, FVMV, Range B, PE disabled, error at calibration
points 0 V and 5 V, error = (VMEASOUT01 − VDUTx)
Measure Voltage Offset Tempco ±10 µV/°C CT Measured at calibration points
Measure Voltage Gain Error −2 ±0.01 +2 % P PMU enabled, FVMV, Range B, PE disabled, gain error from
calibration points 0 V and 5 V
Measure Voltage Gain Tempco 25 ppm/°C CT Measured at calibration points
Measure Voltage INL −7 ±1 +7 mV P PMU enabled, FVMV, Range B, PE disabled, after two-point
gain/offset calibration; measured over output range of −1.5 V
to +6.0 V
Rejection of Measure V vs. IDUTx −1.5 ±0.1 +1.5 mV P PMU enabled, FVMV, Range D, PE disabled, force 0 V into load
of −10 µA and +10 µA; measure V reported at MEASOUT01
MEASOUT01 DC CHARACTERISTICS
MEASOUT01 Voltage Range −1.5 +6.0 V D
DC Output Current 4 mA D
MEASOUT01 Pin Output
Impedance
25 200 Ω P PMU enabled, FVMV, PE disabled; source resistance: PMU force
6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force
−1.5 V and load with 0 mA and −4 mA; resistance = V/I at
MEASOUT01 pin
Output Leakage Current when
Tristated
−1 +1 µA P Tested at −1.5 V and +6.0 V
ADATE305
Rev. 0 | Page 15 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Output Short-Circuit Current −25 +25 mA P PMU enabled, FVMV, PE disabled; source: PMU force +6.0 V,
short MEASOUT01 to −1.5 V; sink: PMU force −1.5 V, short
MEASOUT01 to +6.0 V
VOLTAGE CLAMPS
Low Clamp Range (VCL) −1.5 +4.0 V D
High Clamp Range (VCH) 0.0 6.0 V D
Positive Clamp Voltage Droop −300 +10 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = 5 V,VCL = −1 V, PMU force 2 mA and 32 mA
into open; V seen at DUTx pin
Negative Clamp Voltage Droop −300 −10 +300 mV P PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = 5 V,VCL = −1 V, PMU force −2 mA and −32 mA
into open; V seen at DUTx pin
Uncalibrated Accuracy −250 ±100 +250 mV P PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; VCH errors at calibration points 0 V
and 5 V; VCL errors at the calibration points 0 V and 4 V
INL −70 ±5 +70 mV P PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; after two-point gain/offset
calibration; measured over PMU clamp range
DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of PMU clamp
functional range
SETTLING/SWITCHING TIMES SCAP = 330 pF, FFCAP = 220 pF
Voltage Force Settling Time to
0.1% of Final Value:
PMU enabled, FV, PE disabled, program PMUDAC steps of
500 mV and 5.0 V; simulation of worst case, 2000 pF load,
PMUDAC step of 5.0 V
Range A, 200 pF and
2000 pF Load
15 µs S
Range B, 200 pF and
2000 pF Load
20 µs S
Range C, 200 pF and
2000 pF Load
124 µs S
Range D, 200 pF and
2000 pF Load
1015 µs S
Range E, 200 pF and
2000 pF Load
3455 µs S
Voltage Force Settling Time to
1.0% of Final Value:
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 500 mV
Range A, 200 pF and
2000 pF Load
14 µs CB
Range B, 200 pF and
2000 pF Load
14 µs CB
Range C, 200 pF and
2000 pF Load
14 µs CB
Range D, 200 pF Load 45 µs CB
Range D, 2000 pF Load 45 µs CB
Range E, 200 pF Load 45 µs CB
Range E, 2000 pF Load 225 µs CB
Voltage Force Settling Time to
1.0% of Final Value:
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 5.0 V
Range A, 200 pF and
2000 pF Load
4.0 µs CB
Range B, 200 pF Load 4.2 µs CB
Range B, 2000 pF Load 4.2 µs CB
Range C, 200 pF Load 5.8 µs CB
Range C, 2000 pF Load 19 µs CB
Range D, 200 pF Load 50 µs CB
Range D, 2000 pF Load 210 µs CB
Range E, 200 pF Load 360 µs CB
Range E, 2000 pF Load 610 µs CB
ADATE305
Rev. 0 | Page 16 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
Current Force Settling Time to
0.1% of Final Value
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
Range A, 200 pF in Parallel
with 120 Ω
8.2 µs S
Range B, 200 pF in Parallel
with 1.5 kΩ
9.4 µs S
Range C, 200 pF in Parallel
with 15.0 kΩ
30 µs S
Range D, 200 pF in Parallel
with 150 kΩ
281 µs S
Range E, 200 pF in Parallel
with 1.5 MΩ
2668 µs S
Current Force Settling Time to
1.0% of Final Value:
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
Range A, 200 pF in Parallel
with 120 Ω
4.2 µs CB
Range B, 200 pF in Parallel
with 1.5 kΩ
4.3 µs CB
Range C, 200 pF in Parallel
with 15.0 kΩ
8.1 µs CB
Range D, 200 pF in Parallel
with 150 kΩ
205 µs CB
Range E, 200 pF in Parallel
with 1.5 MΩ
505 µs CB
INTERACTION AND CROSSTALK
Measure Voltage Channel-to-
Channel Crosstalk
±0.125 %FSR CT PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into
0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA
into 0 V load; report V of MEASOUT01 pin under test;
0.125% × 8.0 V = 10 mV
Measure Current Channel-to-
Channel Crosstalk
±0.01 %FSR CT PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into
0 mA current load; other channel: Range E, forcing a step of 0 V
to 5 V into 0 mA current load; report V of MEASOUT01 pin
under test; 0.01% × 5.0 V = 0.5 mV
EXTERNAL SENSE (PMUS_CHX)
Table 8.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
EXTERNAL SENSE (PMUS_CHX)
Voltage Range −1.5 +6.0 V D
Input Leakage Current −20 +20 nA P Tested at −1.5 V and +6.0 V
DUTGND INPUT
Table 9.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DUTGND INPUT
Input Voltage Range, Referenced to GND −0.1 +0.1 V D
Input Bias Current 1 100 A P Tested at −100 mV and +100 mV
ADATE305
Rev. 0 | Page 17 of 56
SERIAL PERIPHERAL INTERFACE
Table 10.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
SERIAL PERIPHERAL INTERFACE
Serial Input Logic High 1.8 VCC V PF
Serial Input Logic Low 0 0.7 V PF
Input Bias Current −10 1 +10 A P Tested at 0.0 V and 3.3 V
SCLK Clock Rate 50 MHz PF
SCLK Pulse Width 9 ns CT
SCLK Crosstalk on DUTx Pin 8 mV CB PE disabled, PMU FV enabled and forcing 0 V
Serial Output Logic High VCC − 0.4 VCC V PF Sourcing 2 mA
Serial Output Logic Low 0 0.8 V PF Sinking 2 mA
Update Time 10 s D Maximum delay time required for the part to enter a stable state after
a serial bus command is loaded
HVOUT DRIVER
Table 11.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
VHH BUFFER VHH = (VT + 1 V) × 2 + DUTGND
Voltage Range 5.9 VPLUS − 3.25 V D VPLUS = 16.75 V nominal; in this condition, VHVOUT max = 13.5
V
Output High 13.5 V P VHH mode enabled, RCV active, VHH level = full scale,
sourcing 15 mA
Output Low 5.9 V P VHH mode enabled, RCV active, VHH level = zero scale,
sinking 15 mA
Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCV active, VHVOUT error measured at
the calibration points of 7 V and 12 V
Offset Tempco 1 mV/°C CT Measured at calibration points
Resolution 1.21 1.5 mV PF VHH mode enabled, RCV active, after two-point gain/offset
calibration; range/number of DAC bits as measured at the
calibration points of 7 V and 12 V
INL −30 ±15 +30 mV P VHH mode enabled, RCV active, after two-point gain/offset
calibration; measured over VHH range of 5.9 V to 13.5 V
DUTGND Voltage Accuracy ±1 mV CT Over ±0.1 V range; measured at end points of VHH
functional range
Output Resistance 1 10 Ω P VHH mode enabled, RCV active, source: VHH = 10.0 V,
IHVOUT= 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and
−15 mA; V/I
DC Output Current Limit
Source
60 100 mA P VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT
pin to 5.9 V, measure current
DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT
pin to 14.1 V, measure current
Rise Time (From VL or VH to
VHH)
200 ns CB VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
Fall Time (From VHH to VL or
VH)
26 ns CB VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
Preshoot, Overshoot, and
Undershoot
±125 mV CB VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; for DATA = high and DATA = low
ADATE305
Rev. 0 | Page 18 of 56
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
VL/VH BUFFER
Voltage Range −0.1 +6.0 V D
Accuracy Uncalibrated −500 ±100 +500 mV P VHH mode enabled, RCV inactive, error measured at the
calibration points 0 V and 5 V
Offset Tempco 1 mV/°C CT Measured at calibration points
Resolution 0.61 0.75 mV PF VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; range/number of DAC bits as
measured at the calibration points 0 V and 5 V
INL −20 ±4 +20 mV P VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; measured over range of −0.1 V to
+6.0 V
DUTGND Voltage Accuracy ±2 mV CT Over ±0.1 V range; measured at end points of VH and VL,
functional range
Output Resistance 46 48 50 Ω P VHH mode enabled, RCV inactive, source: VH = 3.0 V, IHVOUT
= 1 mA and 50 mA; sink: VL = 2.0 V, IHVOUT = −1 mA and −50
mA; V/I
DC Output Current Limit
Source
60 100 mA P VHH mode enabled, RCV inactive, VH = 6.0 V, short HVOUT
pin to −0.1 V, DATA high, measure current
DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCV inactive, VL = −0.1 V, short HVOUT
pin to 6.0 V, DATA low, measure current
Rise Time (VL to VH) 10.0 ns CB VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
Fall Time (VH to VL) 11.3 ns CB VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
Preshoot, Overshoot, and
Undershoot
±54 mV CB VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA
OVERVOLTAGE DETECTOR (OVD)
Table 12.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC CHARACTERISTICS
Programmable Voltage Range −3.0 +7.0 V D
Accuracy Uncalibrated −200 +200 mV P OVD offset errors measured at programmed levels of +7.0 V
and −3.0 V
Hysteresis 112 mV CB
LOGIC OUTPUT CHARACTERISTICS
Off State Leakage 10 1000 nA P Disable OVD alarm, apply 3.3 V to OVD pin, measure
leakage current
Max On Voltage @ 100 A 0.2 0.7 V P Activate alarm, force 100 A into OVD pin, measure active
alarm voltage
Propagation Delay 1.6 s CB For OVD high: DUTx = 0 V to 6 V swing, OVD high = 3.0 V,
OVD low = −3.0 V; for OVD low: DUTx = 0 V to 6 V swing,
OVD high = 7.0 V, OVD low = 3.0 V
16-BIT DAC MONITOR MUX
Table 13.
Parameter Min Typ Max Unit
Test
Level Conditions/Comments
DC CHARACTERISTICS
Programmable Voltage Range −2.5 +7.5 V D
Output Resistance 16 kΩ CT PMUDAC = 0.0 V, FV, I = 0, 200 A; V/I
ADATE305
Rev. 0 | Page 19 of 56
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 14.
Parameter Rating
Supply Voltages
Positive Supply Voltage (VDD to GND) −0.5 V to +11.0 V
Positive VCC Supply Voltage (VCC to GND) −0.5 V to +4.0 V
Negative Supply Voltage (VSS to GND) −6.25 V to +0.5 V
Supply Voltage Difference (VDD to VSS) −1.0 V to +16.5 V
Reference Ground (DUTGND to GND) −0.5 V to +0.5 V
AGND to DGND −0.5 V to +0.5 V
VPLUS Supply Voltage (VPLUS to GND) −0.5 V to +17.5 V
Input Voltages
Input Common-Mode Voltage VSS to VDD
Short-Circuit Voltage1 −3.0 V to +8.0 V
High Speed Input Voltage2 0.0 V to VCC
High Speed Differential Input Voltage3 0.0 V to VCC
VREF −0.5 V to +5.5 V
DUTx I/O Pin Current
DCL Maximum Short-Circuit Current4 ±140 mA
Temperature
Operating Temperature, Junction 125°C
Storage Temperature Range −65°C to +150°C
For liquid cooled applications, θJC = 1.1°C/W.
Table 15. Thermal Resistance
Airflow θJA Unit
Natural Convection 33 °C/W
1 meter per second 30 °C/W
2 meters per second 28.5 °C/W
EXPLANATION OF TEST LEVELS
D Definition
S Design verification simulation
P 100% production tested
PF Functionally checked during production test
CT Characterized on tester
CB Characterized on bench
ESD CAUTION
1 RL = 0 Ω, VDUT continuous short-circuit condition, (VH, VL, VT, high-Z, VCOM,
clamp modes).
2 DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω.
3 DATAxP to DATAxN, RCVxP, RCVxN.
4 RL = 0 Ω, VDUTx = –3 V to +8 V; DCL current limit. Continuous short-circuit
condition. ADATE305 must current limit and survive continuous short circuit.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADATE305
Rev. 0 | Page 20 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
ADATE305
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
767778798081828384858687888990919293949596979899100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
07280-002
NC
NC
AGND
AGND
AGND
COMP_QH1N
COMP_QH1P
COMP_VTT1
COMP_QL1N
COMP_QL1P
AGND
RCV1P
RCV1N
VSS
FFCAP_1A
DATA1P
DATA1N
OVD_CH1
VDD
FFCAP_1B
SCAP1
V
DD/VDD_TMPSNS
TEMPSENSE
NC
NC
NC
NC
AGND
AGND
AGND
COMP_QH0N
COMP_QH0P
COMP_VTT0
COMP_QL0N
COMP_QL0P
AGND
RCV0P
RCV0N
VSS
FFCAP_0A
DATA0P
DATA0N
OVD_CH0
VDD
FFCAP_0B
SCAP0
VPLUS
HVOUT
NC
NC
NC
NC
PMUS_CH0
VSS
VDD
VSSO_0 (DRIVE)
DUT0
VDDO_0 (DRIVE)
AGND
AGND
VSS
VDD
AGND
VDD
VSS
AGND
AGND
VDDO_1 (DRIVE)
DUT1
VSSO_1 (DRIVE)
VDD
VSS
PMUS_CH1
NC
NC
NC
NC
VREF_GND
VREF
AGND
AGND
AGND
RST
VSS
VCC
VDD
SDIN
SCLK
SDOUT
DGND
VDD
VSS
DAC16_MON
CS
AGND
AGND
DUTGND
MEASOUT01/TEMP SENSE
NC
NC
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD IS CONNEC TED TO V
SS
.
Figure 2. Pin Configuration
Table 16. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connect. No physical connection to die.
2 NC No Connect. No physical connection to die.
3 TEMPSENSE Temperature Sense Output.
4 VDD/VDD_TMPSNS Temperature Sense Supply +10.0 V.
5 SCAP1 PMU Stability Capacitor Connection Channel 1 (330 pF).
6 FFCAP_1B PMU Feed Forward Capacitor Connection B Channel 1 (220 pF).
7 VDD Supply +10.0 V.
8 OVD_CH1 Overvoltage Detection Flag Output Channel 1.
9 DATA1N Driver Data Input (Negative) Channel 1.
10 DATA1P Driver Data Input (Positive) Channel 1.
11 FFCAP_1A PMU Feedforward Capacitor Connection A Channel 1 (220 pF).
12 VSS Supply −5.75 V.
ADATE305
Rev. 0 | Page 21 of 56
Pin No. Mnemonic Description
13 RCV1N Receive Data Input (Negative) Channel 1.
14 RCV1P Receive Data Input (Positive) Channel 1.
15 AGND Analog Ground.
16 COMP_QL1P Low-Side Comparator Output (Positive) Channel 1.
17 COMP_QL1N Low-Side Comparator Output (Negative) Channel 1.
18 COMP_VTT1 Comparator Supply Channel 1.
19 COMP_QH1P High-Side Comparator Output (Positive) Channel 1.
20 COMP_QH1N High-Side Comparator Output (Negative) Channel 1.
21 AGND Analog Ground.
22 AGND Analog Ground.
23 AGND Analog Ground.
24 NC No Connect. No physical connection to die.
25 NC No Connect. No physical connection to die.
26 NC No Connect. No physical connection to die.
27 NC No Connect. No physical connection to die.
28 MEASOUT01/TEMP SENSE
Shared Muxed Output. Muxed output shared by PMU MEASOUT Channel 0, PMU
MEASOUT Channel 1, and the temperature sense and temperature sense GND
reference.
29 DUTGND Device Under Test Ground Reference.
30 AGND Analog Ground.
31 AGND Analog Ground.
32 CS Serial Peripheral Interface (SPI®) Chip Select.
33 DAC16_MON 16-Bit DAC Monitor Mux Output.
34 VSS Supply −5.75 V.
35 VDD Supply +10.0 V.
36 DGND Digital Ground.
37 SDOUT Serial Programmable Interface (SPI) Data Output.
38 SCLK Serial Programmable Interface (SPI) Clock.
39 SDIN Serial Programmable Interface (SPI) Data Input.
40 VDD Supply +10.0 V.
41 VCC Supply +3.3 V.
42 VSS Supply −5.75 V.
43 RST Serial Peripheral Interface (SPI) Reset.
44 AGND Analog Ground.
45 AGND Analog Ground.
46 AGND Analog Ground.
47 VREF +5 V DAC Reference Voltage.
48 VREF_GND DAC Ground Reference.
49 NC No Connect. No physical connection to die.
50 NC No Connect. No physical connection to die.
51 NC No Connect. No physical connection to die.
52 NC No Connect. No physical connection to die.
53 AGND Analog Ground.
54 AGND Analog Ground.
55 AGND Analog Ground.
56 Comp_QH0N High-Side Comparator Output (Negative) Channel 0.
57 Comp_QH0P High-Side Comparator Output (Positive) Channel 0.
58 Comp_VTT0 Comparator Supply Channel 0.
59 Comp_QL0N Low-Side Comparator Output (Negative) Channel 0.
60 Comp_QL0P Low-Side Comparator Output (Positive) Channel 0.
61 AGND Analog Ground.
62 RCV0P Receive Data Input (Positive) Channel 0.
ADATE305
Rev. 0 | Page 22 of 56
Pin No. Mnemonic Description
63 RCV0N Receive Data Input (Negative) Channel 0.
64 VSS Supply −5.75 V.
65 FFCAP_0A PMU Feedforward Capacitor Connection A Channel 0 (220 pF).
66 DATA0P Driver Data Input (Positive) Channel 0.
67 DATA0N Driver Data Input (Negative) Channel 0.
68 OVD_CH0 Overvoltage Detection Flag Output Channel 0.
69 VDD Supply +10.0 V.
70 FFCAP_0B PMU Feedforward Capacitor Connection B Channel 0 (220 pF).
71 SCAP0 PMU Stability Capacitor Connection Channel 0 (330 pF).
72 VPLUS Supply +16.75 V.
73 HVOUT High Voltage Driver Output.
74 NC No Connect. No physical connection to die.
75 NC No Connect. No physical connection to die.
76 NC No Connect. No physical connection to die.
77 NC No Connect. No physical connection to die.
78 PMUS_CH0 PMU External Sense Path Channel 0.
79 VSS Supply −5.75 V.
80 VDD Supply +10.0 V.
81 VSSO_0 (DRIVE) Driver Output Supply −5.75 V Channel 0.
82 DUT0 Device Under Test Channel 0.
83 VDDO_0 (DRIVE) Driver Output Supply +10.0 V Channel 0.
84 AGND Analog Ground.
85 AGND Analog Ground.
86 VSS Supply −5.75 V.
87 VDD Supply +10.0 V.
88 AGND Analog Ground.
89 VDD Supply +10.0 V.
90 VSS Supply −5.75 V.
91 AGND Analog Ground.
92 AGND Analog Ground.
93 VDDO_1 (DRIVE) Driver Output Supply +10.0 V Channel 1.
94 DUT1 Device Under Test Channel 1.
95 VSSO_1 (DRIVE) Driver Output Supply −5.75 V Channel 1.
96 VDD Supply +10.0 V.
97 VSS Supply −5.75 V.
98 PMUS_CH1 PMU External Sense Path Channel 1.
99 NC No Connect. No physical connection to die.
100 NC No Connect. No physical connection to die.
EP Exposed Pad. The exposed pad is connected to VSS.
ADATE305
Rev. 0 | Page 23 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05 0 2 4 6 8 10 12 14 16 18
TIME (ns)
VOLTAGE (V)
07280-023
0.2V
0.5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2 4.54.03.52.5 3.02.01.51.00.50
TIME (ns)
VOLTAGE (V)
07280-022
1V
2V
3V
Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V, 50 Ω Termination
Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V;
VL = 0.0 V; 50 Ω Termination
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
VOLTAGE (V)
018
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2 190 2 3 4 5 6 7 8 9 101112131415161718
TIME (ns)
VOLTAGE (V)
07280-021
1V
2V
3V
1V
2V
3V
161412108642
TIME (ns)
07280-024
Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
6
5
4
3
2
1
0
–1
VOLTAGE (V)
018
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0010987654321
TIME (ns)
VOLTAGE (V)
07280-032
1V
2V
3V
161412108642
TIME (ns)
07280-031
1V
5V
3V
Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V;
VL = 0 .0 V; 500 Ω Termination
Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
ADATE305
Rev. 0 | Page 24 of 56
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.56.0
TIME (ns)
VOLTAGE (V)
07280-026
1V
2V
3V
0.5V
Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
000.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
TIME (ns)
VOLTAGE (V)
07280-027
1V
2V
3V
0.5V
Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
1.2
1.0
0.8
0.6
0.4
0.2
0
200 250 300 350 400 450 500 550 600
FREQUENCY (MHz)
VOLTAGE (V)
07280-084
Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Ω Termination
0.6
0.5
0.4
0.3
0.2
0.1
0
VOLTAGE (V)
07280-028
TIME (ns)
18161412108642117151311975310 9
Figure 12. Driver Active (VH and VL) to and from VTERM Transition;
VH = 1.0 V, VT = 0.5 V, VL = 0.0 V
1.2
1.0
0.8
0.6
0.4
0.2
0
VOLTAGE (V)
TIME (ns)
07280-029
18161412108642117151311975310 9
Figure 13. Driver Active (VH and VL) to and from VTERM Transition;
VH = 2.0 V, VT = 1.0 V, VL = 0.0 V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
VOLTAGE (V)
0
TIME (ns)
07280-030
2018161412108642
Figure 14. Driver Active (VH and VL) to and from VTERM Transition;
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V
ADATE305
Rev. 0 | Page 25 of 56
–20
–40
–60
–80
0
20
12345678
PULSEWIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-036
910
0.2V NEG
0.2V POS
Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V
–20
–40
–60
0
20
12345678
PULSEWIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-037
910
0.5V NEG
0.5V POS
Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V
0
–10
–20
–30
–40
–50
–60
10
12345678
PULSEWIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-033
910
1V NEG
1V POS
Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V
0
–20
–40
–60
–80
–100
40
20
12345678
PULSEWIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-034
910
2V NEG
2V POS
Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V
–20
–40
–60
–80
–100
40
20
0
12345678
PULSE WIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-035
910
3V NEG
3V POS
Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2 –1 0 1 2 3 4 5 6 7
DRIVER OUTPUT VOLTAGE (V)
LINEARITY ERROR (mV)
07280-051
Figure 20. Driver VH Linearity Error
ADATE305
Rev. 0 | Page 26 of 56
1.5
1.0
0.5
0
–1.0
–0.5
–1.5
–2–10123456
DRIVER OUTPUT VOLTAGE (V)
LINEARITY ERROR (mV)
07280-052
Figure 21. Driver VL Linearity Error
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2–10123456
DRIVER OUTPUT VOLTAGE (V)
LINEARITY ERROR (mV)
07280-053
Figure 22. Driver VT Linearity Error
48.5
48.0
47.5
47.0
46.5
46.0
–60 –40 –20 0 20 40 60
DRIVER OUTPUT CURRENT (mA)
DRIVER OUTPUT RESISTANCE ()
007280-054
Figure 23. Driver Output Resistance vs. Output Current
100
90
80
70
50
60
40
30
20
0
10
–10
–2–10123456
V
DUTx
(V)
DRIVER OUTPUT CURRENT (mA)
07280-055
Figure 24. Driver Output Current Limit; Driver Programmed to −2.0 V;
VDUTx Swept from −2.0 V to +6.0 V
0
–10
–20
–30
–50
–40
–60
–70
–80
–100
–90
–2–10123456
V
DUTx
(V)
DRIVER OUTPUT CURRENT (mA)
07280-056
Figure 25. Driver Output Current Limit; Driver Programmed to 6.0 V;
VDUTx Swept from −2.0 V to +6.0 V
–
722
–723
–724
–725
–726
–727
–728
–729
–730–1 0 1 2 3 4 5 6
VL PROGRAMMED VOLTAGE (V)
LINEARITY ERROR (mV)
07280-057
Figure 26. HVOUT VL Linearity Error
ADATE305
Rev. 0 | Page 27 of 56
6
4
2
0
–2
–4
–6
–8
–10
–12
567891011121314
VL PROGRAMMED VOLTAGE (V)
LINEARITY ERROR (mV)
07280-058
Figure 27. HVOUT VHH Linearity Error
70
80
60
50
40
30
20
10
0
–10
–1 0 1 2 3 4 5 6
V
HVOUT
(V)
HVOUT DRIVER CURRENT (mA)
07280-059
Figure 28. HVOUT VH Current Limit; VH = −0.1 V;
VHVOUT Swept from −0.1 V to +6.0 V
80
60
40
20
0
–20
–40
–60
–80
5 6 7 8 9 101112131415
V
HVOUT
(V)
HVOUT DRIVER CURRENT (mA)
07280-060
Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V;
VHVOUT Swept from −5.9 V to +14.1 V
1.0
0.8
0.6
0.4
0.2
0
0 0.6 1.2 1.8 2.4 3.0
TIME (ns)
VOLTAGE (V)
07280-049
RISE INPUT
FALL INPUT
RISE SHMOO
FALL SHMOO
Figure 30. Comparator Shmoo, 1.0 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
1.6
1.2
0.8
0.4
0
0 0.6 1.2 1.8 2.4 3.0
TIME (ns)
VOLTAGE (V)
07280-048
RISE INPUT
FALL INPUT
RISE SHMOO
FALL SHMOO
Figure 31. Comparator Shmoo, 1.5 V Input, 1.5 ns (10% to 90%) Input,
50 Ω Terminated
1.6
1.2
0.8
0.4
0
0 0.6 1.2 1.8 2.4 3.0
TIME (ns)
VOLTAGE (V)
07280-047
RISE INPUT
FALL INPUT
RISE SHMOO
FALL SHMOO
Figure 32. Comparator Shmoo, 1.5 V Input, 1.2 ns (10% to 90%) Input,
50 Ω Terminated
ADATE305
Rev. 0 | Page 28 of 56
1.6
1.2
0.8
0.4
0
0 0.6 1.2 1.8 2.4 3.0
TIME (ns)
VOLTAGE (V)
07280-046
RISE INPUT
FALL INPUT
RISE SHMOO
FALL SHMOO
Figure 33. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
1.6
1.2
0.8
0.4
0
0 0.6 1.2 1.8 2.4 3.0
TIME (ns)
VOLTAGE (V)
07280-045
RISE INPUT
FALL INPUT
RISE SHMOO
FALL SHMOO
Figure 34. Comparator Shmoo, 1.5 V Input, 0.625 ns (10% to 90%) Input,
50 Ω Terminated
0
–10
–20
–30
–40
–50
–60
–70
–80
10
12345678
PULSEWIDTH (ns)
TRAILING EDGE ERROR (ps)
07280-038
910
1V NEG
1V POS
Figure 35. Comparator Minimum Pulse Width, 1.0 V
100
75
50
25
0
–25
–50
0.5 1.0 1.5 2.0 2.5
INPUT SLEW RATE (10%-90%) (ns)
PROPAGATION DELAY VARIATION (ps)
07280-050
RISING
FALLING
TOTAL
Figure 36. Comparator Slew Rate Dispersion, Input Swing = 1.5 V,
Comparator Threshold = 0.75 V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VOLTAGE (V)
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
07280-025
COMP_QH0N
COMP_QH0P
Figure 37. Comparator Output Waveform, COMP_QH0P, COMP_QH0N
0.8
0.6
0.4
0.2
–0.2
0
–0.4
–0.6
–0.8
–1.2
–1.0
–1.4
–2–10123456
PROGRAMMED THRESHOLD VOLTAGE (V)
LINEARITY ERROR (mV)
07280-061
Figure 38. Comparator Threshold Linearity
ADATE305
Rev. 0 | Page 29 of 56
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
–2 –1 0 1 2 3 4 5
INPUT COMMON-MODE VOLTAGE (V)
DIFFERENTIAL COMPARATOR OFFSET (mV)
07280-062
Figure 39. Differential Comparator CMRR
15
10
5
0
–10
–5
–15
–2–10123456
V
DUTx
(V)
LOAD CURRENT (mA)
07280-063
Figure 40. Active Load Commutation Response; VCOM = 2.0 V;
IOH = IOL = 12 mA
6
4
2
0
–2
–4
–6
–8
0 2 4 6 8 10 12
ACTIVE LOAD CURRENT (mA)
LINEARITY ERROR (µA)
07280-064
Figure 41. Active Load Current Linearity
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–2 –1 0 1 2 3 4 5 6
VCOM VOLTAGE (V)
LINEARITY ERROR (mV)
07280-065
Figure 42. Active Load VCOM Linearity
3.4
3.2
3.0
2.8
2.4
2.6
2.2
2.0
–2–10123456
VDUTx (V)
IDUTx (nA)
07280-067
Figure 43. DUTx Pin Leakage in Low Leakage Mode
3.0
2.5
2.0
1.5
0.5
1.0
0
–0.5
–2–10123456
VDUTx (V)
IDUTx (nA)
07280-066
Figure 44. DUTx Pin Leakage in High-Z Mode
ADATE305
Rev. 0 | Page 30 of 56
40
20
0
–20
–40
–60
–80
–100
–120
–140
–40 –30 –20 –10 0 10 20 30 40
PMU OUTPUT CURRENT (mA)
LINEARITY ERROR (µA)
07280-068
Figure 45. PMU Force Current Range A Linearity
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
PMU OUTPUT CURRENT (mA)
LINEARITY ERROR (µA)
07280-069
Figure 46. PMU Force Current Range B Linearity
0.08
0.06
0.04
0.02
–0.02
0
–0.04
–0.06
–0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20
PMU OUTPUT CURRENT (mA)
LINEARITY ERROR (µA)
07280-070
Figure 47. PMU Force Current Range C Linearity
0.008
0.006
0.004
0.002
–0.002
0
–0.004
–0.006
–0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020
PMU OUTPUT CURRENT (mA)
LINEARITY ERROR (µA)
07280-071
Figure 48. PMU Force Current Range D Linearity
0.0005
0.0004
0.0003
0.0002
0
0.0001
–0.0001
–0.0002
–0.0003
–0.0005
–0.0004
–0.0006
–0.0020 –0.0015 –0.0010 –0.0050 0 0.0050 0.0010 0.0015 0.0020
PMU OUTPUT CURRENT (mA)
LINEARITY ERROR (µA)
07280-072
Figure 49. PMU Force Current Range E Linearity
5
4
3
2
1
0
–1
–2
–3
–4
–40 –30 –20 –10 0 10 20 30 40
I
DUTx
(mA)
PMU VOLTAGE ERROR (mV)
07280-073
Figure 50. PMU Force Voltage Range A Output Voltage Error at 6.0 V vs.
Output Current
ADATE305
Rev. 0 | Page 31 of 56
5
4
3
2
1
0
–1
–2
–3
–4
–40 –30 –20 –10 0 10 20 30 40
IDUTx (mA)
PMU VOLTAGE ERROR (mV)
07280-074
Figure 51. PMU FV Range A Output Voltage Error at −1.5 V vs. Output Current
0.6
0.4
0.2
0
–0.4
–0.2
–0.6
–0.8
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
I
DUTx
(mA)
PMU VOLTAGE ERROR (mV)
07280-075
Figure 52. PMU FV Range B Output Voltage Error at 6.0 V vs. Output Current
0.6
0.4
0.2
0
–0.4
–0.2
–0.6
–0.8
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
I
DUTx
(mA)
PMU VOLTAGE ERROR (mV)
07280-076
Figure 53. PMU FV Range B Output Voltage Error at −1.5 V vs. Output Current
10
0
–10
–20
–40
–30
–50
–60
–2–10123456
V
DUTx
(V)
PMU CURRENT ERROR (µA)
07280-077
Figure 54. PMU FI Range A Output Current Error at −32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
10
0
–10
–20
–40
–30
–50
–60
–2–10123456
V
DUTx
(V)
PMU CURRENT ERROR (µA)
07280-078
Figure 55. PMU FI Range A Output Current Error at +32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
0.5
0.4
0.3
0.2
0
0.1
–0.1
–0.2
–2 –1 0 1 2 3 4 5 6
V
DUTx
(V)
PMU CURRENT ERROR (µA)
07280-079
Figure 56. PMU FI Range B Output Current Error at −2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
ADATE305
Rev. 0 | Page 32 of 56
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–2 –1 0 1 2 3 4 5 6
VDUTx (V)
PMU CURRENT ERROR (µA)
07280-080
Figure 57. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
0.0015
0.0010
0.0005
0
–0.0010
–0.0005
–2–10123456
VDUTx (V)
PMU CURRENT ERROR (µA)
07280-081
Figure 58. PMU FI Range E Output Current Error at −2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
0.0016
0.0014
0.0012
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–2–10123456
V
DUTx
(V)
PMU CURRENT ERROR (µA)
07280-082
Figure 59. PMU FI Range E Output Current Error at +2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–2 –1 0 1 2 3 4 5
V
DUTx
(V)
PMU VOLTAGE ERROR (mV)
07280-083
Figure 60. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI; Error
of MI vs. External 1 mA
07280-039
960ps/DIV
89mV/DI
V
Figure 61. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
07280-040
400ps/DIV
89mV/DI
V
Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
ADATE305
Rev. 0 | Page 33 of 56
07280-041
250ps/DIV
100mV/DI
V
07280-043
400ps/DIV
130mV/DI
V
Figure 63. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V Figure 65. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
07280-042
200ps/DIV
100mV/DI
V
07280-044
250ps/DIV
130mV/DI
V
Figure 66. Eye Diagram, 600 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
Figure 64. Eye Diagram, 800 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
ADATE305
Rev. 0 | Page 34 of 56
SPI DETAILS
07280-003
SCLK
CS
SDIN
t
CH
t
CL
t
CSSA
t
CSHA
t
CSHD
t
CSSD
t
DH
t
DS
t
CSW
SDOUT DO_2
LAST
DO_12
LAST
DO_13
LAST
DO_14
LAST
DO_15
LAST
DO_1
LAST
DO_0
LAST
t
DO
DATA[14]DATA[15]
CH[1] R/W
ADDR[1] ADDR[0]
Figure 67. SPI Timing Diagram
Table 17. Serial Peripheral Interface Timing Requirements
Symbol Parameter Min Max Unit
tCH SCLK minimum high 9.0 ns
tCL SCLK minimum low 9.0 ns
tCSHA CS assert hold 3.0 ns
tCSSA CS assert setup 3.0 ns
tCSHD CS deassert hold 3.0 ns
tCSSD CS deassert setup 3.0 ns
tDH SDIN hold 3.0 ns
tDS SDIN setup 3.0 ns
tDO SDOUT Data Out 15.0 ns
tCSW CS minimum between assertions1
2 SCLK cycles
CS minimum directly after a read request 3 SCLK cycles
tCSTP Minimum delay after CS is deasserted before SCLK can be
stopped (not shown in ); this allows any internal
operations to complete
Figure 67
16 SCLK cycles
1 An extra cycle is needed after a read request to prime the read data into the SPI shift register.
ADATE305
Rev. 0 | Page 35 of 56
DEFINITION OF SPI WORD
The SPI can accept variable length words, depending on the
operation. At most, the word length equals 24 bits: 16 bits of
data, two channel selects, one R/W selector, and a 5-bit address.
Depending on the operation, the data can be smaller or, in the
case of a read operation, nonexistent.
Table 18. Channel Selection
Channel 1 Channel 0 Channel Selected
0 0 NOP (no channel selected, no register
changes)
0 1 Channel 0 selected
1 0 Channel 1 selected
1 1 Channel 0 and Channel 1 selected
Table 19. R/W Definition
R/W Description
0 Current register specified by address shifts out of
SDOUT on next shift operation
1 Current data is written to the register specified by
address and channel select
Example 1: 16-Bit Write
Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are
applied to the 14-bit DAC.
07280-004
DATA[15:0] CH[1:0] R/W ADDR[4:0]
Figure 68. 16-Bit Write
Example 2: 14-Bit Write
Write 14 bits of data to the DAC.
07280-00
5
DATA[13:0] CH[1:0] R/W ADDR[4:0]
Figure 69. 14-Bit Write
Example 3a: 2-Bit Write
Write two bits of data to the 2-bit register.
07280-006
DATA[1:0] CH[1:0] R/W ADDR[4:0]
Figure 70. 2-Bit Write
Example 3b: 2-Bit Write
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.
07280-007
DATA[15:0] CH[1:0] R/W ADDR[4:0]
Figure 71. 2-Bit Write
Example 4: Read Request
Read request and follow with a second instruction (could be NOP) to clock out the data.
07280-008
DATA[15:0] CH[1:0] R/W ADDR[4:0]
CH[1:0] R/W = 0 ADDR[4:0]
Figure 72. Read Request
ADATE305
Rev. 0 | Page 36 of 56
WRITE OPERATION
07280-009
0232221201918171615141312 24 25
NOTES
1. R/W = 1.
2. X = DON’T CARE.
DATA[15] DATA[14] DATA[13]
DATA[2] DATA[1] DATA[0] CH[1] CH[0]
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0] X
R/W
SCLK
INPUT
SDIN
INPUT
CS
INPUT
SDOUT
OUTPUT
X
Figure 73. 16-Bit SPI Write
07280-010
01110987654123
DATA[1] DATA[0] CH[ 1] CH[0] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]R/W
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
X
X
CS
INPUT
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 74. 2-Bit SPI Write
ADATE305
Rev. 0 | Page 37 of 56
READ OPERATION
The read operation is a two-stage operation. First, a word is
shifted in, specifying which register to read. CS is deasserted
for three clock cycles, and then a second word is shifted in to
obtain the readback data. This second word can be either
another operation or an NOP address. If another operation is
shifted in, it needs to shift in at least eight bits of data to read
back the previous specified data. The NOP address can be used
for this read if there is no need to write/read another register. To
maintain the clarity of the operation, it is strongly recommended
that the NOP address be used for all reads.
Any register read that is fewer than 16 bits has zeroes filled in
the top bits to make it a 16-bit word.
07280-011
XXREAD INSTRUCTION NOP
XREAD DATAX
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
CS
INPUT
NOTES
1. X = DON’T CARE.
Figure 75. SPI Read Overview
07280-012
X
DATA[15:0], VALUE IS A DON’T CARE
02524232221201918171615141312
CH[1]
X
R/WCH[0] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
CS
INPUT
NOTES
1. X = DON’T CARE.
Figure 76. SPI Read—Details of Read Request
07280-013
X
DATA[15:0], VALUE IS A DON’T CARE
02524232221201918171615141312
CH[1]
RDATA[15] RDATA[2] RDATA[1] RDATA[0]
RDATA[14]
X
R/W = 1
ADDR[4:0] = 0x00 (NOP)
CH[0]
SCLK
INPUT
SDIN
INPUT
SDOUT
OUTPUT
CS
INPUT
NOTES
1. RDATA IS THE REGISTER VALUE BEING READ.
2. X = DON’T CARE.
Figure 77. SPI Read—Details of Read Out
ADATE305
Rev. 0 | Page 38 of 56
RESET OPERATION
The ADATE305 contains an asynchronous reset feature. The
ADATE305 can be reset to the default values shown in Table 2 0
by utilizing the RST pin. To initiate the reset operation, deassert
the RST pin for a minimum of 100 ns and deassert the CS pin
for a minimum of two SCLK cycles.
07280-014
RST
CS
SCLK
100ns
MINIMUM
MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.
Figure 78. Reset Operation
ADATE305
Rev. 0 | Page 39 of 56
REGISTER MAP
The ADDR[4:0] bits determine the destination register of the data being written to the ADATE305.
Table 20. Register Selection
DATA[15:0] CH[1:0] R/W ADDR[4:0] Register Selected Reset State
N/A1N/A N/A 0x00 NOP N/A
DATA[13:0] CH[1:0] R/W 0x01 VH DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x02 VL DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x03 VT/VCOM DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x04 VOL DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x05 VOH DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x06 VCH DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x07 VCL DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x08 V(IOH ) DAC level 4096d
DATA[13:0] CH[1:0] R/W 0x09 V(IOL ) DAC level 4096d
DATA[13:0] CH[1] R/W 0x0A OVD high level 4096d
DATA[13:0] CH[0] R/W 0x0A OVD low level 4096d
DATA[15:0] CH[1:0] R/W 0x0B PMUDAC level 16384d
DATA[2:0] CH[1:0] R/W 0x0C PE/PMU enable 000b
DATA[2:0] CH[1:0] R/W 0x0D Channel state 000b
DATA[9:0] CH[1:0] R/W 0x0E PMU state 0d
DATA[2:0] CH[1:0] R/W 0x0F PMU measure enable 000b
DATA[0] CH[1:0] R/W 0x10 Differential comparator enable 0b
DATA[1:0] CH[1:0] R/W 0x11 16-bit DAC monitor 00b
DATA[1:0] CH[1:0] R/W 0x12 OVD_CHx alarm mask 01b
DATA[2:0] CH[1:0] R 0x13 OVD_CHx alarm state N/A
N/A N/A N/A 0x14 to 0x1F Reserved N/A
1 N/A means not applicable.
ADATE305
Rev. 0 | Page 40 of 56
DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit Name Description
DATA[2] PMU enable 0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU state bits are ignored, except for PMU sense path (Data[7])
DATA[1] Force VT 0 = normal driver operation
1 = force driver to VT
See Table 29 for complete functionality of this bit
DATA[0] PE disable 0 = enable driver functions
1 = disable driver (low leakage)
See Table 29 for complete functionality of this bit
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit Name Description
DATA[2] HV mode select 0 = HV driver in low impedance.
1 = enable HV driver.
This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
DATA[1] Load enable 0 = disable load.
1 = enable load.
See Table 29 for complete functionality of this bit.
DATA[0] Driver high-Z or VT 0 = enable Driver high-Z function.
1 = enable Driver VTERM function.
See Table 29 for complete functionality of this bit.
Table 23. PMU State (ADDR[4:0] = 0x0E)1, 2
Bit Name Description
DATA[9:8] PMU input selection 00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
DATA[7] PMU sense path 0 = internal sense
1 = external sense
DATA[6] Reserved
DATA[5] PMU clamp enable 0 = disable clamps
1 = enable clamps
DATA[4] PMU measure voltage or current 0 = measure voltage mode
1 = measure current mode
DATA[3] PMU force voltage or current 0 = force voltage mode
1 = force current mode
DATA[2:0] PMU range 0XX = 2 A range
100 = 20 A range
101 = 200 A range
110 = 2 mA range
111 = 32 mA range
1 Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.
PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.
2 X = don’t care.
ADATE305
Rev. 0 | Page 41 of 56
Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F)1
Bit Name Description
DATA[2:1] MEASOUT01 select 00 = PMU MEASOUT Channel 0
01 = PMU MEASOUT Channel 1
10 = Temp sensor ground reference
11 = Temp sensor
DATA[0] MEASOUT01 output enable 0 = MEASOUT01 is tristated
1 = MEASOUT01 is enabled
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10)1
Bit Name Description
DATA[0] Differential Comparator Enable 0 = differential comparator is disabled; the Channel 0 normal window
comparator (NWC) outputs are located on Channel 0
1 = differential comparator is enabled; the differential comparator outputs
are located on Channel 0
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11)1
Bit Name Description
DATA[1] 16-Bit DAC mux enable 0 = 16-bit DAC mux is tristated
1 = 16-bit DAC mux is enabled
DATA[0] 16-Bit DAC mux select 0 = 16-bit DAC Channel 0
1 = 16-bit DAC Channel 1
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)
Bit Name Description
DATA[1] PMU mask 0 = disable PMU alarm flag
1 = enable PMU alarm flag
DATA[0] OVD mask 0 = disable OVD alarm flag
1 = enable OVD alarm flag
Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13)1
Bit Name Description
DATA[2] PMU clamp flag 0 = PMU is not clamped
1 = PMU is clamped
DATA[1] OVD high flag 0 = DUT voltage < OVD high voltage
1 = DUT voltage > OVD high voltage
DATA[0] OVD low flag 0 = DUT voltage > OVD low voltage
1 = DUT voltage < OVD low voltage
1 This register is a read-only register.
ADATE305
Rev. 0 | Page 42 of 56
USER INFORMATION
Table 29. Driver and Load Truth Table1
Registers Signals
Driver State Load State
PE Disable
DATA[0]
ADDR[4:0] = 0x0C
Force VT
DATA[1]
ADDR[4:0] = 0x0C
Load Enable
DATA[1]
ADDR[4:0] = 0x0D
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0D DATAx RCVx
1 X X X X X High-Z without clamps Power-down
0 1 X X X X VT Power-down
0 0 0 0 0 0 VL Power-down
0 0 0 0 0 1 High-Z with clamps Power-down
0 0 0 0 1 0 VH Power-down
0 0 0 0 1 1 High-Z with clamps Power-down
0 0 0 1 0 0 VL Power-down
0 0 0 1 0 1 VT Power-down
0 0 0 1 1 0 VH Power-down
0 0 0 1 1 1 VT Power-down
0 0 1 0 0 0 VL Active off
0 0 1 0 0 1 High-Z with clamps Active on
0 0 1 0 1 0 VH Active off
0 0 1 0 1 1 High-Z with clamps Active on
0 0 1 1 0 0 VL Active on
0 0 1 1 0 1 High-Z with clamps Active on
0 0 1 1 1 0 VH Active on
0 0 1 1 1 1 High-Z with clamps Active on
1 X = don’t care.
Table 30. HVOUT Truth Table1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
Channel 0
RCV
Channel 0
DATA HVOUT Driver Output
1 1 X VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
1 0 0 VL (Channel 0 VL DAC)
1 0 1 VH (Channel 0 VH DAC)
0 X X Disabled (HVOUT pin set to 0 V low impedance)
1 X = don’t care.
Table 31. Comparator Truth Table
Differential
Comparator Enable
DATA[0]
ADDR[4:0] = 0x10 COMP_QH0 COMP_QL0 COMP_QH1 COMP_QL1
0 Normal window mode Normal window mode Normal window mode Normal window mode
Logic high: VOH0 < VDUT0 Logic high: VOL0 < VDUT0 Logic high: VOH1 < VDUT1 Logic high: VOL1 < VDUT1
Logic low: VOH0 > VDUT0 Logic low: VOL0 > VDUT0 Logic low: VOH1 > VDUT1 Logic low: VOL1 > VDUT1
1 Differential comparator mode Differential comparator mode Normal window mode Normal window mode
Logic high: VOH0 < VDUT0 − VDUT1 Logic high: VOL0 < VDUT0 − VDUT1 Logic high: VOH1 < VDUT1 Logic high: VOL1 < VDUT1
Logic low: VOH0 > VDUT0 − VDUT1 Logic low: VOL0 > VDUT0 − VDUT1 Logic low: VOH1 > VDUT1 Logic low: VOL1 > VDUT1
ADATE305
Rev. 0 | Page 43 of 56
DETAILS OF DACS vs. LEVELS
There are ten 14-bit DACs per channel. These DACs provide
levels for the driver, comparator, load currents, VHH buffer, OVD,
and clamp levels. There are three versions of output levels as
follows:
• −2.5 V to +7.5 V and tracks DUTGND. Controls the VH,
VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
• −3.0 V to +7.0 V and tracks DUTGND. Controls the
OVD levels.
• −2.5 V to +7.5 V and does not track DUTGND. Controls
the IOH and IOL levels.
There is one 16-bit DAC per channel. This DAC provides the
levels for the PMU. The output level is as follows:
• −2.5 V to +7.5 V and tracks DUTGND; controls the
PMU levels.
Table 32. Level Transfer Functions
DAC Transfer Function
Programmable Range1
(All 0s to All 1s) Levels
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) – 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
−2.5 V to +7.5 V VH, VL, VT/VCOM,
VOL, VOH, VCH, VCL
VOUT = 4.0 × (VREF − VREF_GND) × (Code/(214)) − 1.0 × (VREF − VREF_GND) + 2.0 + VDUTGND
Code = [VOUT − VDUTGND − 2.0 + 1.0 × (VREF − VREF_GND)] × [(214)/(4.0 × (VREF − VREF_GND))]
−3.0 V to +17.0 V VHH
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.6 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.6 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
−3.0 V to +7.0 V OVD
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND)] × (0.012/5.0)
Code = [(IOUT × (5.0/0.012)) + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
−6 mA to +18 mA IOH, IOL
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−2.5 V to +7.5 V PMUDAC
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.050/5.0)
Code = [(IOUT × (5.0/0.050)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−50 mA to +50 mA PMUDAC
(PMU FI Range A)
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.004/5.0)
Code = [(IOUT × (5.0/0.004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−4 mA to +4 mA PMUDAC
(PMU FI Range B)
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.0004/5.0)
Code = [(IOUT × (5.0/0.0004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−400 A to +400 A PMUDAC
(PMU FI Range C)
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.00004/5.0)
Code = [(IOUT × (5.0/0.00004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−40 A to +40 A PMUDAC
(PMU FI Range D)
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) – 0.5 × (VREF − VREF_GND) − 2.5] × (0.000004/5.0)
Code = [(IOUT × (5.0/0.000004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−4 A to +4 A PMUDAC
(PMU FI Range E)
1 Programmable range includes a margin outside of the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level Transfer Function1
IOL V(IOL)/5 V × 12 mA
IOH V(IOH)/5 V × 12 mA
1 V(IOH), V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode Transfer Functions
Force Voltage VOUT = PMUDAC
Measure Voltage VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense)
Force Current IOUT = [PMUDAC − (VREF/2)]/(R1 × 5)
Measure Current VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx × 5 × R1)
1 R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.
ADATE305
Rev. 0 | Page 44 of 56
Table 35. PMU User Required Capacitors
Capacitor Location
220 pF Across Pin 70 (FFCAP_0B) and Pin 65 (FFCAP_0A)
220 pF Across Pin 6 (FFCAP_1B) and Pin 11 (FFCAP_1A)
330 pF Between GND and Pin 71 (SCAP0)
330 pF Between GND and Pin 5 (SCAP1)
Table 36. Temperature Sensor
Temperature Output
0 K 0 V
300 K 3 V
x K (x K) × 10 mV/K
Table 37. Power Supply Ranges
Parameter Range 1 Range 2
Nominal VDD +10.0 V +10.0 V
Nominal VSS −5.25 V −5.75 V
Driver
VH range −1.4 V to +6.0 V −1.9 V to +6.0 V
VL range −1.5 V to +5.9 V −2.0 V to +5.9 V
VT range −1.5 V to +6.0 V −2.0 V to +6.0 V
Functional Amplitude 7.5 V 8.0 V
Reflection Clamp
VCH Range −1.0 V to +6.0 V −1.5 V to +6.0 V
VCL Range −1.5 V to +5.0 V −2.0 V to +5.0 V
Comparator Input Voltage Range −1.5 V to +6.0 V −2.0 V to +6.0 V
Active Load VCOM Range −1.25 V to +5.75 V −1.75 V to +5.75 V
PMU
Force Voltage Range −1.5 V to +6.0 V −2.0 V to +6.0 V
Measure Voltage Range −1.5 V to +6.0 V −2.0 V to +6.0 V
Force Current Voltage Range −1.5 V to +6.0 V −2.0 V to +6.0 V
Measure Current Voltage Range −1.5 V to +6.0 V −2.0 V to +6.0 V
Low Clamp Range −1.5 V to +4.0 V −2.0 V to +4.0 V
High Clamp Range 0.0 V to +6.0 V 0.0 V to +6.0 V
ADATE305
Rev. 0 | Page 45 of 56
Table 38. Default Test Conditions (Range 1)
Name Default Test Condition
VH DAC Level +2.0 V
VL DAC Level +0.0 V
VT/VCOM DAC Level +1.0 V
VOL DAC Level −1.0 V
VOH DAC Level +6.0 V
VCH DAC Level +7.5 V
VCL DAC Level −2.5 V
IOH DAC Level 0.0 A
IOL DAC Level 0.0 A
OVD Low DAC Level −2.5 V
OVD High DAC Level +6.5 V
PMUDAC DAC Level 0.0 V
PE/PMU Enable 0x0000: PMU disabled, VT not forced through driver, PE enabled
Channel State 0x0000: HV mode disabled, load disabled, VTERM inactive
PMU State 0x0000: Input of DUTGND, internal sense, clamps disabled, FVMV, Range E
PMU Measure Enable 0x0000: MEASOUT01 pin tristated
Differential Comparator Enable 0x0000: Normal window comparator mode
16-Bit DAC Monitor 0x0000: DAC16_MON tristated
OVD_CHx Alarm Mask 0x0000: disable alarm functions
Data Input Logic low
Receive Input Logic low
DUTx Pin Unterminated
Comparator Output Unterminated
ADATE305
Rev. 0 | Page 46 of 56
RECOMMENDED PMU MODE SWITCHING
SEQUENCES
To minimize any possible aberrations and voltage spikes on the
DUT output, specific mode switching sequences are
recommended for the following transitions:
• PMU disable to PMU enable.
• PMU force voltage mode to PMU force current mode.
• PMU force current mode to PMU force voltage mode.
PMU Disable to PMU Enable
Note that in Table 39 through Table 49, X indicates the don’t care bit.
Step 1. Table 39 lists the state of the registers in PMU disabled mode.
Table 39.
Register Bits Setting
PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 0
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] X
DATA[2:0] XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).
Table 40.
Register Bits Setting Comments
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X or 00 Set desired input selection
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 0
This bit must be set to force voltage mode to reduce
aberrations
DATA[2:0] XXX Set desired range
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).
Table 41.
Register Bits Setting Comments
PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1 PMU is now enabled in force voltage mode
PMU Force Voltage Mode to PMU Force Current Mode
Step 1. Table 42 lists the state of registers in force voltage mode.
Table 42.
Register Bits Setting
PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 0
DATA[2:0] XXX
ADATE305
Rev. 0 | Page 47 of 56
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).
Table 43.
Register Bits Setting Comments
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 01 Set 2.5 V + DUTGND input selection
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 1 Set to force current mode
DATA[2:0] 0XX 2 A range has the minimum offset current
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).
Table 44.
Register Bits Setting Comments
VIN 16-Bit DAC, ADDR[4:0] = 0x0B DATA[15:0] X Update the VIN 16-Bit DAC register to the
desired value
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).
Table 45.
Register Bits Setting Comments
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X Set VIN input selection
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 1
DATA[2:0] XXX Set to the desired current range
Transition from PMU Force Current Mode to PMU Force Voltage Mode
Step 1. Table 46 lists the state of the registers in force current mode.
Table 46.
Register Bits Setting
PE/PMU Enable Register, ADDR[4:0] = 0x0C DATA[2] 1
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] XX
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 1
DATA[2:0] XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47).
Table 47.
Register Bits Setting Comments
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 00 Set DUTGND input selection
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 0 Set to force voltage mode
DATA[2:0] XXX Set to the desired current range
ADATE305
Rev. 0 | Page 48 of 56
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48).
Table 48.
Register Bits Setting Comments
VIN 16-Bit DAC, ADDR[4:0] = 0x0B DATA[15:0] X Update the VIN 16-Bit DAC register to the desired value
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49).
Table 49.
Register Bits Setting Comments
PMU State Register, ADDR[4:0] = 0x0E DATA[9:8] 1X Set VIN input selection
DATA[7] X
DATA[6] X
DATA[5] X
DATA[4] X
DATA[3] 0 Force voltage mode
DATA[2:0] XXX
ADATE305
Rev. 0 | Page 49 of 56
BLOCK DIAGRAMS
RCV
VT
V
CL
V
CH
DATA
VH
VL
V(IOL)
V(IOH)
DUT
DRIVER HIGH-Z/VT DATA[0]
(ADDR[4:0] = 0x0D)
VT BUFFER WHEN 1
HIGH-Z BUFFER WHEN 0
FORCE VT DATA[1] (ADDR[4:0] = 0x0C)
OVERRIDES THE RCV PIN AND FORCES
V
TERM MODE ON THE DRIVER AND LOAD
POWER-DOWN MODE
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)
FORCES SWITCHES OPEN AND POWERS
DOWN LOAD WHEN 0
PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)
FORCES SWITCH OPEN WHEN 1
R
OUT
= 47
(TRIMMED)
DRIVER
VCOM
07280-015
Figure 79. Driver and Load Block Diagram
48
VL
DATA
RCV (SHOWN IN
RCV = 0 STATE)
VHH = (VT + 1V) × 2 + DUTGND
VH
~5
HV MODE SELECT DATA[2]
(ADDR [4:0] = 0x0D) DISABLES
HV DRIVER AND FORCES
0V ON HVOUT WHEN 0
HVOUT
07280-016
Figure 80. HVOUT Driver Output Stage
ADATE305
Rev. 0 | Page 50 of 56
07280-017
–
–
–
–
+
DUT0 –
DUT1
2:1
MUX
DIFFERENTIAL
COMPARATOR ENABLE
DATA[0] (ADDR[4:0] = 0x10)
+
VOL0
V
OH0
DUT1
DUT0–
DUT1
DIFFERENTIAL
BUFFER VOL0
VOH0
VOL
NWC
VOH
NWC
VOL
DMC
VOH
DMC
DUT0
COMP_QH0
COMP_QL0
2:1
MUX
NOTES
1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
+
+
Figure 81. Comparator Block Diagram
50
50
GND
VTT = 3.3V
OUT HIGH = 1.55V
OUT CM = 1.42V
OUT LOW = 1.30V
100
RECEIVER
07280-018
COMPARATOR
OUTPUT (AB)
Figure 82. Comparator Output Scheme
ADATE305
Rev. 0 | Page 51 of 56
2.5 + DUTGND
10k
225k
2µA 20µA 200µA 2mA
22.5k2.25k250
CRA = 220pF
FFCAP_xA FFCAP_xB
MV
15.5
DUTx
REF
IN-AMP G = 5
MEASOUT01 SELECT DATA[2:1]
(ADDR[4:0] = 0x0F)
PMU FORCE V/I DATA[3]
(ADDR[4:0] = 0x0E)
PMU INPUT SELECTION DATA[9:8]
(ADDR[4:0] = 0x0E)
PMU CLAMP ENABLE DATA[5]
(ADDR[4:0] = 0x0E)
PMU SENSE P
A
TH D
A
T
A
[7]
(ADDR[4:0] = 0x0E)
EXTERNAL DUT
SENSE PIN
PMU MEASURE V/I DATA[4]
(ADDR[4:0] = 0x0E)
CH[1] PMU V/I
MUX
MUX MUX
MUX
MUX
VCH
VCL
MEASURE V
(AT OUTPUT OF
SENSE MUX)
NOTES
1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL
SWITCHES OPEN AND PMU POWERS DOWN.
2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.
3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER.
4. 32mA BUFFER TRISTATES WHEN NOT IN USE.
330pF
SCAPx
(EXTERNAL)
32mA
32mA BUFFER
TEMP SENSE
GND REF
MEASURE V
MEASURE I
TEMP SENSE
VIN
2.5V + DUTGND
DUTGND
MEASURE
OUT
MEASOUT01 OUTPUT
ENABLE DATA[0]
(ADDR[4:0] = 0x0F)
ONE PER DEVICE
07280-019
Figure 83. PMU Block Diagram
ADATE305
Rev. 0 | Page 52 of 56
PMU
V/I CLAMP
FLAG
–2.5V
OVD LOW LEVEL
DAC (ADDR[4:0] = 0x0A, CH[0])
(ADDR[4:0] = 0x12) DATA[1]
PMU MASK ENABLES PMU V/I
FLAG TO ALARM OVD_CHx PIN
ADATE305
(ADDR[4:0] = 0x12) DATA[0]
OVD MASK ENABLES OVD
FLAGS TO ALARM OVD_CHx PIN
OVD_CHx
SHORT-CIRCUIT
CURRENT = 100µA
(ADDR[4:0] = 0x13)
2
DATA[2] DATA[1] DATA[0]
1
THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE
LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED
HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)
2
THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
6.5V
OVD HIGH LEVEL
DAC (ADDR[4:0] = 0x0A, CH[1])
DUT
1
1
07280-020
Figure 84. OVD Block Diagram
ADATE305
Rev. 0 | Page 53 of 56
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HU
072408-A
1
25
26 50
76
100
75
51
14.00 BSC SQ
16.00 BSC SQ
0.75
0.60
0.45
1.20
MAX
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05 VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
0.27
0.22
0.17
0.50 BSC
LEAD PITCH
8.00
BSC SQ
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 85. 100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP]
(SV-100-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADATE305BSVZ1−40°C to +85°C 100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP] SV-100-7
1 Z = RoHS Compliant Part.
ADATE305
Rev. 0 | Page 54 of 56
NOTES
ADATE305
Rev. 0 | Page 55 of 56
NOTES
ADATE305
Rev. 0 | Page 56 of 56
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07280-0-8/08(0)
