TB62D612FTG
2018-06-27
1
TOSHIBA BiCD Process Integrated Circuit Silicon Monolithic
TB62D612FTG
24-Channel Constant-Current LED Driver of the 3.3-V or 5-V Power Supply Voltage
Operation
The TB62D612FTG is a constant-current driver designed for LED and
LED display lighting.
This product incorporates 7-bit PWM dimming controllers and 24
channels of constant-current drivers. 24 channels constant-current
drivers are divided into three blocks, and each block can be
independently adjusted by the relevant external resistor.
This product is controlled using the SDA and SCLK input signals, and
capable of high-speed data transfers.
This product can be set address with ID setting pins. (Up to 64
addresses can be controlled independently.)
High-speed processing is capable by applying BiCD process.
This product operates with a supply voltage of 3.3 V or 5 V.
1. Features
• Power supply voltages: Vcc = 3.3 V/5 V
• Maximum output current capability: 80 mA (max) × 24 channels
• Constant-current output range: 5 to 40 mA
• Output voltage at constant-current drive: 0.4 V (min, IOUT = 5 to 40 mA)
• Designed for common-anode LEDs
• The input interface is controlled by the SDA and SCLK signal lines
• Thermal shutdown (TSD)
• Logical Input and output: 3.3-V or 5-V CMOS interfaces (Schmitt trigger input)
• Maximum output voltage: 28 V
• Incorporating PWM control circuitry: Provides 7-bit PWM control.
• Driver identification: Up to 64 driver ICs can be controlled individually.
• Operating temperature range: Topr = -40 to 85°C
• Package: P-WQFN36-0606-0.50-001
• Constant-current accuracy
P-WQFN36-0606-0.50-001
Weight: 0.083 g ( typ.)
Condition
Constant-current accuracy
between channels
Constant-current accuracy
between ICs
Output voltage : 0.4 V
Output current : 15 mA ± 3.0% ± 6.0%
© 2014-2018
Toshiba Electronic Devices & Storage Corporation
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2. Pin A ssignment (top view)
3. Block Diagram
8754321
14
13
12
11
18
17
15
16
2324252627
28
29
30
9
10
19
20
33
34
35
36
32
31
2122
6
/OUTB2
/OUTR3
/OUTB3
/OUTG3
PGND
/OUTR4
/OUTG4
/OUTB4
/OUTR5
/OUTG5
/OUTB5
/OUTR6
/OUTB6
/OUTG7
/OUTB7
Rext-R
/OUTG6
ID0
ID1
Rext-B
Vcc
SDA
ID2
SCLK
RESET
/OUTR0
/OUTB0
/OUTR1
/OUTG1
/OUTB1
/OUTR2
/OUTG2
/OUTG0
GND
TOP VIEW
/OUTR7
Rext-G
Address
setting
ID0 ID1 ID2
Vcc
SDA
SCLK
RESET
Logic
processing
Data
buffer
GND
CLK
generation
TSD
PWM (7-bit)
PWM (7-bit)
PWM (7-bit)
PWM (7-bit)
PWM (7-bit)
PWM (7-bit)
Constant-
current driver
Constant-
current driver
Constant-
current driver
Constant-
current driver
Constant-
current driver
Constant-
current driver
/OUTR0
/OUTR7
/OUTG0
/OUTG7
/OUTB0
/OUTB7
Rext-R
Rext-B
Rext-G
PGND
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4. Terminal Description
Pin No Symbol Function
1 /OUTB2 Constant-current output pin (Open-drain type)
2 /OUTR3 Constant-current output pin (Open-drain type)
3 /OUTG3 Constant-current output pin (Open-drain type)
4 /OUTB3 Constant-current output pin (Open-drain type)
5 PGND Power Ground pin
6 /OUTR4 Constant-current output pin (Open-drain type)
7 /OUTG4 Constant-current output pin (Open-drain type)
8 /OUTB4 Constant-current output pin (Open-drain type)
9 /OUTR5 Constant-current output pin (Open-drain type)
10 /OUTG5 Constant-current output pin (Open-drain type)
11 /OUTB5 Constant-current output pin (Open-drain type)
12 /OUTR6 Constant-current output pin (Open-drain type)
13 /OUTG6 Constant-current output pin (Open-drain type)
14 /OUTB6 Constant-current output pin (Open-drain type)
15 /OUTR7 Constant-current output pin (Open-drain type)
16 /OUTG7 Constant-current output pin (Open-drain type)
17 /OUTB7 Constant-current output pin (Open-drain type)
18 Rext-R External resistor connection pin for output current configuration (/OUTR0 to /OUTR7)
19 Rext-G External resistor connection pin for output current configuration (/OUTG0 to /OUTG7)
20 Rext-B External resistor connection pin for output current configuration (/OUTB0 to /OUTB7)
21 GND Ground pin
22 ID0 ID configuration pin (Note 1)
23 ID1 ID configuration pin (Note 1)
24 ID2 ID configuration pin (Note 1)
25 Vcc Supply voltage pin
26 SDA Serial data input pin
27 SCLK Serial clock input pin
28 RESET Reset signal input. (Setting this pin High resets internal data.) (Note 1)
29 /OUTR0 Constant-current output pin (Open-drain type)
30 /OUTG0 Constant-current output pin (Open-drain type)
31 /OUTB0 Constant-current output pin (Open-drain type)
32 /OUTR1 Constant-current output pin (Open-drain type)
33 /OUTG1 Constant-current output pin (Open-drain type)
34 /OUTB1 Constant-current output pin (Open-drain type)
35 /OUTR2 Constant-current output pin (Open-drain type)
36 /OUTG2 Constant-current output pin (Open-drain type)
Note 1: After the reset is released, it should be ensured that IDs (slave addresses) are properly configured.
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5. Equivalent Circuits for Inputs and Outputs
SDA and SCLK Terminals
RESET Terminals
Constant-Current Output Terminals
ID0, ID1 , and ID2 Terminals
Vcc
GND
Vcc
GND
RESET
SDA
SCLK
/OUTR0 to /OUTR7
/
OUTG0 to /OUTG7
/
OUTB0 to /OUTB7
PGND
Vcc
GND
Comparison
ID0
ID1
ID2
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6. Programming the TB62D612FTG
The TB62D612FTG can be programmed by the SDA and SCLK signals.
The TB62D612FTG should be programmed using one of the following formats: (1) Serial Packet Format in Normal
Programming Mode or (3) Serial Packet Format in Special Mode.
(1) Serial Packet Format in Normal programming Mode
<Typical>
Start Command
[11111111]
Slave address
8 bits
Sub-address
(Channel select)
8 bits
Data byte
(PWM configuration)
8 bits
Period Command
[10000001]
･Normal programming Mode should be set as the following flow.
“Start Command” “Slave address” “Sub-address” “Data byte” “Period Command”
As for example of data input, refer to Page8.
･Input data from SDA signal is written to the shift register at the rising edge of SCLK every 8 bit.
This data is transferred at the falling edge of the eighth CLK. So, at the eighth CLK, data should be input to the falling
edge.
Block diagram of data setting part
In case of period command
SDA
SCLK
D
ata are transferred
at
the falling edge of the
eighth
SCLK.
Data are written to the shift register at
the rising edge of the SCLK.
Data are transferred at
the falling edge of the
eighth
SCLK.
8bit shift-resister
Slave Address
Sub Address
Data
Byte
B6
Terminal command
Data
Byte
R7
Data
Byte
R0
Data
Byte
G0
Data
Byte
B0
Data
Byte
R1
Data
Byte
G7
Data
Byte
B7
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
OUT
R0
OUT
G0
OUT
B0
OUT
R1
OUT
B6
OUT
R7
OUT
G7
OUT
B7
8bit
8bit
8bit
8bit
8bit
8bit
8bit
8bit
SDA
SCLK
8bit
Counter
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(2) Data Settings
a) Slave Addresses
Input voltages and logic states of the ID0, ID1 and ID2 pins are determined as follows.
(MSB = 0. LSB = 0 (Except of all selection))
Vcc =”11”, 2/3Vcc =”10”, 1/3Vcc = "01”, GND =”00”
Slave Addresses
ID2
ID1
ID0
00000000
GND
GND
GND
00000010
GND
GND
1/3Vcc
00000100
GND
GND
2/3Vcc
00000110
GND
GND
Vcc
00001000
GND
1/3Vcc
GND
00001010
GND
1/3Vcc
1/3Vcc
00001100
GND
1/3Vcc
2/3Vcc
00001110
GND
1/3Vcc
Vcc
00010000
GND
2/3Vcc
GND
00010010
GND
2/3Vcc
1/3Vcc
00010100
GND
2/3Vcc
2/3Vcc
00010110
GND
2/3Vcc
Vcc
00011000
GND
Vcc
GND
00011010
GND
Vcc
1/3Vcc
00011100
GND
Vcc
2/3Vcc
00011110
GND
Vcc
Vcc
00100000
1/3Vcc
GND
GND
00100010
1/3Vcc
GND
1/3Vcc
00100100
1/3Vcc
GND
2/3Vcc
00100110
1/3Vcc
GND
Vcc
00101000
1/3Vcc
1/3Vcc
GND
00101010
1/3Vcc
1/3Vcc
1/3Vcc
00101100
1/3Vcc
1/3Vcc
2/3Vcc
00101110
1/3Vcc
1/3Vcc
Vcc
00110000
1/3Vcc
2/3Vcc
GND
00110010
1/3Vcc
2/3Vcc
1/3Vcc
00110100
1/3Vcc
2/3Vcc
2/3Vcc
00110110
1/3Vcc
2/3Vcc
Vcc
00111000
1/3Vcc
Vcc
GND
00111010
1/3Vcc
Vcc
1/3Vcc
00111100
1/3Vcc
Vcc
2/3Vcc
00111110
1/3Vcc
Vcc
Vcc
01000000
2/3Vcc
GND
GND
01000010
2/3Vcc
GND
1/3Vcc
01000100
2/3Vcc
GND
2/3Vcc
01000110
2/3Vcc
GND
Vcc
01001000
2/3Vcc
1/3Vcc
GND
01001010
2/3Vcc
1/3Vcc
1/3Vcc
01001100
2/3Vcc
1/3Vcc
2/3Vcc
01001110
2/3Vcc
1/3Vcc
Vcc
01010000
2/3Vcc
2/3Vcc
GND
01010010
2/3Vcc
2/3Vcc
1/3Vcc
01010100
2/3Vcc
2/3Vcc
2/3Vcc
01010110
2/3Vcc
2/3Vcc
Vcc
01011000
2/3Vcc
Vcc
GND
01011010
2/3Vcc
Vcc
1/3Vcc
01011100
2/3Vcc
Vcc
2/3Vcc
01011110
2/3Vcc
Vcc
Vcc
01100000
Vcc
GND
GND
01100010
Vcc
GND
1/3Vcc
01100100
Vcc
GND
2/3Vcc
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01100110
Vcc
GND
Vcc
01101000
Vcc
1/3Vcc
GND
01101010
Vcc
1/3Vcc
1/3Vcc
01101100
Vcc
1/3Vcc
2/3Vcc
01101110
Vcc
1/3Vcc
Vcc
01110000
Vcc
2/3Vcc
GND
01110010
Vcc
2/3Vcc
1/3Vcc
01110100
Vcc
2/3Vcc
2/3Vcc
01110110
Vcc
2/3Vcc
Vcc
01111000
Vcc
Vcc
GND
01111010
Vcc
Vcc
1/3Vcc
01111100
Vcc
Vcc
2/3Vcc
01111110
Vcc
Vcc
Vcc
0XXXXXX1
All Select
b) Sub-Addresses
Output channel setting, All channels setting or Special mode setting can be set.
In output channel set, a channel which defines PWM configuration is selected. In all channels set, PWM is configured
for all channels. For special mode, refer to page 8.
7bit
6bit
5bit
4bit
3bit
2bit
1bit
0bit
Channel set
0
0
0
0
0
0
1
0
/OUTR0
0
0
0
0
0
1
0
0
/OUTG0
0
0
0
0
0
1
1
0
/OUTB0
0
0
0
0
1
0
0
0
/OUTR1
0
0
0
0
1
0
1
0
/OUTG1
0
0
0
0
1
1
0
0
/OUTB1
0
0
0
0
1
1
1
0
/OUTR2
0
0
0
1
0
0
0
0
/OUTG2
0
0
0
1
0
0
1
0
/OUTB2
0
0
0
1
0
1
0
0
/OUTR3
0
0
0
1
0
1
1
0
/OUTG3
0
0
0
1
1
0
0
0
/OUTB3
0
0
0
1
1
0
1
0
/OUTR4
0
0
0
1
1
1
0
0
/OUTG4
0
0
0
1
1
1
1
0
/OUTB4
0
0
1
0
0
0
0
0
/OUTR5
0
0
1
0
0
0
1
0
/OUTG5
0
0
1
0
0
1
0
0
/OUTB5
0
0
1
0
0
1
1
0
/OUTR6
0
0
1
0
1
0
0
0
/OUTG6
0
0
1
0
1
0
1
0
/OUTB6
0
0
1
0
1
1
0
0
/OUTR7
0
0
1
0
1
1
1
0
/OUTG7
0
0
1
1
0
0
0
0
/OUTB7
0
1
0
0
0
0
0
0
All channels select
0
1
1
0
0
0
0
0
Special mode
(MSB and LSB must be set 0.)
c) Data Bytes (PWM configuration)
Data bytes set PWM diming. (LSB must be set 0.)
7bit
6bit
5bit
4bit
3bit
2bit
1bit
0bit
PWM Dimming (for reference only)
0
0
0
0
0
0
0
0
OFF (Default)
0
0
0
0
0
0
1
0
1/127
0
0
0
0
0
1
0
0
2/127
･･･
1
1
1
1
1
1
0
0
126/127
1
1
1
1
1
1
1
0
127/127
Note: Any data other than those specified above must not be programmed.
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(3) Serial Packet Format in Special Mode
When data of 01100000 is input to the sub address, the operation moves to the special mode where all channels are
selected in order. Data of 24 channels should be input.
(If data of more than 24 channels are provided, the 25th and subsequent data are treated as invalid. If data of less than
24 channels are provided, those data are written to the channels in order and the remaining channels retain the previous
data.)
To return to the normal mode, input data from the start command (ALL”H”8bit). In case of using this mode configuration,
volume of data can be omitted.
(4) Input example of data set
a) In case PWM 127 /127(100% ON) are configured to all channels of slave address 00h.
b) In case PWM 127 /127 (100% ON) are configured to only /OUTR0 pin and /OUTB7 pin of slave address 02h.
As for other than /OUTR0 and /OUTB7 terminals in above configuration, output pins which have already output data
continue to output prior data. (In case of changing only outputting data which is required to be changed, this configuration
is valid.)
(11111111)
(00000010)
Sub-address
(R0)
(00000010)
Data bytes
(11111110)
Sub-address
(B7)
(00110000)
Data bytes
(11111110)
Period
Command
(10000001)
Start
command
(00000000)
Sub address(R0)
(00000010)
(11111110)
(00000100)
(11111110)
(00000110)
Start command
Slave address
(11111111)
(11111110)
(00001010)
(11111110)
(00001100)
(11111110)
Data bytes
(00001000)
Sub a ddress(R1)
Data bytes
Sub a ddress(G 1)
Data bytes
Sub a ddress(B1)
(11111110)
Data bytes
(11111110)
Data bytes
Sub address(B0)
Data bytes
Sub address(G0)
Data bytes
(00101100)
Sub a ddress(R7)
(11111110)
Data bytes
(00101110)
Sub address(G7)
Data bytes
(11111110)
(00110000)
Sub address(B7)
(10000001)
Period command
Start
Command
[11111111]
Slave
address
(Special mode set)
[01100000]
OUTR7
Data
OUTR0
OUTG0
OUTB0
OUTR1
OUTB6
Period
Command
[10000001]
OUTG7
OUTB7
Data
Data
Data
Data
Data
Data
Data
Sub-address
Slave
Addresses
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(5) Data settings and Timing of outputs
Note: Data is transferred by synchronizing period command (10000001) with the internal PWM counter (MAX). So, if data is input after the period command is input and before
the internal PWM counter counts its maximum, data which is input after period input is not accepted. In order to set data to the same ID (IC), next data should be input
after 3 ms which corresponds to 128 internal PWM clocks are passed since the period command is input. However, in order to set data to the different ID, terminal of 3 ms
which corresponds to 128 internal PWM clocks should not be taken. Data is written to the shift register at the rising edge of SCLK every 8 bits, and is transferred at the
falling edge of 8th CLK. So, data should be input to the falling edge at the 8th CLK.
0
1
2
3
124
125
126
127
0
1
2
3
124
125
126
127
0
1
2
3
124
125
126
127
0
1
2
3
124
125
126
127
0
1
2
3
124
125
126
127
0
1
Previous data (PW M) output
Previous data (PWM) output
Previous data (PWM) output
Received data (0/127)
Repeat until setting
Received data (1/127)
Received data (127/127)
Hold until setting
ID s e tti n g
8 bi ts ALL " H"
Start c ommand
Slave address 0
Sub addr ess 0 (/ OUT R 0)
Data byte 0 (0/127)
Sub addr ess 1 (/ OUT G0)
Data byte 1 (1/127)
ch setting & Special mode setting
PWM setting
ch setting & Special mode s ett ing
PWM setting
ch setting & Special mode s ett ing
Lsetting
L s etting
L s etting
L
s ettin g
L
s ettin g
PWM setting
Previous data
Previous data
Previous data
PWM co unter
starts
PWM co unter
MAX
1 cycle of in ter n a l PWM cl ock
(asynchronous with external SCLK signal)
14 µs
SCLK
SDA
SCLK
SDA
Typical
setti ng
Operation timing
example
Data byte 0
Data byte 1
Data byte 23
Start replacing data
(PWM counter reaches max value (127)
＆
period command)
Outp ut (new data) starts.
/OUTR0
/OUTG0
/OUTB7
Previous data
Previous data
Previous data
SCLK
SDA
SCLK
SDA
Data byte 0
Data byte 1
Data byte 23
/OUTR0
/OUTG0
/OUTB7
Previous data (PWM) output
Previous data (PWM) output
Previous data (PWM) output
Start command
Data byte 1
Slave address
Sub addr ess 0
Data byte 0
Sub addr ess 1
8 bi ts ALL " H"
Sub addr ess 8
Data byte 8
Sub addr ess 8 (/ OUT B 7)
Per iod com mand
Per iod com mand
Data byte 8 (127/127)
L
L
L
L
L
L
L s etting
L s etting
L s etting
Lsetting
L
L
L
L
Counter max.
Prior data
Data transfer
Period
command
No
Ye s
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(6) Example of data input to the same ID
a) In case data A is input up to the rising edge of 127th internal PWM clock.
Outputting data A starts at the rising edge of 0th internal PWM clock.
Inputting is invalid from the rising edge of 127th internal PWM clock to the rising edge of 0th internal PWM clock
which is just after this 127th PWM clock.
b) In case data A is input after the rising edge of 127th internal PWM clock.
Outputting data A does not start at the rising edge of 0th internal PWM clock just after the data A is input. It starts at
the next rising edge of 0th internal PWM clock.
Inputting is invalid from the period command of data A input to the rising edge of after the next 0th internal PWM
clock.
c) In case data B is input after data of pattern 1 starts outputting.
Outputting data A starts at the rising edge of 0th internal PWM clock just after the data A is input. Outputting data B
starts at the rising edge of 0th internal PWM clock which is just after the data B input.
Inputting is invalid in the following term.
From the rising edge of 127th internal PWM clock which is just after the data A is input to the rising edge of 0th
internal PWM clocks which is just after this 127th clock.
From the rising edge of 127th internal PWM clock which is just after the data B input to the rising edge of 0th internal
PWM clock which is just after this 127th clock.
Pay attention that the IC does not operate according to the configuration while the following patterns (patterns 4 and
5) are input.
d) In case data B is input by the time the output of pattern 2 starts.
Inputting is invalid from the period command of data A input to the rising edge of the second internal clock. So, data
B is invalid and data A is output.
Transferring data A
Start output
0
0
0
0
Transferring data A
Start output
Transferring data B
Start output
Transferring data A
Start output
Internal PWM clock
Pattern 1
Internal PWM clock
Pattern 4
127
127
Start
Data A output
Data A
Period
Input invalid term
0
0
Transferring data A
Start output
Internal PWM clock
Pattern 2
127
127
Start
Data A
Period
Input invalid term
Data A output
127
127
Start
Data A
Period
Input invalid term
Data A output
Start
Data B
Period
0
0
Internal PWM clock
Pattern 3
Data A output
Start
Data A
Period
127
127
Data B output
Start
Data B
Period
Input invalid term
Input invalid term
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11
e) In case the period command mistakes.
Outputting data A does not start at the rising edge of 0th internal clock which is just after the data A input. Outputting
data B starts at the rising edge of 0th internal PWM clock which is just after the data B input.
f) In case of matching asynchronously the timing between data pattern end and internal data update
In case of matching asynchronously the timing between SCLK end and internal data update, the start command at
the beginning of next pattern may not be received. That may occur in the pattern of first IC if there are patterns for
two or more ICs. That does not occur if the pattern length is as follows.
1. Less than minimum 10.6 μs after inputting period command
2. Exceeding maximum 3 ms from point of 1.
This time management is difficult. We recommend that the following measures are applied from initial state to avoid
the occurrence of the event.
Dummy data are added to the beginning of the data pattern, and 1 time or more SCLKs should be added.
The following figure shows the dummy data = L. However, the dummy data =H is also possible.
START DATA “A”
SDA
Internal PWM
clock
DATA “A” transfer
0
125 126 127 0
125 126 127
1 cycle of internal PWM counter =
3 ms (Max)
START DATA ”A”
Internal PWM
clock
0
126 127 0
126 127
PERIOD
Receiving
initialization
Ready for
transfer
Receiving
initialization
Ready
for
transfer
START DATA ”B”
*1 DATA”A” is reflected to LED output and waiting for
receiving.
START DATA ”B”
636261
646362
11
SCLK
DATA “A” transfer *1
SDA
SCLK
DATA transfer and receiving
initialization after inputting period
command is created at random in
1 cycle of internal PWM counter.
PERIOD
Waiting for receiving
Internal PWM
clock
DATA “A”
transfer
0
125 126 127 0
125 126 127
1 cycle of internal PWM counter =
3 ms (Max)
Receiving
initialization
Ready for
transfer
63
6261
SCLK
DATA “B”
START
SDA
Dum
my
Dummy
SCLK
SDA START
8 times 8 times
DATA ”A”
0
0
Transferring data B
Start output
Internal PWM clock
Pattern 5
Data B output
Start
Data B
Period
Start
Data A
127
127
Input invalid term
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(7) Example of data input to the different ID.
a) In case the data B is input to slave (= 02h) just after the data A is input to slave (= 00h).
Both data A and data B are output at the rising edge of 0th internal PWM clock which is just after the data A and the
data B inputs.
Pay attention that the IC does not operate according to the configuration while following patterns (patterns 7 and 8)
are input.
b) In case period command after inputting data A to the slave (=00h) is missed or omitted or in case period command
after inputting data B to the slave (=02h) is missed or omitted.
Data A is output. Data B is not output.
c) In case start command is input after data B of pattern 7 is input.
Data A is output. Data B is not output.
0
Transferring data A and data B.
Start output
Transferring data A
Start output
Internal PWM clock
Pattern 8
Internal PWM clock
Pattern 6
127
Slave=00h, Data A
Slave=00h output
Start
Period
Start
Slave=02h, Data B
Period
Data A output
Data B output
Slave=02h output
0
Transferring data A
Start output
Internal PWM clock
Pattern 7
Slave=00h, Data A
Start
Start
Slave=02h, Data B
127
Data A output
Slave=00h output
Slave=02h output
Slave=00h, Data A
Start
Start
Slave=02h, Data B
Start
127
0
Data A output
Slave=00h output
Slave=02h output
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7. Power-ON Reset (P OR)
The POR circuitry resets all the internal data to the default values upon powering up the TB62D612FTG in order to
ensure proper device operation.
The POR circuitry is only activated when Vcc rises from 0 V. To reactivate POR, Vcc must be powered down to 0 V.
The internal data hold voltage is guaranteed after Vcc has once reached or exceeded 3.0 V.
8. Thermal Shutdown (TSD)
When the IC internal temperature reaches 150°C, the thermal shutdown circuit operates and all constant current
outputs are turned off. When the temperature falls, the constant current outputs restart.
TSD operating temperature: 150°C to 180°C
TSD release temperature: 30°C below TSD operating temperature
*Please avoid positively using TSD because TSD is a detecting function of the product.
Initial Clear
Vcc Waveform
POR Active
POR Not Active
POR Active
2.0 V
1.8 V
0 V
POR Completed
Reset Completion Voltage
Minimum Data Hold Voltage
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9. Points to Note when Setting Up the TB62D612FTG
1. External resistors for specifying the LED driving current (Rext-R, Rext-G, Re xt-B)
External resistors should be separately connected to the Rext-R, Rext-G and Rext-B pins. Three resistors must
not be collected as one resister. If they are collected, current error is generated in each RGB.
2. External resistors for ID configuration
The total resistance value of three external resistors used for specifying a device ID (which are connected between
Vcc and GND) should be about 30 kΩ or lower.
3. ID configuration sequence
ID configuration can be performed after POR is released upon powering on. However, to avoid false operation of
the ID configuration, transient input signals of less than two clock cycles of the reference clock for the internal
oscillator are not accepted.
4. ID configuration
Make sure to set IDs after releasing reset condition.
5. Data configuration
Do not input the data which is not on the list of the data configuration table in page 6 and 7.
Data is written to the shift resister at the rising edge of SCLK every 8 bits. And data is transferred at the falling
edge of the eighth clock. So, input data to the falling edge at the eighth clock.
6. Special mode
Data which corresponds to 24 channels should be input. If data of more than 24 channels are provided, the 25th
and subsequent data are treated as invalid. If data of less than 24 channels are provided, those data are written to
the channels in order and the remaining channels retain the previous data.
7. Timing of data configuration
In order to set data to the same slave address, next data should be input after 3 ms which corresponds to 127
internal PWM clocks is passed since the period command is input. However, in order to set data to the different
slave address, terminal of 3 ms which corresponds to 127 internal PWM clocks should not be taken.
Vcc
1.8V
ID Configuratio
n Allowed
ID Configuration Not Allowed
ID Configuration
Not Allowed
2V
Care should be taken during the period between the POR released timing and
the timing when power supply has reached the rated Vcc voltage.
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10. State Transition Diagram
Power-ON
Vcc reaches the POR release threshold voltage.
ID recognition
RESET=”L” RESET=”H”
After the TB62D612FTG is powered on, data can
be programmed after 15 ms has elapsed at least.
When the die temperature exceeds the
TSD
trip threshold temperature, all the
output s are disabl e d, while i nternal
data is retained.
RESET=”L”
Compares IDs again
TSD detection
temperature or
more
TSD detection
temperature or
less
Output data is programmed for each ID
device using the
SDA and SCLK
signals for providing dimming control
Please refer the description from page
5 to 1
2 in details.
Reset Mode
Internal data
(ID/PWM data) are reset.
RESET
= ”H”:
Data is reset forcedly.
Output is turned off.
Operation moves to low consumption
mode.
TSD Mode
(Thermal Shutdown
)
RESET=”H”
Normal Mode
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11. Absolute Maxi m um Ratings (Ta = 25°C)
Characteristics Symbol Rating Unit
Supply voltage Vcc 6.0 V
Input voltage VIN -0.3 to Vcc + 0.3 (Note 1) V
Output current (/ch) IOUT 85 mA
Output voltage VOUT -0.3 to 29 V
Power dissipation Pd 4.3 (Notes 2 and 3) W
Thermal resistance Rth (j-a) 29 (Note 2) °C / W
Operating temperature range Topr -40 to 85 °C
Storage temperature range Tstg -55 to 150 °C
Maximum junction temperature Tj 150 °C
Note 1: However, do not exceed 6.0 V.
Note 2: When mounted on a PCB (76.2 × 114.3 × 1.6 mm; Cu = 30%; 35-μm-thick; SEMI-compliant, 4 layer)
Note 3: Power dissipation is reduced by 1/Rth (j-a) for each °C above 25°C ambient.
12. Operating Ranges (Ta = -40°C to 8 5°C, unless otherwise specified)
Characteristics Symbol Test condition Min Typ. Max Unit
Supply voltage Vcc - 3 - 5.5 V
Output voltage VOUT (ON) All Output 0.4 - 4 V
Output current (/ch) IOUT All Output 5 - 40 mA
Input voltage
VIH
SDA, SCLK, RESET
0.7 ×
Vcc - Vcc
V
VIL GND - 0.3 ×
Vcc
VID0
ID0, ID1, ID2
0 - 0.3
VID1 1/3Vcc
-0.3
1/3
Vcc
1/3Vcc
+0.3
VID2 2/3Vcc
-0.3
2/3
Vcc
2/3Vcc
+0.3
VID3 Vcc
-0.3 - Vcc
SCLK clock frequency fCLK SCLK (Note. 4) - - 10 MHz
Data setup time tSU;DAT SDA-SCLK (Note. 4) 10 - -
ns
Data hold time tHD;DAT SCLK-SDA (Note. 4) 10 - -
“L” term of SCLK clock tLOW SCLK (Note. 4) 50 - -
“H” term of SCLK clock tHIGH SCLK (Note. 4) 50 - -
Note. 4: Please refer to following timing chart.
tHD;DAT
tHIGH
50%
50%
50%
50%
tSU;DAT
SDA
SCLK
50%
tLOW
1/fCLK
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13. Electrical Characteristics (Ta = 25°C, Vcc = 4.5 to 5.5 V, unless otherwise
specified)
Characteristics Symbol Test
Circuit Test Condition Min Typ. Max Unit
Output current IOUT1 4 VOUT = 0.4 V, REXT = 1.2kΩ
Vcc = 5 V, 12.69 13.5 14.31 mA
Output current accuracy between
channels ∆IOUT2 4 VOUT = 0.4 V, REXT =1.2kΩ
All ch ON, Vcc = 5 V - - ±3.0 %
Output leakage current IOZ 4 VOUT = 28 V - - 1 μA
Input current
IIH 1
SDA, SCLK - - 1
μA
RESET (Vcc=5 V) 25 50 75
IIL 2 SDA, SCLK, RESET - - -1
IID 1,2 ID0, ID1, ID2 - - ±0.1
Changes in constant output current
dependent on VCC %/Vcc 4 Vcc = 4.5 V to 5.5 V - 1 2 %
Supply current at operating
Icc 1 3 REXT=1.2 kΩ, VOUT =0.4 V,
RESET=L - 9 14
mA
Icc 2 3 REXT = OPEN, VOUT = 28.0 V - 3 5
Current consumption in Reset mode Icc (PS) 3
REXT = 1.2 kΩ, VOUT = 0.4 V,
RESET = H (The input current of the
RESET pin is excluded.)
- - 1 μA
Time required for a mode transition
from Reset mode to Normal mode
tON2
(Note1) -
Time between a High to Low
transition on RESET and the timing
when an output current is generated
after input data is applied.
- - 3 ms
Note1: Internal data is reset forcedly by RESET pin. In order to turn on the output current, data should be input again.
Pay attention that the output current flows after PWM counter counts its maximum (128 internal PWM clocks)
though data are input again. RESET recovery time: 3 ms (MAX) ← In case the voltage is input until the PWM
counter counts one cycle after RESET release. (After RESET release, PWM counter starts from zero.)
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14. Test Circuits
Vcc
Test Circuit 1: High-Level Input Current (IIH)
REXT
VIN = VDD
A
A
A
A
Vcc
Test Circuit 2: Low-Level Input Current (IIL)
A
A
A
A
Vcc = 4.5 to 5.5 V
GND
ID0,1,2
SDA
Rext-R
Test Circuit 3: Supply Current
F.G
V
IH = Vcc
V
IL = 0V
A
GND
Rext-R
Vcc = 4.5 to 5.5 V
/OUTR0
/OUTB7
RESET
SCLK
Rext-G
Rext-B
REXT
REXT
REXT
GND
Rext-R
Rext-G
Rext-B
REXT
R
EXT
ID0,1,2
SDA
RESET
SCLK
/OUTR0
/OUTB7
/OUTR0
/OUTB7
Rext-G
SDA
RESET
SCLK
Rext-B
Vcc
Vcc = 4.5 to 5.5 V
ID set
ID1
ID0
ID2
V
ID0 =0.3V
V
ID1 =1/3Vcc±0.3V
V
ID2 =2/3Vcc±0.3V
V
ID3 =Vcc-0.3V
R
EXT
=1.2kΩ
REXT
=1.2kΩ
R
EXT
=1.2kΩ
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Vcc
F.G
A
A
A
V
IH
= Vcc
V
IL = 0 V
VOUT = 0.4 V, 28 V
Vcc = 4.5 to 5.5 V
SDA
RESET
SCLK
/OUTR0
/OUTB7
/OUTG1
GND
Rext-R
Rext-G
Rext-B
Test Circuit 5: Switching Characteristics
CL
IOUT
Vcc
F.G
V
IH
= Vcc
V
IL = 0 V
VL = 5 V
CL
=
10.5 pF
RL=300
Ω
Vcc = 4.5 to 5.5 V
SDA
RESET
SCLK
GND
Rext-R
Rext-G
Rext-B
/OUTR0
/OUTB7
ID set
ID1
ID0
ID2
V
ID0 =0.3V
V
ID1 =1/3Vcc±0.3V
V
ID2 =2/3Vcc±0.3V
V
ID3 =Vcc-0.3V
ID Set
ID1
ID0
ID2
V
ID0 =0.3V
V
ID1 =1/3Vcc±0.3V
V
ID2 =2/3Vcc±0.3V
V
ID3 =Vcc-0.3V
Test Circuit 4: Output
Current, Output Leakage Current, Output current accuracy,
Changes in constant output current dependent on Vcc
R
EXT
=1.2kΩ
REXT
=1.2kΩ
R
EXT
=1.2kΩ
R
EXT
=1.2kΩ
REXT
=1.2kΩ
REXT
=1.2kΩ
TB62D612FTG
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15. Characteristics of Output Current vs. External resistor (For reference)
( Reference )
The TB62D612FTG IOUT calculation.
The typical relational expression of the output-current and external resistor is shown below.
It is doesn't include a current accuracy.
The output-current ( mA ) = 14.5 × 1.12 / REXT (kΩ)
Output current – REXT
External resistor
Outp ut cur r e nt [mA]
External resistor REXT[kΩ]
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16. Application Circuit Example
C.P.U.
VLED
SCLK
TB62D612FTG
TB62D612FTG
GND
SDA
SDA
SCLK
SDA
SCLK
/OUTR0
/OUTB7
00
01
10
/OUTR0
/OUTB7
ID0
ID1
ID2
ID2
11
ID1
ID0
ID=“00000000”
ID=“00100000”
Rext-R
Rext-G
Rext-B
GND
Rext-R
Rext-G
Rext-B
Vcc
Vcc
VCC
TB62D612FTG
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Package Dimensions
P-WQFN36-0606-0.50-001
Weight: 0.083 g (typ.)
Unit: mm
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Examples
The application examples provided in this data sheet are provided for reference only. Thorough evaluation and
testing should be implemented when designing your application’s mass production design.
In providing these application examples, Toshiba does not grant the use of any industrial property rights.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause breakdown, damage or deterioration of the device, and may result
in injury by explosion or combustion.
(2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in the
event of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly, or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow. Such a
breakdown can lead to smoke or ignition. To minimize effects of a large current flow in the event of
breakdown, fuse capacity, fusing time, insertion circuit location, and other such suitable settings are
required.
(3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current caused by inrush current at
power ON or the negative current caused by the back electromotive force at power OFF. IC
breakdown may cause injury, smoke or ignition.
For ICs with built-in protection functions, use a stable power supply. An unstable power supply may
cause the protection function to not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4) Do not insert devices incorrectly or in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause breakdown, damage or deterioration of the device, which may
result in injury by explosion or combustion.
In addition, do not use any device that has had current applied to it while inserted incorrectly or in
the wrong orientation even once.
TB62D612FTG
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24
(5) Carefully select power amp, regulator, or other external components (such as inputs and negative
feedback capacitors) and load components (such as speakers),.
If there is a large amount of leakage current such as input or negative feedback capacitors, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause
smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied
Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
(1) Heat Dissipation Design
In using an IC with large current flow such as a power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at
any time or under any condition. These ICs generate heat even during normal use. An inadequate IC
heat dissipation design can lead to decrease in IC life, deterioration of IC characteristics or IC
breakdown. In addition, please design the device taking into consideration the effect of IC heat
dissipation on peripheral components.
(2) Back-EMF
When a motor rotates in the reverse direction, stops, or slows down abruptly, a current flows back to
the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power
supply is small, the device’s motor power supply and output pins might be exposed to conditions
beyond absolute maximum ratings. To avoid this problem, take the effect of back-EMF into
consideration in your system design.
(3) Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
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