LTC1257 Complete Single Supply 12-Bit Voltage Output DAC in SO-8 U FEATURES DESCRIPTIO 8-Pin SO Package Buffered Voltage Output Built-In 2.048V Reference 500V/LSB with 2.048V Full Scale 1/2LSB Max DNL Error Guaranteed 12-Bit Monotonic 3-Wire Cascadable Serial Interface Wide Single Supply Range: VCC = 4.75V to 15.75V Low Power: ICC Typ = 350A with 5V Supply U APPLICATIO S Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment The LTC (R)1257 is a complete single supply, 12-bit voltage output D/A converter (DAC) in an SO-8 package. The LTC1257 includes an output buffer amplifier, 2.048V voltage reference and an easy to use three-wire cascadable serial interface. An external reference can be used to override the internal reference and extend the output voltage range to 12V. The power supply current is a low 350A when operating from a 5V supply, making the LTC1257 ideal for battery-powered applications. The spacesaving 8-pin SO package and operation with no external components provide the smallest 12-bit D/A system available. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Daisy-Chained Control Outputs Differential Nonlinearity vs Input Code 5V 0.5 CONTROL OUTPUT 1 VCC VOUT LTC1257 GND VREF 0.1F CONTROL OUTPUT 2 VCC VOUT LTC1257 GND VREF DIN CLK P LOAD DNL ERROR (LSBs) 0.1F DOUT DIN 0.0 CLK LOAD DOUT -0.5 0 TO NEXT DAC 1257 TA01 512 1024 1536 2048 2560 3072 3584 4098 CODE 1257 TA05 1 LTC1257 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) VCC to GND ............................................ - 0.5V to 16.5V TTL Input Voltage .......................... - 0.5V to VCC + 0.5V VOUT .............................................. - 0.5V to VCC + 0.5V REF ................................................ - 0.5V to VCC + 0.5V Operating Temperature Range LTC1257C ............................................. 0C to 70C LTC1257I ........................................ - 40C to 85C Maximum Junction Temperature Plastic Package ............................. - 65C to 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C TOP VIEW CLK 1 8 VCC DIN 2 7 VOUT LOAD 3 6 REF DOUT 4 5 GND ORDER PART NUMBER LTC1257CN8 LTC1257IN8 N8 PACKAGE 8-LEAD PDIP TJMAX = 125C, JA = 100C/W TOP VIEW CLK 1 8 VCC DIN 2 7 VOUT LOAD 3 6 REF DOUT 4 5 GND LTC1257CS8 LTC1257IS8 S8 PART MARKING 1257 1257I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125C, JA = 150C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V VREF VCC - 2.7V), unless otherwise noted. SYMBOL DAC PARAMETER DNL INL Resolution Differential Nonlinearity Integral Nonlinearity OFF Offset Error OFFTC Offset Error Tempco Gain Error Gain Error Tempco CONDITIONS MIN Guaranteed Monotonic (Note 4) LTC1257C (Note 4) LTC1257I (Note 4) When Using Internal Reference, LTC1257C When Using Internal Reference, LTC1257I When Using External Reference, LTC1257C When Using External Reference, LTC1257I When Using Internal Reference (Note 2) When Using External Reference (Note 2) TYP MAX UNITS 0.02 15 0.5 0.01 0.5 3.5 4.0 8 10 4 5 0.066 30 2 0.02 Bits LSB LSB LSB LSB LSB mV mV LSB/C V/C LSB LSB/C 12 (Note 2) IREF = 0, LTC1257C IREF = 0, LTC1257I IREF = 0 IREF = 0, LTC1257C IREF = 0, LTC1257I 0 IREF 100A VCC > VREF + 2.7V Reference Reference Output Voltage Reference Output Tempco Reference Line Regulation Reference Load Regulation Reference Input Range Reference Input Resistance Reference Input Capacitance Short-Circuit Current 2 2.048 2.068 2.078 0.06 (Note 2) VREF Shorted to GND 2.028 2.018 2.475 8 14 15 0.4 0.7 1 12 18 90 V V LSB/C LSB/ V LSB/V LSB V k pF mA LTC1257 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V VREF VCC - 2.7V), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 15.75 V 600 1500 A A 60 mA 60 mA 500 Power Supply VCC Positive Supply Voltage For Specified Performance ICC Supply Current 4.75V VCC 5.25V 4.75V VCC 15.75V Short-Circuit Current Low VOUT Shorted to GND Short-Circuit Current High VOUT Shorted to VCC Output Impedance to GND Input Code = 0 Voltage Output Slew Rate 5k in Parallel with 100pF Voltage Output Settling Time To 1/2LSB, 5k in Parallel with 100pF, VCC = 4.75V Digital Feedthrough (Notes 2,3) 4.75 350 800 Op Amp DC Performance 250 AC Performance 1.0 V/s 6 50 s nV/s Digital I/O VIH Digital Input High Voltage VIL Digital Input Low Voltage VOH Digital Output High Voltage IOUT = -1mA, DOUT Only VCC - 1 V VOL Digital Output Low Voltage IOUT = 1mA, DOUT Only 0.4 V ILEAK Digital Input Leakage VIN = GND to VCC 10 A CIN Digital Input Capacitance (Note 2) 10 pF 2.4 V 0.8 V Switching (Note 2) t1 DIN Valid to CLK Setup t2 DIN Valid to CLK Hold 25 ns t3 CLK High Time 350 ns t4 CLK Low Time 350 ns t5 LOAD Pulse Width 150 ns t6 LSB CLK to LOAD 0 ns t7 LOAD High to CLK 0 ns t8 DOUT Output Delay 35 fCLK Maximum Clock Frequency CLOAD = 15pF Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Guaranteed by design; not subject to test. 100 ns 150 ns 1.4 MHz Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code. Note 4: Guaranteed with internal VREF or with external VREF range of 2.475V to 12V. Tested at 10V. 3 LTC1257 U W TYPICAL PERFOR A CE CHARACTERISTICS Minimum Supply Voltage vs Load Current #2 Minimum Supply Voltage vs Load Current #1 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0.01 0.1 1 OUTPUT LOAD CURRENT (mA) VREF = 10V VOUT = FULL SCALE TA = 25C 14.5 14.0 13.5 13.0 12.5 12.0 0.1 1 OUTPUT LOAD CURRENT (mA) OUTPUT VOLTAGE SWING (V) 0.39 4.0 ZERO SCALE RL TIED TO VCC 3.5 3.0 FULL SCALE RL TIED TO GND 2.5 2.0 1.5 1.0 0.5 0.34 4 100 1k LOAD RESISTANCE () 0.8 2.0480 2.0475 2.0470 125 1257 G07 4 COLD ROOM 1 1 10 100 OUTPUT SINK CURRENT (A) Integral Nonlinearity (INL) VCC = 5V INTERNAL REFERENCE 1.6 1.2 0.7 0.8 0.6 0.5 0.4 0.3 0.4 0 -0.4 -0.8 0.2 0 -50 1000 2.0 VCC = 5V INTERNAL REFERENCE TA = 25C -1.2 0.1 100 HOT 1257 G06 ERROR (LSB) ZERO-SCALE VOLTAGE (mV) FULL-SCALE VOLTAGE (V) VCC = 5V INTERNAL REFERENCE 50 25 75 0 TEMPERATURE (C) 10 10k 0.9 2.0465 -50 -25 100 Zero-Scale Voltage vs Temperature 2.0495 125 Pull-Down Voltage vs Output Sink Current Capability 1257 G05 Full-Scale Voltage vs Temperature 2.0485 100 1257 G03 0.1 0 10 5 1257 G04 2.0490 50 25 75 0 TEMPERATURE (C) 1000 VCC = 5V 4.5 0.44 3 2 LOGIC VOLTAGE (V) 0.31 -50 -25 10 5.0 VCC = 5V TA = 25C 1 VCC = 4.75V 0.33 Output Swing vs Load Resistance 0.59 0 0.34 1257 G02 Supply Current vs Logic Input Voltage 0.49 VCC = 5V 0.35 0.32 1257 G01 0.54 VCC = 5.25V 0.36 11.5 11.0 0.01 10 0.37 OUTPUT PULL-DOWN VOLTAGE (mV) MINIMUM SUPPLY VOLTAGE (V) 4.6 MINIMUM SUPPLY VOLTAGE (V) VREF = INTERNAL VOUT = FULL SCALE TA = 25C 4.8 0.38 SUPPLY CURRENT (mA) 5.0 SUPPLY CURRENT (mA) Supply Current vs Temperature 15.0 -1.6 -2.0 -25 0 25 50 75 TEMPERATURE (C) 100 125 1257 G08 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1257 G09 LTC1257 U W TYPICAL PERFOR A CE CHARACTERISTICS Reference Compensation Resistance vs CL Differential Nonlinearity (DNL) 0.0 -0.5 0 512 1024 1536 2048 2560 3072 3584 4098 CODE 70 CODE = FFFH BW = 3Hz TO 1MHz GAIN = 1100x 60 50 40 0.1V/DIV REFERENCE COMPENSATION RESISTANCE () DNL ERROR (LSBs) 0.5 Broadband Noise 30 20 10 0 0.01 0.1 1257 TA05 1 CL (F) 10 100 TIME = 5ms/DIV 1257 G12 1257 G11 U U U PI FU CTIO S CLK (Pin 1): The TTL level input for the serial interface clock. DIN (Pin 2): The TTL level input for the serial interface data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. LOAD (Pin 3): The TTL level input for the serial interface load control. Data is loaded from the shift register into the DAC register, thus updating the DAC output when LOAD is pulled low. The DAC register is transparent as long as LOAD is held low. DOUT(Pin 4): The output of the shift register which becomes valid on the rising edge of the serial clock. The DOUT pin is driven from GND to VCC by an internal CMOS inverter. Multiple LTC1257s may be cascaded by connecting the DOUT pin to the DIN pin of the next chip. GND (Pin 5): Ground. REF (Pin 6): The output of the 2.048V reference and the input to the DAC resistor ladder. An external reference with voltage from 2.475V to VCC - 2.7V may be used to override the internal reference. VOUT (Pin 7): The buffered DAC output is capable of sourcing 2mA over temperature while pulling within 2.7V of VCC. The output will pull to ground through an internal 250 equivalent resistance. VCC (Pin 8): The positive supply input. 4.75V VCC 15.75V. Requires a bypass capacitor to ground. 5 LTC1257 U U DEFI ITIO S LSB: The least significant bit or the ideal voltage difference between two successive codes. LSB = n = VOS = VFS = (VFS - VOS)/2n - 1 The number of digital input bits The zero code error or offset of the DAC The full-scale output voltage of the DAC measured when all bits are set to 1 Resolution: The resolution is the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. INL: End-point integral nonlinearity is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below ground, the linearity is measured between full-scale and the first code that guarantees a positive output. The INL error at a given input code is calculated as follows: Offset Error: The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below ground. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. OUTPUT VOLTAGE NEGATIVE OFFSET { 0V DAC CODE 1257 F01 Figure 1. Effect of Negative Offset The offset of the part is measured at the first code that produces an output voltage 0.5LSB greater than the previous code: VOS = VOUT - [(Code)(VFS)/(2n - 1)] INL = (VOUT - VIDEAL)/LSB VIDEAL = (Code)(LSB) + VOS VOUT = The output voltage of the DAC measured at the given input code Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output voltages with all bits set to one (Code = 4095). The full-scale error includes the offset error and is calculated as follows: DNL: Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: FSE = (VOUT - VIDEAL)/LSB VIDEAL = (VREF)(1 - 2-n) - VOS VREF = The reference voltage, either internal or external DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes Gain Error: Gain error is the difference between the ideal and measured slope of the DAC transfer characteristic. Gain error is equal to full-scale error minus offset error. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). 6 LTC1257 W BLOCK DIAGRA LOGIC SUPPLY CLK DIN 5V REGULATOR VCC 12-BIT SHIFT REGISTER DOUT 12 LOAD GND 12-BIT LATCH 12 REF 2.048V REFERENCE + DAC VOUT - 1257 BD WU W TI I G DIAGRA t1 t2 t6 CLK t4 B11 MSB DIN t7 t3 B0 LSB B1 B10 t5 LOAD t8 DOUT B11 (PREVIOUS WORD) B10 B1 B0 B11 CURRENT WORD 1257 TD 7 LTC1257 U OPERATIO Serial Interface Reference The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first and the LSB last. The DAC register loads the data from the shift register when LOAD is pulled low, and remains transparent until LOAD is pulled high and the data is latched. The LTC1257 includes an internal 2.048V reference, making 1LSB equal to 500V. The internal reference output is turned off when the pin is forced above the reference voltage, allowing an external reference to be connected to the reference pin. The external reference must be greater than 2.475V and less than VCC - 2.7V, and be capable of driving the 10k minimum DAC resistor ladder. An internal 5V regulator provides the supply for the digital logic. By limiting the internal digital signal swings to 5V, digital noise is reduced. The buffered output of the 12-bit shift register is available on the DOUT pin which will swing from GND to VCC. Multiple LTC1257s may be daisy chained together by connecting the DOUT pin to the DIN pin of the next chip, while the clock and load signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the LOAD signal is pulled low to update all of them simultaneously. The maximum clocking rate is 1.4MHz. If the reference output is driving a large capacitive load, a series resistor must be added to insure stability. For any capacitive load greater than 1F, a 10 series resistor will suffice. Voltage Output The LTC1257 voltage output is able to pull within 2.7V of VCC while sourcing 2mA. A internal NMOS transistor with a 200 equivalent impedance pulls the output to ground. The output is protected against short circuits and is able to drive up to a 500pF capacitive load without oscillation. If digital noise on the output causes a problem, a simple 100, 0.1F RC circuit can be used to filter the noise. U TYPICAL APPLICATIO S DAC with External Reference Filtering VREF and VOUT 15V VCC IN 0.1F LT1021-10 GND OUT 0.1F DIN CLK VCC CONTROL OUTPUT VREF VOUT LTC1257 GND DIN CLK LOAD LOAD P 100 5% LTC1257 VOUT DOUT GND VOUT 0.1F VREF 1F DOUT 1257 TA06 1257 TA03 8 VCC 10 5% LTC1257 U TYPICAL APPLICATIO S Auto Ranging 8-Channel ADC with Shutdown 22F 5V VCC CH0 8 ANALOG INPUT CHANNELS CS DOUT * * * LTC1296 P CLK DIN CH7 COM REF + REF - SSO 50k 50k 5V 74HC04 0.1F VCC DIN 100 VOUT LTC1257 0.1F DIN 100 VOUT LTC1257 GND VREF 0.1F LOAD DOUT GND VREF VCC CLK CLK LOAD DOUT 1257 TA02 12-Bit Single 5V Control System with Shutdown 5V 100k 10k 10F 2N3906 VCC -IN - J DATA CLK GND COMMON P DAC LOAD LTC1297 ADC LT1025A + CLK DOUT 0.1F VIN CB/POWER DOWN CS +IN GND + 10F VREF 47k LTC1050 - 1F 1F 100k VREF 74k 1k CONTORL OUTPUT VCC DIN CLK VOUT LTC1257 LOAD GND DOUT 1257 TA04 9 LTC1257 U PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 0.015* (6.477 0.381) 0.300 - 0.325 (7.620 - 8.255) 0.009 - 0.015 (0.229 - 0.381) ( +0.035 0.325 -0.015 8.255 +0.889 -0.381 ) 0.045 - 0.065 (1.143 - 1.651) 0.065 (1.651) TYP 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 10 0.130 0.005 (3.302 0.127) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076) N8 1098 LTC1257 U PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.189 - 0.197* (4.801 - 5.004) 8 7 6 5 0.150 - 0.157** (3.810 - 3.988) 0.228 - 0.244 (5.791 - 6.197) 1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP 0.016 - 0.050 (0.406 - 1.270) 0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2 3 4 0.004 - 0.010 (0.101 - 0.254) 0.050 (1.270) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 1298 11 LTC1257 UO TYPICAL APPLICATI Driving LTC1257 with Optoisolators 12V 2k 5% MOC5008 CLK LT1021-5 VOUT VIN 2k 5% 2k 5% 0.1F CLK VCC 6 VREF DIN VOUT LOAD LTC1257 1 4 2 DOUT VOUT GND 5 MOC5008 DIN 6 1 4 2 5 MOC5008 LOAD 1 6 4 2 5 1257 TA07 RELATED PARTS PART NUMBER 12 Bit LTC1446/LTC1446L DESCRIPTION COMMENTS Dual 12-Bit VOUT DACs in SO-8 Package LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package, VCC: 2.7V to 5.5V LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1451 LTC1452 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package LTC1453 LTC1454/LTC1454L Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458/LTC1458L LTC1659 14 Bit LTC1658 LTC1654 16 Bit LTC1655(L) 12 Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC = 2.7V to 5.5V 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC = 2.7V to 5.5V Dual 14-Bit VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Linear Technology Corporation Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC Output Swings from GND to REF, REF Input Can Be Tied to VCC Programmable Speed/Power, SO-8 Footprint VCC = 5V (3V), Low Power, Deglitched, VOUT = 0V to 4.096V (0V to 2.5V) 1257fb LT/TP 1101 REV B 1.5K * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 1994