1
LTC1257
Complete Single Supply
12-Bit Voltage Output
DAC in SO-8
CODE
0
DNL ERROR (LSBs)
0.5
0.0
–0.5 1024 2048 2560
1257 TA05
512 1536 3072 3584 4098
Differential Nonlinearity
vs Input Code
■
Digital Offset/Gain Adjustment
■
Industrial Process Control
■
Automatic Test Equipment
The LTC
®
1257 is a complete single supply, 12-bit voltage
output D/A converter (DAC) in an SO-8 package. The
LTC1257 includes an output buffer amplifier, 2.048V
voltage reference and an easy to use three-wire cascadable
serial interface. An external reference can be used to
override the internal reference and extend the output
voltage range to 12V. The power supply current is a low
350µA when operating from a 5V supply, making the
LTC1257 ideal for battery-powered applications. The space-
saving 8-pin SO package and operation with no external
components provide the smallest 12-bit D/A system
available.
■
8-Pin SO Package
■
Buffered Voltage Output
■
Built-In 2.048V Reference
■
500µV/LSB with 2.048V Full Scale
■
1/2LSB Max DNL Error
■
Guaranteed 12-Bit Monotonic
■
3-Wire Cascadable Serial Interface
■
Wide Single Supply Range: V
CC
= 4.75V to 15.75V
■
Low Power: I
CC
Typ = 350µA with 5V Supply
, LTC and LT are registered trademarks of Linear Technology Corporation.
µP
5V
0.1µF
0.1µF
CONTROL OUTPUT 1
CONTROL OUTPUT 2
V
CC
V
REF
GND
V
OUT
D
IN
CLK
LOAD
D
OUT
LTC1257
V
CC
V
REF
GND
V
OUT
D
IN
CLK
LOAD
D
OUT
LTC1257
TO NEXT DAC
1257 TA01
Daisy-Chained Control Outputs
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1257
(Note 1)
V
CC
to GND ............................................ –0.5V to 16.5V
TTL Input Voltage .......................... –0.5V to V
CC
+ 0.5V
V
OUT
.............................................. –0.5V to V
CC
+ 0.5V
REF ................................................ –0.5V to V
CC
+ 0.5V
Operating Temperature Range
LTC1257C ............................................. 0°C to 70°C
LTC1257I ........................................ –40°C to 85°C
Maximum Junction Temperature
Plastic Package ............................. –65°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LTC1257CN8
LTC1257IN8
S8 PART MARKING
TJMAX = 125°C, θJA = 100°C/W
TJMAX = 125°C, θJA = 150°C/W
LTC1257CS8
LTC1257IS8
1
2
3
4
8
7
6
5
TOP VIEW
N8 PACKAGE
8-LEAD PDIP
V
CC
V
OUT
REF
GND
CLK
D
IN
LOAD
D
OUT
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
VCC
VOUT
REF
GND
CLK
DIN
LOAD
DOUT
1257
1257I
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted.
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC
Resolution ●12 Bits
DNL Differential Nonlinearity Guaranteed Monotonic (Note 4) ●±0.5 LSB
INL Integral Nonlinearity LTC1257C (Note 4) ●±3.5 LSB
LTC1257I (Note 4) ●±4.0 LSB
OFF Offset Error When Using Internal Reference, LTC1257C ●±8 LSB
When Using Internal Reference, LTC1257I ●±10 LSB
When Using External Reference, LTC1257C ●±4mV
When Using External Reference, LTC1257I ●±5mV
OFF
TC
Offset Error Tempco When Using Internal Reference (Note 2) ●±0.02 ±0.066 LSB/°C
When Using External Reference (Note 2) ●±15 ±30 µV/°C
Gain Error ●0.5 ±2 LSB
Gain Error Tempco (Note 2) ●±0.01 ±0.02 LSB/°C
Reference
Reference Output Voltage I
REF
= 0, LTC1257C ●2.028 2.048 2.068 V
I
REF
= 0, LTC1257I ●2.018 2.078 V
Reference Output Tempco I
REF
= 0 ●±0.06 LSB/°C
Reference Line Regulation I
REF
= 0, LTC1257C ●±0.4 LSB/V
I
REF
= 0, LTC1257I ●±0.7 LSB/V
Reference Load Regulation 0 ≤ I
REF
≤ 100µA●±1 LSB
Reference Input Range V
CC
> V
REF
+ 2.7V ●2.475 12 V
Reference Input Resistance ●81418 kΩ
Reference Input Capacitance (Note 2) 15 pF
Short-Circuit Current V
REF
Shorted to GND ●90 mA
3
LTC1257
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
Positive Supply Voltage For Specified Performance ●4.75 15.75 V
I
CC
Supply Current 4.75V ≤ V
CC
≤ 5.25V ●350 600 µA
4.75V ≤ V
CC
≤ 15.75V ●800 1500 µA
Op Amp DC Performance
Short-Circuit Current Low V
OUT
Shorted to GND ●60 mA
Short-Circuit Current High V
OUT
Shorted to V
CC
●60 mA
Output Impedance to GND Input Code = 0 ●250 500 Ω
AC Performance
Voltage Output Slew Rate 5kΩ in Parallel with 100pF ●1.0 V/µs
Voltage Output Settling Time To ±1/2LSB, 5kΩ in Parallel with 100pF, V
CC
= 4.75V ●6µs
Digital Feedthrough (Notes 2,3) 50 nV/s
Digital I/O
V
IH
Digital Input High Voltage ●2.4 V
V
IL
Digital Input Low Voltage ●0.8 V
V
OH
Digital Output High Voltage I
OUT
= –1mA, D
OUT
Only ●V
CC
– 1 V
V
OL
Digital Output Low Voltage I
OUT
= 1mA, D
OUT
Only ●0.4 V
I
LEAK
Digital Input Leakage V
IN
= GND to V
CC
●±10 µA
C
IN
Digital Input Capacitance (Note 2) ●10 pF
Switching (Note 2)
t1 D
IN
Valid to CLK Setup ●100 ns
t2 D
IN
Valid to CLK Hold ●25 ns
t3 CLK High Time ●350 ns
t4 CLK Low Time ●350 ns
t5 LOAD Pulse Width ●150 ns
t6 LSB CLK to LOAD ●0ns
t7 LOAD High to CLK ●0ns
t8 D
OUT
Output Delay C
LOAD
= 15pF ●35 150 ns
f
CLK
Maximum Clock Frequency 1.4 MHz
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Guaranteed by design; not subject to test.
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at
TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Note 4: Guaranteed with internal V
REF
or with external V
REF
range of
2.475V to 12V. Tested at 10V.
4
LTC1257
TEMPERATURE (°C)
–50
0.38
0.37
0.36
0.35
0.34
0.33
0.32
0.31 25 75
1257 G03
–25 0 50 100 125
SUPPLY CURRENT (mA)
V
CC
= 5.25V
V
CC
= 5V
V
CC
= 4.75V
Supply Current vs Temperature
OUTPUT SINK CURRENT (µA)
1
OUTPUT PULL-DOWN VOLTAGE (mV)
1000
100
10
1
0.1 10 100 1000
1257 G06
HOT COLD
ROOM
Pull-Down Voltage vs Output Sink
Current Capability
TEMPERATURE (°C)
–50
FULL-SCALE VOLTAGE (V)
2.0495
2.0490
2.0485
2.0480
2.0475
2.0470
2.0465 25 75
1257 G07
–25 0 50 100 125
V
CC
= 5V
INTERNAL REFERENCE
OUTPUT LOAD CURRENT (mA)
0.01
MINIMUM SUPPLY VOLTAGE (V)
0.1 1 10
1257 G01
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
V
REF
= INTERNAL
V
OUT
= FULL SCALE
T
A
= 25°C
Minimum Supply Voltage
vs Load Current #1
LOGIC VOLTAGE (V)
0
SUPPLY CURRENT (mA)
0.59
0.54
0.49
0.44
0.39
0.34 4
1257 G04
1235
V
CC
= 5V
T
A
= 25°C
Minimum Supply Voltage
vs Load Current #2
OUTPUT LOAD CURRENT (mA)
0.01
MINIMUM SUPPLY VOLTAGE (V)
0.1 1 10
1257 G02
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
V
REF
= 10V
V
OUT
= FULL SCALE
T
A
= 25°C
LOAD RESISTANCE (Ω)
10
OUTPUT VOLTAGE SWING (V)
100 1k 10k
1257 G05
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FULL SCALE
R
L
TIED TO GND
ZERO SCALE
R
L
TIED TO V
CC
V
CC
= 5V
Output Swing vs Load Resistance
Supply Current vs
Logic Input Voltage
Full-Scale Voltage vs
Temperature
TEMPERATURE (°C)
–50 –25 25 50
ZERO-SCALE VOLTAGE (mV)
75 100
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1257 G08
0 125
V
CC
= 5V
INTERNAL REFERENCE
Zero-Scale Voltage vs
Temperature
CODE
0
ERROR (LSB)
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0 1024 2048 2560
1257 G09
512 1536 3072 3584 4096
V
CC
= 5V
INTERNAL REFERENCE
T
A
= 25°C
Integral Nonlinearity (INL)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5
LTC1257
CL (µF)
0.01
REFERENCE COMPENSATION RESISTANCE (Ω)
70
60
50
40
30
20
10
00.1 1
1257 G11
10 100
Reference Compensation
Resistance vs CLBroadband Noise
GND (Pin 5): Ground.
REF (Pin 6): The output of the 2.048V reference and the
input to the DAC resistor ladder. An external reference with
voltage from 2.475V to V
CC
– 2.7V may be used to override
the internal reference.
V
OUT
(Pin 7): The buffered DAC output is capable of
sourcing 2mA over temperature while pulling within 2.7V
of V
CC
. The output will pull to ground through an internal
250Ω equivalent resistance.
V
CC
(Pin 8): The positive supply input. 4.75V ≤ V
CC
≤
15.75V. Requires a bypass capacitor to ground.
CLK (Pin 1): The TTL level input for the serial interface
clock.
D
IN
(Pin 2): The TTL level input for the serial interface data.
Data on the D
IN
pin is latched into the shift register on the
rising edge of the serial clock.
LOAD (Pin 3): The TTL level input for the serial interface
load control. Data is loaded from the shift register into the
DAC register, thus updating the DAC output when LOAD is
pulled low. The DAC register is transparent as long as
LOAD is held low.
D
OUT
(Pin 4): The output of the shift register which
becomes valid on the rising edge of the serial clock. The
D
OUT
pin is driven from GND to V
CC
by an internal CMOS
inverter. Multiple LTC1257s may be cascaded by connect-
ing the D
OUT
pin to the D
IN
pin of the next chip.
CODE
0
DNL ERROR (LSBs)
0.5
0.0
–0.5 1024 2048 2560
1257 TA05
512 1536 3072 3584 4098
Differential Nonlinearity (DNL)
TIME = 5ms/DIV
0.1V/DIV
1257 G12
CODE = FFF
H
BW = 3Hz TO 1MHz
GAIN = 1100×
TYPICAL PERFOR A CE CHARACTERISTICS
UW
UU
U
PI FU CTIO S
6
LTC1257
LSB: The least significant bit or the ideal voltage difference
between two successive codes.
LSB = (V
FS
– V
OS
)/2
n
– 1
n = The number of digital input bits
V
OS
= The zero code error or offset of the DAC
V
FS
= The full-scale output voltage of the DAC
measured when all bits are set to 1
Resolution: The resolution is the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
INL: End-point integral nonlinearity is the maximum de-
viation from a straight line passing through the end-points
of the DAC transfer curve. Because the part operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at a
given input code is calculated as follows:
INL = (V
OUT
– V
IDEAL
)/LSB
V
IDEAL
= (Code)(LSB) + V
OS
V
OUT
= The output voltage of the DAC measured at
the given input code
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
∆V
OUT
= The measured voltage difference between
two adjacent codes
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is oper-
ated from a single supply, the output cannot go below
ground. If the offset is negative, the output will remain near
0V resulting in the transfer curve shown in Figure 1.
Figure 1. Effect of Negative Offset
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the pre-
vious code:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Full-Scale Error: Full-scale error is the difference be-
tween the ideal and measured DAC output voltages with all
bits set to one (Code = 4095). The full-scale error includes
the offset error and is calculated as follows:
FSE = (V
OUT
– V
IDEAL
)/LSB
V
IDEAL
=(V
REF
)(1 – 2
–n
) – V
OS
V
REF
= The reference voltage, either internal or
external
Gain Error: Gain error is the difference between the ideal
and measured slope of the DAC transfer characteristic.
Gain error is equal to full-scale error minus offset error.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
{
DAC CODE 0V
1257 F01
DEFI ITIO S
UU
7
LTC1257
–
+
DAC
5V REGULATOR
12-BIT
SHIFT REGISTER
12-BIT LATCH
2.048V REFERENCE
VCC
DOUT
GND
VOUT
DIN
LOGIC
SUPPLY
CLK
LOAD
REF 12
12
1257 BD
B10
B11
(PREVIOUS WORD)
B11
MSB B10
t
1
B1
t
6
B1
B0
LSB
B0 B11
CURRENT WORD
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
LOAD
t
5
1257 TD
BLOCK DIAGRA
W
TI I G DIAGRA
UWW
8
LTC1257
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first and
the LSB last. The DAC register loads the data from the shift
register when LOAD is pulled low, and remains transpar-
ent until LOAD is pulled high and the data is latched.
An internal 5V regulator provides the supply for the digital
logic. By limiting the internal digital signal swings to 5V,
digital noise is reduced. The buffered output of the 12-bit
shift register is available on the D
OUT
pin which will swing
from GND to V
CC
.
Multiple LTC1257s may be daisy chained together by
connecting the D
OUT
pin to the D
IN
pin of the next chip,
while the clock and load signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips, then the LOAD signal is pulled low to update all
of them simultaneously. The maximum clocking rate is
1.4MHz.
Reference
The LTC1257 includes an internal 2.048V reference, mak-
ing 1LSB equal to 500µV. The internal reference output is
turned off when the pin is forced above the reference
voltage, allowing an external reference to be connected to
the reference pin. The external reference must be greater
than 2.475V and less than V
CC
– 2.7V, and be capable of
driving the 10k minimum DAC resistor ladder.
If the reference output is driving a large capacitive load, a
series resistor must be added to insure stability. For any
capacitive load greater than 1µF, a 10Ω series resistor will
suffice.
Voltage Output
The LTC1257 voltage output is able to pull within 2.7V of
V
CC
while sourcing 2mA. A internal NMOS transistor with
a 200Ω equivalent impedance pulls the output to ground.
The output is protected against short circuits and is able
to drive up to a 500pF capacitive load without oscillation.
If digital noise on the output causes a problem, a simple
100Ω, 0.1µF RC circuit can be used to filter the noise.
DAC with External Reference Filtering VREF and VOUT
0.1µF
0.1µF
1µF
V
CC
V
CC
V
REF
GND
V
OUT
V
OUT
D
IN
CLK
LOAD
D
OUT
LTC1257
1257 TA06
10Ω
5%
100Ω
5%
µP
15V
0.1µF
CONTROL OUTPUT
V
CC
V
REF
GND
V
OUT
D
IN
CLK
LOAD
D
OUT
LTC1257
1257 TA03
IN
OUT
GND
LT1021-10
OPERATIO
U
TYPICAL APPLICATIO S
U
9
LTC1257
Auto Ranging 8-Channel ADC with Shutdown
12-Bit Single 5V Control System with Shutdown
5V
1µF
CONTORL
OUTPUT
V
CC
V
REF
GND
V
OUT
D
IN
CLK
LOAD
D
OUT
LTC1257
1257 TA04
2N3906
–IN CB/POWER DOWN
CLK
DATA
DAC LOAD
–
+
V
CC
CS
D
OUT
CLK
+IN
LTC1297
ADC
V
REF
GND
0.1µF
10µF
V
IN
LT1025A
COMMONGND
J
74k
1k
10µF
+
–
100k 10k
100k
1µF
47k
LTC1050
µP
5V
0.1µFVCC
VREF
VOUT
DIN
CLK
LOAD
DOUT
LTC1257
VCC
VREF
GND
VOUT
DIN
CLK
LOAD
DOUT
LTC1257
1257 TA02
0.1µF
0.1µF
100Ω
100Ω
µP
8 ANALOG
INPUT CHANNELS LTC1296
CS
DOUT
CLK
DIN
CH0
•
•
•
CH7
COM
REF+REF–SSO
22µF
5V
50k 50k
VCC
74HC04
GND
TYPICAL APPLICATIO S
U
10
LTC1257
PACKAGE DESCRIPTIO
U
N8 1098
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
12 34
8765
0.255 ± 0.015*
(6.477 ± 0.381)
0.400*
(10.160)
MAX
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.325 +0.035
–0.015
+0.889
–0.381
8.255
()
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
11
LTC1257
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
12
LTC1257
LINEAR TECHNOLOGY CORPORATION 1994
1257fb LT/TP 1101 REV B 1.5K • PRINTED IN USA
U
A
O
PPLICATITYPICAL
Driving LTC1257 with Optoisolators
LT1021-5
V
OUT
V
IN
12V
V
REF
GND
CLK
6
1
2
1
2
1
2
4
5
6
4
5
6
4
5
2k
5% 2k
5% 2k
5%
V
OUT
V
OUT
0.1µF
V
CC
D
IN
CLK
D
IN
LOAD
D
OUT
LTC1257
MOC5008
MOC5008
MOC5008
LOAD
1257 TA07
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
12 Bit
LTC1446/LTC1446L Dual 12-Bit V
OUT
DACs in SO-8 Package LTC1446: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1446L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1448 Dual 12-Bit V
OUT
DAC in SO-8 Package, V
CC
: 2.7V to 5.5V Output Swings from GND to REF,
REF Input Can Be Tied to V
CC
LTC1450/LTC1450L Single 12-Bit V
OUT
DACs with Parallel Interface LTC1450: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1450L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1451 Single Rail-to-Rail 12-Bit V
OUT
DAC, Full Scale: 4.095V, V
CC
: 4.5V to Low Power, Complete V
OUT
DAC in SO-8 Package
5.5V, Internal 2.048V Reference Brought Out to Pin
LTC1452 Single Rail-to-Rail 12-Bit V
OUT
Multiplying DAC, V
CC
: 2.7V to 5.5V Low Power, Multiplying V
OUT
DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453 Single Rail-to-Rail 12-Bit V
OUT
DAC, Full Scale: 2.5V, V
CC
: 2.7V to 5.5V 3V, Low Power, Complete V
OUT
DAC in SO-8 Package
LTC1454/LTC1454L Dual 12-Bit V
OUT
DACs in SO-16 Package with Added Functionality LTC1454: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1454L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Low Power, Complete V
OUT
DAC in SO-8
Full Scale: 4.095V, V
CC
: 4.5V to 5.5V Package with Clear Pin
LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1458L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1659 Single Rail-to-Rail 12-Bit V
OUT
DAC in MSOP-8 Package, Output Swings from GND to REF,
V
CC
= 2.7V to 5.5V REF Input Can Be Tied to V
CC
14 Bit
LTC1658 14-Bit Rail-to-Rail Micropower DAC in MSOP, V
CC
= 2.7V to 5.5V Output Swings from GND to REF,
REF Input Can Be Tied to V
CC
LTC1654 Dual 14-Bit V
OUT
DAC Programmable Speed/Power, SO-8 Footprint
16 Bit
LTC1655(L) Single 16-Bit V
OUT
DAC with Serial Interface in SO-8 V
CC
= 5V (3V), Low Power, Deglitched,
V
OUT
= 0V to 4.096V (0V to 2.5V)
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
