CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B – SEPTEMBER 1994 – REVISED OCT OBER 2001
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
D
Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D
Ioff Supports Partial-Power-Down Mode
Operation
D
Matched Rise and Fall Times
D
Fully Compatible With TTL Input and
Output Logic Levels
D
64-mA Output Sink Current
32-mA Output Source Current
D
Independent Register for A and B Buses
D
Multiplexed Real-Time and Stored Data
Transfer
D
3-State Outputs
description
The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA
inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or
stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time data. A low input level selects real-time data,
and a high input level selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins.
When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal
D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus
lines remains at its last state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Q OR SO PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CPAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CPBA
SBA
GBA
B1
B2
B3
B4
B5
B6
B7
B8
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGESPEED
(ns) ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QSOP Q Tape and reel 5.4 CY74FCT652CTQCT FCT652C
SOIC SO
Tube 5.4 CY74FCT652CTSOC
FCT652C
SOIC
SO
Tape and reel 5.4 CY74FCT652CTSOCT
FCT652C
40°C to 85°CQSOP Q Tape and reel 6.3 CY74FCT652ATQCT FCT652A
SOIC SO
Tube 6.3 CY74FCT652ATSOC
FCT652A
SOIC
SO
Tape and reel 6.3 CY74FCT652ATSOCT
FCT652A
QSOP Q Tape and reel 9 CY74FCT652TQCT FCT652
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS DATA I/O OPERATION OR
GAB GBA CPAB CPBA SAB SBA A1–A8B1–B8FUNCTION
L H H or L H or L X X Input Input Isolation
L H X X Input Input Store A and B data
X H H or L X X Input Unspecified§Store A, hold B
H H XX Input Output Store A in both registers
L X H or L X X Unspecified§Input Hold A, store B
L L XX
Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
HH H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output Stored A data to B bus and
Stored B data to A bus
H = High logic level, L = Low logic level, X = Dont care, = Low-to-high transition
Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both
registers.
§The data output functions can be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions
always are enabled, i.e., data at the bus pins are stored on every low-to-high transition of the clock inputs.
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
GAB
X
L
L
GAB
LL
CPAB
XCPBA
XSAB
XSBA
LCPAB
XCPBA
XSAB
LSBA
X
HCPAB CPBA
XSAB
XSBA
XCPAB CPBA SAB SBA
X
HXX
XX
X
H L H or L H H
GBA
GBA
HH
GAB GBA
GAB GBA H or L
REAL-TIME TRANSFER
BUS B TO BUS A REAL-TIME TRANSFER
BUS A TO BUS B
STORE DATA
FROM A AND/OR B TRANSFER STORED DATA
TO A AND/OR B
3 21 1 23 2 22 1 23 2 22321
3 21 23 2 22 3 21 1 2 22
123
Figure 1. Bus-Management Functions
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
GBA
A1B1
1D
C1
1D
C1
One of Eight Channels
SAB
CPAB
SBA
CPBA
GAB
To Seven Other Channels
21
3
23
22
1
2
420
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): Q package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, TA 65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current 32 mA
IOL Low-level output current 64 mA
TAOperating free-air temperature 40 85 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK VCC = 4.75 V, IIN = 18 mA 0.7 1.2 V
VOH
VCC 475V
IOH = 32 mA 2
V
V
OH
V
CC =
4
.
75
V
IOH = 15 mA 2.4 3.3
V
VOL VCC = 4.75 V, IOL = 64 mA 0.3 0.55 V
Vhys All inputs 0.2 V
IIVCC = 5.25 V, VIN = VCC 5µA
IIH VCC = 5.25 V, VIN = 2.7 V ±1µA
IIL VCC = 5.25 V, VIN = 0.5 V ±1µA
IOZH VCC = 5.25 V, VOUT = 2.7 V 10 µA
IOZL VCC = 5.25 V, VOUT = 0.5 V 10 µA
IOSVCC = 5.25 V, VOUT = 0 V 60 120 225 mA
Ioff VCC = 0 V, VOUT = 4.5 V ±1µA
ICC VCC = 5.25 V, VIN0.2 V, VIN VCC 0.2 V 0.1 0.2 mA
ICC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2 mA
ICCDVCC = 5.25 V, One input switching at 50% duty cycle, Outputs open,
GAB or GBA = GND, VIN0.2 V or VIN VCC 0.2 V 0.06 0.12 mA/
MHz
VCC = 5.25 V,
f0=10MHz
One bit switching
at f1 = 5 MHz VIN0.2 V or
VIN VCC 0.2 V 0.7 1.4
IC#
f0
=
10
MHz
,
Outputs open,
1
at 50% duty cycle VIN = 3.4 V or GND 1.2 3.4
mA
I
C
#
,
GAB = GBA = GND,
SAB = CPAB = GND,
SBA V
Eight bits switching
at f1 = 5 MHz VIN0.2 V or
VIN VCC 0.2 V 2.8 5.6||
mA
SBA
=
V
CC
1
at 50% duty cycle VIN = 3.4 V or GND 5.1 14.6||
Ci5 10 pF
Co9 12 pF
Typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
This parameter is derived for use in total power-supply calculations.
#IC= ICC + ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC= Total supply current
ICC = Power-supply current with CMOS input levels
ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH= Duty cycle for TTL inputs high
NT= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
CY74FCT652T CY74FCT652AT CY74FCT652CT
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, clock high or low 6 5 5 ns
tsu Setup time, before CPAB or CPBAA or B 4 2 2 ns
thHold time, after CPAB or CPBAA or B 2 1.5 1.5 ns
switching characteristics over operating free-air temperature range (see Figure 2)
PARAMETER
FROM TO CY74FCT652T CY74FCT652AT CY74FCT652CT
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
UNIT
tPLH
AorB
BorA
1.5 9 1.5 6.3 1.5 5.4
ns
tPHL
A
or
B
B
or
A
1.5 9 1.5 6.3 1.5 5.4
ns
tPZH
GAB or GBA
AorB
1.5 14 1.5 9.8 1.5 7.8
ns
tPZL
GAB
or
GBA
A
or
B
1.5 14 1.5 9.8 1.5 7.8
ns
tPHZ
GAB or GBA
AorB
1.5 9 1.5 6.3 1.5 6.3
ns
tPLZ
GAB
or
GBA
A
or
B
1.5 9 1.5 6.3 1.5 6.3
ns
tPLH
CPAB or CPBA
AorB
1.5 9 1.5 6.3 1.5 5.7
ns
tPHL
CPAB
or
CPBA
A
or
B
1.5 9 1.5 6.3 1.5 5.7
ns
tPLH
SBA or SAB
AorB
1.5 11 1.5 7.7 1.5 6.2
ns
tPHL
SBA
or
SAB
A
or
B
1.5 11 1.5 7.7 1.5 6.2
ns
CY74FCT652T
8-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCCS032B SEPTEMBER 1994 REVISED OCTOBER 2001
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL + 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1 7 V
500 GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH 0.3 V
500
500
1.5 V1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 2. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CY74FCT652ATQCT ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652ATQCTE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652ATQCTG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652ATSOC ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652ATSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652ATSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652ATSOCT ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652ATSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652ATSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652CTQCT ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652CTQCTE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652CTQCTG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652CTSOC OBSOLETE SOIC DW 24 TBD Call TI Call TI
CY74FCT652CTSOCE4 OBSOLETE SOIC DW 24 TBD Call TI Call TI
CY74FCT652CTSOCG4 OBSOLETE SOIC DW 24 TBD Call TI Call TI
CY74FCT652CTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652CTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT652CTSOCTG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 25-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CY74FCT652TQCT ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652TQCTE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT652TQCTG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CY74FCT652ATQCT SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CY74FCT652ATSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
CY74FCT652CTQCT SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CY74FCT652CTSOCT SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
CY74FCT652TQCT SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CY74FCT652ATQCT SSOP DBQ 24 2500 367.0 367.0 38.0
CY74FCT652ATSOCT SOIC DW 24 2000 367.0 367.0 45.0
CY74FCT652CTQCT SSOP DBQ 24 2500 367.0 367.0 38.0
CY74FCT652CTSOCT SOIC DW 24 2000 367.0 367.0 45.0
CY74FCT652TQCT SSOP DBQ 24 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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