eS 4 Meg x 4 bit CMOS Dynamic Random Access Memory * Access Times: 60 and 70ns + 32ms Refresh Rate * Low Operating Power Dissipation * Low Standby Power > Common lO * All Inputs/Outputs TTL Compatible Package Style > 24/28 Thinpack Flatpack > 24/28 Pin Flatpack Single +5 (+10%) Supply Operation PRM eCUeny veel oo Lo 26 VSS 0a12co bro 27004 0a23 co Es 2g 003 w 40 fC 25 CAS Rass CO fo 24.G\ nc 6CQ [4 23 A5 4108c5 fT 20 a8 A0 1c ES if A7 Al 11-4 PO 1g A6 a2 12-7 [T1745 a3 1300 FO gaa voc14C Fo is vss EDI444096C 4Megr4 Fast Page DRAM 4 Megabit x 4 Dynamic RAM 5U Fast Page The EDI444096C is a high perfomance, lov power CMOS Dynamic RAM organized as 4 Megabit x 4. During READ and WRITE cycles each bit is addressed through 22 address bits which are entered 11 at a time (A@- A10). RAS\ is used to latch the first 11 bits and CAS\, the second 11 bits. A READ or WRITE cydeis selected with the WA input. A logic HIGH on WA dictates READ mode, while a logic LOW on W\ dictates WRITE mode. During a WRITE cyde Data-inis latched by thefalling edgeaf WiorCASt whichever occurslast. IFW goeslow priartoCAS\ going LOW, the output pins remain open (HIGH-Z) until the next CAS\ cycle, regardless of the status of G\. If Wi goes LOW after data reaches the output pins, Data-out pins are activated andretain the selectedcell data aslongasC AS\ and Giremain LOW, regardess of Wi or RAS\. This late Wi pulse results in a DELAYED WRITE or READ-WRITE cyde. The four data inputs and four data outputs are routed through four pins using common I/O and pin direction is controlled by W\and Gl. FAST PAGE MODE operations allow faster data operations, READ, WRITE or READ-MODIFY-WRITE, within a row address. Allinputs and outputs are TTL compatible and operate from a single 5 volt supply. Note WALOW priorte CAS\ LOW, EW detection circuit output is a HlGH {EARLY WRITE). CAS\LOW priorto Wi LOW, EW detection circuit output isa LOW (LATE WRITE). Pin Names AG-A10 Address Inputs CASI Column Address Strobe RAS\ Raw Address Strobe wi Write Control Input G\ Quipul Enable DO1-DO4 Data Inputs/Ouiputs vcc Power (+5V410%) vss Ground NC No Connedion Electronic Designs Incorporated + One Research Drive + Westborough, MA 01581 USA + 508-366-5151 + FAX 508-836-4850 http://www. lectronic-designs.com 7 Endaanesc Rey 2d son ECO nas,sie MRE ea wt t CAS. Pow ale Sesae Amplifier contal Address | Buffers (14) FT ern en ent | pw Desoder | 208 a Data In 4 \_______te [fom AS Buffers be | bee patie OCS Enily White Detection Grout 4 =F >} Date un pat a w| Bules Yt) Py a Column n Decoder | oat , ~io yoo 2 vss Recommended DC Operating Conditions Note Vollage on any pin relative to VSS -L.0V to 7.0V Parameter m Mn TT Max Units Operating Temperature TA (Ambient) Supply Voltage vec 45 450 #55 V Industrial A0T to +85T Supply Vollage VSS 0 0 0 V Military -55C 10 +125. Input High Votage VIH_ 2.4 - Veer] V Storage Temperature (Ceramic) 645T to +150T InputLow Votage VIL -1.0- ag sv Power Dissipation 1 Watt Qulput Current 50 mA Notes: 1. All voltage values are with respect taV'SS. *Siress greater than those listed under "Absolute Maximum Ratings may cause pemanent damage tothe device Thisis.a cress rating only and functional operaion of the device at these or any other conditions qreater than those indicated inthe operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may aifect reliability. Swe PMs em eet (VCC = 5.0 410%) Nate 2 Parameter Sym Conditions Mn Typ Max Units Average Supply Current fram VCC IcC1 RAS, CASI Cycing 10 mA Operaing (Noles 3 4) TRC = TWC = Min, Quiput Open Supply Curent from VCC ICC2 RAS\ = CAS\= VIH, Quipuis Open 2 mA Standby RAS\ = CAS\ 2 VCC41?, Quiputs Open 2 mA Average Supply Current from VOC ICC3 RAS\ Cycing, CAS\= IH 100m Refreshing (Nate 3} TRC = Min, Quiputs Open Average Supply Current from VCC Icc4 RASt= VIL, CASI = Cycing 80 mA Fast Page Mode (Notes 3 4) TPC = Min, Quiputs Gpen Average Supply Current from VCC ICC CAS| before RAS\ Refresh Cycing 100 mA CASibefore RAS\ Refresh Made (Nate 3) TRC = Min Quiputs Open Input Curent Il OVS VIN S55V 2 2 WA All Other Input Pins= OV OM-Slale Output Curent 10 Q Floaing OVS V QUTS 55V -10 10 LA Quiput High Voltage VOH 1OH = -5mA 24 ve V Output Low Voltage VOL IOL= 4.2mA 0 = 04 V Notes: 2. Currert flowing intoan |C is positive, out is negative. 3, ICC fay), |CC3fay), |CCafay), and |OCE are dependent on eyele rate. Maximumeurtent is measured at the fastest eyde rate. 4, /CC' fay), and |CCa{ay) are dependent on outputloading Specified values are obtained wih the output open ED444096C 4Mog x4 Fast Page O A i 2 ERdddnec Rey 2 fon ECoR naasEDI444096C | 4Megu4d Fasi Page DRAM (f1.0MHz, VN=VCC or VSS) Parameter Sym Test Conditions Mn Typ Max Unit Address Input Capacitance CA VW= VSS 6G pF Input Capacitance (D) cD f= MHz & pF Input Capacitance (CAS WW, RAS) cc, CW, CR Vis 25nVims 7 pF Qulput Capacitance (Q) co VO = VSS f= 1MHz, Vi= 24mVims 8 opr The EDI444096C provides, in addition to namal Read, Wiite, and Read-modify-Wrte ACT = Adive VLD = Valid operations, a number of other funciions, eg. Fast Page Made, RAS\-only Refresh, and = NAC= Non-active APD = Applied Delayed Wiile. The inpul conditians for each are shown below. DNC= Don't care OPN = Open Inputs Input/Output Operation RAS = CAS\ WG Row Column OD Q Address Address Read ACT ACT NAC ACT APD APD OPN VLD Early Write* ACT ACT ACT DNC APD APD VLD OPN ReadModify-Write ACT ACT ACT ACT APD APD VLD VLD RAS\-only Refresh ACT NAC DNC DNC APD DNC DNC OPN Hidden Refresh ACT ACT DNC ACT APD DNC OPN VLD CAStbefore RAS\ Refresh ACT ACT ACT DNC DNC DNC DNC OPN Standby NAC DNC DNC DNC DNC DNC DNC OPN *Fast Page Mode | dentical (VCC=5. 0V210%8) Note ,11,12 60ns 7dns Parameter Sym Min Max Min Max Units Notes Access Time fram CAS\ Tcac 20 20 ns 67 Access Time from RAS| TRAC 60 70 ns 68 Column Address Access Time TCAA 35 Bb ns 6 Access Time from CAS\ Precharge TCPA 40 40 ns. Access Time from G\ TOEA 20 20 ns 6 Quiput Low Impedance Time from CAS\ law TCL? 3 3 ns 9 Oulput Disable Time ale CAS\Hidh TOFF 3 20 3 40 ns 10 Qutput Disable Time after Gi High TDISOE 3 20 3 0 ns 10 Notes: & Aninitial pause of 100usis required ater power-up, fallowedby any RAS\ only refresh or CAS\ before RAS\ refresh eycles with WA HIGH before proper device operation is achieved N ote tha: RAS\ may be cycled during the initial pause, Any RAS\ only refresh or CAS\ before RAS\ refresh eydes with Wi HIGH are required alter prolonged periods of RASK inactivity before proper device operation. Measured with a load circuit equivalert to 2TTL loads and 100pF. Assumes that TRCD > TRCD (max). Assumes that TRCD <TRED (max). Guaranteed, but not tested, mn oo 4 TOFF (max) delines the time at which the output achieves the high impedance state (!OUT - [2 70yA)) and is not reference to VOH{min) or VOL (max). 3 Endaanesc Rey 2d son ECO nas,ee er neh eee mos Sele AU Emer mee ec are tLe a 8 od (VCC=5 OV 10%) Note 5,11,12 GOns 70s Parameter Sym Min Max Min Max Uni Notes Refresh Cycle TREF Ryd B ms RASI\ Precharge Time TRP 50 50 ns RAS\io CAS\ Delay Time TRCD 20 40 20 40 ns 13 Delay CAS\ Hich to RAS Low TCRP 4 4 ns CAS\ Precharge Time (Non Page Mode) TCPN 10 10 ns Coumn Address Delay from RAS| Low TRAD 15 3 15 35 ns 14 Raw Address Sel Up Time TASR 0 0 ns Coumn Address Set Up Time TASC 0 0 ns 15 Raw Address Had Time TRAH 10 10 ns Coumn Address Hold Time TCAH 14 15 ns Transiim Time TT 3 40 3 50 ns 16 Notes: 11. The timing requirements are assumed TT = 5ns. 12, VIH {min} and VIL (max) are reference levels for measuring timing of input signals. 13. TRCD(may) is specified a5 4 reference poirt only. If TRCD is lessthan TRCD(max), access timeis TRAC. If TRCD is greater than TRCD(max}, access time is defined as TCAC and TCAA as shown in nate 7. 14, TRAD (max) is specified as a reference point only. If TRAD - TRAD(max), access time is assumed byTCAA for read cycle. 15, TASC(max) is specified as areference point onfy of address acess time, 16. TT is measured between VIH{min) and IL{nmay). Pu cet BOS) (VOC=5.0210%) Note 5,11,12 G0ns 7Ons Parameter Sym Min Max Min Max Unt Notes Read Cyce Time TRC 130 130 ns RAS\ Low Pulse Width TRAS 60 100,000 70 _:100,000 ns CAS\Low Pulse Width TCAS 40: 100,000 20 100,000 ns CAS\Had Time afer RAS\ Low TCSH 6 70 ns RAS|Had Time after CAS\ Low TRSH A 70 ns Read Set Up Time before CAS\ Law TRCS 0 0 ns Read Had Time after CAS\ High TRCH a 0 ns Ww Read Had Time after RAS\ High TRRH a 0 ns W Coumn Address to RAS\ Sep TRAL 35 3 ns Precharge to CAS! Active TRPC 0 0 ns Delay Time, Datato Gi Low TDOEL 0 0 ns Delay Time, Gi Hich to Data TOEHD 20 20 ns Note 17. Ether TRCH or TRRH must be satistied for aRead Cycle ED444096C 4Mog x4 Fast Page O A i 4 ERdddnec Rey 2 fon ECoR naasEDI444096C | 4Megu4d Fasi Page DRAM VE ree yee (VCC = 5(0V210%) Notes$,11,12 Gins 70ns Parameter Sym Mn Max Min Max Unt Notes Wite Cyde Time Twe 130 130 ns RAS\ Low Pulse Width TRAS 60 100,000 70 100,000 ns CAS\ Law Pulse Width TCAS 70 100,000 70 100000 ns CAS\Had Time aller RAS\ Low TCSH 60 70 ns. RAS\Had Time afta CAS\ Law TRSH 20 20 ns. Witte Selup Time before CAS\ Law TwCcs 0 0 ns 18 Wite Had Time after CAS\ Law TWCH 15 15 ns CAS\Hdd Time after Write Law TCWL Al 20 ns RAS\ Had Time after Write Low TRWL 20 20 ns. Write Pulse Width TWP 15 15 ns. Data Setup Time TS 0 0 ns. 18 Data Had Time aller CAS\ Law TDH 15 15 ns 18 Deay Time, Gi High to Dafa TOEHD A 20 ns G\Had Time aller Wire Law THWOE A 20 ns ee Nee eRe Cele te (fe ea eee) (VCC = SOV 10%) 6Ons 70s Parameter Sym Mn Max Mn Max Unit Notes Read-Modify-Write Cydelime TRWC 180 205 ns RAS\ Low Pulse Width TRASRW 60: 100,000 80 100,000 ns CAS\ Low Pulse Width TCASRW 70: 100,000 70: 100,000 ns CAS\ Hold Time after RAS\ Low TCSHRW 60 80 ns. RAS\ Hold Time after CAS| Law TRSHRW. A 70 ns Read Setup time before CAS\ Law TRCS Q 0 ns. CAS\ Low to Wi Low Delay TCwD 40 30 ns 18 RAS\ Low to WA Low Delay TRWD 95 110 ns 18 CAS) Had after Wi Low TCWL 20 20 ns RAS\ Had after Wi Low TRWL 20 20 ns Wile Pulse Widh Twe 15 15 ns Data Sef up Time ws 0 a ns Data Had Time afler Wi Low DH 15 15 ns Address to W\ Low Delay TAWD 65 70 ns. 18 Delay Time Gi High to Dala TOEHD 20 70 ns Gi Hold Time after Write Low THWOE 20 20 ns Notes 18 TWCS, TRWD, TCWD, and TAWD do not define the limits of operation, but are included as electrical characteristics only. When TWCS - TWCS{min), an early write cycle is performed, and the data output keeps the high-impedance state. When TRWD- TRWD( min}, TCWD - TCWD{min) and TAWD = TAWD(min), aread write cycle is pertormed, and the data of the selected address will be read out on the data output. If neither of the above conditions is satistied, the condition of Q (at the access time and until CAS\ goes back to VIH) isindeterminate. 5 Endaanesc Rey 2d son ECO nas,Rear Ven eee Ce UME AU CMa CMC ea pac (VCC = 5.0210%) Notes 5,11,12 GOns 70ns Parameter Sym Min Max Min Max Unit Notes Fast Page Mode Cyce Time TPC 40 ns Fast Page Made for RAV, RIMM Cycle Time TPRWC 95 ns. RAS\L aw Pulse Width for Read, Write Cyde TRASP & 100,000 70 100,000 ns CAS Low Pulse Width for Read Cycle TCAS 70 100,000 70 100,000 ns CAS\ Pulse Width (Page Made) TCP 10 10 ns RAS\Had Time after CAS\ Low TRSH 20 20 ns (VCC = 5.0V210%) Notes 5,11,12 GOns 70ns Parameter Min Max Min Max Unit Notes CASI Sdup for CAS before RAS| Refresh TCSR 4 5 ns 19 CAS\Hold for CAS\ before RAS! Refresh TCHR 15 15 ns 19 Precharge ta CAS\ Acive TRPC a a ns 19 Wie Sa Up TWRP 10 10 ns 19 Write Hod TWRH 10 10 ns 19 Note 19 Eight or more CAS) before RAS\ cycles are necessary for proper operation of CAS\ before RAS\ refresh mode. ene nag, VIE Doi - DM IMR BO2-DM ORT ETT s ED444096C ser 4Mog x4 Fast Page O A i 6 ERdddnec Rey 2 fon ECoR naasEDI444096C | 4Megu4d Fasi Page DRAM A eee A PAA pry CAM pre mL api- NPT a 201 -Ipa WOR, OMRPOTE yor i Endaanesc Rey 2d son ECO nas,read TRF rag TRF | cr hh | Fay oar H rege rene rena TAPCO gel pa ogi-age INSGTS mime *% ven az-E eur raTe a RAS|-only Refresh Cycle Note 20 | rac ! reas or hh Rady err | rene Tere 4 | |g rere Tas row none 53 yi-mye ed mime Or eorrors ror = ay Note 20 Wi Dont Cae ED444096C 4Mog x4 Fast Page O A i 4 ERdddnec Rey 2 fon ECoR naasEDI444096C 4Megu4 Fast Page DRAM Hidden Refresh Cycic mae 1m K fo ot i L AX Agian Ww Dgl- Daa TIEITs Dal- pga VOI aQuTaIts Van cy 9 Endaanesc Rey 2d son ECO nas,rier o et lie mae EN | Ee agi-gge mgi-mge eoreoTa stage wy De@l-og4 mrETd Dog corFOTs ay ED444096C 4Mog x4 Fast Page O A i 10 ERdddnec Rey 2 fon ECoR naasEDI444096C | 4Megu4d Fasi Page DRAM LU en Part No. Speedins) Package No. Part No. Speedins) Package No. EDI444096C60BB 60 a EDI444096C60FB 60 347 EDI444096C7 0BB 70 a EDI444096C70FB 70 347 Note For commercial, Industrial or Mil-Temp-Ony qrade products use C,! or Mi Tespectively to replace 8 or Q in the suffix of the part number, eg. D|444096C 7088 (Compiart) becomes ED|444096C708) (Industrial). Package Description Package No. 317 P30 MAX, 2428 Pin Ceramic a r Thinpack Flatpack ARAAER AABAGE Weight = 1.2.gm j Tieta JC = 13 CW 4382 Ws Theta JA = 38 CM Max Ma TOTTI. cota ' O50 TYP. 016.004 O04 MAX. COPLANARITY 0g (LOWEST TO HIGHEST LEAD) MAX, (ogoton TTo0go) i fh ro mero | |. aoo.004 730 MAX. Package Na, M7 4 180 fe ws 24/28 Pin Ceramic Flatpack P T O17 REF MAX Meight = 1.2 gn 300.010 L S _ 4 Theta JC = 15 CW ; Titta JA= 38 TA | 006 + 902 tT ne Wawel Wunwelule O50 TYP. ell ores ona Electronic Designs Incorporated + One Research Drive + Westborough, MA O1581U SA + 50B-366-5151 + FAX 508-836-4850 + http /wwe. el ectronic-designs. com Eedroric Desigeir:. rsevestte ightoctengesrertica onswithoutrdtice CAGENn Gait i Endaanesc Rey 2d son ECO nas,