905X0205100 - TEXAS INSTRUMENTS

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Input Voltage (V)

Output Current (A)

VO = –3.3 V

VO = –5 V

VO = –12 V

VO = –15 V

G000

INH/UVLO

VOUTVIN

LMZ34002

VADJ

A_VOUT

GND

-V

OUT

STSEL

SET

OUT

VOUT_PT

CLK

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMZ34002

SNVS989C –JULY 2013–REVISED APRIL 2018

LMZ34002 15-W Negative Output Power Module With

4.5-V to 40-V Input in QFN Package

1 Features

1• Complete Integrated Power Solution Allows

Small Footprint, Low-Profile Design

• Wide Input Voltage Range from 4.5 V to 40 V

• Output Adjustable from –3 V to –17 V

• Supplies up to 2-A of Output Current

• 45-V Surge Capability

• Synchronizes to an External Clock

• Adjustable Slow-Start

• Programmable Undervoltage Lockout (UVLO)

• Output Overcurrent Protection

• Over Temperature Protection

• Operating Temperature Range: –40°C to +85°C

• Enhanced Thermal Performance: 14°C/W

• Meets EN55022 Class B Emissions

- Integrated Shielded Inductor

• For Design Help visit

http://www.ti.com/product/lmz34002

• Create a Custom Design Using the LMZ34002

With the WEBENCH®Power Designer

2 Applications

• Industrial and Motor Controls

• Automated Test Equipment

• Bipolar Amplifiers in Audio/Video

• High Density Power Systems

Safe Operating Current

3 Description

The LMZ34002 SIMPLE SWITCHER® power module

is an easy-to-use, negative output voltage power

module that combines a 15-W DC-DC converter with

a shielded inductor, and passives into a low profile,

QFN package. This total power solution allows as few

as five external components and eliminates the loop

compensation and magnetics part selection process.

The 9×11×2.8 mm QFN package is easy to solder

onto a printed circuit board and allows a compact

design with fewer components and excellent power

dissipation capability. The LMZ34002 offers the

flexibility and the feature-set of a discrete design and

is ideal for powering a wide range of ICs and analog

circuits requiring a negative output voltage. Advanced

packaging technology affords a robust and reliable

power solution compatible with standard QFN

mounting and testing techniques.

Simplified Application

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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This voltage rating is referenced to A_VOUT, not GND.

(3) See the temperature derating curves in the Typical Characteristics section for thermal information.

(4) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.

(5) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.

4 Specifications

4.1 Absolute Maximum Ratings(1)

over operating temperature range (unless otherwise noted) MIN MAX UNIT

Input Voltage

VIN –0.3 45 V

INH/UVLO –0.3 5(2) V

VADJ –0.3 3(2) V

SS –0.3 3(2) V

STSEL –0.3 3(2) V

RT –0.3 3.6(2) V

CLK –0.3 3.6(2) V

Output Voltage PH –0.6 45 V

PH 10ns Transient –2 45 V

VOUT –0.6 VIN(2) V

VDIFF (VOUT to exposed

thermal pad) ±200 mV

Source Current INH/UVLO 100 µA

Sink Current SS 200 µA

Operating Junction Temperature –40 105(3) °C

Storage Temperature –65 150 °C

Peak Reflow Case Temperature(4) 250(5) °C

Maximum Number of Reflows Allowed(4) 3(5)

Mechanical Shock Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted 1500 G

Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz 20

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIN Input Voltage 4.5 40 V

VOUT Output Voltage –3 –17 V

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics (SPRA953)

application report.

(2) The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with 1 oz.

copper and natural convection cooling. Additional airflow reduces θJA.

(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TTis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TBis

the temperature of the board 1mm from the device.

4.3 Thermal Information

THERMAL METRIC(1) LMZ34002

UNITRKG

41 PINS

θJA Junction-to-ambient thermal resistance(2) 14 °C/W

ψJT Junction-to-top characterization parameter(3) 3.3 °C/W

ψJB Junction-to-board characterization parameter(4) 6.8 °C/W

4.4 Package Specifications LMZ34002 UNIT

Weight 0.9 grams

Flammability Meets UL 94 V-O

MTBF Calculated reliability Per Bellcore TR-332, 50% stress, TA= 40°C, ground benign 31.7 MHrs

(1) This device can regulate VOUT down to 0 A, however the ripple may increase due to pulse-skipping at light loads. See Light-Load

Behavior for more information. See No-Load Operation when operating at 0 A.

(2) The maximum current is dependant on VIN and VOUT, see Figure 33.

(3) The sum of VIN + |VOUT| must not exceed 50 V.

(4) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal

adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.

(5) This product is not designed to endure a sustained (> 5 sec) over-current condition.

4.5 Electrical Characteristics

-40°C ≤TA≤+85°C, VIN = 12 V, VOUT = –5 V, IOUT = 2 A

CIN = 2 × 2.2 µF ceramic, COUT = 2 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOUT Output current Over input voltage and output voltage range 0(1) 2(2) A

VIN Input voltage range Over output current range 4.5 40(3) V

UVLO VIN Undervoltage lockout Rising only, RUVLO1 = 174 kΩ, RUVLO2 = 63.4 kΩ4.5 V

VOUT(adj) Output voltage adjust range Over output current range –3 –17(3) V

VOUT

Set-point voltage tolerance TA= 25°C, IOUT = 100 mA 2.0% (4)

Temperature variation –40°C ≤TA≤+85°C ±0.5% ±1%

Line regulation Over input voltage range ±0.1%

Load regulation From 100 mA to IOUT(max) ±0.4%

Total output voltage variation Includes set-point, line, load, and temperature variation 3% (4)

ηEfficiency

VIN = 24 V

VOUT = –12 V, IOUT = 1.0 A 85%

VOUT = –5.0 V, IOUT = 1.0 A 81%

VOUT = –3.3 V, IOUT = 1.0 A 77%

VIN = 12 V VOUT = –12 V, IOUT = 0.6 A 86%

VOUT = –5.0 V, IOUT = 1.0 A 81%

VOUT = –3.3 V, IOUT = 1.0 A 78%

Output voltage ripple 20 MHz bandwith, 100 mA ≤IOUT ≤IOUT(max) 1% VOUT

ILIM Current limit threshold 3 (5) A

Transient response 1.0 A/µs load step from 25 to 75%

IOUT(max)

Recovery time 500 µs

VOUT over/undershoot 80 mV

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Electrical Characteristics (continued)

-40°C ≤TA≤+85°C, VIN = 12 V, VOUT = –5 V, IOUT = 2 A

CIN = 2 × 2.2 µF ceramic, COUT = 2 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(6) If this pin is left open circuit, the device operates when input power is applied. An external level-shifter is required to interface with this

pin. See Output On/Off Inhibit (INH) for further guidance.

(7) The synchronization frequency is dependant on VIN and VOUT as shown in Switching Frequency. RRT must be either 0 Ωor 93.1kΩ.

(8) A minimum of 4.7 µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation.

Locate the capacitor close to the device. See Table 1 for more details.

(9) The amount of required capacitance must include at least 2 x 47 µF ceramic capacitor (or 4 x 22 µF). Locate the capacitance close to

the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 1 for

more details. See Inrush Current section when adding additional output capacitance.

VINH Inhibit threshold voltage INH with respect to A_VOUT 1.15 1.25 1.36 (6) V

IINH INH Input current VINH < 1.15 V –0.9 μA

VINH > 1.36 V –3.8 μA

II(stby) Input standby current INH pin to A_VOUT 1.3 4 µA

fSW Switching frequency RT pin to A_VOUT 700 800 900 kHz

fCLK Synchronization frequency RRT = 0 Ω700 (7) 900 (7) kHz

RRT = 93.1 kΩ400 (7) 600 (7) kHz

VCLK-H CLK High-Level Threshold With respect to A_VOUT 1.9 2.2 V

VCLK-L CLK Low-Level Threshold With respect to A_VOUT 0.5 0.7 V

DCLK CLK Duty cycle 25% 50% 75%

Thermal Shutdown Thermal shutdown 180 °C

Thermal shutdown hysteresis 15 °C

CIN External input capacitance Ceramic 4.7 (8) 10 µF

Non-ceramic 22

COUT External output capacitance 100(9) 430 (9) µF

VIN

VOUT

GND

VADJ

STSEL

LMZ34002

VREF Comp

Power

Stage

and

Control

Logic

Thermal Shutdown

Shutdown

Logic

OCP VIN

UVLO

OSC

w/PLL

A_VOUT

INH/UVLO

CLK

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5 Device Information

Functional Block Diagram

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Pin Functions

TERMINAL DESCRIPTION

NAME NO.

VIN 26 Input voltage. This pin supplies all power to the converter. Connect this pin to the input supply and connect

bypass capacitors between this pin and GND.

VOUT

Negative output voltage with respect to GND. Connect these pins to the output load and connect external

bypass capacitors between these pins and GND. Pad 40 should be connected to PCB VOUT planes using

multiple vias for good thermal performance.

GND

This is the return current path for the power stage of the device. These pins are connected to the internal

output inductor. Connect these pins to the load and to the bypass capacitors associated with VIN and

VOUT.

Phase switch node. Do not place any external component on these pins or tie them to a pin of another

function.

VOUT_PT 8 VOUT and A_VOUT Connection Point. Connect VOUT to A_VOUT at these pins as shown in the Layout

Considerations section. These pins are not connected to internal circuitry, and are not connected to one

other.

DNC

Do Not Connect. Do not connect these pins to GND, to another DNC pin, or to any other voltage. These pins

are connected to internal circuitry. Each pin must be soldered to an isolated pad.

A_VOUT

These pins are connected to the internal analog reference (A_VOUT) of the device. This node should be

treated as the negative voltage reference for the analog control circuitry. Pad 37 should be connected to the

PCB A_VOUT plane using multiple vias for good thermal performance. Not all pins are connected together

internally. All pins must be connected together externally with a copper plane or pour directly under the

module. Connect A_VOUT to VOUT at a single point (VOUT_PT; pins 8 & 9). See Layout

Recommendations.

RT 30 Switching frequency adjust pin. To operate at the recommended free-running frequency, connect this pin to

A_VOUT. Connecting a resistor between this pin and A_VOUT will reduce the switching frequency. See

Switching Frequency section.

CLK 31 Use this pin to synchronize to an external clock. If unused, isolate this pin from any other signal.

INH/UVLO 27 Inhibit and UVLO adjust pin. Use an external level-shifter device to ground this pin to control the INH

function. A resistor divider between this pin, A_VOUT, and VIN sets the UVLO voltage.

SS 28 Slow-start pin. Connecting an external capacitor between this pin and A_VOUT adjusts the output voltage

rise time.

STSEL 29 Slow-start select. Connect this pin to A_VOUT to enable the internal SS capacitor.

VADJ 36 Connecting a resistor between this pin and GND sets the output voltage. A dedicated GND sense line

connected at the load will improve regulation at the load. See Figure 48 in the Layout Considerations

section.

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RKG PACKAGE

(TOP VIEW)

0 0.05 0.1 0.15 0.2 0.25 0.3

Output Current (A)

Ambient Temperature (°C)

Natural Convection

VO = –12 V

G000

0 0.05 0.1 0.15 0.2 0.25

Output Current (A)

Ambient Temperature (°C)

Natural Convection

VO = –15 V

G000

0.5

1.5

2.5

0 0.2 0.4 0.6 0.8 1

Output Current (A)

Power Dissipation (W)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

0 0.1 0.2 0.3 0.4 0.5 0.6

Output Current (A)

Ambient Temperature (°C)

Natural Convection

VO = –5 V

G000

100

0 0.2 0.4 0.6 0.8 1

Output Current (A)

Efficiency (%)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

0 0.2 0.4 0.6 0.8 1

Output Current (A)

Output Voltage Ripple (mV)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

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6 Typical Characteristics (VIN = 5 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 1,Figure 2, and Figure 3. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 4,Figure 5, and

Figure 6.

Figure 1. Efficiency vs. Output Current Figure 2. Voltage Ripple vs. Output Current

Figure 3. Power Dissipation vs. Output Current

Figure 4. Safe Operating Area

Figure 5. Safe Operating Area Figure 6. Safe Operating Area

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Output Current (A)

Ambient Temperature (°C)

Natural Convection

VO = –12 V

G000

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Output Current (A)

Ambient Temperature (°C)

200 LFM

Natural Convection

VO = –15 V

G000

0 0.3 0.6 0.9 1.2 1.5 1.8

Output Current (A)

Power Dissipation (W)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –5 V

G000

100

0 0.3 0.6 0.9 1.2 1.5 1.8

Output Current (A)

Efficiency (%)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

0 0.3 0.6 0.9 1.2 1.5 1.8

Output Current (A)

Output Voltage Ripple (mV)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 800 kHz

VO = –3.3 V, fsw = 800 kHz

G000

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7 Typical Characteristics (VIN = 12 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 7,Figure 8, and Figure 9. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 10,Figure 11, and

Figure 12.

Figure 7. Efficiency vs. Output Current Figure 8. Voltage Ripple vs. Output Current

Figure 9. Power Dissipation vs. Output Current Figure 10. Safe Operating Area

Figure 11. Safe Operating Area Figure 12. Safe Operating Area

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –12 V

G000

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –15 V

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Power Dissipation (W)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –5 V

G000

100

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Efficiency (%)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Output Voltage Ripple (mV)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

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8 Typical Characteristics (VIN = 24 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 13,Figure 14, and Figure 15. At light load the output voltage ripple may increase due to pulse

skipping. See Light-Load Behavior for more information. Applies to Figure 14. The temperature derating curves represent the

conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits

apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 16,

Figure 17, and Figure 18.

Figure 13. Efficiency vs. Output Current Figure 14. Voltage Ripple vs. Output Current

Figure 15. Power Dissipation vs. Output Current Figure 16. Safe Operating Area

Figure 17. Safe Operating Area Figure 18. Safe Operating Area

0 0.3 0.6 0.9 1.2 1.5 1.8

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –12 V

G000

0 0.25 0.5 0.75 1 1.25

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –15 V

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Power Dissipation (W)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Ambient Temperature (°C)

400 LFM

200 LFM

Natural Convection

VO = –5 V

G000

100

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Efficiency (%)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

0 0.4 0.8 1.2 1.6 2

Output Current (A)

Output Voltage Ripple (mV)

VO = –15 V, fsw = 800 kHz

VO = –12 V, fsw = 800 kHz

VO = –5.0 V, fsw = 500 kHz

VO = –3.3 V, fsw = 500 kHz

G000

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9 Typical Characteristics (VIN = 36 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 19,Figure 20, and Figure 21. At light load the output voltage ripple may increase due to pulse

skipping. See Light-Load Behavior for more information. Applies to Figure 20. The temperature derating curves represent the

conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits

apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 22,

Figure 23, and Figure 24.

Figure 19. Efficiency vs. Output Current Figure 20. Voltage Ripple vs. Output Current

Figure 21. Power Dissipation vs. Output Current Figure 22. Safe Operating Area

Figure 23. Safe Operating Area Figure 24. Safe Operating Area

1000 10000 100000 300000

−40

−30

−20

−10

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−90

−60

−30

120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

−120

−90

−60

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120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

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−90

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Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

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−90

−60

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120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

−120

−90

−60

−30

120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

−120

−90

−60

−30

120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

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10 Typical Characteristics (Bode Plots)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter.

Figure 25. VIN= 5 V, VOUT= –5 V, IOUT= 0.6 A,

COUT= 4 x 22µF ceramic, fSW= 800 kHz Figure 26. VIN= 5 V, VOUT= –12 V, IOUT= 0.3 A,

COUT= 4 x 22 µF ceramic, fSW= 800 kHz

Figure 27. VIN= 12 V, VOUT= –5 V, IOUT= 1.6 A,

COUT= 4 x 22 µF ceramic, fSW= 800 kHz Figure 28. VIN= 12 V, VOUT= –12 V, IOUT= 0.8 A,

COUT= 4 x 22 µF ceramic, fSW= 800 kHz

Figure 29. VIN= 24 V, VOUT= –5 V, IOUT= 2.0 A,

COUT= 4 x 22 µF ceramic, fSW= 500 kHz Figure 30. VIN= 24 V, VOUT= –12 V, IOUT= 1.5 A,

COUT= 4 x 22 µF ceramic, fSW= 800 kHz

1000 10000 100000 300000

−40

−30

−20

−10

−120

−90

−60

−30

120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

1000 10000 100000 300000

−40

−30

−20

−10

−120

−90

−60

−30

120

Frequency (kHz)

Gain (dB)

Phase (°)

Gain

Phase

G000

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Typical Characteristics (Bode Plots) (continued)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter.

Figure 31. VIN= 36 V, VOUT= –5 V, IOUT= 2.0 A,

COUT= 4 x 22 µF ceramic, fSW= 500 kHz Figure 32. VIN= 36 V, VOUT= –12 V, IOUT= 1.8 A,

COUT= 4 x 22 µF ceramic, fSW= 800 kHz

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(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Maximum ESR @ 100 kHz, 25°C.

11 Capacitor Recommendations for the LMZ34002 Power Supply

11.1 Capacitor Technologies

11.1.1 Electrolytic, Polymer-Electrolytic Capacitors

When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.

Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature

is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,

power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide

adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures

are above 0°C.

11.1.2 Ceramic Capacitors

The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.

Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the

regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient

response of the output.

11.1.3 Tantalum, Polymer-Tantalum Capacitors

Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is

less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many

other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and

small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended

for power applications.

11.2 Input Capacitor

The LMZ34002 requires a minimum input capacitance of 4.7 μF of ceramic type. The voltage rating of input

capacitors must be greater than the maximum input voltage. The ripple current rating of the capacitor must be at

least 450 mArms. Table 1 includes a preferred list of capacitors by vendor.

11.3 Output Capacitor

The required output capacitance of the LMZ34002 can be comprised of either all ceramic capacitors, or a

combination of ceramic and bulk capacitors. The required output capacitance must include at least 2 × 47 µF of

ceramic type (or 4 × 22 µF). The voltage rating of output capacitors must be greater than the output voltage.

When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in Table 1

are required. Additional capacitance above the required minimum is determined by actual transient deviation

requirements. Table 1 includes a preferred list of capacitors by vendor.

Table 1. Recommended Input/Output Capacitors(1)

VENDOR SERIES PART NUMBER CAPACITOR CHARACTERISTICS

WORKING

VOLTAGE (V) CAPACITANCE

(µF) ESR (2)

(mΩ)

Murata X5R GRM31CR61H225KA88L 50 2.2 2

TDK X5R C3216X5R1H475K 50 4.7 2

Murata X5R GRM32ER61E226K 16 22 2

TDK X5R C3225X5R0J476K 6.3 47 2

Murata X5R GRM32ER60J476M 6.3 47 2

Sanyo POSCAP 16TQC68M 16 68 50

Sanyo POSCAP 6TPE100MI 6.3 100 25

Kemet T530 T530D227M006ATE006 6.3 220 6

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

5 10 15 20 25 30 35 40

Input Voltage (V)

Output Current (A)

VO = –3.3 V

VO = –5 V

VO = –12 V

VO = –15 V

G000

( )

OUT

SET

R 10 1 k

0.798

æ ö

= ´ - W

ç ÷

è ø

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12 Application Information

12.1 Adjusting the Output Voltage

The LMZ34002 is designed to provide output voltages from –3 V to –17 V. The output voltage is determined by

the value of RSET, which must be connected between the VADJ pin (Pin 36) and GND. Table 2 gives the

standard external RSET resistor for a number of common bus voltages.

Table 2. Standard RSET Resistor Values for Common Output Voltages

OUTPUT VOLTAGE VOUT (V) –3.3 –5.0 –8.0 –12.0 –15.0

RSET (kΩ)31.6 52.3 90.9 140 178

For other output voltages the value of RSET can be calculated using the following formula, or simply selected from

the range of values given in Table 3.

(1)

Table 3. Standard RSET Resistor Values

VOUT (V) RSET (kΩ) VOUT (V) RSET (kΩ) VOUT (V) RSET (kΩ)

–3.0 27.4 –7.5 84.5 –12.5 147

–3.3 31.6 –8.0 90.9 –13.0 154

–3.5 34.0 –8.5 97.6 –13.5 158

–4.0 40.2 –9.0 102 –14.0 165

–4.5 46.4 –9.5 110 –14.5 174

–5.0 52.3 –10.0 115 –15.0 178

–5.5 59.0 –10.5 121 –15.5 187

–6.0 64.9 –11.0 127 –16.0 191

–6.5 71.5 –11.5 133 –16.5 196

–7.0 78.7 –12.0 140 –17.0 205

12.2 Safe Operating Current

The amount of output current that can safely be delivered by the LMZ34002 depends on the input voltage and

the output voltage. Figure 33 shows the maximum output current for four standard output voltages over input

voltage.

Figure 33. Safe Operating Current

INH/UVLO

VOUT

VIN

LMZ34002

VADJ

A_VOUT

GND

OUT

–5 V @ 1.5 A

12 V

STSEL

4.7 F

25 V

52.3kΩ

47 F

6.3 V

VOUT_PT

174 kΩ

24.3 kΩ

47 F

6.3 V

INH/UVLO

VOUT

VIN

LMZ34002

VADJ

A_VOUT

GND

OUT

–12 V @ 1.25 A

24 V

STSEL

4.7 F

50 V

140 kΩ

47 F

16 V

VOUT_PT

174 kΩ

11.5 kΩ

47 F

16 V

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12.3 Application Schematics

Figure 34. Typical Schematic

VIN = 24 V, VOUT = –12 V

Figure 35. Typical Schematic

VIN = 12 V, VOUT = –5 V

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12.4 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ34002 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

INH/UVLO

VIN

UVLO1

UVLO2

A_VOUT

( ) ( )

= W

æ ö

-+ ´

ç ÷

è ø

UVLO2

ON 3

UVLO1

1.25

R k

V 1.25

0.9 10

( )

UVLO1 3

0.5

R k

2.9 10-

= W

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12.5 Input Voltage

The LMZ34002 operates over the input voltage range of 4.5 V to 40 V. The maximum input voltage is 40 V,

however, the sum of VIN + |VOUT| must not exceed 50 V.

See the Undervoltage Lockout (UVLO) Threshold section of this datasheet for more information.

12.6 Undervoltage Lockout (UVLO) Threshold

At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power

conversion. RUVLO1 and RUVLO2 set the turn-on threshold as shown in Figure 36. The UVLO threshold is not

present during the power-down sequence. Applications requiring a turn-off threshold must monitor the input

voltage with external circuitry and shut-down using the INH control (see Output On/Off Inhibit (INH)).

The VON UVLO threshold must be set to at least 4.5 V to insure proper start-up and reduce current surges on the

host input supply as the voltage rises. If possible, it is recommended to set the UVLO threshold to

appproximantely 80 to 85% of the minimum expected input voltage.

Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during

power-up when the input voltage is rising. Table 4 lists standard resistor values for RUVLO1 and RUVLO2 for

adjusting the VON UVLO threshold for several input voltages.

(2)

(3)

Figure 36. Adjustable VIN UVLO

Table 4. Standard Resistor Values to set VON UVLO Threshold

VON THRESHOLD (V) 4.5 5.0 6.5 8.0 9.0 10.0 15.0 20.0 30.0

RUVLO1 (kΩ)174 174 174 174 174 174 174 174 174

RUVLO2 (kΩ)63.4 56.2 40.2 31.6 27.4 24.3 15.8 11.5 7.50

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12.7 Power-Up Characteristics

When configured as shown in the application schematics, the LMZ34002 produces a regulated output voltage

following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate

that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input

source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is

recognized. Figure 37 shows the start-up waveforms for a LMZ34002, operating from a 12 V input and the output

voltage adjusted to –5 V. The waveform were measured with a 1.5-A constant current load.

Figure 37. Start-Up Sequence

12.8 Light-Load Behavior

The LMZ34002 is a non-synchronous converter. One of the characteristics of non-synchronous operation is that

as the output load current decreases, a point is reached where the energy delivered by a single switching pulse

is more than the load can absorb. This energy causes the output voltage to rise slightly. This rise in output

voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles until

the output voltages falls back to the set point. At very light loads or no load, many switching cycles are skipped.

The observed effect during this pulse skipping mode of operation is an increase in the peak to peak ripple

voltage, and a decrease in the ripple frequency. The amount of load current when pulse skipping begins is a

function of the input voltage, the output voltage, and the switching frequency.

12.9 No-Load Operation

When operating at no load or very light load and the input voltage is removed, the output voltage discharges very

slowly. If the input voltage is re-applied before the output voltage discharges, the slow-start circuit does not

activate and the amount of inrush current is extremely large and may cause an over-current condition. To avoid

this condition the output voltage must be allowed to discharge before re-applying the input voltage. Applying a

50-mA to 100-mA minimum load helps discharge the output voltage. Additionally, monitoring the input voltage

with a supervisor and shuting-down using the INH control (see Output On/Off Inhibit (INH)) activates the internal

slow-start circuit.

A_VOUT

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12.10 Switching Frequency

The recommended switching frequency of the LMZ34002 is 800 kHz. To operate at the recommended switching

frequency, connect the RT pin (Pin 30) to A_VOUT (at pin 32).

It is recommended to adjust the switching frequency in applications with both, higher input voltage (> 18V) and

lower output voltage (< –8V). For these applications, improved operating performance can be obtained by

decreasing the operating frequency to 500 kHz by adding a resistor, RRT of 93.1 kΩbetween the RT pin and

A_VOUT as shown in Figure 38.Figure 39 shows the recommended switching frequency over input voltage and

output voltage.

Figure 38. RRT Resistor Placement Figure 39. Recommended Switching Frequency

Table 5. Standard Resistor Values For Setting Switching Frequency

fSW (kHz) 500 800

RRT(kΩ)93.1 0 (short)

12.11 Synchronization (CLK)

An internal phase locked loop (PLL) allows synchronization from 700 kHz to 900 kHz for 800 kHz applications, or

400 kHz to 600 kHz for 500 kHz applications. See Figure 39 to determine switching frequency based on input

voltage and output voltage. To implement the synchronization feature, connect a square wave clock signal to the

RT/CLK pin with a duty cycle between 25% to 75%. The clock signal amplitude must transition lower than 0.5 V

and higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In

applications requiring CLK mode, configure the device as shown in Figure 40 (800 kHz) and Figure 41 (500kHz).

Before the external clock is present, the device works in RT mode where the switching frequency is set by the

RRT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK

pin is pulled above the RT/CLK high threshold (2.2 V), the device switches from RT mode to CLK mode and the

CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not

recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100

kHz first before returning to the switching frequency set by the RT resistor.

A_VOUTRT

93.1k

CLK

External Clock

400 kHz to 600 kHz 1 kΩ

470 pF

GND

3.3 V

BAV99

A_VOUT

CLK

External Clock

700 kHz to 900 kHz 1 kΩ

470 pF

GND

3.3 V

BAV99

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Synchronization (CLK) (continued)

Figure 40. CLK Configuration (800 kHz Typ) Figure 41. CLK Configuration (500 kHz Typ)

INH

Control

INH/UVLO

VIN

RUVLO1

RUVLO2

A_VOUT

VIN

GND

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12.12 Output On/Off Inhibit (INH)

The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold

voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator

stops switching and enters low quiescent current state.

The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.

If an application requires controlling the INH pin, an external level-shifter is required to interface with the pin

because in a positive-to-negative buck-boost supply, the INH pin is referenced to VOUT, not GND. Adding a

level-shifter (U1) as shown in Figure 42, allows the INH control to be refernced to GND. A recommended level-

shifter part # is DCX144EH-7 from Diodes Inc.

Pulling the input of U1 to GND applies a low voltage to the inhibit control pin and disables the output of the

supply, shown in Figure 43. Releasing the input of U1 enables the device, which executes a soft-start power-up

sequence, as shown in Figure 44. The device produces a regulated output voltage within 10 ms. The waveforms

were measured with a 1.5-A constant current load.

Figure 42. Typical Inhibit Control

Figure 43. Inhibit Turn-Off Figure 44. Inhibit Turn-On

STSEL A_VOUT

(Optional)

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12.13 Slow-Start Circuit (SS)

Connecting the STSEL pin (Pin 29) to A_VOUT while leaving SS pin (Pin 28) open, enables the internal SS

capacitor with a slow-start interval of approximately 10 ms. Adding additional capacitance between the SS pin

and A_VOUT increases the slow-start time. Figure 45 shows an additional SS capacitor connected to the SS pin

and the STSEL pin connected to A_VOUT. See Table 6 below for SS capacitor values and timing interval.

Figure 45. Slow-Start Capacitor (CSS) and STSEL Connection

Table 6. Slow-Start Capacitor Values and Slow-Start Time

CSS (nF) open 10 15 22

SS Time (ms) 10 15 17 20

(1) This amount of capacitance includes the required 100 µF of ceramic capacitance with additional bulk capacitance.

12.14 Inrush Current

During turn-on, as the LMZ34002 performs a slow-start sequence, an inrush current is induced as the output

capacitors charge up. The inrush current is in addition to the DC input current. The amount of inrush current

depends on the input voltage, output voltage and amount of output capacitance. Table 7 shows the typical inrush

current for the input voltage, output voltage and the amount of output capacitance. Increasing the slow-start

capacitor reduces the inrush current by slowing down the ramp of the output voltage. See Slow-Start Circuit (SS).

Table 7. Typical Inrush Current

Output Capacitance →100 µF ceramic 200 µF (1) 320 µF (1) 430 µF (1)

VIN (V) VOUT (V) Inrush Current (A)

–3.3 0.1 0.1 0.1 0.1

–5 0.1 0.2 0.2 0.3

–12 0.3 0.8 1.2 1.8

–15 0.4 1.3 2.5 3.6

–3.3 0.1 0.1 0.1 0.1

–5 0.1 0.1 0.1 0.2

–12 0.2 0.4 0.6 0.8

–15 0.3 0.5 0.9 1.3

–3.3 0.1 0.1 0.1 0.1

–5 0.1 0.1 0.2 0.2

–12 0.2 0.2 0.3 0.5

–15 0.3 0.3 0.5 0.7

36 –3.3 0.2 0.2 0.2 0.2

–5 0.2 0.2 0.2 0.2

–12 0.2 0.3 0.4 0.4

VOUTVIN

LMZ34002 -V

OUT

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12.15 Input to Output Coupling Capacitor

Adding an input to output coupling capacitor (CIO) across VIN to VOUT as shown in Figure 46 can help reduce

output voltage ripple and improve transient response. A typical value for CIO is 2.2 µF ceramic with a voltage

rating greater than the sum of VIN + |VOUT|.

Figure 46. Input to Output Coupling Capacitor

12.16 Overcurrent Protection

For protection against load faults, the LMZ34002 incorporates cycle-by-cycle current limiting. During an

overcurrent condition the output current is limited and the output voltage is reduced. If the output voltage drops

more than 25%, the switching frequency is lowered to reduce power dissipation within the device. When the

overcurrent condition is removed, the output voltage returns to the established voltage.

The LMZ34002 is not designed to endure a sustained short circuit condition. The use of an output fuse, voltage

supervisor circuit, or other overcurrent protection circuit is recommended.

12.17 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

180°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C

typically.

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12.18 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 47 through

Figure 50 show four layers of a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (VIN, VOUT, and GND) to minimize conduction loss and thermal

stress.

• Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.

• Locate additional output capacitors between the ceramic capacitor and the load.

• Place a dedicated A_VOUT copper area beneath the LMZ34002.

• Isolate the PH copper area from the GND copper area using the VOUT copper area.

• Connect the VOUT and A_VOUT copper areas at one point; at pins 8 & 9.

• Place RSET, RRT, and CSS as close as possible to their respective pins.

• Use multiple vias to connect the power planes to internal layers.

• Use a dedicated sense line to connect RSET to GND near the load for best regulation.

Figure 47. Typical Top-Layer Recommended Layout Figure 48. Typical GND-Layer Recommended Layout

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Layout Considerations (continued)

Figure 49. Typical VOUT-Layer Recommended Layout Figure 50. Typical Bottom-Layer Recommended Layout

12.19 EMI

The LMZ34002 complies with EN55022 Class B radiated emissions. Figure 51 shows a typical example of

radiated emissions plots for the LMZ34002. The graph includes the plot of the antenna in the horizontal and

vertical positions.

Figure 51. Radiated Emissions 19-V Input, -5-V Output, 2-A Load (EN55022 Class B)

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13 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (June 2017) to Revision C Page

• Added WEBENCH® design links for the LMZ34002.............................................................................................................. 1

• Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved

manufacturability .................................................................................................................................................................... 2

• Added Device Support section ............................................................................................................................................ 28

Changes from Revision A (September 2013) to Revision B Page

• Added peak reflow and maximum number of reflows information ........................................................................................ 2

Changes from Original (JULY 2013) to Revision A Page

• Changed incorrect RSET value for -5.5 VOUT in Table 3........................................................................................................ 15

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14 Device and Documentation Support

14.1 Device Support

14.1.1 Development Support

14.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ34002 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

14.2 Documentation Support

14.2.1 Related Documentation

For related documentation see the following:

Soldering Requirements for BQFN Packages (SLTA069)

14.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.5 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1

Q2 Q2

Q3 Q3Q4 Q4

Reel

Diameter

User Direction of Feed

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14.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

15.1 Tape and Reel Information

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width W1

(mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMZ34002RKGR B1QFN RKG 41 500 330.0 24.4 9.35 11.35 3.1 16.0 24.0 Q1

LMZ34002RKGT B1QFN RKG 41 250 330.0 24.4 9.35 11.35 3.1 16.0 24.0 Q1

TAPE AND REEL BOX DIMENSIONS

Width (mm)

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Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMZ34002RKGR B1QFN RKG 41 500 383.0 353.0 58.0

LMZ34002RKGT B1QFN RKG 41 250 383.0 353.0 58.0

PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2019

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMZ34002RKGR ACTIVE B1QFN RKG 41 500 RoHS Exempt

& Green CU NIPDAU Level-3-250C-168 HR -40 to 85 (54260, LMZ34002)

LMZ34002RKGT ACTIVE B1QFN RKG 41 250 RoHS Exempt

& Green CU NIPDAU Level-3-250C-168 HR -40 to 85 (54260, LMZ34002)

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2019

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMZ34002RKGT B1QFN RKG 41 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMZ34002RKGT B1QFN RKG 41 250 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2019

Pack Materials-Page 2

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