INTEGRATED CIRCUITS DATA Sil 74LV153 = = | Dual 4-input multiplexer Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook Philips Semiconductors PHILIPS Q 1998 Apr 28 PHILIPSPhilips Semiconductors Product specification Dual 4-input multiplexer 74LV153 FEATURES Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Voc = 2.7 V and Voc = 3.6 V Typical Vo_p (output ground bounce) < 0.8 V at Voc = 3.3 V, Tamb = 25C Typical Voyy (output Voy undershoot) > 2 V at Voc = 3.3 V, Tamb = 25C Non-inverting outputs Separate enable for each output Common select inputs Permits multiplexing from n lines to 1 line Enable line provided for cascading (n lines to 1 line) Output capability: standard loc category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; t= t}<2.5ns DESCRIPTION The 74LV153 is a low-voltage CMOS device that is pin and function compatible with 74HC/HCT153. The 74LV153 is a dual 4-input multiplexer which selects 2 bits of data from up to four sources selected by common data select inputs (So, S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH. The 74LV153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch, is determined by the logic levels applied to Sq and S,. The logic equations for the outputs are: 1Y=1E.(1 Io-Sy Sot F Sy Sot lo Sy Sot Ig.84 So) 2Y=2E. (2lp.S4 Sot2ly Sy Sot2lo.$4 Sot2l3.S, So) The 74LV153 can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay In, ly to nY C_ = 15 pF; 14 teHU/tPLH Sn to nY Veo =33V 14 ns nE to nY 10 Cc Input capacitance 3.5 pF Cpp Power dissipation capacitance per gate V| = GND to Vcc! 30 pF NOTE: 1. Cpp is used to determine the dynamic power dissipation (Pp in u.W) Pp = Cpp x Voc? x fi + (CL x Voc? x fo) where: f, = input frequency in MHz; C_ = output load capacitance in pF; fy = output frequency in MHz; Vcc = supply voltage in V; (CL x Voc? x fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL 40C to +125C 74LV153 N 74LV153 N SOT38-4 16-Pin Plastic SO 40C to +125C 74LV153 D 74LV153 D SOT109-1 16-Pin Plastic SSOP Type II 40C to +125C 74LV153 DB 74LV153 DB SOT338-1 16-Pin Plastic TSSOP Type | 40C to +125C 74LV153 PW 74LV153PW DH SOT403-1 1998 Apr 28 853-1921 19309Philips Semiconductors Product specification Dual 4-input multiplexer 74LV153 PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 14 SV00539 FUNCTIONAL DIAGRAM 1E [7 | M 76 | Voo s; [2 | p15 | 2 ts [3 | 14 | So Il [4 | 13 | 2lg wh [| 12 | 2le Ilo at] 2h 1Y [7 | 0 | 2lo GND [8 | El 2y SV00538 PIN DESCRIPTION PIN SYMBOL FUNCTION NUMBER 1,15 1E, 2E Output enable inputs (active LOW) 14,2 So, Sy Common data select inputs 6,5,4,3 Alp to Al3 Data inputs from source 1 7 1Y Multiplexer output from source 1 8 GND Ground (0 V) 9 2yY Multiplexer output from source 2 10, 11,12, 13 | 2lg to 2lg Data inputs from source 2 16 Voc Positive supply voltage LOGIC SYMBOL 6 5 3 10 4 12 13 Ilo th 1389 2lp = 2h lglg 14 So 2 Sy 1 Voc + 0.5V 20 mA tlox DC output diode current Vo < 0.5 or Vo > Voc + :0.5V 50 mA DC output source or sink current _ tlo standard outputs 0.5V PH I LI PS