ANALOG LC7M0S DEVICES ops 8-Bit ADC with Track/Hold AD7575 REV. B 1.1 Scope. This specification covers the detail requirements for an 8-bit microprocessor compatible analog-to-digital converter with a built-in track/hold function. The successive approximation technique is used to achieve a conversion time of 5ys, while the on-chip track/hold allows full-scale signals up to 50kHz to be digitized. The AD7575 operates with a single +5V supply, a + 1.23V bandgap reference and converts an input signal range of 0 to 2Vpgr. 1.2 Part Number. The complete part numbers per Table 1 of this specification are as follows: Device Part Number! -1 AD7575S(XY/883B -2 AD7575T(X)/883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-18 18-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vpp toAGND .. 20.1... ee 0.3V, +7V Vpp toDGND .. 0. ee ee 0.3V, +7V AGND toDGND ... 2... 2... 0 0.3V, Vpp Digital Input Voltage to DGND (Pins 1,2). .......0...2. 0... 0.0 0050007 0.3V, Vpp Digital Output Voltage to DGND (Pins 4, 6-8, 10-14)... 2 2. eee -0.3V, Vpp CLK Input Voltage (Pin 5) to DGND ............ 020.002 eee eee 0.3V, Vpp VREF toAGND .. 0... ee eee 0.3V to Vpp AINtoAGND ........0 2.2.0.0 eee ee ee 0.3V to Vpp Power Dissipation Upto +75C 2 eee 450mW Derates above +75C 20 ee 6mW/C Operating Temperature Range .. 2... 0. ee ee ee et 55C to + 125C Storage Temperature Range... .. 2.2.2 2 ee ee es 65C to + 150C Lead Temperature (Soldering 10sec) . 2... 2. ee ee ee + 300C 1.5 Thermal Characteristics. Thermal Resistance 0;c = 35C/W for Q-18 and E-20A Osa = 120C/W for Q-18 and E-20A ANALOG-TO-DIGITAL CONVERTERS 6-93AD7575 SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group | Group | Group Test Symbol| Device | Tinis-Tmax| 1 2,3 4 Test Condition! Units Resolution RES -1,2 8 This is the minimum resolu- Bits tion for which no missing codes are guaranteed. Total Unadjusted Error TUE -1 2 2 2 + LSB max -2 1 2 1 1 Relative Accuracy RA -1 1 1 1 + LSB max -2 0.5 1 0.5 0.5 Full-Scale Error -1,2 1 ! 1 + LSB max Offset Error -1,2 0.5 0.5 0.5 Measured with respect toan + LSB max ideal first code transition which occurs at 1/2LSB. Analog Input Voltage Range AIN ~1,2 0to2VReF Vv DC Input Impedance Zin -1,2 10 10 10 MO min Slew Rate Tracking -1,2 0.386 V/s max Signal Noise Ratio -1,2 45 Vin = 2.46V p-p @ 10kHz dBmin Reference Input Current IpeF -1,2 500 500 500 vA max Digital Input Low Voltage Vir -1,2 0.8 0.8 0.8 CS,RD,CLK Vmax Digital Input High Voltage Vin -1,2 | 24 2.4 2.4 CS,RD, CLK Vmin Digital Input Current Uw ~1,2 10 1 10 CS, RD, Vin =Oor Vpn; +A max Vop =5.2V Digital Input Capacitance Cin 1,2 10 . cs,RD pF max Digital Input Low Current Un -1,2 800 800 800 CLK; Vi, = 0V pA max Digital Input High Current Thy ~1,2 800 800 800 CLK, Vin = Vop pA max Digital Output Low Voltage Voi -1,2 0.4 0.4 0.4 BUSY, DBO to DB7 Vmax Isink = 1.6mA; Vop =4,75V Digital Output High Voltage Vou ~1,2 4.0 4.0 4.0 BUSY, DBO to DB7 Vmin TsourcE = 40pA; Vop =4.75V Floating State Leakage Current Tout ~1,2 10 10 10 DBO to DB7 +pA max Vout = 000 Vpp; Vpp = 5.2V Floating State Output Capacitance | Cour | 1,2 10 DB0 to DB7 pF max Conversion Time with External Clock tconv | 1,2 5 5 5 fork = 4MHz ps Conversion Time with External Clock @ + 25C toonv | -1,2 5 5 R ded Clock ps min 15 15 Components: R = 100kN, ps max C = 100pF CS toRD Setup Time, t, twscs | -1,2 | 0 ns min RD to BUSY Propagation Delay, t2 twepp | 1,2 120 ns max Data Access Time after RD, t;? toar a 120 ns max RD Pulse Width, t, tro -1,2 120 ns min CS toRD Hold Time, ts tens | -1,2 | 0 ns min Data Access Time after BUSY, t.?_ | tpas -1,2 100 ns max Data Hold Time, tj? ton -1,2 10 ns min 100 ms max BUSY toCS Delay, tg tecp -1,2 0 ns min Power Supply Current Ipp ~1,2 7 7 7 Vop = 5.2V mA max Power Supply Rejection -1,2 0.25 0.25 0.25 + LSB max NOTES "Vpn = + 5V; (unless otherwise stated) Vage = +1.23V;AGND = DGND = OV; fc.x = 4MHz external. All input contro! jtisnalsare ipecified with t, = ty = 20ns (10% to 90% of + $V) and timed from a voltage level of 1.6V. 2ty and ts are measured with the load circuits of Figure | and defined as the time required for an output to cross 0. BV t02.4V. 3+; is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. 6-94 ANALOG-TO-DIGITAL CONVERTERS REV.AD7579 +5V +5V 3kn 3ks2 OBN DBN OBN DBN 3th 100pF 100pF 3kQh sal 4 b. High-Z to Vou 10pF 10pF ob I OGNO a. High-Z to Vow a. Vow to High-Z b. Vo, to High-Z Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test 3.2.1 Functional Block Diagram and Terminal Assignments. CLOCK OSCILLATOR i $ CONTROL LoGic LATCH AND THREE STATE TPUT DRIVER: ou Ss Q Package (Cerdip) 1 2 3 BUSY | 4 CLK [LS pe? (sei (6 | DBE | ? oa5| 8 OGND [9 lsaa wn AD7575 TOP VIEW (Not to Scale) 18] Voo 7} Vaer 16] AIN [1s] AGND [14] DBo (LSB) [13] DB. [12] 082 11] DBs [19] Bs wi 2 @2@@ 2 3 2 1 20 19 BUSY 18 AIN CLK 17 AGND AD7575 DB? (MSB) TOP VIEW 16 DBO (LSB) OBB 15 DB1 D65 14 DB2 OGND wo REV. B 10 1 12 9 238 o DB3 ANALOG-TO-DIGITAL CONVERTERS 6-95 ERTERS ANALOG-TO-DIGITAL CONVAD7575 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (81). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). R2 4.7% R3 R2 2s ~~ 10022 47k ro cs Veo [18] W080 + 5V (SEE ANN _ BELOW! Lf 2 | Ro Vaer 7 }-~w0 +12 R4 nt [3] 1p ain [16 10022 220k > b ne [4 | BUSY AGND [15 [-] oO c x 3 o Ft ca 1000F I ne [6 087 pei [13] nc ~ ne (7 ] pss DB2 a Nc NC | 3 | O85 DB3}11 | NC T{2]ocn ea] ne ALL RESISTORS ARE 1/4W. CS AND AD ARE TAKEN HIGH FOR 0.6ms 0.7ms APPROXIMATELY AND ARE THEN BROUGHT LOW. THIS IS ACHIEVED AS FOLLOWS: NOTE CS/RD PULSE MAY BE GENERATED EXTERNALLY. +5V R6 100ks2 TO CS & AD { | ONE INVERTER PER \ ROW OF AD7575s ' ro CS & AD c2 I 0.01hF 5414 6-96 ANALOG-TO-DIGITAL CONVERTERS REV. BAD7575 REV. B 5.0 Timing and Control of the AD7575. The two logic inputs on the AD7575, CS and RD, control both the starting of conversion and the reading of data from the part. A conversion is initiated by bringing both these control inputs LOW. Two interface options then exist for reading the output data from the AD7575. These are the Slow Memory Interface and ROM Interface and their operation is outlined below. It should be noted that the TP pin of the AD7575 must be hardwired HIGH to ensure correct operation of the part. This pin is used in testing the device and should not be used as a feedthrough pin in double-sided printed circuit boards. s | fo = ty ~> Its RD J T 1 1 ~ tb ~~ 1 t tcony et BUSY \ \ te pe wed ty bee st wits te t HIGH IMPEDANCE x New x HIGH IMPEDANCE DATA BUS a OLD DATA DATA Bus Figure 3. Slow Memory interface Timing Diagram 5.1 Slow Memory Interface. The first interface option is intended for use with microprocessors which can be forced into a WAIT STATE for at least 5s (such as the 8085A). The microprocessor starts a conversion and is halted until the result of the conversion is read from the converter. Conversion is initiated by executing a memory READ to the AD7575 address bringing CS and RD LOW. BUSY subsequently goes LOW (forcing the microprocessor READY input LOW) placing the processor into a WAIT state. The input signal, which had been tracked by the analog input, is held on the third falling clock edge of the input clock after CS and RD have gone LOW. The AD7575 then performs a conversion on this acquired input signal value. When the conversion is complete (BUSY goes HIGH), the processor completes the memory READ and acquires the newly-converted data. The timing diagram for this interface is shown in Figure 3. The major advantage of this interface is that it allows the microprocessor to start conversion, WAIT and then READ data with a single READ instruction. The fast conversion time of the AD7575 ensures that the microprocessor is not placed in a WAIT state for an excessive amount of time. Faster versions of many processors, including the 8085A-2, test the condition of the READY input very soon after the start of an instruction cycle. Therefore, BUSY of the AD7575 must go LOW very early in the cycle for the READY input to be effective in forcing the processor into a WAIT state. When using the 8085A-2, the processor SO status signal provides the earliest possible indication that a READ operation is about to occur. Hence, SO (which is LOW for a READ cycle) provides the READ signal to the AD7575. The connection diagram for the AD7575 to 8085A-2 Slow-Memory interface is shown in Figure 4. AB-ANS ADDRESS 8US 5 J L +5V Love 80BSA-2 ADDRESS x DEcovE 97 S AD7575* so RD BUSY ADDRESS ALE-) LATCH Zz DBO-0B7 ADO-AD? OATA BUS 45 READY jd *LINEAR CIRCUITRY OMITTED FOR CLARITY $O=0 FOR READ CYCLES Figure 4. AD7575 to 8085A-2 Slow Memory Interface ANALOG-TO-DIGITAL CONVERTERS 6-97 ANALOG-TO-DIGITAL CONVERTERS aAD7579 5.2 ROM Interface. The alternative interface option on the AD7575 avoids placing the microprocessor into a WAIT state. In this interface, a conversion is started with the first READ instruction and the second READ instruction accesses the data and starts a second conversion. The timing diagram for this interface is shown in Figure 5. It is possible to avoid starting another conversion on the second READ (see below). a ae 1 ets et beet ! tl i $5 RD pou ty \ te | | ' I ~ ty 1 t ' ' ___+} 1 ! meee ee we ee eK BUSY ' I s | ra eee eee _ ie. an py oT TTT ~y mel ty jee th eed ty pe | | ATA HIGH ow . HIGH DATA WAPEDANCE BUS DATA HIGH IMPEDANCE BUS DATA IMPEDANCE BUS Lid Figure 5. ROM Interface Timing Diagram Conversion is initiated by executing a memory READ instruction to the AD7575 address causing CS and RD to go LOW. Data is also obtained from the AD7575 during this instruction. This is old data and may be disregarded if not required. BUSY goes LOW indicating that conversion is in progress and returns HIGH when conversion is complete. Once again the input signal is held on the third falling edge of the input clock after CS and RD have gone LOW. The BUSY line may be used to generate an interrupt to the microprocessor or monitored to indicate that conversion is complete. The processor then reads the newly-converted data. Alternatively, the delay between the convert start (first READ instruction) and the data READ (second READ instruction) must be at least as great as the AD7575 conversion time. For the AD7575 to operate correctly in the ROM interface mode CS and RD should not go LOW before BUSY returns HIGH. Normally, the second READ instruction starts another conversion as well as accessing the output data. However, if CS and RD are brought LOW within one external clock period of BUSY going HIGH then a second conversion does not occur. Figures 6 and 7 show connection diagrams for interfacing the AD7575 in the ROM Interface mode. Figure 6 shows the AD7575 interface to the 6502/6809 microprocessors while the connection diagram for interfacing to the Z-80 is shown in Figure 7. ADDRESS AG-AI5 BUS s J L +SV 6502/6809 Lt. ADDRESS aiw en OECODE ts AD7575* 2 or E RD ba0-087 00-07 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 6. AD7575 to 6502/6809 ROM interface 6-98 ANALOG-TO-DIGITAL CONVERTERS ADDRESS BUS z-80 J L +5V Lot. ___ ADDRESS MREG EN DECODE =PI1TS pn gage ab RD DB? [_ Deo De7 DATA BUS S DEO *LINEAR CIRCUITRY OMITTED FOR GLARITY Figure 7. AD7575 to 2-80 ROM Interface REV. BAD7575 As a result of its very fast interface timing the AD7575 can also be interfaced to the DSP processor, the TMS32010. The AD7575 will interface (within specifications) to the TMS32010 running at up to 18MHz but will typically work over the full clock frequency range of the TMS32010. Figure 8 shows the connection diagram for this interface. The AD7575 is mapped at a port address. Conversion is initiated using an IN A, PA instruction where PA is the decoded port address for the AD7575. The conversion result is obtained from the part using a second IN A, PA instruction and the resultant data is placed in the TMS32010 accumulator. PaA2 ADDRESS BUS 6 PAO 7MS32010 L aN Lv. ADORESS MEN EN DECODE io___4 cs AD7575* DEN RO Da? [| DBO o70 DATA BUS DO *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 8. AD7575 to TMS32010 ROM Interface In many applications it is important that the signal sampling occurs at exactly equal intervals to minimize errors due to sampling uncertainty or jitter. The interfaces outlined previously require that for sampling at equi-distant intervals the user must count clock cycles or match software delays. This is especially difficult in interrupt driven systems where uncertainty in interrupt servicing delays would require that the AD7575 would have to have priority interrupt status and even then redundant software delays may be necessary to equalize loop delays. This problem can be overcome by using a real time clock to control the starting of conversion. This can be derived from the clock source used to drive the AD7575 CLK pin. Since the sampling instant occurs three clock cycles after CS and RD go LOW then the input signal sampling intervals are equi-distant. The resultant data is placed in a FIFO latch which can be accessed by the microprocessor at its own rate whenever it requires the data. This ensures that data is not READ from the AD7575 during a conversion. If a data READ is performed during a conversion, valid data from the previous conversion will be accessed but the conversion in progress may be interfered with and an incorrect result is likely. If CS and RD go LOW within 20ns of a falling clock edge the AD7575 may or may not see that falling edge as the first of the three falling clock edges to the sampling instant. In this case the sampling instant could vary by one clock period. If it is important to know the exact sampling instant, CS and RD should not go LOW within 20ns of a falling clock edge. ANALOG-TO-DIGITAL CONVERTERS 6-99 ANALOG-TO-DIGITAL CONVERTERS =