M24C01-WDW3T - STMicroelectronics

1/20May 2000

M24C16, M24C08

M24C04, M24C02, M24C01

16/8/4/2/1 Kbit Serial I²C Bus EEPROM

■Two Wire I2C Serial Interface

Supports 400 kHz Protocol

■Single Supply Voltage:

– 4.5V to 5.5V for M24Cxx

– 2.5V to 5.5V for M24Cxx-W

– 1.8V to 3.6V for M24Cxx-R

■Hardware Write Control

■BYTE and PAG E WRIT E (u p to 16 Byte s)

■RANDOM and SEQ UEN TIAL READ Modes

■Self-Tim ed P ro g ra m ming Cyc le

■Automatic Addres s Incrementing

■Enhanced E SD/La tch-Up Behavior

■1 Million Erase/Write Cycles (minimum)

■40 Year Data Retention (minimum)

DESCRIPTION

These I2C-compatible electrically erasable

programmable memory (EEPROM) devices are

organized as 2048/1024/512/256/128 x 8 bit

(M24C16, M24C08, M24C04, M24C02, M24C01),

and operate with a power supply down to 2.5 V (for

the -W version of each device), and down to 1.8 V

(for the -R version of each device).

The M24C16, M24C08, M24C04, M24C02,

M24C01 are available in Plastic Dual-in-Line,

Plastic Small Outline and Thin Shrink Small

Outline packages. The M24C16-R is also

available in a chip-scale (SBGA) pac kage.

Figure 1. Logic Diagram

AI02033

E0-E2 SDA

VCC

M24Cxx

SCL

VSS

Table 1. Signal Names

E0, E1, E2 Chip Enable Inputs

SDA Serial Data/Address Input/

Output

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

PSDIP8 (BN)

0.25 mm frame SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

SBGA

SBGA5 (EA)

75 mil width

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

2/20

Figure 2A. DIP Connections

Note: 1. NC = Not Connected

Figure 2B. SO Connections

Note: 1. NC = Not Connected

Figure 2C. Standard-TSSOP Connections

Note: 1. NC = Not Connected

SDAVSS SCL

VCC

/ E2

AI02034D

M24Cxx

/ E2/ E2/ E2NC / E1

/ E1/ E1/ NCNC / E0

/ E0/ NC/ NCNC /1Kb

/2Kb/4Kb/8Kb16Kb

AI02035D

5SDAVSS SCL

VCC

/ E2

M24Cxx

/ E2/ E2/ E2NC / E1

/ E1/ E1/ NCNC / E0

/ E0/ NC/ NCNC /1Kb

/2Kb/4Kb/8Kb16Kb

AI02036D

5SDAVSS SCL

VCC

/ E2

M24Cxx

/ E2/ E2/ E2NC / E1

/ E1/ E1/ NCNC / E0

/ E0/ NC/ NCNC /1Kb

/2Kb/4Kb/8Kb16Kb

Figure 2D. SBGA Connections (top view, marki ng side, with balls on the underside)

AI02796E

SCL VSS

SDA

WC VCC

M24C16

Ball "1"

3/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

These memory devices are compatible with the

I2C memory standard. This is a two wire serial

interface that uses a bi-directional data bus and

serial clock. The memory carries a built-in 4-bit

unique Device Type Identifier code (1010) in

accordance with the I2C bus definition.

The memory behaves as a slave device in the I2C

protocol, with all memory operat ions sy nchroni zed

by the serial clock. Read and Write operations are

initiated by a START condition, gene rated by the

bus master. The START condition is foll owed by a

Device Select Code and RW bit (as described in

Table 3) , terminated by an acknowledge bit.

When writing data to the memory, the memory

inserts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master ackn owledg es t he receipt of the data b yte

in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and

after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until the VCC voltage has reached

the POR threshold value, and all operations are

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

Table 2. Absolute Maximum Ratings 1

Note: 1. Except for the rating “O perating Temperature Range”, str esses a bove th ose listed in the Table “Absolute M aximum Rati ngs” m ay

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions

above thos e indicated in t he Op erating sect i ons of this specification is not i m plied. Ex posure to A bsol ut e M aximum R ating condi -

tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2 . MIL -S T D-88 3C, 3015. 7 (100 p F, 1500 Ω)

Symbol Parameter Value Unit

TAAmbient Operating Temperature -40 to 125 °C

TSTG Storage

Temperature -65 to 150 °C

TLEAD Lead Temperature

during Soldering

PSDIP8: 10 sec

SO8: 40 sec

TSSOP8: 40 sec

SBGA5: t.b.c.

260

215

t.b.c.

°C

VIO Input or Output range -0.6 to 6.5 V

VCC Supply Voltage -0.3 to 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model2)4000 V

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

4/20

disabled – the device will not respond to any

command. In the same way, when VCC drops from

the operating voltage, below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable and

valid VCC must be applied before applying any

logic signal.

SIGNAL DESCRIPTION

Serial Clock (SCL)

The SCL input pin is used to s trobe all data in and

out of the mem ory. In applications where this line

is used by slaves to synchronize the bus to a

slower clock, the master must have an open drain

output, and a pull-up resistor must be connected

from the SC L line to VCC. ( F igure 3 indicate s how

the value of the pull-up resistor can be calculated) .

In most applications, though, this method of

synchronization is not employed , and so the pull-

up resistor is not necessary, provided that the

master has a push-pull (rather than open drain)

output.

Serial Data (S DA)

The SDA pin is bi-directional, and is used to

transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other

open drain or open collect or signals on the bus. A

pull up resistor must be connected from the SDA

bus to VCC. (Figure 3 indicates how the value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs ar e used t o set the v alue

that is to be looked for on the t hree least significant

bits (b3, b2, b1) of the 7-bit device select code (but

see the description of memory addressing, on

page 6, for more details). These inputs may be

driven dynamically or tied to VCC or VSS to

establish the device selec t code (but note that the

VIL and VIH levels for the inputs are CMOS

compatible, not TTL compatible ).

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

CONDITION SDA

INPUT SDA

CHANGE

AI00792

STOP

CONDITION

123 789

MSB ACK

START

CONDITION

SCL 123 789

MSB ACK

STOP

CONDITION

5/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Write Control (WC)

The hardware Write Con trol pin (WC) is useful for

protecting the entire contents of the mem ory from

inadvertent erase/write. The Write Control signal is

used to enable (WC=VIL) or disable (WC=VIH)

write instructions to the entire memory area. When

unconnected, the WC input is internally read as

VIL, and write operations are allow ed.

When WC=1, Device Select and Address bytes

are acknowledged, Data bytes are not

acknowledged.

Please see the Application Note

AN404

for a more

detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol.

This is summarized in Figure 4, and is compared

with other seria l bu s prot ocols in Application Not e

AN1001

. Any device that sends dat a on to the bus

is defined to be a transmitter, and any device that

reads the data to be a receiver. The device that

controls the dat a t ransfe r is k nown as the master,

and the other as the slave. A data transfer can only

be initiated b y the m aster, which wi ll also provide

the serial clock for synchronization. The memory

device is always a slave device in all

communication.

Start Condition

START is identified by a high to low transition of

the SDA lin e whi le the clock, SCL, i s s table i n t he

high state. A START condition must precede any

data transfer command. The memory device

continuously monitors (except during a

programming cycle) the SDA and SCL lines for a

START condition, and wi ll not respond unless one

is given.

Stop Condition

STOP is identified by a low to high transition of the

SDA lin e wh ile th e clock SCL is s table in the h igh

state. A STOP condition terminates

communication between the memory device and

the bus mast er. A STOP condition at the end of a

Read command, after (and only after) a NoAck,

forces the memory device into its standby state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a

successful byte transfer. The bus transmitter,

whether it be master or slave, releases the SDA

bus af ter sending eight bits of data. During the 9th

Table 3. Device Select Code 1

No te : 1 . The most signific ant bit, b7, is sent first.

2. E0, E 1 and E2 are com par ed against the respective external pins o n the memory dev i ce.

3. A10, A9 a nd A8 represent hi gh sign i ficant bits of the address .

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

M24C01 Select Code 1010E2E1E0RW

M24C02 Select Code 1010E2E1E0RW

M24C04 Select Code 1010E2E1A8RW

M24C08 Select Code 1010E2A9A8RW

M24C16 Select Code 1010A10A9A8RW

Table 4. Operating Modes

No te: 1 . X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

Random Address Read 0X1

START, Device Select, RW = ‘0’, Address

1 X reSTART, Device Select, RW = ‘1’

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = ‘0’

Page Write 0 VIL ≤ 16 START, Device Select, RW = ‘0’

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

6/20

Figu re 5. Wri t e Mode Se qu e nces with W C =1 (data writ e inhibi ted)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

DATA IN 3

AI02803B

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK NO ACK

R/W

ACK ACK NO ACK NO ACK

R/W

NO ACK NO ACK

clock pulse period , the receiver pulls the SDA bus

low to acknowledge the receipt of the eight data

bits.

Data Input

During data input, the memory dev ice samples the

SDA bus signal on the rising edge of the clock,

SCL. For correct device operation, the SDA signal

must be stable during the clock low-to-high

transition, and the data must change

only

when

the SCL line is lo w .

Memory Addressing

To start communication between the bus master

and the slave memory, the master must initiate a

START condition. Following this, the master sends

the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the

7-bit Device Select Code, and the 1-bit Read/Write

Designator (RW). The Device Select Code is

further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,

E1 , E0) .

To address the memory array, the 4-bit Device

Type Identifier is 1010b.

Up to eight memory devices can be c onnect ed on

a single I 2C bus. Eac h one is given a uniq ue 3-bit

code on its Chip E nable input s. When the Device

Select Code is received, the memory only

responds if the Chip Enable Code (shown in Tabl e

3) is the same as the pattern applied to its Chip

Enable pins.

Those device s with larger memory capacities (the

M24C16, M24C08 and M24C04) need more

address bits. E0 is not available for use on devices

that need to use address line A8; E1 is not

available for devices that need to use address line

A9, and E2 is not available for devices that need to

use address line A10 (see Figure 2A to Figure 2D

and Table 3 for details). Using the E0, E1 and E2

inputs pins, up to eight M24C02 (or M24C01) , four

M24C04, two M24C08 or one M24C16 device can

be connected to one I2C bus. I n each case, and in

the hybrid cases, this gives a total memory

7/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Figu re 6. Wri t e Mode Se qu e nces with W C =0 (data writ e enab led)

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

DATA IN 3

AI02804

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

capacity of 16 Kbits, 2 KBytes (except where

M24C01 devices ar e used).

The 8th b it is the R W bit. This is set to ‘1’ for read

and ‘0’ for write operations. If a match occurs on

the Device Select Code, the corresponding

memory gives an acknowledgment on the SDA

bus during the 9th bit time. If the memory does not

match the Device Select Code, it deselects itself

from t he bus, and goes into stand-by mode.

There are two modes both for read and write.

These are summarized in Table 4 and described

later. A communication between the master and

the slave is ended with a STOP cond ition.

Write Operations

Following a ST ART con dition t he ma ster sen ds a

Device Select Code with the R W bit se t to ’0’, as

shown in Table 4. The memory acknowledges this ,

and waits for an address byte. The memory

responds to the address byte with an acknowledge

bit, and th en waits for the data byte.

Writing to the memory may be inhibited if the WC

input pin is taken high. Any write command with

WC=1 (during a period of time from the START

condition until the end of the address byte) will not

modify the memory contents, and the

accompanying data bytes will

not

acknowledg ed (as shown in Fig ure 5).

Byte Write

In the Byte Write mode, after the Device Select

Code and the address, the master sends one data

byte. If the addressed location is write protected by

the WC pin, the memory replies wi th a NoAck, and

the location is not modif ied. If, instead, the WC pin

has been held at 0, as shown in Figure 6, the

memory replies with an Ack. The master

terminates the transfer by generating a STOP

condition.

Page Write

The Page Write m ode allows up to 16 by tes to be

written in a single write cycle, provided that they

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

8/20

A STOP condition at any other time does not

trigger the internal write cycle.

During the internal write cycle, the SDA input is

disabled internally, and the device does not

respond to any requests.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory

disconnects itself from the bus, and copies the

data from its interna l latches to the memory cells.

Th e maxi mum write tim e (tw) is shown in Table 6B,

but the typical time is shorter. To make use of t his,

an Ack polling sequence can be used by the

master.

are all located in the same ’row’ in the memory:

that is the most significant memory address bits

are the same. If more bytes are sent than will fit up

to the end of the row, a condition known as ‘roll-

over’ occurs. Data starts to become overwritten, or

otherwise al t ered.

The master sends from one up to 16 bytes of data,

each of wh ich is acknowledged by the memory if

the WC pin is low. If the WC pin is high, the

contents of the addressed memory location are

not modif ied, and each dat a byte i s followed by a

NoAck. Af ter each by te i s transferred, t he i ntern al

byte address counter (the 4 least significant bits

only) is incremented. The trans fer is terminated by

the master generating a STO P condition.

When the master generates a STOP condition

immediat ely after the Ack bi t (in t he “10th bit” time

slot), either at the end of a byte write or a page

write, the internal m emo ry write cycle is triggered.

Figu re 7. Wri t e C yc le Pol l in g Fl owchart using A C K

WRITE Cycle

in Progress

AI01847

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

Proceed

WRITE Operation Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by M24xxx

9/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Read Operation s

Read operations are performed independently of

the stat e of the WC pin.

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 8.

Then,

without

sending a STOP condition, the

master sends another START condition, and

repeats the Device Select Code, with the RW bit

set to ‘1’. The memory acknowledges this, and

outputs the contents of the addressed byte. The

maste r must

not

acknowledge the byte output, and

terminates t he transfer wi th a STOP condit ion.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write is in progress.

– Step 1: the master issues a START condition

followed by a Device Select Code (the first byte

of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the

master goes back to Step 1. If the memory has

terminated the internal write cycle, it responds

with an Ac k, indicat ing that the memory is ready

to receive the second part of the next instruction

(the first byte of this instruction having been sent

during Step 1).

Figure 8. Read Mode S equences

No te : 1 . The s even most si gnificant bit s of the D evice Select Code of a Ra ndom Read (in the 1st and 3rd bytes) must be identic al .

START

DEV SEL * BYTE ADDR

START

DEV SEL DATA OUT 1

AI01942

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

10/20

Table 5A. DC Characteristics

(TA = 0 to 70 °C, or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 t o 5.5 V )

(TA = 0 to 70 °C, or –40 to 85 °C; VCC = 1.8 to 3.6 V)

Not e: 1. This is preliminary data.

Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current

(SCL, SDA) 0V

≤ VIN ≤ VCC ± 2 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current

VCC=5V, fc=400kHz (rise/fall time < 30ns) 2mA

-W series: VCC =2.5 V, fc=400kHz (rise/fall time < 30ns) 1mA

-R series: VCC =1.8 V, fc=400kHz (rise/fall time < 30ns) 0.81mA

ICC1 Supply Current

(Stand-by)

VIN = VSS or VCC , VCC = 5 V 1 µA

-W series: VIN = VSS or VCC , VCC = 2.5 V 0.5 µA

-R series: VIN = VSS or VCC , VCC = 1.8 V 0.11µA

VIL Input Low Voltage

(E0, E1, E2, SCL, SDA) – 0.3 0.3 VCC V

VIH Input High Volta ge

(E0, E1, E2, SCL, SDA) 0.7VCC VCC+1 V

VIL Input Low Voltage (WC) – 0.3 0.5 V

VIH Input High Voltage (WC) 0.7VCC VCC+1 V

VOL Output Low

Voltage

IOL = 3 mA, VCC = 5 V 0.4 V

-W series: IOL = 2.1 mA, VCC = 2.5 V 0.4 V

-R series: IOL = 0.7 mA, VCC = 1.8 V 0.21V

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read mode, following a START

condition, the master sends a Device Select Code

with the RW bit set to ‘1’. The memory

acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The master

terminates the transfer with a STOP condition, as

shown in Figure 8,

without

acknowledging the byte

output.

Sequenti al R ead

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master

does

acknowledg e the data by te output in

this case, and the memory continues to output the

next byte in sequence. To term inate the stream of

bytes, the master must

not

acknowledge the last

byte output, and

must

generate a STOP condition.

The output data comes from consecutive

addresses, with the internal address counter

automatical ly i ncremen ted af ter each byt e out put.

After the last memory address, the address

counter ‘rolls-over’ and the memory continues to

output data from memory address 00h.

Acknowledge in Read Mode

In all read modes, the memory waits, after each

byte read, for an acknowledgment during the 9th

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its stand-by state.

11/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Table 5B. DC Characteristics 1

(TA = –40 to 125 °C; VCC = 4.5 to 5.5 V)

Not e: 1. This is preliminary data.

Table 6A. AC Characteristics

No te : 1 . For a r eSTART condi ti on, or fo l l owing a w ri te cycle.

2. Sam p l ed only, n ot 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. Thi s i s prel imina ry d ata.

Symbol Parameter Test Condition Min. Max. Unit

ILI Input Leakage Current (SCL, SDA) 0V

≤ VIN ≤ VCC ± 2 µA

ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC=5V, fc=400kHz (rise/fall

time < 30ns) 3mA

CC1 Supply Current (Stand-by) VIN = VSS or VCC , VCC = 5 V 5 µA

VIL Input Low Voltage (E0, E1, E2, SCL, SDA) – 0.3 0.3 VCC V

VIH Input High Voltage (E0, E1, E2, SCL, SDA) 0.7VCC VCC+1 V

VIL Input Low Voltage (WC) – 0.3 0.5 V

VIH Input High Voltage (WC) 0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V

Symbol Alt. Parameter

M24C16, M24C08, M24C04, M24C02, M24C01

Unit

VCC=4.5 to 5.5 V

TA=0 to 70°C or

–40 to 85°C

VCC=2.5 to 5.5 V

TA=0 to 70°C or

–40 to 85°C

VCC=1.8 to 3.6 V

TA=0 to 70°C or

–40 to 85°C4

Min Max Min Max Min Max

tCH1CH2 tRClock Rise Time 300 300 300 ns

tCL1CL2 tFClock Fall Time 300 300 300 ns

tDH1DH2 2tRSDA Rise Time 20 300 20 300 20 300 ns

tDL1DL2 2tFSDA Fall Time 20 300 20 300 20 300 ns

tCHDX 1tSU:STA Clock High to Input Transition 600 600 600 ns

tCHCL tHIGH Clock Pulse Width High 600 600 600 ns

tDLCL tHD:STA Input Low to Clock Low (START) 600 600 600 ns

tCLDX tHD:DAT Clock Low to Input Transition 0 0 0 µs

tCLCH tLOW Clock Pulse Width Low 1.3 1.3 1.3 µs

tDXCX tSU:DAT Input Transition to Clock

Transition 100 100 100 ns

tCHDH tSU:STO Clock High to Input High (STOP) 600 600 600 ns

tDHDL tBUF Input High to Input Low (Bus

Free) 1.3 1.3 1.3 µs

tCLQV 3tAA Clock Low to Data Out Valid 200 900 200 900 200 900 ns

tCLQX tDH Data Out Hold Time After Clock

Low 200 200 200 ns

fCfSCL Clock Frequency 400 400 400 kHz

tWtWR Write Time 5 10 10 ms

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

12/20

Table 6B. AC Characteristics 4

No te : 1 . For a r eSTART condi ti on, or fo l l owing a w ri te cycle.

2. Sam p l ed only, n ot 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. Thi s i s prel imina ry d ata.

Symbol Alt. Parameter

M24C16, M24C08, M24C04, M24C02, M24C01

Unit

VCC=4.5 to 5.5 V; TA=–40 to 125°C

Min Max

tCH1CH2 tRClock Rise Time 300 ns

tCL1CL2 tFClock Fall Time 300 ns

tDH1DH2 2tRSDA Rise Time 20 300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tCHDX 1tSU:STA Clock High to Input Transition 600 ns

tCHCL tHIGH Clock Pulse Width High 600 ns

tDLCL tHD:STA Input Low to Clock Low (START) 600 ns

tCLDX tHD:DAT Clock Low to Input Transition 0 µs

tCLCH tLOW Clock Pulse Width Low 1.3 µs

tDXCX tSU:DAT Input Transition to Clock Transition 100 ns

tCHDH tSU:STO Clock High to Input High (STOP) 600 ns

tDHDL tBUF Input High to Input Low (Bus Free) 1.3 µs

tCLQV 3tAA Clock Low to Data Out Valid 200 900 ns

tCLQX tDH Data Out Hold Time After Clock Low 200 ns

fCfSCL Clock Frequency 400 kHz

tWtWR Write Time 10 ms

Table 7. AC Measu rem ent Conditions

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.2VCC to 0.8VCC

Input and Output Timing

Reference Voltages 0.3VCC to 0.7VCC

Figure 9. AC Testing Input Output Waveforms

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Table 8. Input Parameters 1 (TA = 25 °C, f = 4 00 kHz)

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

CIN Input Capacitance (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance VIN < 0.5 V 5 70 kΩ

ZWCH WC Input Impedance VIN > 0.7VCC 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 1 00 ns

13/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

SDA IN

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLCH

tDXCX

tCLDX

SDA

INPUT SDA

CHANGE

tCHDH

tDHDL

STOP &

BUS FREE

DATA VALID

tCLQV tCLQX

DATA OUTPUT

tCHDH

STOP

CONDITION

tCHDX

START

CONDITION

WRITE CYCLE

AI00795B

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

14/20

Table 9. Ordering Information Scheme

No te : 1 . Temperature range 1 avai l a ble only o n reque st .

2. SBGA5 p ackage av ai l able only for t he “M24C 16-R EA 6 T”

Example: M24C08 –WDW1T

Memory Capacity Option

16 16 Kbit (2048 x 8) T Tape and Reel Packing

08 8 Kbit (1024 x 8)

04 4 Kbit (512 x 8) Temperature Range

02 2 Kbit (256 x 8) 110 °C to 70 °C

01 1 Kbit (128 x 8) 6 –40 °C to 85 °C

3 –40 °C to 125 °C

Operating Voltage Package

blank 4.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)

W 2.5 V to 5.5 V MN SO8 (150 mil width)

R1.8 V to 3.6 V DW TSSOP8 (169 mil width)

EA SBGA52

ORDERING INFORMATION

Devices are shipped from the factory with the

memory c ontent set at all ‘1’s (FFh).

The notation used for the device number is as

shown in Table 9. For a list of available options

(speed, package, etc.) or for f urt her information on

any aspect of this device, please contact your

nearest S T Sales Of fice.

15/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Figure 11. PSDIP8 (BN)

No te : 1. D rawing is not t o scale.

PSDIP-a

E1 E

Table 10. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lea d frame

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0.49 – 0.019 –

A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014

D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –

E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –

eA 7.80 – 0.307 –

eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

16/20

Table 11. SO8 - 8 lead Plasti c Small Outline, 150 m ils body wi dth

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

Figure 12. SO8 narrow (MN)

No te : 1. D rawing is not t o scale.

SO-a

LA1 α

h x 45˚

17/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Table 12. TSSOP8 - 8 lead Thin Shrink Small Outline

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043

A1 0.05 0.15 0.002 0.006

A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 2.90 3.10 0.114 0.122

E 6.25 6.50 0.246 0.256

E1 4.30 4.50 0.169 0.177

e 0.65 – – 0.026 – –

L 0.50 0.70 0.020 0.028

α0° 8° 0° 8°

N8 8

CP 0.08 0.003

Figure 13. TSSOP8 (DW)

No te : 1. D rawing is not t o scale.

TSSOP

N/2

DIE

EE1

A2A

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

18/20

Figure 14. SBGA5 (EA) – Underside view (ball side)

No te : 1. D rawing is not t o scale.

SBGA-00

E1 E

BALL "1"

Table 13. SBGA5 - 5 ball Shell Ball Grid Array

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.430 0.380 0.480 0.017 0.015 0.019

A1 0.180 0.150 0.210 0.007 0.006 0.008

D 1.900 1.870 1.930 0.075 0.074 0.076

D1 1.190 1.160 1.220 0.047 0.046 0.048

E 1.750 1.720 1.780 0.069 0.068 0.070

E1 1.070 1.040 1.100 0.042 0.041 0.043

e 0.800 0.770 0.830 0.031 0.030 0.033

ball diameter 0.350 0.320 0.380 0.014 0.013 0.015

N5 5

19/20

M24C16, M 24C 08, M24C04, M24C02, M24C01

Table 14. R evision History

Date Description of Revision

10-Dec-1999 TSSOP8 Turned-Die package removed (p 2 and order information)

Lead temperature added for TSSOP8 in table 2

18-Apr-2000 Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13

05-May-2000 Extra labelling to Fig-2D

M24C16, M 24C08, M2 4C04, M24C 02, M 24C01

20/20

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