Lattice =s Semiconductor au Corporation ispLSP 2032VE 3.3V In-System Programmable High Density SuperFAST PLD * SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 1/0 Pins, Two Dedicated inputs 32 Registers High Speed Global Interconnect Wide input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional/JEDEC Upward Compatible with ispLS1 2032V Devices * 3.3V LOW VOLTAGE 2032 ARCHITECTURE - Interfaces With Standard 5V TTL Devices 80 mA Typical Active Current Fuse Map Compatible with 5V ispLSI 2032 and 2032E * HIGH PERFORMANCE ECMOS* TECHNOLOGY fmax = 200 MHz Maximum Operating Frequency tpd = 4.0 ns Propagation Delay Electricalty Erasable and Reprogrammabie Non-Volatile 100% Tested at Time of Manufacture * IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability Using Bou Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus In e Capability, Allowing Easy Impleme' ion of Wired-OR or Bus Arbitration Logig ( Increased Manufacturing Yield Market and Improved Produ: * 100% IEEE 1149.1 BOUNDARY * THE EASE OF USE AN PLDs WITH THE DEN Optimized Global Routing Poo! Provides Global Interconnectivity * ispEXPERT ~ LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms Global Routing Pog ) Description SI 2032VE is a High Density Programmable Device that can be used in both 3.3V and 5V ems. The device contains 32 Registers, 32 Universal pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLS! 2032VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The isoLS! 2032VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032VE device is the Generic Logic Block (GLB). The GLBs are labeled AO, At .. A7 (see Figure 1). There are a total of eight GLBs in the ispLS|] 2032VE device. Each GLB is made up of four macroceils. Each GLB has 18 inputs, a programmabie AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. Ali of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 1998 Lattice Semiconductor Cora, All brand or sroduct names are trademarks or registerec trademarks of their respective holders, The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124. U.S.4. October 1998 Tel. (503) 681-0118; 1-B800-LATTICE; FAX (503) 681-3037; htto:/wwww.latticesemi.com5 TM ena Latti C e zaaee Semiconductor auanen Corporation Specifications ispLS!I 2032VE Functional Block Diagram Figure 1. ispLS! 2032VE Functional Block Diagram GOEO a 7 bee = La! = input Bus B [Te maneed Output Routing Poot (ORP} N TMS'NC SCAN connected to an i/O pin. Each | programmed to be a comb| | tout or bi- eprie signal levels he Sutput drivers can output can be pro- or slow output slew rate are TTL compatible vol source 4 mA or Si Eight GLBs, 32 1/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1}. The outputs of the eight GLBs are connected to a set of 32 universal |/O cells by the ORP. EachispLsi 2032VE device contains one Megabiock. The GRP has as its inputs the outputs from all ofthe GLBs and ail of the inputs from the bi-directional I/O cells. Ail of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Global Routing Pod! (GRP) arc Logic : Blocks (GLBs) Clocks in the ispLSI 2032VE device are selected using the dedicated clock pins. Three dedicated clock pins (YO. Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLS! 2032VE are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels. whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. Th:s output configuration is controlled by a pro- grammable fuse. When this fuse is erased (JEDEC 1}, the output is configured as a totem-pole output. When this fuse is programmed (JEDEC O), the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is se- lectable through the ispEXPERT software tools. 72Lattice Specifications ispLSI 2032VE 22 Corporation External Timing Parameters Over Recommended Operating Conditions a) i PARAMETER | sun | # DESCRIPTION aia AK ac lax UNITS | tpd1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass | 40) - | 5.0) ns tpd2 A 2 | Data Propagation Delay ~|55: 175; ns - fmax A 3 | Clock Frequency with Internal Feedback 200) - i 180) -- | MHz | fmax (Ext.) ~- | 4 | Clock Frequency with External Feedback (3';) 154] : 125] ~ | MHz | fmax (Tog,) - | 5 | Clock Frequency, Max. Toggle 250] --| 200) | MHz . tsut _ 6 | GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 30) ns : teo! A | 7 | GLB Reg. Clock to Output Delay, ORP Bypass )} 40) ns | thi - | 8 | GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 | - | ns tsu2 | 9 | GLB Reg. Setup Time before Clock 5 | .o0; | ns tco2 | 10} GLB Reg. Clock to Output Delay 40: 145] ns the | 11) GLB Reg. Hold Time after Clock 00% OO} -- | as tr A 12] Ext. Reset Pin to Output Delay 5.01 | 7.0 ns tr - | 13] Ext. Reset Pulse Duration 35 | --| 40} | ns tptoeen B 14| input to Output Enable |7.0} -- 710.0] ns tptoedis Cc 15| input to Output Disable | 7.0) -- /10.0} ns tgoeen B 16| Global OE Output Enable ~- | 35) - | 5.0 ns tgoedis Cc 17 | Global OE Output Disable ~|35) - | 50 ns, twh -- | 18] External Synchronous Clock Pu ti igh 20| | 25) ns: tw - | 19] External Synchronous CI . Low 20| | 25) ~| ms | . Unless noted otherwise, all parameters use the G 0 _ ORP and YO clock. Table 2-0030A/2032VE 1 2. Refer to Timing Model in this data sheet for further 3. Standard 16-bit counter using GRP feedba 4, Reference Switching Test Conditions sectid 73Specifications ispLS! 2032VE Over Recommended Operating Conditions ! 4 | PARAMETER conp. # DESCRIPTION oa MAX a Tae UNITS tpd1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass _ 75 | -- ) 10.01 ns tpd2 A 2 | Data Propagation Delay Too! 130) ns | | fmax A i3 Clock Frequency with internal Feedback* 187, --~ | 14 | MHz fax (Ext.) -- | 4 | Clock Frequency with External Feedback (2-=5,) 100 gp | 77.0) | MHz fax (Tog.} 5 | Clock Frequency, Max. Toggle 167 - | 125 | MHz tsut -- ; 6 | GLB Reg. Setup Time before Clock, 4 PT Bypass : B ) 55) | ns tco1 A | 7 | GLB Reg. Clock to Output Delay, ORP Bypass 65 | ons | thi |! 8 | GLB Reg. Hold Time after Clock, 4 PT Bypass ; 0.90 ns tsu2 _ 9 | GLB Reg. Setup Time before Clock w= | FS - ns ! teo2 -~ +10] GLB Reg. Clock to Output Delay 55) 65 ons : the ~~ | 11] GLB Reg. Hold Time after Clock 100!} -- | ns trt A | 12| Ext. Reset Pin to Output Delay _ ~|100) 1185) ns trw4 - | 13] Ext. Reset Pulse Duration 50! | 65) ns tptoeen B 14 | Input to Output Enable 7 ~ )12.0) -- (145 ns; totoedis Cc 16 | input to Output Disable | Ta20] -- b145) ns : tgoeen B | 16| Global OE Output Enable 601 --1701 ns ! tgoedis C | 17] Global OE Output Disabil. 7 |60]; !7.0) ns | twh -~ | 18| External Synchronow@C oO aUrsaigayration, High 3.0 co ns | twi | 19] External Synchronous tamigk Pld ip Duration, Low _ BO) | Lo | ns | 1. Unless noted otherwise, all parameters us GIFXOR path, ORP and YO clock. Table 2-0030B/2032VE 2. Refer to Timing Model in this data sh 3. Standard 16-bit counter using GRP. 4. Reference Switching Test Conditj 74