High Performance
Narrow-Band Transceiver IC
Data Sheet ADF7021
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Low power, narrow-band transceiver
Frequency bands using dual VCO
80 MHz to 650 MHz
862 MHz to 950 MHz
Modulation schemes
2FSK, 3FSK, 4FSK, MSK
Spectral shaping
Gaussian and raised cosine filtering
Data rates supported
0.05 kbps to 32.8 kbps
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 63 steps
Automatic PA ramp control
Receiver sensitivity
−130 dBm at 100 bps, 2FSK
−122 dBm at 1 kbps, 2FSK
−113 dBm at 25 kbps, raised cosine 2FSK
Patent pending, on-chip image rejection calibration
On-chip VCO and fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC)
Digital received signal strength indication (RSSI)
Integrated Tx/Rx switch
0.1 μA leakage current in power-down mode
APPLICATIONS
Narrow-band standards
ETSI EN 300 220, FCC Part 15, FCC Part 90, FCC Part 95,
ARIB STD-T67
Low cost, wireless data transfer
Remote control/security systems
Wireless metering
Private mobile radio
Wireless medical telemetry service (WMTS)
Keyless entry
Home automation
Process and building control
Pagers
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
05876-001
Tx/Rx
CONTROL
AFC
CONTROL
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
RSSI/
7-BIT ADC
GAIN
DIV R
RFOUT
LNA
PFD
CP
OSC1 OSC2
N/N + 1
DIV P
TEMP
SENSOR
OSC CLK
DIV
CLKOUT
TEST MUX
VCOIN CPOUT
LDO(1:4)
MUXOUTRSET CREG(1:4)
R
LNA
R
FIN
RFINB
CE
TxRxCLK
SWD
TxRxDATA
SERIAL
PORT
SLE
SDATA
SREAD
SCLK
IF FILTER
Σ-∆
MODULATOR
PA RAMP
L1 L2
LOG AMP
MUX
2FSK
3FSK
4FSK
MOD CONTROL
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
AGC
CONTROL
MUX
÷1/÷2
VCO1
VCO2
÷2
ADF7021 Data Sheet
Rev. D | Page 2 of 62
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
RF and PLL Specifications ........................................................... 5
Transmission Specifications ........................................................ 6
Receiver Specifications ................................................................ 8
Digital Specifications ................................................................. 10
General Specifications ............................................................... 11
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings .......................................................... 15
ESD Caution ................................................................................ 15
Pin Configuration and Function Descriptions ........................... 16
Typical Performance Characteristics ........................................... 18
Frequency Synthesizer ................................................................... 22
Reference Input ........................................................................... 22
MUXOUT .................................................................................... 23
Voltage Controlled Oscillator (VCO) ...................................... 24
Choosing Channels for Best System Performance ................. 25
Transmitter ...................................................................................... 26
RF Output Stage .......................................................................... 26
Modulation Schemes .................................................................. 26
Spectral Shaping ......................................................................... 28
Modulation and Filtering Options ........................................... 29
Transmit Latency ........................................................................ 29
Test Pattern Generator ............................................................... 29
Receiver Section .............................................................................. 30
RF Front End ............................................................................... 30
IF Filter ........................................................................................ 30
RSSI/AGC .................................................................................... 31
Demodulation, Detection, and CDR ....................................... 32
Receiver Setup ............................................................................. 34
Demodulator Considerations ................................................... 36
AFC Operation ........................................................................... 36
Automatic Sync Word Detection (SWD) ................................ 37
Applications Information .............................................................. 38
IF Filter Bandwidth Calibration ............................................... 38
LNA/PA Matching ...................................................................... 38
Image Rejection Calibration ..................................................... 39
Packet Structure and Coding .................................................... 41
Applications Circuit ................................................................... 44
Serial Interface ................................................................................ 45
Readback Format ........................................................................ 45
Interfacing to Microcontroller/DSP ........................................ 46
Register 0—N Register ............................................................... 47
Register 1—VCO/Oscillator Register ...................................... 47
Register 2—Transmit Modulation Register ............................ 49
Register 3—Transmit/Receive Clock Register ........................ 50
Register 4—Demodulator Setup Register ............................... 51
Register 5—IF Filter Setup Register ......................................... 52
Register 6—IF Fine Cal Setup Register ................................... 53
Register 7—Readback Setup Register ...................................... 54
Register 8—Power-Down Test Register .................................. 55
Register 9—AGC Register ......................................................... 56
Register 10—AFC Register ....................................................... 57
Register 11—Sync Word Detect Register ................................ 58
Register 12—SWD/Threshold Setup Register ........................ 58
Register 13—3FSK/4FSK Demod Register ............................. 59
Register 14—Test DAC Register ............................................... 60
Register 15—Test Mode Register ............................................. 61
Outline Dimensions ....................................................................... 62
Ordering Guide .......................................................................... 62
Data Sheet ADF7021
Rev. D | Page 3 of 62
REVISION HISTORY
9/2016—Rev. C to Rev. D
Changes to General Description Section ....................................... 4
Changes to Interfacing to Microcontroller/DSP Section and
Figure 58 ........................................................................................... 46
10/2014—Rev. B to Rev. C
Changes to Table 8 .......................................................................... 16
Change to Figure 36 ........................................................................ 24
Change to IF Filter Fine Calibration Overview Section ............ 30
Change to Post Demodulator Filter Setup Section ..................... 34
Change to Battery Voltage/ADCIN/Temperature Sensor
Readback Section ............................................................................ 45
Change to Register 4—Demodulator Setup Register Section ... 51
Change to Register 7—Readback Setup Register Section .......... 54
Change to Register 10—AFC Register Section ........................... 57
4/2013—Rev. A to Rev. B
Changes to Figure 10 ...................................................................... 16
Updated Outline Dimensions ........................................................ 62
Changes to Ordering Guide ........................................................... 62
9/2007—Rev. 0 to Rev. A
Change to UART/SPI Mode Section ............................................ 14
Changes to Figure 10 ...................................................................... 16
Change to Table 8 ............................................................................ 16
Changes to Figure 12 ...................................................................... 18
Change to Internal Inductor VCO Section .................................. 24
Changes to Figure 40 ...................................................................... 26
Changes to Figure 47 ...................................................................... 32
Change to Table 19 .......................................................................... 34
Changes to Figure 56 ...................................................................... 44
Change to SPI Mode Section ......................................................... 46
Changes to Figure 59 ...................................................................... 46
Changes to Figure 60 ...................................................................... 46
Change to Register 3—Transmit/Receive Clock
Register Section ............................................................................... 50
Change to Register 4—Demodulator Setup Register Section ......... 51
Change to Register 7—Readback Setup Register ........................ 54
Change to Register 13—3FSK/4FSK Demod Register Heading .... 59
3/2007—Revision 0: Initial Version
ADF7021 Data Sheet
Rev. D | Page 4 of 62
GENERAL DESCRIPTION
The ADF7021 is a high performance, low power, highly integrated
2FSK/3FSK/4FSK transceiver. It is designed to operate in the
narrowband, license-free ISM bands, and in the licensed bands
with frequency ranges of 80 MHz to 650 MHz and 862 MHz to
950 MHz. The device has both Gaussian and raised cosine transmit
data filtering options to improve spectral efficiency for narrow-
band applications. It is suitable for circuit applications targeted
at European ETSI EN 300 220, the Japanese ARIB STD-T67, the
Chinese short range device regulations, and the North American
FCC Part 15, Part 90, and Part 95 regulatory standards. A complete
transceiver can be built using a small number of external discrete
components, making the ADF7021 very suitable for price
sensitive and area sensitive applications.
The range of on-chip FSK modulation and data filtering options
allows users greater flexibility in their choice of modulation
schemes while meeting tight spectral efficiency requirements.
The ADF7021 also supports protocols that dynamically switch
between 2FSK/3FSK/4FSK to maximize communication range
and data throughput.
The transmit section contains dual voltage controlled oscillators
(VCOs) and a low noise fractional-N PLL with an output resolution
of <1 ppm. The ADF7021 has a VCO using an internal LC tank
(431 MHz to 475 MHz, 862 MHz to 950 MHz) and a VCO using
an external inductor as part of its tank circuit (80 MHz to
650 MHz). The dual VCO design allows dual-band operation
where the user can transmit and/or receive at any frequency
supported by the internal inductor VCO and can also transmit
and/or receive at a particular frequency band supported by the
external inductor VCO.
The frequency agile PLL allows the ADF7021 to be used in
frequency hopping spread spectrum (FHSS) systems. Both
VCOs operate at twice the fundamental frequency to reduce
spurious emissions and frequency pulling problems.
The transmitter output power is programmable in 63 steps from
−16 dBm to +13 dBm, and has an automatic power ramp control to
prevent spectral splatter and help meet regulatory standards.
The transceiver RF frequency and modulation are programmable
using a simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.
A low IF architecture is used in the receiver (100 kHz), which
minimizes power consumption and the external component
count, yet avoids dc offset and flicker noise at low frequencies. The
IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and
25 kHz. The ADF7021 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency
control (AFC) loop with programmable pull-in range that allows
the PLL to track out the frequency error in the incoming signal.
The receiver achieves an image rejection performance of 56 dB
using a patent-pending IR calibration scheme that does not
require the use of an external RF source.
An on-chip ADC provides readback of the integrated temperature
sensor, external analog input, battery voltage, and RSSI signal,
which provides savings on an ADC in some applications. The
temperature sensor is accurate to ±10°C over the full operating
temperature range of −40°C to +85°C. This accuracy can be
improved by performing a 1-point calibration at room
temperature and storing the result in memory.
Data Sheet ADF7021
Rev. D | Page 5 of 62
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, T A = 25°C. All
measurements are performed with the E VA L -ADF7021DB evaluation boards using the PN9 data sequence, unless otherwise noted.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS See Table 9 for required VCO_BIAS and
VCO_ADJUST settings
Frequency Ranges (Direct Output)
160
650
MHz
External inductor VCO
862 950 MHz Internal inductor VCO
Frequency Ranges (RF Divide-by-2 Mode) 80 325 MHz External inductor VCO, RF divide-by-2 enabled
431 475 MHz Internal inductor VCO, RF divide-by-2 enabled
Phase Frequency Detector (PFD) Frequency1 RF/256 26/30 MHz Crystal reference/external reference
PHASE-LOCKED LOOP (PLL)
VCO Gain2
868 MHz, Internal Inductor VCO 58 MHz/V VCO_ADJUST = 0, VCO_BIAS = 8
434 MHz, Internal Inductor VCO 29 MHz/V VCO_ADJUST = 0, VCO_BIAS = 8
426 MHz, External Inductor VCO 27 MHz/V VCO_ADJUST = 0, VCO_BIAS = 3
160 MHz, External Inductor VCO 6 MHz/V VCO_ADJUST = 0, VCO_BIAS = 2
Phase Noise (In-Band)
868 MHz, Internal Inductor VCO −97 dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
433 MHz, Internal Inductor VCO
−103
dBc/Hz
10 kHz offset, PA = 10 dBm, V
DD
= 3.0 V,
PFD = 19.68 MHz, VCO_BIAS = 8
426 MHz, External Inductor VCO −95 dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V,
PFD = 9.84 MHz, VCO_BIAS = 3
Phase Noise (Out-of-Band) −124 dBc/Hz 1 MHz offset, fRF = 433 MHz, PA = 10 dBm,
VDD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8
Normalized In-Band Phase Noise Floor3 −203 dBc/Hz
PLL Settling 40 µs Measured for a 10 MHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, loop
bandwidth (LBW) = 100 kHz
REFERENCE INPUT
Crystal Reference4 3.625 26 MHz
External Oscillator4, 5 3.625 30 MHz
Crystal Start-Up Time6
XTAL Bias = 20 µA
0.930
ms
10 MHz XTAL, 33 pF load capacitors, V
DD
= 3.0 V
XTAL Bias = 35 µA 0.438 ms 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
Input Level for External Oscillator7
OSC1 0.8 V p-p Clipped sine wave
OSC2 CMOS levels V
ADC PARAMETERS
INL ±0.4 LSB VDD = 2.3 V to 3.6 V, TA = 25°C
DNL ±0.4 LSB VDD = 2.3 V to 3.6 V, TA = 25°C
1 The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value.
2 VCO gain measured at a VCO tuning voltage of 1 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this
variation.
3 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the PA output: −203 + 10 log(fPFD) + 20 logN.
4 Guaranteed by design. Sample tested to ensure compliance.
5 A TCXO, VCXO, or OCXO can be used as an external oscillator.
6 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
7 Refer to the Reference Input section for details on using an external oscillator.
ADF7021 Data Sheet
Rev. D | Page 6 of 62
TRANSMISSION SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DATA RATE
2FSK, 3FSK 0.05 251 kbps IF_BW = 25 kHz
4FSK 0.05 32.82 kbps IF_BW = 25 kHz
MODULATION
Frequency Deviation (fDEV)3 0.056 28.26 kHz PFD = 3.625 MHz
0.306 156 kHz PFD = 20 MHz
Deviation Frequency Resolution 56 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Raised Cosine Filter Alpha 0.5/0.7 Programmable
TRANSMIT POWER
Maximum Transmit Power4 +13 dBm VDD = 3.0 V, TA = 25°C
Transmit Power Variation vs.
Temperature
±1
dB
−40°C to +85°C
Transmit Power Variation vs. VDD ±1 dB 2.3 V to 3.6 V at 915 MHz, TA = 25°C
Transmit Power Flatness ±1 dB 902 MHz to 928 MHz, 3 V, TA = 25°C
Programmable Step Size 0.3125 dB −20 dBm to +13 dBm
ADJACENT CHANNEL POWER (ACP)
426 MHz, External Inductor VCO PFD = 9.84 MHz
12.5 kHz Channel Spacing −50 dBc Gaussian 2FSK modulation, measured in a ±4.25 kHz bandwidth
at ±12.5 kHz offset, 2.4 kbps PN9 data, 1.2 kHz frequency deviation,
compliant with ARIB STD-T67
25 kHz Channel Spacing −50 dBc Gaussian 2FSK modulation, measured in a ±8 kHz bandwidth at
±25 kHz offset, 9.6 kbps PN9 data, 2.4 kHz frequency deviation,
compliant with ARIB STD-T67
868 MHz, Internal Inductor VCO PFD = 19.68 MHz
12.5 kHz Channel Spacing −46 dBm Gaussian 2FSK modulation, 10 dBm output power, measured in
a ±6.25 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data,
1.2 kHz frequency deviation, compliant with ETSI EN 300-220
25 kHz Channel Spacing −43 dBm Gaussian 2FSK modulation, 10 dBm output power, measured in
a ±12.5 kHz bandwidth at ±25 kHz offset, 9.6 kbps PN9 data,
2.4 kHz frequency deviation, compliant with ETSI EN 300-220
433 MHz, Internal Inductor VCO PFD = 19.68 MHz
12.5 kHz Channel Spacing −50 dBm Gaussian 2FSK modulation, 10 dBm output power, measured in
a ±6.25 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data,
1.2 kHz frequency deviation, compliant with ETSI EN 300-220
25 kHz Channel Spacing −47 dBm Gaussian 2FSK modulation, 10 dBm output power, measured in
a ±12.5 kHz bandwidth at ±25 kHz offset, 9.6 kbps PN9 data,
2.4 kHz frequency deviation, compliant with ETSI EN 300-220
OCCUPIED BANDWIDTH 99.0% of total mean power; 12.5 kHz channel spacing (2.4 kbps
PN9 data, 1.2 kHz frequency deviation); 25 kHz channel spacing
(9.6 kbps PN9 data, 2.4 kHz frequency deviation)
2FSK Gaussian Data Filtering
12.5 kHz Channel Spacing 3.9 kHz
25 kHz Channel Spacing 9.9 kHz
2FSK Raised Cosine Data Filtering
12.5 kHz Channel Spacing 4.4 kHz
25 kHz Channel Spacing 10.2 kHz
3FSK Raised Cosine Filtering
12.5 kHz Channel Spacing 3.9 kHz
25 kHz Channel Spacing 9.5 kHz
4FSK Raised Cosine Filtering 19.2 kbps PN9 data, 1.2 kHz frequency deviation
25 kHz Channel Spacing 13.2 kHz
Data Sheet ADF7021
Rev. D | Page 7 of 62
Parameter Min Typ Max Unit Test Conditions/Comments
SPURIOUS EMISSIONS
Reference Spurs −65 dBc 100 kHz loop bandwidth
HARMONICS5 13 dBm output power, unfiltered conductive/filtered conductive
Second Harmonic −35/−52 dBc
Third Harmonic −43/−60 dBc
All Other Harmonics −36/−65 dBc
OPTIMUM PA LOAD IMPEDANCE6
fRF = 915 MHz 39 + j61 Ω
fRF = 868 MHz 48 + j54 Ω
fRF = 450 MHz 98 + j65 Ω
f
RF
= 426 MHz
100 + j65
Ω
fRF = 315 MHz 129 + j63 Ω
fRF = 175 MHz 173 + j49 Ω
1 Using Gaussian or raised cosine filtering. Choose the frequency deviation to ensure that the transmit occupied signal bandwidth is within the receiver IF filter
bandwidth.
2 Using raised cosine filtering with an alpha = 0.7. The inner frequency deviation = 1.78 kHz, and the POST_DEMOD_BW = 24.6 kHz.
3 For the definition of frequency deviation, refer to the Register 2—Transmit Modulation Register section.
4 Measured as maximum unmodulated power.
5 Conductive filtered harmonic emissions measured on the EVAL-ADF7021DB models, which includes a T-stage harmonic filter (two inductors and one capacitor).
6 For matching details, refer to the LNA/PA Matching section.
ADF7021 Data Sheet
Rev. D | Page 8 of 62
RECEIVER SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
SENSITIVITY
Bit error rate (BER) = 10
−3
, low noise amplifier (LNA) and
power amplifier (PA) matched separately
2FSK
Sensitivity at 0.1 kbps −130 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 0.25 kbps −127 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 1 kbps −122 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 9.6 kbps −115 dBm fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
Sensitivity at 25 kbps −110 dBm fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
Gaussian 2FSK
Sensitivity at 0.1 kbps −129 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 0.25 kbps −127 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 1 kbps
−121
dBm
f
DEV
= 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 9.6 kbps −114 dBm fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
Sensitivity at 25 kbps −111 dBm fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
GMSK
Sensitivity at 9.6 kbps −113 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
Raised Cosine 2FSK
Sensitivity at 0.25 kbps −127 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 1 kbps −121 dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 9.6 kbps −114 dBm fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
Sensitivity at 25 kbps −113 dBm fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
3FSK
Sensitivity at 9.6 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz,
Viterbi detection on
Raised Cosine 3FSK
Sensitivity at 9.6 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 12.5 kHz,
alpha = 0.5, Viterbi detection on
Sensitivity at 19.6 kbps −106 dBm fDEV = 4.8 kHz, high sensitivity mode, IF_BW = 18.75 kHz,
alpha = 0.5, Viterbi detection on
4FSK
Sensitivity at 9.6 kbps −112 dBm fDEV (inner) = 1.2 kHz, high sensitivity mode, IF_BW = 12.5 kHz
Sensitivity at 19.6 kbps −107 dBm fDEV (inner) = 2.4 kHz, high sensitivity mode, IF_BW = 25 kHz
Raised Cosine 4FSK
Sensitivity at 9.6 kbps −109 dBm fDEV (inner) = 1.2 kHz, high sensitivity mode,
IF_BW = 12.5 kHz, alpha = 0.5
Sensitivity at 19.2 kbps −103 dBm fDEV (inner) = 1.2 kHz, high sensitivity mode,
IF_BW = 18.75 kHz, alpha = 0.5
Sensitivity at 32.8 kbps −100 dBm fDEV (inner) = 1.8 kHz, high sensitivity mode, IF_BW = 25 kHz,
alpha = 0.7
INPUT IP3 Two-tone test, fLO = 860 MHz, F1 = fLO + 100 kHz, F2 = fLO − 800 kHz
Low Gain Enhanced Linearity
Mode
−3 dBm LNA_GAIN = 3, MIXER_LINEARITY = 1
Medium Gain Mode
−13.5
dBm
LNA_GAIN = 10, MIXER_LINEARITY = 0
High Sensitivity Mode −24 dBm LNA_GAIN = 30, MIXER_LINEARITY = 0
Data Sheet ADF7021
Rev. D | Page 9 of 62
Parameter Min Typ Max Unit Test Conditions/Comments
ADJACENT CHANNEL REJECTION
868 MHz Wanted signal is 3 dB above the sensitivity point (BER = 10−3);
unmodulated interferer is at the center of the adjacent
channel; rejection measured as the difference between
interferer level and wanted signal level in dB
12.5 kHz Channel Spacing 25 dB 12.5 kHz IF_BW
25 kHz Channel Spacing 27 dB 25 kHz IF_BW
25 kHz Channel Spacing 39 dB 18 kHz IF_BW
426 MHz, External Inductor VCO Wanted signal 3 dB above reference sensitivity point (BER = 10−2);
modulated interferer (1 kHz sine, ±2 kHz deviation) at the center
of the adjacent channel; rejection measured as the difference
between interferer level and reference sensitivity level in dB
12.5 kHz Channel Spacing 25 dB 12.5 kHz IF_BW
25 kHz Channel Spacing 30 dB 25 kHz IF_BW
25 kHz Channel Spacing 41 dB 18 kHz IF_BW, compliant with ARIB STD-T67
CO-CHANNEL REJECTION Wanted signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 10 dB
above the sensitivity point (BER = 10−3), modulated interferer
868 MHz −3 dB
IMAGE CHANNEL REJECTION Wanted signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 10 dB
above the sensitivity point (BER = 10−3); modulated interferer
(2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the image
frequency of fRF − 200 kHz; interferer level is increased until
BER = 10−3
900 MHz 23/39 dB Uncalibrated/calibrated1, VDD = 3.0 V, TA = 25°C
450 MHz 29/50 dB Uncalibrated/calibrated1,VDD = 3.0 V, TA = 25°C
450 MHz, External Inductor VCO 38/53 dB Uncalibrated/calibrated1, VDD = 3.0 V, TA = 25°C
BLOCKING Wanted signal is 10 dB above the input sensitivity level;
CW interferer level is increased until BER = 10−3
±1 MHz 69 dB
±2 MHz
75
dB
±5 MHz 78 dB
±10 MHz 78.5 dB
SATURATION
(MAXIMUM INPUT LEVEL)
12 dBm 2FSK mode, BER = 10−3
RSSI
Range at Input
2
−120 to
−47
dBm
Linearity ±2 dB Input power range = −100 dBm to −47 dBm
Absolute Accuracy ±3 dB Input power range = −100 dBm to −47 dBm
Response Time 300 µs See the RSSI/AGC section
AFC
Pull-In Range 0.5 1.5 × IF_BW kHz The range is programmable, R10_DB[24:31]
Response Time 48 Bits
Accuracy
0.5
kHz
Input power range = −100 dBm to +12 dBm
Rx SPURIOUS EMISSIONS3
Internal Inductor VCO −91/−91 dBm <1 GHz at antenna input, unfiltered conductive/filtered
conductive
−52/−70 dBm >1 GHz at antenna input, unfiltered conductive/filtered
conductive
External Inductor VCO −62/−72 dBm <1 GHz at antenna input, unfiltered conductive/filtered
conductive
−64/−85 dBm >1 GHz at antenna input, unfiltered conductive/filtered
conductive
ADF7021 Data Sheet
Rev. D | Page 10 of 62
Parameter Min Typ Max Unit Test Conditions/Comments
LNA INPUT IMPEDANCE RFIN to RFGND
fRF = 915 MHz 24 − j60 Ω
fRF = 868 MHz 26 − j63 Ω
fRF = 450 MHz 63 − j129 Ω
f
RF
= 426 MHz
68 − j134
Ω
fRF = 315 MHz 96 − j160 Ω
fRF = 175 MHz 178 − j190 Ω
1 Calibration of the image rejection used an external RF source.
2 For received signal levels < −100 dBm, it is recommended to average the RSSI readback value over a number of samples to improve the RSSI accuracy at low input powers.
3 Filtered conductive receive spurious emissions measured on the EVAL-ADF7021DB evaluation boards, which includes a T-stage harmonic filter (two inductors and one
capacitor).
DIGITAL SPECIFICATIONS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
TIMING INFORMATION
Chip Enabled to Regulator Ready 10 µs CREG = 100 nF
Chip Enabled to Tx Mode 32-bit register write time = 50 µs
TCXO Reference
1
ms
XTAL 2 ms
Chip Enabled to Rx Mode 32-bit register write time = 50 µs, IF filter coarse
calibration only
TCXO Reference 1.2 ms
XTAL 2.2 ms
Tx to Rx Turnaround Time 300 µs + (5 × tBIT) Time to synchronized data out, includes AGC
settling and CDR synchronization; see AGC
Information and Timing section for more details;
tBIT = data bit period
LOGIC INPUTS
Input High Voltage, VINH 0.7 × VDD V
Input Low Voltage, VINL 0.2 × VDD V
Input Current, IINH/IINL ±1 µA
Input Capacitance, C
IN
10
pF
Control Clock Input 50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V IOH = 500 µA
Output Low Voltage, VOL 0.4 V IOL = 500 µA
CLKOUT Rise/Fall 5 ns
CLKOUT Load 10 pF
Data Sheet ADF7021
Rev. D | Page 11 of 62
GENERAL SPECIFICATIONS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE RANGE (T
A
)
−40
+85
°C
POWER SUPPLIES
Voltage Supply, V
DD
2.3
3.6
V
All VDD pins must be tied together
TRANSMIT CURRENT CONSUMPTION1 VDD = 3.0 V, PA is matched into 50 Ω
868 MHz VCO_BIAS = 8
0 dBm 20.2 mA
5 dBm 24.7 mA
10 dBm 32.3 mA
450 MHz, Internal Inductor VCO VCO_BIAS = 8
0 dBm 19.9 mA
5 dBm 23.2 mA
10 dBm
29.2
mA
426 MHz, External Inductor VCO VCO_BIAS = 2
0 dBm 13.5 mA
5 dBm 17 mA
10 dBm 23.3 mA
RECEIVE CURRENT CONSUMPTION VDD = 3.0 V
868 MHz VCO_BIAS = 8
Low Current Mode 22.7 mA
High Sensitivity Mode 24.6 mA
433MHz, Internal Inductor VCO VCO_BIAS = 8
Low Current Mode 24.5 mA
High Sensitivity Mode 26.4 mA
426 MHz, External Inductor VCO VCO_BIAS = 2
Low Current Mode 17.5 mA
High Sensitivity Mode
19.5
mA
POWER-DOWN CURRENT CONSUMPTION
Low Power Sleep Mode
0.1
1
µA
CE low
1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021DB evaluation boards. Improved
PA efficiency is achieved by using a separate PA matching network.
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, DGND = AGND = 0 V, T A = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 6.
Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 >10 ns SDATA to SCLK setup time
t2 >10 ns SDATA to SCLK hold time
t3 >25 ns SCLK high duration
t
4
>25
ns
SCLK low duration
t
5
>10
ns
SCLK to SLE setup time
t6 >20 ns SLE pulse width
t8 <25 ns SCLK to SREAD data valid, readback
t9 <25 ns SREAD hold time after SCLK, readback
t10 >10 ns SCLK to SLE disable time, readback
t11 5 < t11 < (¼ × tBIT) ns TxRxCLK negative edge to SLE
t12 >5 ns TxRxDATA to TxRxCLK setup time (Tx mode)
t13 >5 ns TxRxCLK to TxRxDATA hold time (Tx mode)
t14 >¼ × tBIT µs TxRxCLK negative edge to SLE
t15 >¼ × tBIT µs SLE positive edge to positive edge of TxRxCLK
ADF7021 Data Sheet
Rev. D | Page 12 of 62
Timing Diagrams
Serial Interface
Figure 2. Serial Interface Timing Diagram
Figure 3. Serial Interface Readback Timing Diagram
2FSK/3FSK Timing
Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode
Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode
SCLK
SLE
DB31 (MSB) DB30 DB2 DB1
(CONTROL BIT C2)
S
DATA DB0 (LSB)
(CONTROL BIT C1)
t
6
t
1
t
2
t
3
t
4
t
5
05876-002
05876-003
t
8
t
3
t
1
t
2
t
10
t
9
XRV16
RV15 RV2
SCLK
SDATA
SLE
S
READ
REG7 DB0
(CONTROL BIT C1)
RV1 X
TxRxCLK
DATA
T
xRxDATA
±1 × DATA RATE/32 1/DATA RATE
05876-004
TxRxCLK
DATA
TxRxDATA
SAMPLEFETCH
1/DATA RATE
05876-005
Data Sheet ADF7021
Rev. D | Page 13 of 62
4FSK Timing
In 4FSK receive mode, MSB/LSB synchronization is guaranteed by SWD in the receive bit stream.
Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode
Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode
Rx SYMBOL
MSB
Rx SYMBOL
LSB Rx SYMBOL
MSB
Rx SYMBOL
LSB Tx SYMBOL
MSB
Tx SYMBOL
LSB
TxRxDATA
TxRxCLK
SLE
Rx MODE Tx MODE
REGISTER 0 WRITE
SWITCH FROM Rx TO Tx
Tx/Rx MODE
Tx SYMBOL
MSB
t
11
t
12
t
13
t
BIT
t
SYMBOL
05876-074
Tx SYMBOL
MSB
Tx SYMBOL
LSB Tx SYMBOL
MSB
Tx SYMBOL
LSB Rx SYMBOL
LSB
Rx SYMBOL
MSB
TxRxDATA
TxRxCLK
SLE
Tx MODE Rx MODE
REGISTER 0 WRITE
SWITCH FROM Tx TO Rx
Tx/Rx MODE
t
15
t
14
t
BIT
t
SYMBOL
05876-075
ADF7021 Data Sheet
Rev. D | Page 14 of 62
UART/SPI Mode
UART mode is enabled by setting R0_DB28 to 1. SPI mode is enabled by setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7.
The transmit/receive data clock is available on the CLKOUT pin.
Figure 8. Transmit Timing Diagram in UART/SPI Mode
Figure 9. Receive Timing Diagram in UART/SPI Mode
Tx BIT Tx BIT Tx BIT Tx BIT
TxRxCLK
(TRANSMIT DATA INPUT
IN UART/SPI MODE.)
CLKOUT
(TRANSMIT/RECEIVE DATA
CLOCK IN SPI MODE.
NOT USED IN UART MODE.)
Tx MODE
Tx/Rx MODE
TxRxDATA
(RECEIVE DATA OUTPUT
IN UART/SPI MODE.) HIGH-Z
Tx BIT
t
BIT
FETCH SAMPLE
05876-082
Rx BIT Rx BIT Rx BIT Rx BIT
TxRxCLK
(TRANSMIT DATA INPUT
IN UART/SPI MODE.)
CLKOUT
(TRANSMIT/RECEIVE DAT
A
CLOCK IN SPI MODE.
NOT USED IN UART MODE.)
Rx MODE
Tx/Rx MODE
TxRxDATA
(RECEIVE DATA OUTPUT
IN UART/SPI MODE.)
HIGH-Z
Rx BIT
t
BIT
FETCH SAMPLE
05876-078
Data Sheet ADF7021
Rev. D | Page 15 of 62
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter Rating
VDD to GND1 −0.3 V to +5 V
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
MLF θJA Thermal Impedance 26°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1 GND = CPGND = RFGND = DGND = AGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Take proper
precautions for handling and assembly.
ESD CAUTION
ADF7021 Data Sheet
Rev. D | Page 16 of 62
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 10. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCOIN Regulator Voltage for PA Block and VCO Cores. The tuning voltage on this pin determines the output
frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output
frequency.
2 CREG1 Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
3 VDD1 Voltage Supply for PA Block and VCO Cores. Place decoupling capacitors of 0.1 μF and 100 pF as close as
possible to this pin. Tie all VDD pins together.
4 RFOUT The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. Impedance
match the output to the desired load using suitable components (see the Transmitter section).
5 RFGND Ground for Output Stage of Transmitter. Tie all GND pins together.
6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer (see the LNA/PA Matching section).
7 RFINB Complementary LNA Input (see the LNA/PA Matching section).
8 RLNA External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9 VDD4 Voltage Supply for LNA/MIXER Block. Decouple this pin to ground with a 10 nF capacitor.
10 RSET External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.
11 CREG4 Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator
stability and noise rejection.
12, 19, 22 GND4 Ground for LNA/MIXER Block.
13 to 18 MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
Signal Chain Test Pins. These pins are high impedance under normal conditions; leave the pins unconnected.
20, 21, 23 FILT_Q, FILT_Q,
TEST_A
Signal Chain Test Pins. These pins are high impedance under normal conditions; leave the pins unconnected.
24 CE Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE
is low, and the device must be reprogrammed once CE is brought high.
25 SLE Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
26 SDATA Serial Data Input. The serial data is loaded MSB first with the 4 LSBs as the control bits. This pin is a high
impedance CMOS input.
27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK
input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET
CREG4
GND4
MIX_I
MIX_Q
FILT_I
GND4
FILT_Q
GND4
TEST_A
CE
CLKOUT
TxRxCLK
TxRxDATA
SWD
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
CVCO
GND1
L1
GND
L2
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
MUXOUT
MIX_I
MIX_Q
FILT_I
FILT_Q
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
ADF7021
TOP VIEW
(Not to Scale)
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
05876-006
Data Sheet ADF7021
Rev. D | Page 17 of 62
Pin No. Mnemonic Description
29 GND2 Ground for Digital Section.
30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to
1.9 V. Readback is made using the SREAD pin.
31 CREG2 Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator
stability and noise rejection.
32 VDD2 Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin.
33 SWD Sync Word Detect. The ADF7021 asserts this pin when it has found a match for the sync word sequence
(see the Register 11—Sync Word Detect Register section). This provides an interrupt for an external
microcontroller indicating valid data is being received.
34 TxRxDATA Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. In UART/SPI
mode, this pin provides an output for the received data in receive mode. In transmit UART/SPI mode, this pin
is high impedance (see the Interfacing to Microcontroller/DSP section).
35 TxRxCLK Outputs the data clock in both receive and transmit modes. This is a digital pin and normal CMOS levels
apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin
outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact
required data rate. In UART/SPI mode, this pin is used to input the transmit data in transmit mode. In receive
UART/SPI mode, this pin is high impedance (see the Interfacing to Microcontroller/DSP section).
36 CLKOUT A divided-down version of the crystal reference with output driver. The digital clock output can be used to drive
several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio and is
inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in
applications where the CLKOUT feature is being used.
37 MUXOUT Provides the DIGITAL_LOCK_DETECT Signal. This signal is used to determine if the PLL is locked to the correct
frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the
serial interface regulator (see the MUXOUT section for more information).
38 OSC2 Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin
with CMOS levels and disabling the internal crystal oscillator.
39 OSC1 Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin
with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator.
40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor.
41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground
for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
43 VDD Voltage Supply for XTAL and Bandgap Core. Decouple this pin to ground with a 10 nF capacitor.
44, 46 L2, L1
External VCO Inductor Pins. If using an external VCO inductor, connect a chip inductor across these pins to set
the VCO operating frequency. If using t internal VCO inductor, these pins can be left floating. See the Voltage
Controlled Oscillator (VCO) section he for more information.
45, 47 GND, GND1 Grounds for VCO Block.
48 CVCO Place a 22 nF capacitor between this pin and CREG1 to reduce VCO noise.
49 EPAD Exposed Pad. The exposed pad must be connected to GND.
ADF7021 Data Sheet
Rev. D | Page 18 of 62
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. Phase Noise Response at 900 MHz, VDD = 2.3 V
Figure 12. RF Output Power vs. PA Setting
Figure 13. PA Output Harmonic Response with T-Stage LC Filter
Figure 14. Output Spectrum in 2FSK and GFSK Modes
Figure 15. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes
Figure 16. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes
05876-060
FREQUENCY OFFSET (MHz)
PHASE NOISE (dBc/Hz)
–150
–140
–130
–120
–110
–100
–90
–80
–
70
1 10 100 1000 10000
RF FREQ = 900MHz
VDD = 2.3V
TEMPERATURE = 25°C
VCO BIAS = 8
VCO ADJUST = 3
ICP = 0.8mA
ICP = 1.4mA
ICP = 2.2mA
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
05876-051
PA SETTING
RF OUTPUT POWER (dBm)
PA BIAS = 5µA
PA BIAS = 11µA
PA BIAS = 9µA
PA BIAS = 7µA
VBW 100Hz
05876-050
START 300MHz
RES BW 100Hz SWEEP 385.8ms (601pts)
STOP 3.5GHz
RF FREQ = 440MHz
OUTPUT POWER = 10dBm
FILTER = T-STAGE LC FILTER
MARKER ∆ = 52.2dB
1R
1
05876-047
CENTER 869.5 25MHz
RES BW 300Hz SWEEP 2.118s (601pts)
SPAN 50kHz
DR = 9.6kbps
DATA = PRBS9
f
DEV
= 2.4kHz
RF FREQ = 869.5MHz
VBW 300Hz
GFSK
FSK
05876-048
CENTER 869.5 25MHz
RES BW 300Hz SWEEP 2.118s (601pts)VBW 300Hz
SPAN 50kHz
DR = 9.6kbps
DATA = PRBS9
f
DEV
= 2.4kHz
RF FREQ = 869.5MHz
RC2FSK
2FSK
VBW 300Hz
05876-049
CENTER 869.493 8MHz
RES BW 300Hz SWEEP 4.237s (601pts)
SPAN 100kHz
SR = 4.8ksym/s
DATA = PRBS9
f
DEV
= 2.4kHz
RF FREQ = 869.5MHz
RC4FSK
4FSK
Data Sheet ADF7021
Rev. D | Page 19 of 62
Figure 17. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes
Figure 18. Output Spectrum in Maximum Hold
for Various PA Ramp Rate Options
Figure 19. 2FSK Sensitivity vs. VDD and Temperature, fRF = 868 MHz
Figure 20. 2FSK Sensitivity vs. VDD and Temperature, fRF = 135 MHz
Figure 21. 3FSK Sensitivity vs. VDD and Temperature, fRF = 440 MHz
Figure 22. 4FSK Sensitivity vs. VDD and Temperature, fRF = 420 MHz
05876-070
RES BW 300Hz
CENTER 869.5MHz VBW 300Hz SPAN 50Hz
SWEEP2.226s (401pts)
REF 15dBm
SAMP LOG 10dB/ ATTEN 25dB
V
AVG 100
V1 V2
S3 FC
DR = 9.6kbps
DATA = PRS9
f
DEV
= 2.4kHz
RF FREQ = 869.5MHz
3FSK
RC3FSK
05876-068
FREQUENCY OFFSET (kHz)
OUTPUT POWER (dBm)
0
–10
10
–20
–30
–40
–100 –50 500100
–50
–60
RAMP RATE:
CW ONLY
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
TRACE = MAX HOLD
PA ON/OFF RATE = 3Hz
PA ON/OFF CYCLES = 10000
V
DD
= 3.0V
–8
–7
–6
–5
–4
–3
–2
–1
0
–122 –120 –118 –116 –114 –112 –110 –108 –106 –104
3.0V, +25°C
3.6V, –40°C
2.3V, +85°C
05876-052
RF INPUT POWER (dBm)
LOG BER
DATA RATE = 9.6kbps
f
DEV
= 4kHz
RF FREQ = 868MHz
IF BW = 25kHz
–8
–7
–6
–5
–4
–3
–2
–1
0
–130 –128 –126 –124 –122 –120 –118 –116 –114 –112 –110 –108
3.6V, –40°C
3.0V, +25°C 2.3V, +85°C
05876-053
RF INPUT POWER (dBm)
LOG BER
DATA RATE = 1kbps
f
DEV
= 1kHz
RF FREQ = 135MHz
IF BW = 12.5kHz
–8
–7
–6
–5
–4
–3
–2
–1
0
–120 –115 –110 –105 –100 –95
0
5876-065
RF INPUT POWER (dBm)
LOG BER
2.3V +25°C
3.0V +25°C
3.6V +25°C
2.3V –40°C
3.0V –40°C
3.6V –40°C
2.3V +85°C
3.0V +85°C
3.6V +85°C
3FSK MODULATION
DATA RATE = 9.6kbps
f
DEV
= 2.4kHz
MOD INDEX = 0.5
RF FREQ = 440 MHz
–8
–7
–6
–5
–4
–3
–2
–1
0
–120 –115 –110 –105 –100 –95
0
5876-066
RF INPUT POWER (dBm)
LOG BER
2.3V +25°C
3.0V +25°C
3.6V +25°C
2.3V –40°C
3.0V –40°C
3.6V –40°C
2.3V +85°C
3.0V +85°C
3.6V +85°C
DATA RATE = 19.6kbps
SYMBOL RATE = 9.8ksym/s
f
DEV
(inner) = 2.4kHz
MOD INDEX = 0.5
RF FREQ = 420MHz
IF BW = 12.5kHz
ADF7021 Data Sheet
Rev. D | Page 20 of 62
Figure 23. Wideband Interference Rejection
Figure 24. Digital RSSI Readback Linearity
Figure 25. Image Rejection, Uncalibrated vs. Calibrated
Figure 26. 2FSK Sensitivity vs. Modulation Index vs. Correlator
Discriminator Bandwidth
Figure 27. 3FSK Receiver Sensitivity Using Viterbi Detection and
Threshold Detection
05876-059
FREQUENCY OFFSET (MHz)
BLOCKING (dB)
–10
0
10
20
30
40
50
60
70
80
90
–22 –18 –14 –10 –6 –2 0 2 6 10 14 18 22
RF FREQ = 868MHz
WANTED SIGNAL
(10dB ABOVE SENSITIVITY
POINT) = 2FSK,
f
DEV
= 4kHz,
DATA RATE = 9.8kbps
BLOCKER = 2FSK,
f
DEV
= 4kHz,
DATA RATE = 9.8kbps
V
DD
= 3.0V
TEMPERATURE = 25°C
–140
–120
–100
–80
–60
–40
–
20
–122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 –52.5 –42.5
ACTUAL RF INPUT LEVEL
05876-055
RF INPUT (dBm)
RSSI LEVEL (dBm)
RSSI
READBACK LEVEL
–10
0
10
20
30
40
50
60
70
429.80 429.85 429.90 429.95 430.00 430.05 430.10 430.15 430.20
RF FREQ = 430MHz
EXTERNAL VCO INDUCTOR
DATA RATE = 9.6kbps
TEMPERATURE = 25°C, VDD = 3.0V
05876-054
RF FREQUENCY (MHz)
BLOCKING (dB)
CALIBRATED
UNCALIBRATED
05876-058
MODULATION INDEX
SENSITIVITY POINT (dBm)
–118
–116
–114
–112
–110
–108
–106
–104
–102
–
100
0 0.2 0.4 0.6 0.8 1.0 1.2
RF FREQ = 860MHz
2FSK MODULATION
DATA RATE = 9.6kbps
IF BW = 25kHz
V
DD
= 3.0V
TEMPERATURE = 25°C
DISCRIMINATOR BANDWIDTH =
1× FSK FREQUENCY DEVIATION
DISCRIMINATOR BANDWIDTH =
2× FSK FREQUENCY DEVIATION
–120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100
3FSK MODULATION
V
DD
= 3.0V, TEMP = 25°C
DATA RATE = 9.6kbps
f
DEV
= 2.4kHz
RF FREQ = 868MHz
IF BW = 18.75kHz
05876-062
INPUT POWER (dBm)
LOG BER
–7
–6
–5
–4
–3
–2
–1
0
VITERBI DETECTION
THRESHOLD DETECTION
TYPICALLY
3dB
Data Sheet ADF7021
Rev. D | Page 21 of 62
Figure 28. 4FSK Receiver Eye Diagram Measure Using the Test DAC Output
Figure 29. 3FSK Receiver Eye Diagram Measured Using the Test DAC Output
Figure 30. Receive Sensitivity vs. LNA/IF Filter Gain and Mixer Linearity Settings
(The Input IP3 at Each Setting is Also Shown)
RECEIVER SYMBOL LEVEL
+1
+3
–1
–3
0
05876-064
RF I/P LEVEL = –70dBm
DATA RATE = 9.7kbps
f
DEV
(inner) = 1.2kHz
22452 ACQS M 50µs
IF BW = 25kHz
POST DEMOD BW = 12.4kHz
+1
–1
0
05876-063
4
20834 ACQS M 20µs C13 1.7V
RF I/P LEVEL = –70dBm
DATA RATE = 10kbps
f
DEV
= 2.5kHz
IF BW = 12.5kHz
POST DEMOD BW = 12.4kHz
RECEIVER SYMBOL LEVEL
05876-069
LNA GAIN, FILTER GAIN
SENSITIVITY (dBm)
–130
–120
–110
–100
–90
–80
–
70
3, 72
(LOW GAIN MODE)
10, 72
(MEDIUM GAIN MODE)
30, 72
(HIGH GAIN MODE)
HIGH MIXER
LINEARITY
DEFAULT
MIXER
LINEARITY
MODULATION = 2FSK
DATA RATE = 9.6kbps
f
DEV
= 4kHz
IF BW = 12.5kHz
DEMOD = CORRELATOR
SENSITIVITY @ 1E-3 BER
IP3 = –3dBm
IP3= –5dBm
IP3 = –9dBm
IP3 = –13.5dBm
IP3 = –24dBm
IP3 = –20dBm
ADF7021 Data Sheet
Rev. D | Page 22 of 62
FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 31) can use
a quartz crystal as the PLL reference. Using a quartz crystal with
a frequency tolerance of ≤10 ppm for narrow-band applications
is recommended. It is possible to use a quartz crystal with >10 ppm
tolerance, but to comply with the absolute frequency error
specifications of narrow-band regulations (for example, ARIB
STD-T67 and ETSI EN 300-220), compensation for the
frequency error of the crystal is necessary.
The oscillator circuit is enabled by setting R1_DB12 high. It is
enabled by default on power-up and is disabled by bringing CE
low. Errors in the crystal can be corrected by using the automatic
frequency control feature or by adjusting the fractional-N value
(see the N Counter section).
Figure 31. Oscillator Circuit on the ADF7021
Two parallel resonant capacitors are required for oscillation at
the correct frequency. Their values are dependent upon the
crystal specification. When choosing the values of the capacitors,
make sure that the series value of capacitance added to the PCB
track capacitance adds up to the specified load capacitance of the
crystal, usually 12 pF to 20 pF. Track capacitance values vary
from 2 pF to 5 pF, depending on board layout. When possible,
choose capacitors that have a very low temperature coefficient
to ensure stable frequency operation over all conditions.
Using a TCXO Reference
A single-ended reference (TCXO, VCXO, or OCXO) can also be
used with the ADF7021. This is recommended for applications
having absolute frequency accuracy requirements of <10 ppm, such
as ARIB STD-T67 or ETSI EN 300-220. There are two options
for interfacing the ADF7021 to an external reference oscillator.
An oscillator with CMOS output levels can be applied to
OSC2. Disable the internal oscillator circuit by setting
R1_DB12 low.
An oscillator with 0.8 V p-p levels can be ac-coupled through
a 22 pF capacitor into OSC1. Enable the internal oscillator
circuit by setting R1_DB12 high.
Programmable Crystal Bias Current
Bias current in the oscillator circuit can be configured
between 20 μA and 35 μA by writing to the XTAL_BIAS bits
(R1_DB[13:14]). Increasing the bias current allows the crystal
oscillator to power up faster.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 32, and supplies a divided-
down, 50:50 mark-space signal to the CLKOUT pin. The CLKOUT
signal is inverted with respect to the reference clock. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.
Figure 32. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A series resistor (1 kΩ) can be used to slow the
clock edges to reduce these spurs at the CLKOUT frequency.
R Counter
The 3-bit R counter divides the reference input frequency by an
integer of 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The divide
ratio is set in R1_DB[4:6]. Maximizing the PFD frequency reduces
the N value. This reduces the noise multiplied at a rate of 20 log(N)
to the output and reduces occurrences of spurious components.
Register 1 defaults to R = 1 on power-up.
PFD [Hz] = XTAL/R
Loop Filter
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 33.
Figure 33. Typical Loop Filter Configuration
Design the loop so that the loop bandwidth (LBW) is
approximately 100 kHz. This provides a good compromise
between in-band phase noise and out-of-band spurious rejection.
Widening the LBW excessively reduces the time spent jumping
between frequencies, but it can cause insufficient spurious attenua-
tion. Narrow-loop bandwidths can result in the loop taking long
periods to attain lock and can also result in a higher level of power
falling into the adjacent channel. Use the loop filter design on
the EVAL-ADF7021DB evaluation boards for optimum
performance.
OSC1
CP1CP2
OSC2
05876-083
DV
DD
CLKOUT
ENABLE BIT
CLKOUTOSC1 DIVIDER
1TO 15 ÷2
05876-008
CHARGE
PUMP OUT VCO
05876-010
Data Sheet ADF7021
Rev. D | Page 23 of 62
The free design tool ADIsimPLL can also be used to design loop
filters for the ADF7021 (go to www.analog.com/ADIsimPLL for
details).
N Counter
The feedback divider in the ADF7021 PLL consists of an 8-bit integer
counter (R0_DB[19:26]) and a 15-bit Σ-Δ FRACTIONAL_N
divider (R0_DB[4:18]). The integer counter is the standard
pulse-swallow type that is common in PLLs. This sets the
minimum integer divide value to 23. The fractional divide
value provides very fine resolution at the output, where the
output frequency of the PLL is calculated as
15
2
_
_NFRACTIONAL
NINTEGER
R
XTAL
fOUT
When RF_DIVIDE_BY_2 (see the Voltage Controlled
Oscillator (VCO) section) is selected, this formula becomes
15
2
_
_0.5 NFRACTIONAL
NINTEGER
R
XTAL
fOUT
The combination of the INTEGER_N (maximum = 255) and the
FRACTIONAL_N (maximum = 32,768/32,768) give a maximum
N divider of 255 + 1. Therefore, the minimum usable PFD is
1255
Hz
FrequencyOutputRequiredMaximum
PFDMIN
For example, when operating in the European 868 MHz to
870 MHz band, PFDMIN equals 3.4 MHz.
Figure 34. Fractional-N PLL
Voltage Regulators
The ADF7021 contains four regulators to supply stable voltages
to the device. The nominal regulator voltage is 2.3 V. Regulator 1
requires a 3.9 Ω resistor and a 100 nF capacitor in series between
CREG1 and GND, whereas the other regulators require a 100 nF
capacitor connected between CREGx and GND. When CE is
high, the regulators and other associated circuitry are powered
on, drawing a total supply current of 2 mA. Bringing the CE pin
low disables the regulators, reduces the supply current to less
than 1 μA, and erases all values held in the registers. The serial
interface operates from a regulator supply. Therefore, to write to
the device, the user must have CE high and the regulator voltage
must be stabilized. Regulator status (CREG4) can be monitored
using the REGULATOR_READY signal from MUXOUT.
MUXOUT
The MUXOUT pin allows access to various digital points in the
ADF7021. The state of MUXOUT is controlled by R0_DB[29:31].
REGULATOR_READY
REGULATOR_READY is the default setting on MUXOUT
after the transceiver is powered up. The power-up time of
the regulator is typically 50 μs. Because the serial interface
is powered from the regulator, the regulator must be at its
nominal voltage before the ADF7021 can be programmed. The
status of the regulator can be monitored at MUXOUT. When
the regulator ready signal on MUXOUT is high, programming
of the ADF7021 can begin.
Figure 35. MUXOUT Circuit
FILTER_CAL_COMPLETE
MUXOUT can be set to FILTER_CAL_COMPLETE. This signal
goes low for the duration of both a coarse IF filter calibration
and a fine IF filter calibration. It can be used as an interrupt to a
microcontroller to signal the end of the IF filter calibration.
DIGITAL_LOCK_DETECT
DIGITAL_LOCK_DETECT indicates when the PLL has locked.
The lock detect circuit is located at the PFD. When the phase
error on five consecutive cycles is less than 15 ns, lock detect is
set high. Lock detect remains high until a 25 ns phase error is
detected at the PFD.
RSSI_READY
MUXOUT can be set to RSSI_READY. This indicates that the
internal analog RSSI has settled and a digital RSSI readback can
be performed.
Tx_Rx
Tx_Rx signifies whether the ADF7021 is in transmit or receive
mode. When in transmit mode, this signal is low. When in
receive mode, this signal is high. It can be used to control an
external Tx/Rx switch.
VCO
4\N
THIRD-ORDER
Σ-∆ MODULATOR
PFD/
CHARGE
PUMP
4\R
INTEGER-NFRACTIONAL-N
REFERENCE IN
05876-011
05876-009
REGULATOR_READY (DEFAULT)
DIGITAL_LOCK_DETECT
RSSI_READY
Tx_Rx
LOGIC_ZERO
TRISTATE
MUX CONTROL
DGND
D
V
DD
MUXOUT
FILTER_CAL_COMPLETE
LOGIC_ONE
ADF7021 Data Sheet
Rev. D | Page 24 of 62
VOLTAGE CONTROLLED OSCILLATOR (VCO)
The ADF7021 contains two VCO cores. The first VCO, the
internal inductor VCO, uses an internal LC tank and supports
862 MHz to 950 MHz and 431 MHz to 475 MHz operating
bands. The second VCO, the external inductor VCO, uses an
external inductor as part of its LC tank and supports the RF
operating band of 80 MHz to 650 MHz.
To minimize spurious emissions, both VCOs operate at twice
the RF frequency. The VCO signal is then divided by 2 inside
the synthesizer loop, giving the required frequency for the
transmitter and the required local oscillator (LO) frequency
for the receiver. A further divide-by-2 (RF_DIVIDE_BY_2) is
performed outside the synthesizer loop to allow operation in
the 431 MHz to 475 MHz band (internal inductor VCO) and
80 MHz to 325 MHz band (external inductor VCO).
The VCO needs an external 22 nF capacitor between the CVCO
pin and the regulator (CREG1) to reduce internal noise.
Figure 36. Voltage Controlled Oscillator (VCO)
Internal Inductor VCO
To select the internal inductor VCO, set R1_DB25 to Logic 0,
which is the default setting.
VCO bias current can be adjusted using R1_DB[19:22]. To
ensure VCO oscillation, the minimum bias current setting under
all conditions when using the internal inductor VCO is 0x8.
Recenter the VCO, depending on the required frequency of
operation, by programming the VCO_ADJUST bits
(R1_DB[23:24]). This is detailed in Table 9.
External Inductor VCO
When using the external inductor VCO, the center frequency of the
VCO is set by the internal varactor capacitance and the combined
inductance of the external chip inductor, bond wire, and PCB track.
The external inductor is connected between the L2 and L1 pins.
A plot of the VCO operating frequency vs. total external
inductance (chip inductor + PCB track) is shown in Figure 37.
Figure 37. Direct RF Output vs. Total External Inductance
The inductance for a PCB track using FR4 material is approximately
0.57 nH/mm. Subtract this from the total value to determine
the correct chip inductor value.
Typically, a particular inductor value allows the ADF7021 to
function over a range of ±6% of the RF operating frequency.
When the RF_DIVIDE_BY_2 bit (R1_DB18) is selected, this
range becomes ±3%. At 400 MHz, for example, an operating
range of ±24 MHz (that is, 376 MHz to 424 MHz) with a single
inductor (VCO range centered at 400 MHz) can be expected.
The VCO tuning voltage can be checked for a particular RF
output frequency by measuring the voltage on the VCOIN pin
when the device is fully powered up in transmit or receive mode.
The VCO tuning range is 0.2 V to 2 V. Choose the external
inductor value to ensure that the VCO is operating as close as
possible to the center of this tuning range. This is particularly
important for RF frequencies <200 MHz, where the VCO gain
is reduced and a tuning range of <±6 MHz exists.
The VCO operating frequency range can be adjusted by
programming the VCO_ADJUST bits (R1_DB[23:24]). This
typically allows the VCO operating range to be shifted up or
down by a maximum of 1% of the RF frequency.
To select the external inductor VCO, set R1_DB25 to Logic 1.
Set the VCO_BIAS_CURRENT depending on the frequency of
operation (as indicated in Table 9).
Table 9. RF Output Frequency Ranges for Internal and External Inductor VCOs and Required Register Settings
RF Frequency
Output (MHz)
VCO to
Be Used
RF Divide
by 2
Register Settings
(VCO_INDUCTOR)
R1_DB25
(RF_DIVIDE_BY_2)
R1_DB18
(VCO_ADJUST)
R1_DB[23:24]
(VCO_BIAS)
R1_DB[19:22]
900 to 950 Internal L No 0 0 11 8
862 to 900 Internal L No 0 0 00 8
450 to 470 Internal L Yes 0 1 11 8
431 to 450 Internal L Yes 0 1 00 8
450 to 650 External L No 1 0 XX 4
200 to 450 External L No 1 0 XX 3
80 to 200 External L Yes 1 1 XX 2
VCO
LOOP FILTER
VCO BIAS
R1_DB(19:22)
22nF
CVCO PIN
05876-012
DIVIDE-BY-2
R1_DB18
÷2
÷2
MUX
TO
N DIVIDER
TO PA
05876-061
0 5 10 15 20 25 30
200
250
300
350
400
450
500
550
600
650
700
TOTAL EXTERNAL INDUCTANCE (nH)
FREQUENCY (MHz)
750
f
MIN
(MHz)
f
MAX
(MHz)
Data Sheet ADF7021
Rev. D | Page 25 of 62
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
An interaction between the RF VCO frequency and the
reference frequency can lead to fractional spur creation. When
the synthesizer is in fractional mode (that is, the RF VCO and
reference frequencies are not integer related), spurs can appear
on the VCO output spectrum at an offset frequency that
corresponds to the difference frequency between an integer
multiple of the reference and the VCO frequency.
These spurs are attenuated by the loop filter. They are more
noticeable on channels close to integer multiples of the reference
where the difference frequency may be inside the loop bandwidth;
thus, the name integer boundary spurs. The occurrence of these
spurs is rare because the integer frequencies are around multiples
of the reference, which is typically >10 MHz. To avoid having
very small or very large values in the fractional register, choose
a suitable reference frequency.
ADF7021 Data Sheet
Rev. D | Page 26 of 62
TRANSMITTER
RF OUTPUT STAGE
The power amplifier (PA) of the ADF7021 is based on a single-
ended, controlled current, open-drain amplifier that has been
designed to deliver up to 13 dBm into a 50 Ω load at a maximum
frequency of 950 MHz.
The PA output current and consequently, the output power, are
programmable over a wide range. The PA configuration is shown
in Figure 38. The output power is set using R2_DB[13:18].
Figure 38. PA Configuration
The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the appli-
cation, users can design a matching network for the PA to exhibit
optimum efficiency at the desired radiated output power level
for a wide range of antennas, such as loop or monopole antennas.
See the LNA/PA Matching section for more information.
PA Ramping
When the PA is switched on or off quickly, its changing input
impedance momentarily disturbs the VCO output frequency.
This process is called VCO pulling, and it manifests as spectral
splatter or spurs in the output spectrum around the desired carrier
frequency. Some radio emissions regulations place limits on
these PA transient-induced spurs (for example, ETSI EN 300 220).
By gradually ramping the PA on and off, PA transient spurs are
minimized.
The ADF7021 has built-in PA ramping configurability. As
Figure 39 illustrates, there are eight ramp rate settings, defined
as a certain number of PA setting codes per one data bit period.
The PA steps through each of its 64 code levels but at different
speeds for each setting. The ramp rate is set by configuring
R2_DB[8:10].
If the PA is enabled/disabled by PA_ENABLE (R2_DB7), it
ramps up at the programmed rate but turns off hard. If the PA is
enabled/disabled by Tx/Rx (R0_DB27), it ramps up and down
at the programmed rate.
Figure 39. PA Ramping Settings
PA Bias Currents
The PA_BIAS bits (R2_DB[11:12]) facilitate an adjustment of
the PA bias current to further extend the output power control
range, if necessary. If this feature is not required, the default
value of 9 μA is recommended. If output power of greater than
10 dBm is required, a PA bias setting of 11 μA is recommended.
The output stage is powered down by resetting R2_DB7.
MODULATION SCHEMES
The ADF7021 supports 2FSK, 3FSK, and 4FSK modulation. The
implementation of these modulation schemes is shown in
Figure 40.
Figure 40. Transmit Modulation Implementation
0
5876-013
IDAC
2
6R2_DB(13:18)
R2_DB7
R2_DB(11:12)
+
RFGND
RFOUT
FROM VCO
R0_DB27
DATA BITS
PA RAMP 0
(NO RAMP)
PA RAMP 1
(256 CODES PER BIT)
PA RAMP 2
(128 CODES PER BIT)
PA RAMP 3
(64 CODES PER BIT)
PA RAMP 4
(32 CODES PER BIT)
PA RAMP 5
(16 CODES PER BIT)
PA RAMP 6
(8 CODES PER BIT)
PA RAMP 7
(4 CODES PER BIT)
1 2 3 4 ... 8 ... 1
6
05876-014
05876-015
VCO
÷N
THIRD-ORDER
Σ-∆ MODULATOR
PFD/
CHARGE
PUMP
REF
INTEGER-N
F_DEVIATION
TO
PA STAGE
1 – D
2
PR
SHAPING
4FSK
BIT SYMBOL
MAPPER
MUX
TxDATA
2FSK
4FSK
GAUSSIAN
OR
RAISED COSINE
FILTERING
PRE-
CODER
3FSK
÷2
LOOP FILTER
FRAC_N
Data Sheet ADF7021
Rev. D | Page 27 of 62
Setting the Transmit Data Rate
In all modulation modes except oversampled 2FSK mode, an
accurate clock is provided on the TxRxCLK pin to latch the data
from the microcontroller into the transmit section at the required
data rate. The exact frequency of this clock is defined by
DATA CLK =
32____ DIVIDECLKCDRDIVIDECLKDEMOD
XTAL
where:
XTAL is the crystal or TCXO frequency.
DEMOD_CLK_DIVIDE is the divider that sets the demodulator
clock rate (R3_DB[6:9]).
CDR_CLK_DIVIDE is the divider that sets the CDR clock rate
(R3_DB[10:17]).
Refer to the Register 3—Transmit/Receive Clock Register
section for more programming information.
Setting the FSK Transmit Deviation Frequency
In all modulation modes, the deviation from the center frequency
is set using the Tx_FREQUENCY_DEVIATION bits
(R2_DB[19:27]).
The deviation from the center frequency in Hz is as follows:
For direct RF output,
fDEV [Hz] = 16
2
__ DEVIATIONFREQUENCYTxPFD
For RF_DIVIDE_BY_2 enabled,
fDEV [Hz] = 16
2
__
5.0 DEVIATIONFREQUENCYTxPFD
where Tx_FREQUENCY_DEVIATION is a number from 1 to
511 (R2_DB[19:27]).
In 4FSK modulation, the four symbols (00, 01, 11, 10) are
transmitted as ±3 × fDEV and ±1 × fDEV.
Binary Frequency Shift Keying (2FSK)
Two-level frequency shift keying is implemented by setting the
N value for the center frequency and then toggling it with the
TxDATA line. The deviation from the center frequency is set
using the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27].
2FSK is selected by setting the MODULATION_SCHEME bits
(R2_DB[4:6]) to 000.
Minimum shift keying (MSK) or Gaussian minimum shift
keying (GMSK) is supported by selecting 2FSK modulation
and using a modulation index of 0.5. A modulation index of
0.5 is set up by configuring R2_DB[19:27] for a FREQDEVIATION =
0.25 × transmit data rate.
3-Level Frequency Shift Keying (3FSK)
In 3-level FSK modulation (also known as modified Duobinary
FSK), the binary data (Logic 0 and Logic 1) is mapped onto
three distinct frequencies, the carrier frequency (fC), the carrier
frequency minus a deviation frequency (fC − fDEV), and the
carrier frequency plus the deviation frequency (fC + fDEV).
A Logic 0 is mapped to the carrier frequency while a Logic 1 is
either mapped onto frequency fC − fDEV or fC + fDEV.
Figure 41. 3FSK Symbol-to-Frequency Mapping
Compared to 2FSK, this bits-to-frequency mapping results in a
reduced transmission bandwidth because some energy is removed
from the RF sidebands and transferred to the carrier frequency.
At low modulation index, 3FSK improves the transmit spectral
efficiency by up to 25% when compared to 2FSK.
Bit-to-symbol mapping for 3FSK is implemented using a linear
convolutional encoder that also permits Viterbi detection to be
used in the receiver. A block diagram of the transmit hardware
used to realize this system is shown in Figure 42. The convolu-
tional encoder polynomial used to implement the transmit
spectral shaping is
P(D) = 1 − D2
where:
P is the convolutional encoder polynomial.
D is the unit delay operator.
A digital precoder with transfer function 1/P(D) implements an
inverse modulo-2 operation of the 1 − D2 shaping filter in the
transmitter.
Figure 42. 3FSK Encoding
The signal mapping of the input binary transmit data to the 3-level
convolutional output is shown in Table 10. The convolutional
encoder restricts the maximum number of sequential +1s or
−1s to two and delivers an equal number of +1s and −1s to the
FSK modulator, thus ensuring equal spectral energy in both RF
sidebands.
f
C
f
C
–
f
DEV
f
C
+
f
DEV
RF FREQUENCY
0
+1
–1
05876-057
PRECODER
1/P(D)
CONVOLUTIONAL
ENCODER
P(D)
FSK MOD
CONTROL
AND
DATA FILTERING
Tx DATA
05876-046
0, 1
0, +1, –1
0, 1
TO
N DIVIDER
f
C
f
C
+
f
DEV
f
C
–
f
DEV
ADF7021 Data Sheet
Rev. D | Page 28 of 62
Table 10. 3-Level Signal Mapping of the Convolutional Encoder
TxDATA 1 0 1 1 0 0 1 0 0 1
Precoder Output 1 0 0 1 0 1 1 1 1 0
Encoder Output +1 0 −1 +1 0 0 +1 0 0 −1
Another property of this encoding scheme is that the transmitted
symbol sequence is dc-free, which facilitates symbol detection
and frequency measurement in the receiver. In addition, there
is no code rate loss associated with this 3-level convolutional
encoder; that is, the transmitted symbol rate is equal to the data
rate presented at the transmit data input.
3FSK is selected by setting the MODULATION_SCHEME bits
(R2_DB[4:6]) to 010. It can also be used with raised cosine
filtering to further increase the spectral efficiency of the
transmit signal.
4-Level Frequency Shift Keying (4FSK)
In 4FSK modulation, two bits per symbol spectral efficiency is
realized by mapping consecutive input bit-pairs in the Tx data
bit stream to one of four possible symbols (−3, −1, +1, +3). Thus,
the transmitted symbol rate is half of the input bit rate.
By minimizing the separation between symbol frequencies,
4FSK can have high spectral efficiency. The bit-to-symbol
mapping for 4FSK is gray coded and is shown in Figure 43.
Figure 43. 4FSK Bit-to-Symbol Mapping
The inner deviation frequencies (+fDEV and − fDEV) are set using
the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27]. The
outer deviation frequencies are automatically set to three times
the inner deviation frequency.
The transmit clock from Pin TxRxCLK is available after writing
to Register 3 in the power-up sequence for receive mode. Clock
the MSB of the first symbol into the ADF7021 on the first transmit
clock pulse from the ADF7021 after writing to Register 3. Refer to
Figure 6 for more timing information.
Oversampled 2FSK
In oversampled 2FSK, there is no data clock from the TxRxCLK
pin. Instead, the transmit data at the TxRxDATA pin is sampled
at 32 times the programmed rate.
This is the only modulation mode that can be used with the UART
mode interface for data transmission (refer to the Interfacing to
Microcontroller/DSP section for more information).
SPECTRAL SHAPING
Gaussian or raised cosine filtering can be used to improve
transmit spectral efficiency. The ADF7021 supports Gaussian
filtering (bandwidth time [BT] = 0.5) on 2FSK modulation.
Raised cosine filtering can be used with 2FSK, 3FSK, or 4FSK
modulation. The roll off factor (alpha) of the raised cosine filter
has programmable options of 0.5 and 0.7. Both the Gaussian
and raised cosine filters are implemented using linear phase
digital filter architectures that deliver precise control over the
BT and alpha filter parameters, and guarantee a transmit spectrum
that is very stable over temperature and supply variation.
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied
by the transmitted spectrum by digitally prefiltering the transmit
data. The BT product of the Gaussian filter used is 0.5.
Gaussian filtering can only be used with 2FSK modulation. This
is selected by setting R2_DB[4:6] to 001.
Raised Cosine Filtering
Raised cosine filtering provides digital prefiltering of the transmit
data by using a raised cosine filter with a roll-off factor (alpha)
of either 0.5 or 0.7. The alpha is set to 0.5 by default, but the
raised cosine filter bandwidth can be increased to provide less
aggressive data filtering by using an alpha of 0.7 (set R2_DB30
to Logic 1). Raised cosine filtering can be used with 2FSK,
3FSK, and 4FSK.
Raised cosine filtering is enabled by setting R2_DB[4:6] as
outlined in Table 11.
Tx DATA
SYMBOL
FREQUENCIES
f
t
+3
f
DEV
+
f
DEV
–
f
DEV
–3
f
DEV
00011011
05876-016
Data Sheet ADF7021
Rev. D | Page 29 of 62
MODULATION AND FILTERING OPTIONS
The various modulation and data filtering options are described
in Table 11.
Table 11. Modulation and Filtering Options
Modulation Data Filtering R2_DB[4:6]
BINARY FSK
2FSK None 000
MSK1 None 000
OQPSK with half sine
baseband shaping2
None 000
GFSK Gaussian 001
GMSK3 Gaussian 001
RC2FSK Raised cosine 101
Oversampled 2FSK None 100
3-LEVEL FSK
3FSK None 010
RC3FSK Raised cosine 110
4-LEVEL FSK
4FSK None 011
RC4FSK Raised cosine 111
1 MSK is 2FSK modulation with a modulation index = 0.5.
2 Offset quadrature phase shift keying (OQPSK) with half sine baseband
shaping is spectrally equivalent to MSK.
3 GMSK is GFSK with a modulation index = 0.5.
TRANSMIT LATENCY
Transmit latency is the delay time from the sampling of a
bit/symbol by the TxRxCLK signal to when that bit/symbol
appears at the RF output. The latency without any data filtering
is 1 bit. The addition of data filtering adds a further latency as
outlined in Table 12.
It is important that the ADF7021 be left in transmit mode after
the last data bit is sampled by the data clock to account for this
latency. Maintain the ADF7021 in transmit mode for a time
equal to the number of latency bit periods for the applied
modulation scheme. This ensures that all of the data sampled by
the TxRxCLK signal appears at RF.
The figures for latency in Table 12 assume that the positive
TxRxCLK edge is used to sample data (default). If the TxRxCLK
is inverted by setting R2_DB[28:29], an additional 0.5 bit
latency can be added to all values in Table 12.
Table 12. Bit/Symbol Latency in Transmit Mode for Various
Modulation Schemes
Modulation Latency
2FSK 1 bit
GFSK 4 bits
RC2FSK, Alpha = 0.5 5 bits
RC2FSK, Alpha = 0.7 4 bits
3FSK 1 bit
RC3FSK, Alpha = 0.5 5 bits
RC3FSK, Alpha = 0.7 4 bits
4FSK 1 symbol
RC4FSK, Alpha = 0.5 5 symbols
RC4FSK, Alpha = 0.7 4 symbols
TEST PATTERN GENERATOR
The ADF7021 has a number of built-in test pattern generators
that can be used to facilitate radio link setup or RF measurement.
A full list of the supported patterns is shown in Table 13. The
data rate for these test patterns is the programmed data rate set
in Register 3.
The PN9 sequence is suitable for test modulation when carrying
out adjacent channel power (ACP) or occupied bandwidth
measurements.
Table 13. Transmit Test Pattern Generator Options
Test Pattern R15_DB[8:10]
Normal 000
Transmit Carrier 001
Transmit + fDEV tone 010
Transmit − fDEV tone 011
Transmit 1010 pattern 100
Transmit PN9 sequence 101
Transmit SWD pattern repeatedly 110
ADF7021 Data Sheet
Rev. D | Page 30 of 62
RECEIVER SECTION
RF FRONT END
The ADF7021 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from powerline-
induced interference problems.
Figure 44 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption to best suit their application.
To achieve a high level of resilience against spurious reception,
the low noise amplifier (LNA) features a differential input.
Switch SW2 shorts the LNA input when transmit mode is
selected (R0_DB27 = 0). This feature facilitates the design of a
combined LNA/PA matching network, avoiding the need for an
external Rx/Tx switch. See the LNA/PA Matching section for
details on the design of the matching network.
Figure 44. RF Front End
The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 100 kHz.
An important consideration is that the output frequency of the
synthesizer must be programmed to a value 100 kHz below the
center frequency of the received channel. The LNA has two
basic operating modes: high gain/low noise mode and low
gain/low power mode. To switch between these two modes, use
the LNA_MODE bit (R9_DB25). The mixer is also configurable
between a low current and an enhanced linearity mode using
the MIXER_LINEARITY bit (R9_DB28).
Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust the LNA_MODE
bit and MIXER_LINEARITY bit as outlined in Table 14.
The gain of the LNA is configured by the LNA_GAIN bits
(R9_DB[20:21]) and can be set by either the user or the
automatic gain control (AGC) logic.
IF FILTER
IF Filter Settings
Out-of-band interference is rejected by means of a fifth-order
Butterworth polyphase IF filter centered on a frequency of
100 kHz. The bandwidth of the IF filter can be programmed to
12.5 kHz, 18.75 kHz, or 25 kHz by R4_DB[30:31]; choose the
filter value as a compromise between interference rejection and
attenuation of the desired signal.
If the AGC loop is disabled, the gain of the IF filter can be set to one
of three levels by using the FILTER_GAIN bits (R9_DB[22:23]).
The filter gain is adjusted automatically if the AGC loop is
enabled.
IF Filter Bandwidth and Center Frequency Calibration
To compensate for manufacturing tolerances, calibrate the IF filter
after power-up to ensure that the bandwidth and center frequency
are correct. Coarse and fine calibration schemes are provided to
offer a choice between fast calibration (coarse calibration) and
high filter centering accuracy (fine calibration). Coarse
calibration is enabled by setting R5_DB4 high. Fine calibration
is enabled by setting R6_DB4 high.
For details on when it is necessary to perform a filter
calibration, and in what applications to use either a coarse
calibration or fine calibration, refer to the IF Filter Bandwidth
Calibration section.
It is necessary to do a coarse calibration before doing a fine
calibration. If the IF_FINE_CAL bit (R6_DB4) has already been
configured high, it is possible to do a fine calibration by writing
only to Register 5. Once initiated by writing to the device, the
calibration is performed automatically without any user inter-
vention. Calibration time is 200 μs for coarse calibration and a
few milliseconds for fine calibration, during which time the
ADF7021 must not be accessed. The IF filter calibration logic
requires that the IF_FILTER_DIVIDER bits (R5_DB[5:13]) be set
such that
kHz50
__
[Hz]
DIVIDERFILTERIF
XTAL
IF Filter Fine Calibration Overview
The fine calibration uses two internally generated tones at
certain offsets around the IF filter. The LNA is temporarily
detached from the receiver chain to ensure that external signals
do not affect the calibration. The two tones are attenuated by
the IF filter, and the level of this attenuation is measured using
the RSSI. The filter center frequency is adjusted to allow equal
attenuation of both tones. The attenuation of the two test tones
is then remeasured. This continues for a maximum of 10 RSSI
measurements, at which stage the calibration algorithm sets the
IF filter center frequency to within 0.5 kHz of 100 kHz.
The frequency of these tones is set by the following bits:
IF_CAL_LOWER_TONE_DIVIDER (R6_DB[5:12])
IF_CAL_UPPER_TONE_DIVIDER (R6_DB[13:20])
It is recommended to place the lower and upper tones as close
as possible to 65.8 kHz and 131.5 kHz, respectively, as outlined
in the following equations:
kHz8.65
2____
DIVIDETONELOWERCALIF
XTAL
SW2 LNA
RFIN
RFINB
T
x/Rx SELECT
(R0_DB27)
LNA MODE
(R9_DB25)
LNA CURRENT
(R9_DB[26:27])
MIXER LINEARITY
(R9_DB28)
LO
I (TO FILTER)
Q (TO FILTER)
LNA GAIN
(R9_DB[20:21])
LNA/MIXER ENABLE
(R8_DB6)
05876-017
Data Sheet ADF7021
Rev. D | Page 31 of 62
kHz5.131
2____
DIVIDETONEUPPERCALIF
XTAL
The calibration algorithm adjusts the filter center frequency
and measures the RSSI 10 times during the calibration. The
time for an adjustment plus RSSI measurement is given by
CLKSEQ
LL_TIMEIF_CAL_DWE
TimenCalibratioToneIF
It is recommended that the IF tone calibration time be at least
500 μs. The total time for the IF filter fine calibration is given by
IF Filter Fine Calibration Time = IF Tone Calibration Time × 10
RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband (BB) channel filtering. The log amp
achieves ±3 dB log linearity. It also doubles as a limiter to
convert the signal-to-digital levels for the FSK demodulator.
The offset correction circuit uses the BBOS_CLK_DIVIDE bits
(R3_DB[4:5]), which must be set between 1 MHz and 2 MHz.
The RSSI level is converted for user readback and for digitally
controlled AGC by an 80-level (7-bit) flash ADC. This level can
be converted to input power in dBm. By default, the AGC is on
when powered up in receive mode.
Figure 45. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD
(R9_DB[11:17]), the gain is reduced. When the RSSI is
below AGC_LOW_THRESHOLD (R9_DB[4:10]), the gain
is increased. The thresholds default to 30 and 70 on power-up
in receive mode. A delay (set by AGC_CLOCK_DIVIDE,
R3_DB[26:31]) is programmed to allow for settling of the loop.
A value of 10 is recommended.
The user has the option of changing the two threshold values
from the defaults of 30 and 70 (Register 9). Ensure that the
default AGC setup values are adequate for most applications.
The threshold values must be chosen to be more than 30 apart
for the AGC to operate correctly.
Offset Correction Clock
In Register 3, set the BBOS_CLK_DIVIDE bits (R3_DB[4:5]) to
give a baseband offset clock (BBOS CLK) frequency between
1 MHz and 2 MHz.
BBOS CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)
where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32.
AGC Information and Timing
AGC is selected by default and operates by setting the appropriate
LNA and filter gain settings for the measured RSSI level. It is
possible to disable AGC by writing to Register 9 if the user wants to
enter one of the modes listed in Table 14. The time for the AGC
circuit to settle and, therefore, the time it takes to measure the RSSI
accurately, is typically 300 μs. However, this depends on how many
gain settings the AGC circuit has to cycle through. After each gain
change, the AGC loop waits for a programmed time to allow
transients to settle. This AGC update rate is set according to
AGC Update Rate [Hz] = DIVIDECLKAGC
DIVIDECLKSEQ
__
[Hz]__
where:
AGC_CLK_DIVIDE is set by R3_DB[26:31]. A value of 10 is
recommended.
SEQ_CLK_DIVIDE = 100 kHz (R3_DB[18:25]).
By using the recommended setting for AGC_CLK_DIVIDE, the
total AGC settling time is
[Hz]
[sec] RateUpdateAGC
ChangesGainAGCofNumber
TimeSettlingAGC
The worst case for AGC settling is when the AGC control loop
has to cycle through all five gain settings, which gives a maximum
AGC settling time of 500 μs.
Table 14. LNA/Mixer Modes
Receiver Mode
LNA_MODE
(R9_DB25)
LNA_GAIN
(R9_DB[20:21])
MIXER_LINEARITY
(R9_DB28)
Sensitivity (2FSK,
DR = 4.8 kbps, fDEV = 4 kHz)
Rx Current
Consumption (mA)
Input IP3
(dBm)
High Sensitivity Mode
(Default)
0 +30 0 −118 +24.6 −24
Enhanced Linearity
High Gain
0 +30 +1 −114.5 +24.6 −20
Medium Gain +1 +10 0 −112 +22.1 −13.5
Enhanced Linearity
Medium Gain
+1 +10 +1 −105.5 +22.1 −9
Low Gain +1 +3 0 −100 +22.1 −5
Enhanced Linearity
Low Gain
+1 +3 +1 −92.3 +22.1 −3
05876-018
1
IFWR IFWR IFWR IFWR
LATCHAAA
R
CLK
ADC
OFFSET
CORRECTION
RSSI
FSK
DEMOD
ADF7021 Data Sheet
Rev. D | Page 32 of 62
RSSI Formula (Converting to dBm)
The RSSI formula is
Input Power [dBm] =
−130 dBm + (Readback Code + Gain Mode Correction) × 0.5
where:
Readback Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
Gain Mode Correction is given by the values in Table 15.
The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values
are also obtained from the readback register, as part of an RSSI
readback.
Table 15. Gain Mode Correction
LNA Gain (LG2, LG1) Filter Gain (FG2, FG1)
Gain Mode
Correction
H (1, 0) H (1, 0) 0
M (0, 1) H (1, 0) 24
M (0, 1) M (0, 1) 38
M (0, 1) L (0, 0) 58
L (0, 0) L (0, 0) 86
Introduce an additional factor to account for losses in the front-
end-matching network/antenna.
DEMODULATION, DETECTION, AND CDR
System Overview
An overview of the demodulation, detection, and clock and
data recovery (CDR) of the received signal on the ADF7021 is
shown in Figure 46.
The quadrature outputs of the IF filter are first limited and then
fed to either the correlator FSK demodulator or the linear FSK
demodulator. The correlator demodulator is used to demodulate
2FSK, 3FSK, and 4FSK. The linear demodulator is used for
frequency measurement and is enabled when the AFC loop
is active. The linear demodulator can also be used to
demodulate 2FSK.
Following the demodulator, a digital post demodulator filter
removes excess noise from the demodulator signal output.
Threshold/slicer detection is used for data recovery of 2FSK
and 4FSK. Data recovery of 3FSK can be implemented using
either threshold detection or Viterbi detection.
An on-chip CDR PLL is used to resynchronize the received bit
stream to a local clock. It outputs the retimed data and clock on
the TxRxDATA and TxRxCLK pins, respectively.
Figure 46. Overview of Demodulation, Detection, and CDR Process
Correlator Demodulator
The correlator demodulator can be used for 2FSK, 3FSK, and
4FSK demodulation. Figure 47 shows the operation of the
correlator demodulator for 2FSK.
Figure 47. 2FSK Correlator Demodulator Operation
The quadrature outputs of the IF filter are first limited and then
fed to a digital frequency correlator that performs filtering and
frequency discrimination of the 2FSK/3FSK/4FSK spectrum.
For 2FSK modulation, data is recovered by comparing the
output levels from two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of additive white Gaussian noise (AWGN). This
method of FSK demodulation provides approximately 3 dB to
4 dB better sensitivity than a linear demodulator.
POST
DEMOD FILTER
I
Q
LIMITERS
VITERBI
DETECTION
MUX
CLOCK
AND
DATA
RECOVERY
TxRxDATA
TxRx CLK
FREQUENCY
CORRELATOR
LINEAR
DEMODULATOR
MUX
3FSK
05876-080
THRESHOLD
DETECTION
2/3/4FSK
IF –
f
DEV
IF +
f
DEV
I
IF
Q
LIMITERS
R4_DB(10:19)
R4_DB7
DOT/CROSS PRODUCT
FREQUENCY COR
R
ELATOR
DISCRIMINATOR BW
R4_DB9
Rx DATA INVERT
DISCRIM BW
2FSK = +1, –1
3FSK = +1, 0, –1
4FSK = +3, +1, –1, –3
OUTPUT LEVELS:
05876-079
Data Sheet ADF7021
Rev. D | Page 33 of 62
Linear Demodulator
Figure 48 shows a block diagram of the linear demodulator.
Figure 48. Block Diagram of Linear FSK Demodulator
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is filtered and averaged using a combined
averaging filter and envelope detector. The demodulated 2FSK
data from the post demodulator filter is recovered by threshold
detecting the envelope detector output, as shown in Figure 48.
This method of demodulation corrects for frequency errors
between transmitter and receiver when the received spectrum
is close to or within the IF bandwidth. This envelope detector
output is also used for AFC readback and provides the frequency
estimate for the AFC control loop.
Post Demodulator Filter
A second-order, digital low-pass filter removes excess noise from
the demodulated bit stream at the output of the discriminator.
The bandwidth of this post demodulator filter is programmable
and must be optimized for the data rate of the user and received
modulation type. If the bandwidth is set too narrow, performance
degrades due to intersymbol interference (ISI). If the bandwidth
is set too wide, excess noise degrades the performance of the
receiver. The POST_DEMODULATOR_BW bits
(R4_DB[20:29]) set the bandwidth of this filter.
2FSK Bit Slicer/Threshold Detection
2FSK demodulation can be implemented using the correlator
FSK demodulator or the linear FSK demodulator. In both cases,
threshold detection is used for data recovery at the output of the
post demodulation filter.
The output signal levels of the correlator demodulator are
always centered about zero. Therefore, the slicer threshold level
can be fixed at zero, and the demodulator performance is
independent of the run-length constraints of the transmit data
bit stream. This results in robust data recovery that does not
suffer from the classic baseline wander problems that exist in
the more traditional FSK demodulators.
When the linear demodulator is used for 2FSK demodulation,
the output of the envelope detector is used as the slicer threshold,
and this output tracks frequency errors that are within the IF
filter bandwidth.
3FSK and 4FSK Threshold Detection
4FSK demodulation is implemented using the correlator
demodulator followed by the post demodulator filter and threshold
detection. The output of the post demodulation filter is a 4-level
signal that represents the transmitted symbols (−3, −1, +1, +3).
Threshold detection of 4FSK requires three threshold settings,
one that is always fixed at 0 and two that are programmable and
are symmetrically placed above and below 0 using the
3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]).
3FSK demodulation is implemented using the correlator
demodulator, followed by a post demodulator filter. The output
of the post demodulator filter is a 3-level signal that represents
the transmitted symbols (−1, 0, +1). Data recovery of 3FSK can
be implemented using threshold detection or Viterbi detection.
Threshold detection is implemented using two thresholds that
are programmable and are symmetrically placed above and
below zero using the 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]).
3FSK Viterbi Detection
Viterbi detection of 3FSK operates on a four-state trellis and is
implemented using two interleaved Viterbi detectors operating
at half the symbol rate. The Viterbi detector is enabled by
R13_DB11.
To facilitate different run length constraints in the transmitted
bit stream, the Viterbi path memory length is programmable
in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the
VITERBI_PATH_MEMORY bits (R13_DB[13:14]). Set this
equal to or longer than the maximum number of consecutive
0s in the interleaved transmit bit stream.
When used with Viterbi detection, the receiver sensitivity
for 3FSK is typically +3 dB better than that obtained using
threshold detection. When the Viterbi detector is enabled,
however, the receiver bit latency is increased by twice the
Viterbi path memory length.
Clock Recovery
An oversampled digital clock and data recovery (CDR) PLL is used
to resynchronize the received bit stream to a local clock in all
modulation modes. The oversampled clock rate of the PLL (CDR
CLK) must be set at 32 times the symbol rate (see the Register 3—
Transmit/Receive Clock Register sec t ion). Th e max imum dat a/
symbol rate tolerance of the CDR PLL is determined by the
number of zero-crossing symbol transitions in the transmitted
packet. For example, if using 2FSK with a 101010 preamble, a
maximum tolerance of ±3.0% of the data rate is achieved. However,
this tolerance is reduced during recovery of the remainder of
the packet where symbol transitions may not be guaranteed to
occur at regular intervals. To maximize the data rate tolerance
of the CDR, some form of encoding and/or data scrambling is
recommended that guarantees a number of transitions at
regular intervals. For example, using 2FSK with Manchester-
encoded data achieves a data rate tolerance of ±2.0%.
0
5876-073
POST DEMOD
FILTER
ENVELOPE
DETECTOR
SLICER
2FSK
FREQUENCY
IF
LEVEL
I
Q
LIMITER
LINEAR
DISCRIMINATOR
R4_DB(20:29)
FREQUENCY
READBACK
AND AFC LOOP
+2FSK Rx DATA
RxCLK
ADF7021 Data Sheet
Rev. D | Page 34 of 62
The CDR PLL is designed for fast acquisition of the recovered
symbols during preamble and typically achieves bit synchronization
within 5-symbol transitions of preamble.
In 4FSK modulation, the tolerance using the +3, −3, +3, −3
preamble is ±3% of the symbol rate (or ±1.5% of the data rate).
However, this tolerance is reduced during recovery of the
remainder of the packet where symbol transitions may not be
guaranteed to occur at regular intervals. To maximize the symbol/
data rate tolerance, construct the remainder of the 4FSK packet
so that the transmitted symbols retain close to dc-free properties by
using data scrambling and/or by inserting specific dc balancing
symbols that are inserted in the transmitted bit stream at regular
intervals such as after every 8 or 16 symbols.
In 3FSK modulation, the linear convolutional encoder scheme
guarantees that the transmitted symbol sequence is dc-free,
facilitating symbol detection. However, Tx data scrambling is
recommended to limit the run length of zero symbols in the
transmit bit stream. Using 3FSK, the CDR data rate tolerance is
typically ±0.5%.
RECEIVER SETUP
Correlator Demodulator Setup
To enable the correlator for various modulation modes, refer to
Table 16.
Table 16. Enabling the Correlator Demodulator
Received Modulation DEMOD_SCHEME (R4_DB[4:6])
2FSK 001
3FSK 010
4FSK 011
To optimize receiver sensitivity, the correlator bandwidth must be
optimized for the specific deviation frequency and modulation
used by the transmitter. The discriminator bandwidth is
controlled by R4_DB[10:19] and is defined as
3
10400
_
KCLKDEMOD
BWTORDISCRIMINA
where:
DEMOD CLK is as defined in the Register 3—Transmit/Receive
Clock Register section.
K is set for each modulation mode according to the following:
For 2FSK,
DEV
f
RoundK
3
10100
For 3FSK,
DEV
f
RoundK 2
10100 3
For 4FSK,
DEV
FSK f
RoundK 4
10100 3
4
where:
Round is rounded to the nearest integer.
Round4FSK is rounded to the nearest of the following integers: 32,
31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.
fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is
the frequency deviation used for the ±1 symbols (that is, the
inner frequency deviations).
To optimize the coefficients of the correlator, R4_DB7 and
R4_DB[8:9] must also be assigned. The value of these bits
depends on whether K is odd or even. These bits are assigned
according to Table 17 and Table 18.
Table 17. Assignment of Correlator K Value for 2FSK and 3FSK
K K/2 (K + 1)/2 R4_DB7 R4_DB[8:9]
Even Even Not applicable 0 00
Even Odd Not applicable 0 10
Odd Not applicable Even 1 00
Odd Not applicable Odd 1 10
Table 18. Assignment of Correlator K Value for 4FSK
K R4_DB7 R4_DB[8:9]
Even 0 00
Odd 1 00
Linear Demodulator Setup
The linear demodulator can be used for 2FSK demodulation. To
enable the linear demodulator, set the DEMOD_SCHEME bits
(R4_DB[4:6]) to 000.
Post Demodulator Filter Setup
Set the 3 dB bandwidth of the post demodulator filter according
to the received modulation type and data rate. The bandwidth is
controlled by R4_DB[20:29] and is given by
CLKDEMOD
f
BWDEMODPOST CUTOFF
π2
__
11
where fCUTOFF is the target 3 dB bandwidth in Hz of the post
demodulator filter. Round up POST_DEMOD_BW to the
nearest integer value.
Table 19. Post Demodulator Filter Bandwidth Settings for
2FSK/3FSK/4FSK Modulation Schemes
Received Modulation
Post Demodulator Filter Bandwidth,
fCUTOFF (Hz)
2FSK 0.75 × data rate
3FSK 1 × data rate
4FSK 1.6 × symbol rate (= 0.8 × data rate)
Data Sheet ADF7021
Rev. D | Page 35 of 62
3FSK Viterbi Detector Setup
The Viterbi detector can be used for 3FSK data detection. This
is activated by setting R13_DB11 to Logic 1.
The Viterbi path memory length is programmable in steps of 4,
6, 8, or 32 bits (VITERBI_PATH_MEMORY, R13_DB[13:14]).
Set the path memory length equal to or greater than the maximum
number of consecutive 0s in the interleaved transmit bit stream.
The Viterbi detector also uses threshold levels to implement the
maximum likelihood detection algorithm. These thresholds are
programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]).
These bits are assigned as follows:
3FSK/4FSK_SLICER_THRESHOLD =
×
×
×3
10100
75 KDeviationrequencyTransmit F
where K is the value calculated for correlator discriminator
bandwidth.
3FSK Threshold Detector Setup
To activate threshold detection of 3FSK, set R13_DB11 to
Logic 0. Set the 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]) as outlined in the 3FSK Viterbi Detector Setup
section.
3FSK CDR Setup
In 3FSK, a transmit preamble of at least 40 bits of continuous 1s
is recommended to ensure a maximum number of symbol
transitions for the CDR to acquire lock.
The clock and data recovery for 3FSK requires a number of
parameters in Register 13 to be set (see Table 20).
4FSK Threshold Detector Setup
The threshold for the 4FSK detector is set using the
3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]).
Set the threshold according to
3FSK/4FSK_SLICER_THRESHOLD =
×
×
×
3
10100
8
7 K
Deviation
TxOuter4FSK
where K is the value calculated for correlator discriminator
bandwidth.
Table 20. 3FSK CDR Settings
Parameter Recommended Setting Purpose
PHASE_CORRECTION (R13_DB12) 1 Phase correction on
3FSK_CDR_THRESHOLD (R13_DB[15:21])
×
×
×3
10100
62 KDeviationrequencyTransmit F
where K is the value calculated for
correlator discriminator bandwidth.
Sets CDR decision threshold levels
3FSK_PREAMBLE_TIME_VALIDATE (R13_DB [22:25]) 1111 Preamble detector time qualifier
ADF7021 Data Sheet
Rev. D | Page 36 of 62
DEMODULATOR CONSIDERATIONS
2FSK Preamble
The recommended preamble bit pattern for 2FSK is a dc-free
pattern (such as a 10101010… pattern). Preamble patterns with
longer run-length constraints (such as 11001100…) can also be
used but result in a longer synchronization time of the received
bit stream in the receiver. The preamble needs to allow enough
bits for AGC settling of the receiver and CDR acquisition. A
minimum of 16 preamble bits is recommended. When the receiver
is using the internal AFC, the minimum recommended number
of preamble bits is 48.
The remaining fields that follow the preamble header do not
have to use dc-free coding. For these fields, the ADF7021 can
accommodate coding schemes with a run length of up to
eight bits without any performance degradation. If longer run
lengths are required, an encoding scheme such as 8B/10B or
Manchester encoding is recommended.
4FSK Preamble and Data Coding
The recommended preamble bit pattern for 4FSK is a repeating
00100010… bit sequence. This 2-level sequence of repeating
−3, +3, −3, +3 symbols is dc-free and maximizes the symbol
timing performance and data recovery of the 4FSK preamble in
the receiver. The minimum recommended length of the
preamble is 32 bits (16 symbols).
Construct the remainder of the 4FSK packet so that the
transmitted symbols retain close to dc-free property by using
data scrambling and/or by inserting specific dc balancing
symbols in the transmitted bit stream at regular intervals, such
as after every 8 or 16 symbols.
2FSK Correlator Demodulator and Frequency Errors
The ADF7021 has a number of options to combat frequency
errors that exist due to mismatches between the transmit and
receive crystals/TCXOs.
With AFC disabled, the correlator demodulator is tolerant to
frequency errors over the ±0.4 × fDEV range, where fDEV is the
FSK frequency deviation. For larger frequency errors, the
frequency tolerance can be widened to ±0.8 × fDEV by adjusting
the value of K and thus doubling the correlator bandwidth.
Calculate K as
×
×
=
DEV
f
RoundK 2
10100
3
Recalculate the DISCRIMINATOR_BW setting using the new K
value. Doubling the correlator bandwidth to improve frequency
error tolerance in this manner typically results in a 1 dB to 2 dB
loss in receiver sensitivity.
Correlator Demodulator and Low Modulation Indices
The modulation index in 2FSK is defined as
RateData
f
IndexModulation
DEV
×
=2
The receiver sensitivity performance can be maximized at low
modulation index by increasing the discriminator bandwidth of
the correlator demodulator. For modulation indices of less than
0.4, it is recommended to double the correlator bandwidth by
calculating K as follows:
×
=
DEV
f
3
Round
K2
e100
Recalculate the DISCRIMINATOR_BW using the new K value.
Figure 26 highlights the improved sensitivity that can be achieved
for 2FSK modulation, at low modulation indices, by doubling
the correlator bandwidth.
AFC OPERATION
The ADF7021 also supports a real-time AFC loop that is used
to remove frequency errors due to mismatches between the
transmit and receive crystals/TCXOs. The AFC loop uses the
linear frequency discriminator block to estimate frequency
errors. The linear FSK discriminator output is filtered and
averaged to remove the FSK frequency modulation using a
combined averaging filter and envelope detector. In receive
mode, the output of the envelope detector provides an estimate
of the average IF frequency.
Two methods of AFC supported on the ADF7021 are external
and internal.
External AFC
Here, the user reads back the frequency information through
the ADF7021 serial port and applies a frequency correction
value to the fractional-N synthesizer-N divider.
The frequency information is obtained by reading the 16-bit
signed AFC readback, as described in the Readback Format
section, and by applying the following formula:
Frequency Readback [Hz] =
(AFC_READBACK × DEMOD CLK)/218
Although the AFC_READBACK value is a signed number, under
normal operating conditions, it is positive. In the absence of
frequency errors, the frequency readback value is equal to the
IF frequency of 100 kHz.
Internal AFC
The ADF7021 supports a real-time, internal, automatic
frequency control loop. In this mode, an internal control loop
automatically monitors the frequency error and adjusts the
synthesizer-N divider using an internal proportional integral
(PI) control loop.
The internal AFC control loop parameters are controlled in
Register 10. The internal AFC loop is activated by setting R10_DB4
to 1. A scaling coefficient must also be entered, based on the crystal
frequency in use. This is set up in R10_DB[5:16] and can be
calculated using
×
=XTAL
RoundFACTORSCALINGAFC 5002
__
24
Data Sheet ADF7021
Rev. D | Page 37 of 62
Maximum AFC Range
The maximum frequency correction range of the AFC loop is
programmable on the ADF7021. This is set by R10_DB[24:31].
The maximum AFC correction range is the difference in
frequency between the upper and lower limits of the AFC
tuning range. For example, if the maximum AFC correction
range is set to 10 kHz, the AFC can adjust the receiver LO
within the fLO ± 5 kHz range.
However, when RF_DIVIDE_BY_2 (R1_DB18) is enabled, the
programmed range is halved. Account for this halving by
doubling the programmed maximum AFC range.
The recommended maximum AFC correction range is ≤1.5 × IF
filter bandwidth. If the maximum frequency correction range is
set to be > 1.5 × IF bandwidth, the attenuation of the IF filter
can degrade the AFC loop sensitivity.
The adjacent channel rejection (ACR) performance of the
receivers can be degraded when AFC is enabled and the AFC
correction range is close to the IF filter bandwidth. However,
because the AFC correction range is programmable, the user
can trade off correction range and ACR performance.
When AFC errors are removed using either the internal or
external AFC, further improvement in receiver sensitivity can
be obtained by reducing the IF filter bandwidth using the
IF_BW bits (R4_DB[30:31]).
AUTOMATIC SYNC WORD DETECTION (SWD)
The ADF7021 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7021. In receive mode, this
preprogrammed word is compared to the received bit stream.
When a valid match is identified, the external SWD pin is
asserted by the ADF7021 on the next Rx clock pulse.
This feature can be used to alert the microprocessor that a
valid channel has been detected. It relaxes the computational
requirements of the microprocessor and reduces the overall
power consumption.
The SWD signal can also be used to frame the received packet
by staying high for a preprogrammed number of bytes. The data
packet length can be set in R12_DB[8:15].
The SWD pin status can be configured by setting R12_DB[6:7].
R11_DB[4:5] are used to set the length of the sync/ID word, which
can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended
to minimize false sync word detection in the receiver that can
occur during recovery of the remainder of the packet or when
noise/no signal is present at the receiver input. The transmitter
must transmit the sync byte MSB first and the LSB last to ensure
proper alignment in the receiver sync-byte-detection hardware.
An error tolerance parameter can also be programmed that
accepts a valid match when up to 3 bits of the word are incorrect.
The error tolerance value is assigned in R11_DB[6:7].
ADF7021 Data Sheet
Rev. D | Page 38 of 62
APPLICATIONS INFORMATION
IF FILTER BANDWIDTH CALIBRATION
Calibrate the IF filter on every power-up in receive mode to
correct for errors in the bandwidth and filter center frequency
due to process variations. The automatic calibration requires no
external intervention once it is initiated by a write to Register 5.
Depending on numerous factors, such as IF filter bandwidth,
received signal bandwidth, and temperature variation, the user
must determine whether to carry out a coarse calibration or a
fine calibration. For information on calibration setup, refer to
the IF Filter section.
The performance of both calibration methods is outlined in
Table 21.
Table 21. IF Filter Calibration Specifications
Filter Calibration
Method
Center Frequency
Accuracy1
Calibration
Time (Typ)
Coarse Cal 100 kHz ± 2.5 kHz 200 µs
Fine Cal 100 kHz ± 0.5 kHz 5.2 ms
1 After calibration.
When to Use Coarse Calibration
It is recommended to perform a coarse calibration on every
receive mode power-up. This calibration typically takes 200 µs.
The FILTER_CAL_COMPLETE signal from MUXOUT can be
used to monitor the filter calibration duration or to signal the
end of calibration. Do not access the ADF7021 during
calibration.
When to Use a Fine Calibration
In cases where the receive signal bandwidth is very close to the
bandwidth of the IF filter, it is recommended to perform a fine
filter calibration every time the unit powers up in receive mode.
Perform a fine calibration if
OBW + Coarse Calibration Variation > IF_FILTER_BW
where:
OBW is the 99% occupied bandwidth of the transmit signal.
Coarse Calibration Variation is 2.5 kHz.
IF_FILTER_BW is set by R4_DB[30:31].
The FILTER_CAL_COMPLETE signal from MUXOUT (set
by R0_DB[29:31]) can be used to monitor the filter calibration
duration or to signal the end of calibration. A coarse filter
calibration is automatically performed prior to a fine filter
calibration.
When to Use Single Fine Calibration
In applications where the receiver powers up numerous times in
a short period, it is only necessary to perform a one-time fine
calibration on the initial receiver power-up.
After the initial coarse calibration and fine calibration, the result of
the fine calibration can be read back through the serial interface
using the FILTER_CAL_READBACK result (refer to the Filter
Bandwidth Calibration Readback section). On subsequent
power-ups in receive mode, the filter is manually adjusted using
the previous fine filter calibration result. This manual adjust is
performed using the IF_FILTER_ADJUST bits (R5_DB[14:19]).
Use this method only if the successive power-ups in receive
mode are over a short duration, during which time there is little
variation in temperature (<15°C).
IF Filter Variation with Temperature
When calibrated, the filter center frequency can vary with changes
in temperature. If the ADF7021 is used in an application where it
remains in receive mode for a considerable length of time, the
user must consider this variation of filter center frequency with
temperature. This variation is typically 0.7 kHz per 10°C, which
means that if a coarse filter calibration and fine filter calibration
are performed at 25°C, the initial maximum error is ±0.5 kHz,
and the maximum possible change in the filter center frequency
over temperature (−40°C and +85°C) is ±4.5 kHz. This gives a
total error of ±5 kHz.
If the receive signal occupied bandwidth is considerably less
than the IF filter bandwidth, the variation of filter center frequency
over the operating temperature range may not be an issue.
Alternatively, if the IF filter bandwidth is not wide enough to
tolerate the variation with temperature, a periodic filter calibration
can be performed, or alternatively, the on-chip temperature
sensor can be used to determine when a filter calibration is
necessary by monitoring for changes in temperature.
LNA/PA MATCHING
The ADF7021 exhibits optimum performance in terms of
sensitivity, transmit power, and current consumption, only if
its RF input and output ports are properly matched to the antenna
impedance. For cost sensitive applications, the ADF7021 is
equipped with an internal Rx/Tx switch that facilitates the
use of a simple, combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch such as the ADG919 can
be used, which yields a slightly improved receiver sensitivity
and lower transmitter power consumption.
Internal Rx/Tx Switch
Figure 49 shows the ADF7021 in a configuration where the
internal Rx/Tx switch is used with a combined LNA/PA
matching network. This is the configuration used on the EVAL-
ADF7021DB evaluation boards. For most applications, the slight
performance degradation of 1 dB to 2 dB caused by the internal
Rx/Tx switch is acceptable, allowing the user to take advantage
of the cost saving potential of this solution. The design of the
combined matching network must compensate for the reactance
presented by the networks in the Tx and the Rx paths, taking
the state of the Rx/Tx switch into consideration.
Data Sheet ADF7021
Rev. D | Page 39 of 62
Figure 49. ADF7021 with Internal Rx/Tx Switch
The procedure typically requires several iterations until an
acceptable compromise has been reached. The successful
implementation of a combined LNA/PA matching network
for the ADF7021 is critically dependent on the availability of an
accurate electrical model for the PCB. In this context, the use of
a suitable CAD package is strongly recommended. To avoid this
effort, a small form-factor reference design for the ADF7021 is
provided, including matching and harmonic filter components.
The design is on a 2-layer PCB to minimize cost. Gerber files are
available on the product page at www.analog.com/ADF7021.
External Rx/Tx Switch
Figure 50 shows a configuration using an external Rx/Tx
switch. This configuration allows an independent optimization
of the matching and filter network in the transmit and receive
path. Therefore, it is more flexible and less difficult to design
than the configuration using the internal Rx/Tx switch. The PA is
biased through Inductor L1, while C1 blocks dc current. Together,
L1 and C1 form the matching network that transforms the source
impedance into the optimum PA load impedance, ZOPT_PA.
Figure 50. ADF7021 with External Rx/Tx Switch
ZOPT_PA depends on various factors, such as the required output
power, the frequency range, the supply voltage range, and the
temperature range. Selecting an appropriate ZOPT_PA helps to
minimize the Tx current consumption in the AN-764 Application
Note contains a number of ZOPT_PA values for representative
conditions. Under certain conditions, however, it is recommended
to obtain a suitable ZOPT_PA value by means of a load-pull
measurement.
Due to the differential LNA input, the LNA matching network
must be designed to provide both a single-ended-to-differential
conversion and a complex, conjugate impedance match. The
network with the lowest component count that can satisfy these
requirements is the configuration shown in Figure 50, consisting
of two capacitors and one inductor. A first-order implementation
of the matching network can be obtained by understanding the
arrangement as two L-type matching networks in a back-to-
back configuration. Due to the asymmetry of the network with
respect to ground, a compromise between the input reflection
coefficient and the maximum differential signal swing at the
LNA input must be established. The use of appropriate CAD
software is strongly recommended for this optimization.
Depending on the antenna configuration, the user may need a
harmonic filter at the PA output to satisfy the spurious emission
requirement of the applicable government regulations. The
harmonic filter can be implemented in various ways, such as
a discrete LC pi or T-stage filter. Dielectric low-pass filter
components, such as the LFL18924MTC1A052 (for operation in
the 915 MHz and 868 MHz band) by Murata Manufacturing Co.
Ltd., represent an attractive alternative to discrete designs. The
immunity of the ADF7021 to strong out-of-band interference can
be improved by adding a band-pass filter in the Rx path. Apart
from discrete designs, SAW or dielectric filter components such as
the SAFCH869MAM0T00, SAFCH915MAL0N00,
DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by
Murata Manufacturing Co. Ltd., are well-suited for this purpose.
Alternatively, the ADF7021 blocking performance can be improved
by selecting one of the enhanced linearity modes, as described in
Table 14.
IMAGE REJECTION CALIBRATION
The image channel in the ADF7021 is 200 kHz below the desired
signal. The polyphase filter rejects this image with an asymmetric
frequency response. The image rejection performance of the
receiver is dependent on how well matched the I and Q signals
are in amplitude, and how well matched the quadrature is
between them (that is, how close to 90° apart they are). The
uncalibrated image rejection performance is approximately
29 dB (at 450 MHz). However, it is possible to improve on this
performance by as much as 20 dB by finding the optimum I/Q
gain and phase adjust settings.
Calibration Using Internal RF Source
With the LNA powered off, an on-chip generated, low level RF
tone is applied to the mixer inputs. The LO is adjusted to make
the tone fall at the image frequency where it is attenuated by the
image rejection of the IF filter. The power level of this tone is then
measured using the RSSI readback. The I/Q gain and phase adjust
DACs (R5_DB[20:31]) are adjusted and the RSSI is remeasured.
This process is repeated until the optimum values for the gain
and phase adjust are found that provide the lowest RSSI readback
level, thereby maximizing the image rejection performance of
the receiver.
PA
LNA
PA_OUT
RFIN
RFINB
V
BAT
L1
ADF7021
OPTIONAL
BPF OR LPF
L
A
C
A
C1
C
B
Z
IN
_RFIN
Z
OPT
_PA
Z
IN
_RFIN
A
NTENNA
05876-022
05876-021
PA
LNA
PA_OUT
RFIN
RFINB
V
BAT
L1
ADF7021
ADG919
OPTIONAL
BPF
(SAW)
OPTIONAL
LPF
L
A
C
A
C1
C
B
Z
IN
_RFIN
Z
OPT
_PA
Z
IN
_RFIN
ANTENNA
Rx/Tx – SELECT
ADF7021 Data Sheet
Rev. D | Page 40 of 62
Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller
Using the internal RF source, the RF frequencies that can be
utilized for image calibration are programmable and are odd
multiples of the reference frequency.
Calibration Using External RF Source
IR calibration can also be implemented using an external RF
source. The IR calibration procedure is the same as that used for
the internal RF source, except that an RF tone is applied to the
LNA input.
Calibration Procedure and Setup
The IR calibration algorithm available from Analog Devices, Inc. is
based on a low complexity, 2D optimization algorithm that can
be implemented in an external microprocessor or microcontroller.
To enable the internal RF source, set the IR_CAL_SOURCE_
DRIVE_LEVEL bits (R6_DB[28:29]) the maximum level. Set
the LNA to its minimum gain setting, and disable the AGC if
the internal source is being used. Alternatively, an external RF
source can be used.
The magnitude of the phase adjust is set by using the IR_PHASE_
ADJUST_MAG bits (R5_DB[20:23]). This correction can be
applied to either the I channel or Q channel, depending on the
value of the IR_PHASE_ADJUST_DIRECTION bit (R5_DB24).
The magnitude of the I/Q gain is adjusted by the IR_GAIN_
ADJUST_MAG bits (R5_DB[25:29]). This correction can be
applied to either the I or Q channel, depending on the value of
IR_GAIN_ADJUST_I/Q bit (R5_DB30), whereas the
IR_GAIN_ADJUST_UP/DN bit (R5_DB31) sets whether
the gain adjustment defines a gain or an attenuation adjust.
The calibration results are valid over changes in the ADF7021
supply voltage. However, there is some variation with temperature.
A typical plot of variation in image rejection over temperature
after initial calibrations at −40°C, +25°C, and +85°C is shown in
Figure 52. The internal temperature sensor on the ADF7021 can
be used to determine if a new IR calibration is required.
Figure 52. Image Rejection Variation with Temperature after Initial
Calibrations at −40°C, +25°C, and +85°C
INTERNAL
SIGNAL
SOURCE
MUX
RFIN
RFINB
LNA
ADF7021
POLYPHASE
IF FILTER
PHASE ADJUST
GAIN ADJUST
IQ
FROM LO
GAIN ADJUST
REGISTER 5
PHASE ADJUST
REGISTER 5
SERIAL
INTERFACE
4
MICROCONTROLLER
4
RSSI/
LOG AMP
7-BIT ADC
RSSI READBACK
I/Q GAIN/PHASE ADJUST AND
RSSI MEASUREMENT
ALGORITHM
05876-072
0
10
20
30
40
50
60
–60 –40 –20 0 20 40 60 80 100
V
DD
= 3.0V
IF BW = 25kHz
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
PRBS9
f
DEV
= 4kHz
LEVEL= –100dBm
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
PRBS11
f
DEV
= 4kHz
05876-067
TEMPERATURE (°C)
IMAGE REJECTION (dB)
CAL AT +25°C
CAL AT +85°C CAL AT –40°C
Data Sheet ADF7021
Rev. D | Page 41 of 62
PACKET STRUCTURE AND CODING
The suggested packet structure to use with the ADF7021 is
shown in Figure 53.
Figure 53. Typical Format of a Transmit Protocol
Refer to the Receiver Setup section for information on the
required preamble structure and length for the various modulation
schemes.
PROGRAMMING AFTER INITIAL POWER-UP
Table 22 lists the minimum number of writes needed to set up
the ADF7021 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the device to a
particular application, such as setting up sync byte detection or
enabling AFC. When going from Tx to Rx or vice versa, the
user needs to toggle the Tx/Rx bit and write only to Register 0
to alter the LO by 100 kHz.
Table 22. Minimum Register Writes Required for Tx/Rx Setup
Mode Registers
Tx Reg 1 Reg 3 Reg 0 Reg 2
Rx Reg 1 Reg 3 Reg 0 Reg 5 Reg 4
Tx to Rx and Rx to Tx Reg 0
The recommended programming sequences for transmit and
receive are shown in Figure 54 and Figure 55, respectively. The
difference in the power-up routine for a TCXO and XTAL
reference is shown in these figures.
PREAMBLE
SYNC
WORD
ID
FIELD DATA FIELD CRC
05876-023
ADF7021 Data Sheet
Rev. D | Page 42 of 62
Figure 54. Power-Up Sequence for Transmit Mode
POWER-DOWN
CE LOW
XTAL
REFERENCE
TCXO
REFERENCE
CE HIGH
WAIT 10µs (REGULATOR POWER-UP)
WRITE TO REGISTER 1 (TURNS ON VCO)
WAIT 0.7ms (TYPICAL VCO SETTLING)
WRITE TO REGISTER 0 (TURNS ON PLL)
WAIT 40µs (TYPICAL PLL SETTLING)
WRITE TO REGISTER 2 (TURNS ON PA)
WAIT FOR PA TO RAMP UP (ONLY IF PA RAMP ENABLED)
WAIT FOR Tx LATENCY NUMBER OF BITS
(REFER TO TABLE 12)
WRITE TO REGISTER 2 (TURNS OFF PA)
WAIT FOR PA TO RAMP DOWN
WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS)
CE HIGH
WAIT 10µs + 1ms
(REGULATOR POWER-UP + TYPICAL XTAL SETTLING)
CE LOW
POWER-DOWN
Tx MODE
OPTIONAL. ONLY NECESSARY IF PA
RAMP DOWN IS REQUIRED.
05876-086
Data Sheet ADF7021
Rev. D | Page 43 of 62
Figure 55. Power-Up Sequence for Receive Mode
POWER-DOWN
CE LOW
WRITE TO REGISTER 5 (STARTS IF FILTER CALIBRATION)
WAIT 0.2ms (COARSE CAL) OR WAIT 5.2ms
(COARSE CALIBRATION + FINE CALIBRATION)
WRITE TO REGISTER 11 (SET UP SWD)
WRITE TO REGISTER 12 (ENABLE SWD)
WRITE TO REGISTER 6 (SETS UP IF FILTER CALIBRATION)
CE LOW
POWER-DOWN
Rx MODE
WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS)
WRITE TO REGISTER 4 (TURNS ON DEMOD)
WRITE TO REGISTER 10 (TURNS ON AFC)
OPTIONAL.
05876-087
WRITE TO REGISTER 0 (TURNS ON PLL)
WAIT 40µs (TYPICAL PLL SETTLING)
CE HIGH
WAIT 10µs (REGULATOR POWER-UP)
WRITE TO REGISTER 1 (TURNS ON VCO)
WAIT 0.7ms (TYPICAL VCO SETTLING)
CE HIGH
WAIT 10µs + 1ms
(REGULATOR POWER-UP + TYPICAL XTAL SETTLING)
XTAL
REFERENCE
TCXO
REFERENCE
OPTIONAL:
ONLY NECESSARY IF
AFC IS REQUIRED.
OPTIONAL:
ONLY NECESSARY IF
SWD IS REQUIRED.
OPTIONAL:
ONLY NECESSARY IF
IF FILTER FINE CAL IS REQUIRED.
ADF7021 Data Sheet
Rev. D | Page 44 of 62
APPLICATIONS CIRCUIT
The ADF7021 requires very few external components for
operation. Figure 56 shows the recommended application
circuit. Note that the power supply decoupling and regulator
capacitors are omitted for clarity.
For recommended component values, refer to the ADF7021
evaluation board data sheet and the AN-915 Application Note,
accessible from the ADF7021 product page. Follow the reference
design schematic closely to ensure optimum performance in
narrow-band applications.
Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown)
48
47
46
45
44
43
42
41
40
39
38
37
ADF7021
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
LNA
VDD4
RSET
CREG4
GND4
CVCO
GND1
L1
GND
L2
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
MUXOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MIX_I
MIX_I
MIX_Q
MIX_Q
FILT_I
FILT_I
GND4
FILT_Q
FILT_Q
GND4
TEST_A
CE
CLKOUT
TxRxDATA
TxRxCLK
SWD
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VDD
VDD
TCXO
VDD
VDD
VDD
ANTENNA
CONNECTION
TO
MICROCONTROLLER
Tx/Rx SIGNAL
INTERFACE
TO
MICROCONTROLLER
CONFIGURATION
INTERFACE
T-STAGE LC
FILTER
MATCHING
LOOP FILTER
CVCO
CAP
EXT VCO L*
REFERENCE
RSET
RESISTOR
RLNA
RESISTOR
CHIP ENABLE
TO MICROCONTROLLER
*PIN 44 AND PIN 46 CAN BE LEFT FLOATING IF EXTERNAL INDUCTOR VCO IS NOT USED.
NOTES
1. PINS [13:18], PINS [20:21], AND PIN 23 ARE TEST PINS AND ARE NOT USED IN NORMAL OPERATION.
05876-084
Data Sheet ADF7021
Rev. D | Page 45 of 62
SERIAL INTERFACE
The serial interface allows the user to program the 16-/32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register, and 16 latches.
Signals must be CMOS compatible. The serial interface is powered
by the regulator, and, therefore, is inactive when CE is low.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of 16 latches on the
rising edge of SLE. The destination latch is determined by the
value of the four control bits (C4 to C1); these are the bottom
4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be
read back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and enabling the READBACK bit
(R7_DB8 = 1). The readback can begin after the control word
has been latched with the SLE signal. SLE must be kept high
while the data is being read out. Each active edge at the SCLK
pin successively clocks the readback word out at the SREAD
pin, as shown in Figure 57, starting with the MSB first. The data
appearing at the first clock cycle following the latch operation
must be ignored. An extra clock cycle is needed after the 16th
readback bit to return the SREAD pin to tristate. Therefore, 18
total clock cycles are needed for each read back. After the 18th
clock cycle, bring the SLE low.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprising Bit RV1 to Bit RV16 and is scaled according to the
following formula:
FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/218
In the absence of frequency errors, FREQ RB is equal to the IF
frequency of 100 kHz. Note that, for the AFC readback to yield
a valid result, the down converted input signal must not fall outside
the bandwidth of the analog IF filter. At low input signal levels,
the variation in the readback value can be improved by averaging.
RSSI Readback
The format of the readback word is shown in Figure 57. It
comprises the RSSI-level information (Bit RV1 to Bit RV7), the
current filter gain (FG1, FG2), and the current LNA gain (LG1,
LG2) setting. The filter and LNA gain are coded in accordance
with the definitions in the Register 9—AGC Register section. For
signal levels below −100 dBm, averaging the measured RSSI values
improves accuracy. The input power can be calculated from the
RSSI readback value as outlined in the RSSI/AGC section.
Battery Voltage/ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery or ADCIN voltage can be determined using
VBATTERY = (BATTERY_VOLTAGE_READBACK)/21.1
VADCIN = (ADCIN_VOLTAGE_READBACK)/42.1
The temperature can be calculated using
Temp [°C] = 469.5 − (7.2 × TEMP_READBACK)
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers. The silicon revision word is coded with four
quartets in BCD format. The product code (PC) is coded with
three quartets extending from Bit RV5 to Bit RV16. The revision
code (RC) is coded with one quartet extending from Bit RV1 to
Bit RV4. The product code for the ADF7021 reads back as PC =
0x210. The current revision code reads as RC = 0x4.
Filter Bandwidth Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8. This readback can be used for manual filter adjust, thereby
avoiding the need to do an IF filter calibration in some instances.
The manual adjust value is programmed by R5_DB[14:19]. To
calculate the manual adjust based on a filter calibration readback,
use the following formula:
IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128
Program the result into R5_DB[14:19] as outlined in the Register 5—
IF Filter Setup Register section.
Figure 57. Readback Value Table
READBACK MODE
AFC READBACK
DB15
RV16
X
X
RV16
0
RSSI READBACK
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
SILICON REVISION
FILTER CAL READBACK
READBACK VALUE
DB14
RV15
X
X
RV15
0
DB13
RV14
X
X
RV14
0
DB12
RV13
X
X
RV13
0
DB11
RV12
X
X
RV12
0
DB10
RV11
LG2
X
RV11
0
DB9
RV10
LG1
X
RV10
0
DB8
RV9
FG2
X
RV9
0
DB7
RV8
FG1
X
RV8
RV8
DB6
RV7
RV7
RV7
RV7
RV7
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
DB0
RV1
RV1
RV1
RV1
RV1
05876-029
ADF7021 Data Sheet
Rev. D | Page 46 of 62
INTERFACING TO MICROCONTROLLER/DSP
Standard Transmit/Receive Data Interface
The standard transmit/receive signal and configuration interface
to a microcontroller is shown in Figure 58. In transmit mode,
the ADF7021 provides the data clock on the TxRxCLK pin, and
the TxRxDATA pin is used as the data input. The transmit data
is clocked into the ADF7021 on the rising edge of TxRxCLK.
Figure 58. ADuC841 to ADF7021 Connection Diagram
In receive mode, the ADF7021 provides the synchronized data
clock on the TxRxCLK pin. The receive data is available on the
TxRxDATA pin. Use the rising edge of TxRxCLK to clock the
receive data into the microcontroller. Refer to Figure 4 and
Figure 5 for the relevant timing diagrams.
In 4FSK transmit mode, the MSB of the transmit symbol is
clocked into the ADF7021 on the first rising edge of the data
clock from the TxRxCLK pin. In 4FSK receive mode, the MSB
of the first payload symbol is clocked out on the first negative
edge of the data clock after the SWD, and must be clocked into
the microcontroller on the following rising edge. Refer to Figure 6
and Figure 7 for the relevant timing diagrams.
UART Mode
In UART mode, the TxRxCLK pin is configured to input transmit
data in transmit mode. In receive mode, the receive data is available
on the TxRxDATA pin, thus providing an asynchronous data
interface. The UART mode can only be used with oversampled
2FSK. Figure 59 shows a possible interface to a microcontroller
using the UART mode of the ADF7021. To enable this UART
interface mode, set R0_DB28 high. Figure 8 and Figure 9 show
the relevant timing diagrams for UART mode.
Figure 59. ADF7021 (UART Mode) to Asynchronous Microcontroller Interface
SPI Mode
In SPI mode, the TxRxCLK pin is configured to input transmit
data in transmit mode. In receive mode, the receive data is available
on the TxRxDATA pin. The data clock in both transmit and receive
modes is available on the CLKOUT pin. In transmit mode, data
is clocked into the ADF7021 on the positive edge of CLKOUT.
In receive mode, the TxRxDATA data pin is sampled by the
microcontroller on the positive edge of the CLKOUT.
To enable SPI interface mode, set R0_DB28 high and set
R15_DB[17:19] to 0x7. Figure 8 and Figure 9 show the relevant
timing diagrams for SPI mode, while Figure 60 shows the
recommended interface to a microcontroller using the SPI
mode of the ADF7021.
Figure 60. ADF7021 (SPI Mode) to Microcontroller Interface
ADSP-BF533 interface
The suggested method of interfacing to the Blackfin® ADSP-BF533
is given in Figure 61.
Figure 61. ADSP-BF533 to ADF7021 Connection Diagram
05876-026
MISO
ADuC841 ADF7021
MOSI
SCLOCK
SS
P3.7
P3.2/INT0
P2.4
P2.5
TxRxDATA
TxRxCLK
CE
SWD
SREAD
SLE
P2.6
P2.7
SDATA
SCLK
GPIO
UART
ADF7021
TxRxCLK
TxRxDATA
TxDATA
RxDATA
CE
SWD
SREAD
SLE
SDATA
SCLK
GPIO
MICROCONTROLLER
05876-085
SPI
ADF7021
TxRxCLK
TxRxDATA
MISO
MOSI
CE
SWD
SREAD
SLE
SDATA
SCLK
GPIO
MICROCONTROLLER
SCLK CLKOUT
05876-076
05876-027
MOSI
ADSP-BF533
A
DF7021
MISO
PF5
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
SDATA
SLE
TxRxDATA
SWD
CE
SCK SCLK
SREAD
TxRxCLK
Data Sheet ADF7021
Rev. D | Page 47 of 62
REGISTER 0—N REGISTER
Figure 62. Register 0—N Register Map
The RF output frequency is calculated by the following:
For the direct output
15
2
_
_NFRACTIONAL
NINTEGERPFDRFOUT
For the RF_DIVIDE_BY_2 (DB18) selected
15
2
_
_5.0 NFRACTIONAL
NINTEGERPFDRFOUT
In UART/SPI mode, the TxRxCLK pin is used to input the Tx
data. The Rx Data is available on the TxRxDATA pin.
In the MUXOUT map in Figure 62, the FILTER_CAL_COMPLETE
indicates when a coarse or coarse plus fine IF filter calibration
has finished. The DIGITAL_LOCK_DETECT indicates when
the PLL has locked. The RSSI_READY indicates that the RSSI
signal has settled and an RSSI readback can be performed.
Tx_Rx gives the status of DB27 in this register, which can be
used to control an external Tx/Rx switch.
TR1
TRANSMIT/
RECEIVE
0 TRANSMIT
RECEIVE
1
M3 M2 M1 MUXOUT
0 REGULATOR_READY (DEFAULT)
FILTER_CAL_COMPLETE0
0 DIGITAL_LOCK_DETECT
0 RSSI_READY
1 Tx_Rx
1 LOGIC_ZERO
1 TRISTATE
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1 LOGIC_ONE
U1 UART MODE
0DISABLED
1 ENABLED
N8 N7 N6 N5 N4 N3 N2 N1
N COUNTER
DIVIDE RATIO
023
024
.
.
.
1 253
1 254
1
0
0
.
.
.
1
1
1
0
0
.
.
.
.
.
.
1
1
1
1
1
1
1
1
.
.
.
0
1
1
1
1
.
.
.
1
0
1
1
1
.
.
.
1
0
0
1
1
.
.
.
.
.
.
1
0
1
0
1 255
15-BIT FRACTIONAL_N8-BIT INTEGER_N
Tx/Rx
UART
MODE
MUXOUT
ADDRESS
BITS
N5
N4
N8
M5
M6
M7
M8
M12
M13
M15
N1
N2
N3
M14
M9
M10
M11
M4
M3
TR1
U1
M1
M3
M2
C2 (0)
C1 (0)
C3 (0)
C4 (0)
M1
M2
N7
N6
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
FRACTIONAL
DIVIDE RATIO
0
1
2
.
.
.
32764
32765
32766
32767
M15
0
0
0
.
.
.
1
1
1
1
M14
0
0
0
.
.
.
1
1
1
1
M13
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
M3
0
0
0
.
.
.
1
1
1
1
M2
0
0
1
.
.
.
0
0
1
1
M1
0
1
0
.
.
.
0
1
0
1
05876-030
ADF7021 Data Sheet
Rev. D | Page 48 of 62
REGISTER 1—VCO/OSCILLATOR REGISTER
Figure 63. Register 1—VCO/Oscillator Register Map
The R_COUNTER and XTAL_DOUBLER relationship is
expressed as follows:
If XTAL_DOUBLER = 0,
COUNTERR
XTAL
PFD _
If XTAL_DOUBLER =1,
COUNTERR
XTAL
PFD _
2
The CLOCKOUT_DIVIDE is a divided-down and inverted
version of the XTAL and is available on Pin 36 (CLKOUT).
Set XOSC_ENABLE high when using an external crystal. If
using an external oscillator (such as TCXO) with CMOS-level
outputs into Pin OSC2, set XOSC_ENABLE low. If using an
external oscillator with a 0.8 V p-p clipped sine wave output
into Pin OSC1, set XOSC_ENABLE high.
Set the VCO_BIAS bits according to Table 9.
The VCO_ADJUST bits adjust the center of the VCO operating
band. Each bit typically adjusts the VCO band up by 1% of the
RF operating frequency (0.5% if RF_DIVIDE_BY_2 is enabled).
Setting VCO_INDUCTOR to external allows the use of the
external inductor VCO, which gives RF operating frequencies of
80 Hz to 650 MHz. If the internal inductor VCO is being used
for operation, set this bit low.
05876-031
R3 R2 R1
RF R COUNTER
DIVIDE RATIO
0
0
.
.
.
1
1
2
.
.
.
7
1
0
.
.
.
1
0
1
.
.
.
1
X1 XTAL OSC
0OFF
1ON
VA2 VA1
VCO CENTER
FREQ ADJUST
0NOMINAL
0 VCO ADJUST UP 1
1 VCO ADJUST UP 2
1
0
1
0
1 VCO ADJUST UP 3
D1
XTAL
DOUBLER
0 DISABLE
ENABLED
1
CP2
CP1
RSET
I
CP
(mA)
3.6kΩ
000.3
010.9
101.5
112.1
VB4 VB3 VB2 VB1
VCO BIAS
CURRENT
00.25mA
00.5mA
.
1
1
0
.
1
0
1
.
1
0
0
.
13.75mA
CL4 CL3 CL2 CL1
CLKOUT
DIVIDE RATIO
0OFF
0
0
.
.
.
1
0
1
0
.
.
.
1
2
4
.
.
.
0
0
1
.
.
.
1
0
0
0
.
.
.
130
VCO_BIAS
CP_
CURRENT
RF_DIVIDE_
BY_2
XOSC_
ENABLE
VCO_
ENABLE
ADDRESS
BITS
XTAL_
DOUBLER
XTAL_
BIAS
VCO_
ADJUST
VA1
VB4
CL1
CL2
CL3
CL4
CP1
CP2
RFD1
VB1
VB2
VB3
VE1
X1
XB1
XB2
D1
R3
C2 (0)
C1 (1)
C3 (0)
C4 (0)
R1
R2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
VA2 DB24
DB1
DB0
DB2
DB3
XB2 XB1
XTAL
BIAS
020µA
025µA
130µA
1
0
1
0
135µA
RFD1 RF DIVIDE BY 2
0OFF
ON
1
LOOP
CONDITION
VCO OFF
VCO ON
VE1
0
1
DB25
VCL1 VCO_
INDUCTOR
VCO
INTERNAL L VCO
EXTERNAL L VCO
VCL1
0
1
R_COUNTER
CLOCKOUT_
DIVIDE
Data Sheet ADF7021
Rev. D | Page 49 of 62
REGISTER 2—TRANSMIT MODULATION REGISTER
Figure 64. Register 2—Transmit Modulation Register Map
The 2FSK/3FSK/4FSK frequency deviation is expressed by the
following:
Direct output
Frequency Deviation [Hz] =
16
2
PFDONCY_DEVIATITx_FREQUEN
With RF_DIVIDE_BY_2 (R1_DB18) enabled
Frequency Deviation [Hz] =
16
2
5.0 PFDONCY_DEVIATITx_FREQUEN
where Tx_FREQUENCY_DEVIATION is set by DB[19:27] and
PFD is the PFD frequency.
In the case of 4FSK, there are tones at ±3 × the frequency
deviation and at ±1 × the deviation. The power amplifier (PA)
ramps at the programmed rate (R2_DB[8:10]) until it reaches
its programmed level DB[13:18]. If the PA is enabled/disabled
by the PA_ENABLE bit (DB7), it ramps up and down. If it is
enabled/disabled by the Tx/Rx bit (R0_DB27), it ramps up and
turns hard off.
R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised
cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by
default, but the raised cosine filter bandwidth can be increased
to provide less aggressive data filtering by using an alpha of 0.7.
05876-032
P6
0
0
0
0
.
.
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
P2
0
0
1
1
.
.
1
P1
0
1
0
1
.
.
1
0 (PA OFF)
1 (–16.0 dBm)
2
3
.
.
63 (13 dBm)
TFD9
0
0
0
0
.
1
TFD3
0
0
0
0
.
1
...
...
...
...
...
...
...
TFD2
0
0
1
1
.
1
TFD1
0
1
0
1
.
1
0
1
2
3
.
511
Tx_FREQUENCY_DEVIATION POWER_AMPLIFIER
TxDATA_
INVERT PA_BIAS PA_RAMP
MODULATION_
SCHEME
ADDRESS
BITS
PA_
ENABLE
PE1
0
1
POWER AMPLIFIER
OFF
ON
PA2
0
0
1
1
PA1
0
1
0
1
PA BIAS
5µA
7µA
9µA
11µA
DI2
0
0
1
1
DI1
0
1
0
1
TxDATA INVERT
NORMAL
INVERT CLK
INVERT DATA
INV CLK AND DATA
S3
0
0
0
0
1
1
1
1
S2
0
0
1
1
0
0
1
1
MODULATION SCHEME
2FSK
GAUSSIAN 2FSK
3FSK
4FSK
OVERSAMPLED 2FSK
RAISED COSINE 2FSK
RAISED COSINE 3FSK
RAISED COSINE 4FSK
S1
0
1
0
1
0
1
0
1
PR3
0
0
0
0
1
1
1
1
PR2
0
0
1
1
0
0
1
1
PA RAMP RATE
NO RAMP
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
16 CODES/BIT
8 CODES/BIT
4 CODES/BIT
PR1
0
1
0
1
0
1
0
1
TFD5
TFD4
TFD8
PR1
PR2
PR3
PA1
P3
P4
P6
TFD1
TFD2
TFD3
P5
PA2
P1
P2
PE1
S3
TFD9
DI1
DI2
C2 (1)
C1 (0)
C3 (0)
C4 (0)
S1
S2
TFD7
TFD6
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
R-COSINE_
ALPHA
DB30NRC1
NRC1
0
1
RAISED COSINE ALPHA
0.7
0.5 (Default)
f
DEV
PA LEVEL
ADF7021 Data Sheet
Rev. D | Page 50 of 62
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
Figure 65. Register 3—Transmit/Receive Clock Register Map
Baseband offset clock frequency (BBOS CLK) must be greater
than 1 MHz and less than 2 MHz, where
DIVIDECLKBBOS
XTAL
CLKBBOS __
Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤
DEMOD CLK ≤ 15 MHz, where
DIVIDECLKDEMOD
XTAL
CLKDEMOD __
For 2FSK/3FSK, the data/clock recovery frequency (CDR CLK)
needs to be within 2% of (32 × data rate). For 4FSK, the CDR
CLK needs to be within 2% of (32 × symbol rate).
DIVIDECLKCDR
CL
K
DEMOD
CLKCDR __
The sequencer clock (SEQ CLK) supplies the clock to the digital
receive block. It is recommended to be as close to 100 kHz as
possible.
DIVIDECLKSEQ
XTAL
CLKSEQ __
The time allowed for each AGC step to settle is determined by
the AGC update rate. It is recommended to be set close to
10 kHz.
DIVIDECLKAGC
CLKSEQ
RateUpdateAGC __
[Hz]
05876-033
FS8
0
0
.
1
1
FS7
0
0
.
1
1
FS3
0
0
.
1
1
...
...
...
...
...
...
FS2
0
1
.
1
1
FS1
1
0
.
0
1
CDR CLK DIVIDE
1
2
.
254
255
BK2
0
0
1
1
BK1
0
1
0
1
BBOS CLK DIVIDE
4
8
16
32
SK8
0
0
.
1
1
SK7
0
0
.
1
1
SK3
0
0
.
1
1
...
...
...
...
...
...
SK2
0
1
.
1
1
SK1
1
0
.
0
1
SEQ CLK DIVIDE
1
2
.
254
255
OK2
0
0
...
1
OK1
0
1
...
1
DEMOD CLK DIVIDE
INVALID
1
...
15
SEQUENCER_CLK_DIVIDEAGC_CLK_DIVIDE CDR_CLK_DIVIDE
BBOS_CLK_
DIVIDE
DEM_CLK_
DIVIDE
ADDRESS
BITS
GD6
0
0
...
1
GD5
0
0
...
1
GD3
0
0
...
1
GD4
0
0
...
1
GD2
0
0
...
1
GD1
0
1
...
1
AGC CLK DIVIDE
INVALID
1
...
127
SK8
SK7
FS1
FS2
FS3
FS4
FS8
SK1
SK3
SK4
SK5
SK6
SK2
FS5
FS6
FS7
OK2
OK1
OK4
OK3
C2 (1)
C1 (1)
C3 (0)
C4 (0)
BK1
BK2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
GD6
GD5
GD1
GD2
GD3
GD4
DB24
DB25
DB28
DB27
DB26
DB29
DB30
DB31
DB1
DB0
DB2
DB3
OK3
0
0
...
1
0
0
...
1
OK4
Data Sheet ADF7021
Rev. D | Page 51 of 62
REGISTER 4—DEMODULATOR SETUP REGISTER
Figure 66. Register 4—Demodulator Setup Register Map
To solve for DISCRIMINATOR_BW, use the following equation:
DISCRIMINATOR_BW = 3
10400
KCLKDEMOD
where the maximum value = 660.
For 2FSK,
DEV
f
RoundK
3
10100
For 3FSK,
DEV
f
RoundK 2
10100 3
For 4FSK,
DEV
FSK f
RoundK 4
10100 3
4
where:
Round is rounded to the nearest integer.
Round4FSK is rounded to the nearest of the following integers: 32,
31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.
fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is
the frequency deviation used for the ±1 symbols (that is, the
inner frequency deviations).
Rx_INVERT (DB[8:9]) and DOT_PRODUCT (DB7) need to be
set as outlined in Table 17 and Table 18.
CLKDEMOD
f
_BWPOST_DEMOD CUTOFF
π211
where the cutoff frequency (fCUTOFF) of the post demodulator
filter is typically 0.75 × the data rate in 2FSK. Round up
POST_DEMOD_BW to the nearest integer value. In 3FSK, set it
equal to the data rate. In 4FSK, set it equal to 1.6 × symbol rate.
05876-034
DISCRIMINATOR_BW
DOT_PRODUCT
POST_DEMOD_BW
Rx_
INVERTIF_BW
ADDRESS
BITS
TD4
TD3
RI1
RI2
DW1
DW2
DW6
DW7
DW9
DW10
TD1
TD2
DW8
DW3
DW4
DW5
DP1
DS3
C2(0)
C1(0)
C3(1)
C4(0)
DS1
DS2
TD6
TD5
TD10
TD9
TD7
TD8
IFB2
IFB1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
DS1
0
1
0
1
0
1
0
1
DEMODULATOR SCHEME
2FSK LINEAR DEMODULATOR
2FSK CORRELATOR DEMODULATOR
3FSK DEMOD
4FSK DEMOD
RESERVED
RESERVED
RESERVED
RESERVED
DP1
0
1
PRODUCT
CROSS PRODUCT
DOT PRODUCT
RI1
0
1
0
1
INVERT
NORMAL
INVERT CLK
INVERT DATA
INVERT CLK/DATA
IFB1
0
1
0
1
IF FILTER
BW
12.5kHz
18.75kHz
25kHz
INVALID
DS2DS3
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
RI2
IFB2
0
0
1
1
DW3
0
0
.
.
.
.
1
DW1
1
0
.
.
.
.
1
POST DEMOD
BW
1
2
.
.
.
.
1023
DW2
0
1
.
.
.
.
1
DW10
0
0
.
.
.
.
1
DW6
0
0
.
.
.
.
1
.
.
.
.
.
.
.
.
DW5
0
0
.
.
.
.
1
DW4
0
0
.
.
.
.
1
TD3
0
0
.
.
.
.
1
TD1
1
0
.
.
.
.
0
CORRELATOR
DISCRIM BW
1
2
.
.
.
.
660
TD2
0
1
.
.
.
.
0
TD10
0
0
.
.
.
.
1
TD6
0
0
.
.
.
.
0
.
.
.
.
.
.
.
.
TD5
0
0
.
.
.
.
1
TD4
0
0
.
.
.
.
0
DEMOD_
SCHEME
ADF7021 Data Sheet
Rev. D | Page 52 of 62
REGISTER 5—IF FILTER SETUP REGISTER
Figure 67. Register 5—IF Filter Setup Register Map
A coarse IF filter calibration is performed when the
IF_CAL_COARSE bit (DB4) is set. If the IF_FINE_CAL bit
(R6_DB4) has been previously set, a fine IF filter calibration is
automatically performed after the coarse calibration.
Set IF_FILTER_DIVIDER such that
kHz50
__
DIVIDERFILTERIF
XTAL
IF_FILTER_ADJUST allows the IF fine filter calibration result
to be programmed directly on subsequent receiver power-ups,
thereby saving on the need to redo a fine filter calibration in
some instances. Refer to the Filter Bandwidth Calibration
Readback section for information about using the
IF_FILTER_ADJUST bits.
DB[20:31] are used for image rejection calibration. Refer to the
Image Rejection Calibration section for details on how to
program these parameters.
05876-035
IR_PHASE_
ADJUST_MAG
IR PHASE
ADJUST DIRECTION
IR GAIN
ADJUST I/Q
IR GAIN
ADJUST UP/DN
IR_GAIN_
ADJUST_MAG IF_FILTER_DIVIDER
IF_CAL_COARSE
IF_FILTER_ADJUST
ADDRESS
BITS
IFA1
IFD9
IFD5
IFD6
PM2
PM3
GM1
GM2
GM4
GM5
IFD7
IFD8
GM3
PM4
PD1
IFD4
IFD3
C2 (0)
C1 (1)
C3 (1)
C4 (0)
IFD1
CC1
IFD2
IFA3
IFA2
PM1
IFA6
IFA4
IFA5
GA1
GQ1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
CC1
0
1
CAL
NO CAL
DO CAL
PD1
0
1
IR PHASE ADJUST I/Q
ADJUST I CH
ADJUST Q CH
GA1
0
1
IR GAIN ADJUST UP/DN
GAIN
ATTENUATE
GQ1
0
1
IR GAIN ADJUST I/Q
ADJUST I CH
ADJUST Q CH
IFD3
0
0
.
.
.
.
1
IFD1
1
0
.
.
.
.
1
FILTER CLOCK
DIVIDE RATIO
1
2
.
.
.
.
511
IFD2
0
1
.
.
.
.
1
IFA2
0
0
1
..
1
0
0
1
.
1
IF FILTER
ADJUST
IFA6
0
0
0
..
0
1
1
1
1
1
GM3 IR GAIN
ADJUST
GM5
0
0
0
.
1
IFD9
0
0
.
.
.
.
1
IFD6
0
0
.
.
.
.
1
.
.
.
.
.
.
.
.
IFD5
0
0
.
.
.
.
1
IFD4
0
0
.
.
.
.
1
0
1
0
..
1
0
1
0
.
1
IFA1
...
...
...
...
...
...
...
...
...
...
...
0
+1
+2
...
+31
0
–1
–2
...
–31
GM4 GM2 GM1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
1
0
1
2
...
31
PM2 IR PHASE
ADJUST
PM3 PM1 PM1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
1
0
1
2
...
15
IFA5
0
0
0
..
1
0
0
0
.
1
Data Sheet ADF7021
Rev. D | Page 53 of 62
REGISTER 6—IF FINE CAL SETUP REGISTER
Figure 68. Register 6—IF Fine Cal Setup Register Map
A fine IF filter calibration is set by enabling the IF_FINE_CAL
Bit (R6_DB4). A fine calibration is then carried out only when
Register 5 is written to and R5_DB4 is set.
Set the IF upper and lower tones used during fine filter
calibration as follows:
kHz8.65
2____
DIVIDETONELOWERCALIF
XTAL
kHz5.131
2____
DIVIDETONEUPPERCALIF
XTAL
The IF tone calibration time is the amount of time that is spent
at an IF calibration tone. It is dependent on the sequencer clock.
For best practice, is recommended to have the IF tone
calibration time be at least 500 μs.
CLKSEQ
TIMEDWELLCALIF
TimenCalibratioToneIF ___
The total time for a fine IF filter calibration is
IF Tone Calibration Time × 10.
DB[28:30] control the internal source for the image rejection
(IR) calibration. The IR_CAL_SOURCE_DRIVE_LEVEL bits
(DB[28:29]) set the drive strength of the source, whereas the
IR_CAL_SOURCE_÷2 bit (DB30) allows the frequency of the
internal signal source to be divided by 2.
05876-036
IF_CAL_LOWER_TONE_DIVIDEIF_CAL_UPPER_TONE_DIVIDEIF_CAL_DWELL_TIME
IF_FINE_
CAL
ADDRESS
BITS
CD3
CD2
CD6
LT4
LT5
LT6
LT7
UT3
UT4
UT6
UT7
UT8
CD1
UT5
LT8
UT1
UT2
LT3
LT2
CD7
C2 (1)
C1 (0)
C3 (1)
C4 (0)
FC1
LT1
CD5
CD4
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB25
DB1
DB0
DB2
DB3
FC1
0
1
IF FINE CAL
DISABLED
ENABLED
UT3
0
0
0
.
.
1
UT1
1
0
1
.
.
1
IF CAL UPPER
TONE DIVIDE
1
2
3
.
.
UT2
0
1
1
.
.
1
UT8
0
0
0
.
.
0
...
...
...
...
...
...
... 127
LT3
0
0
0
.
.
1
LT1
1
0
1
.
.
1
1
2
3
.
.
LT2
0
1
1
.
.
1
LT8
0
0
0
.
.
1
...
...
...
...
...
...
... 255
IF CAL LOWER
TONE DIVIDE
CD3
0
0
0
.
.
1
CD1
1
0
1
.
.
1
IF CAL
DWELL TIME
1
2
3
.
.
CD2
0
1
1
.
.
1
CD7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
DB28IRC1
DB29
DB30
IRC2
IRD1
IR_CAL_
SOURCE_
DRIVE_LEVEL
IR_CAL_
SOURCE ÷2
IRC1
0
1
0
1
IR CAL SOURCE
DRIVE LEVEL
IRC2
0
0
1
1
OFF
LOW
MED
HIGH
IRD1
0
1
IR CAL SOURCE ÷2
SOURCE ÷2 OFF
SOURCE ÷2 ON
0
0
0
.
.
1
LT7
0
0
0
.
.
1
UT7
ADF7021 Data Sheet
Rev. D | Page 54 of 62
REGISTER 7—READBACK SETUP REGISTER
Figure 69. Register 7—Readback Setup Register Map
Readback of the measured RSSI value is valid only in Rx mode.
Readback of the battery voltage, temperature sensor, or voltage
at the external pin is not valid in Rx mode.
To read back the battery voltage, the temperature sensor, or the
voltage at the external pin in Tx mode, first power up the ADC
using R8_DB8 because it is turned off by default in Tx mode to
save power.
For AFC readback, use the following equations (see the
Readback Format section):
FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/218
VBATTERY = BATTERY_VOLTAGE_READBACK/21.1
VADCIN = ADCIN_VOLTAGE_READBACK/42.1
Temperature [°C] = 469.5 − (7.2 × TEMP_READBACK)
AD1AD2RB1RB2
RB3
DB8 DB7 DB6 DB5 DB4 DB3 DB2
C2 (1) C1 (1)
CONTROL
BITS
DB1 DB0
C3 (1)C4 (0)
READBACK
SELECT
ADC
MODE
AD2
0
0
1
1
AD1
0
1
0
1
ADC MODE
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
RB2
0
0
1
1
RB1
0
1
0
1
READBACK MODE
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
RB3
0
1
READBACK
DISABLED
ENABLED
0
5876-037
Data Sheet ADF7021
Rev. D | Page 55 of 62
REGISTER 8—POWER-DOWN TEST REGISTER
Figure 70. Register 8—Power-Down Test Register Map
It is not necessary to write to this register under normal
operating conditions.
For a combined LNA/PA matching network, always set DB11 to
0, which enables the internal Tx/Rx switch. This is the power-
up default condition.
PD1PD3PD4
PD5
DB8 DB7 DB6 DB5 DB4 DB3 DB2
C2 (0) C1 (0)
CONTROL
BITS
DB1 DB0
C3 (0)C4 (1)
LOG_AMP_
ENABLE
SYNTH_
ENABLE
RESERVED
LNA/MIXER_
ENABLE
FILTER_
ENABLE
ADC_
ENABLE
DEMOD_
ENABLE
Tx/Rx_SWITCH_
ENABLE
PA_ENABLE_
Rx_MODE
COUNTER_
RESET
Rx_RESET
CR1
DB15 DB14 DB13 DB12 DB11
LE1 PD6
DB10 DB9
SW1PD7
PD7
0
1
PA (Rx MODE)
PA OFF
PA ON
CR1
0
1
COUNTER RESET
NORMAL
RESET
DEMOD
RESET
CDR
RESET
SW1
0
1
Tx/Rx SWITCH
DEFAULT (ON)
OFF
PD6
0
1
DEMOD ENABLE
DEMOD OFF
DEMOD ON
PD5
0
1
ADC ENABLE
ADC OFF
ADC ON
LE1
0
1
LOG AMP ENABLE
LOG AMP OFF
LOG AMP ON
PD4
0
1
FILTER ENABLE
FILTER OFF
FILTER ON
PD3
0
1
LNA/MIXER ENABLE
LNA/MIXER OFF
LNA/MIXER ON
PD1
0
1
SYNTH STATUS
SYNTH OFF
SYNTH ON
05876-038
ADF7021 Data Sheet
Rev. D | Page 56 of 62
REGISTER 9—AGC REGISTER
Figure 71. Register 9—AGC Register Map
In receive mode, AGC is set to automatic AGC by default on
power-up. The default thresholds are AGC_LOW_THRESHOLD =
30 and AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC
section for details. It is only necessary to program this register if
AGC settings, other than the defaults, are required.
AGC high and low settings must be more than 30 apart to
ensure correct operation.
An LNA gain of 30 is available only if LNA_MODE (DB25) is
set to 0.
05876-039
AGC_HIGH_THRESHOLD
LNA_
GAIN
AGC_
MODE
FILTER_
GAIN
LNA_
CURRENT
FILTER_
CURRENT
MIXER_
LINEARITY
LNA_MODE
AGC_LOW_THRESHOLD
ADDRESS
BITS
FG2
FG1
GL5
GL6
GL7
GH1
GH5
GH6
GM1
GM2
LG1
LG2
GH7
GH2
GH3
GH4
GL4
GL3
C2 (0)
C1 (1)
C3 (0)
C4 (1)
GL1
GL2
FI1
LG1
ML1
LI1
LI2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
FI1
0
1
FILTER CURRENT
LOW
HIGH
0
1
2
3
AGC MODE
AUTO AGC
MANUAL AGC
FREEZE AGC
RESERVED
FG2
0
0
1
1
FG1
0
1
0
1
FILTER GAIN
8
24
72
INVALID
LG2
0
0
1
1
LG1
0
1
0
1
LNA GAIN
3
10
30
INVALID
GL3
0
0
0
1
.
.
.
1
1
1
GL1
1
0
1
0
.
.
.
1
0
1
AGC LOW
THRESHOLD
1
2
3
4
.
.
.
61
62
63
GL2
0
1
1
0
.
.
.
0
1
1
GL7
0
0
0
0
.
.
.
1
1
1
GL6
0
0
0
0
.
.
.
1
1
1
GL5
0
0
0
0
.
.
.
1
1
1
GL4
0
0
0
0
.
.
.
1
1
1
GH3
0
0
0
1
.
.
.
1
1
0
GH1
1
0
1
0
.
.
.
0
1
0
AGC HIGH
THRESHOLD
1
2
3
4
.
.
.
78
79
80
GH2
0
1
1
0
.
.
.
1
1
0
GH7
0
0
0
0
.
.
.
1
1
1
GH6
0
0
0
0
.
.
.
0
0
0
GH5
0
0
0
0
.
.
.
0
0
1
GH4
0
0
0
0
.
.
.
1
1
0
LI2
0
LI1
0
LNA BIAS
800µA (DEFAULT)
LG1
0
1
LNA MODE
DEFAULT
REDUCED GAIN
ML1
0
1
MIXER LINEARITY
DEFAULT
HIGH
Data Sheet ADF7021
Rev. D | Page 57 of 62
REGISTER 10—AFC REGISTER
Figure 72. Register 10—AFC Register Map
The AFC_SCALING_FACTOR can be expressed as
XTAL
RoundFACTORSCALINGAFC 5002
__
24
The settings for KI and KP affect the AFC settling time and
AFC accuracy. The allowable range of each parameter is
KI > 6 and KP < 7
The recommended settings to give optimal AFC performance
are KI = 11 and KP = 4.
To tradeoff between AFC settling time and AFC accuracy, the
KI and KP parameters can be adjusted from the recommended
settings (staying within the allowable range) such that
AFC Correction Range = MAX_AFC_RANGE × 500 Hz
When the RF_DIVIDE_BY_2 (R1_DB18) is enabled, the
programmed AFC correction range is halved. The user
accounts for this halving by doubling the programmed
MAX_AFC_RANGE value. For example, for a desired
correction range of ±5 kHz, with RF_DIVIDE_BY_2 enabled,
set MAX_AFC_RANGE (R10_DB[24:31]) equal to 20.
Signals that are within the AFC pull-in range but outside the IF
filter bandwidth are attenuated by the IF filter. As a result, the
signal can be below the sensitivity point of the receiver and,
therefore, not detectable by the AFC.
0
5876-040
KIKP AFC SCALING_FACTORMAX_AFC_RANGE
AFC_EN
ADDRESS
BITS
KP3
KP2
MA3
M4
M5
M6
M7
M11
M12
KI2
KI3
KI4
KP1
KI1
M8
M9
M10
M3
M2
MA4
MA5
C2 (1)
C1 (0)
C3 (0)
C4 (1)
AE1
M1
MA2
MA6
MA7
MA8
MA1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
KP1
0
1
.
1
2^0
2^1
...
2^7
AE1
0
1
AFC ENABLE
OFF
AFC ON
MA3
0
0
0
1
.
.
.
1
1
1
MA1
1
0
1
0
.
.
.
1
0
1
MAX AFC
RANGE
1
2
3
4
.
.
.
253
254
255
MA2
0
1
1
0
.
.
.
0
1
1
MA8
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
.
1
0
0
.
1
KP2KP3 KP KI1
0
1
.
1
2^0
2^1
...
2^15
0
0
.
1
0
0
.
1
KI2
KI3 KIKI4
0
0
.
1
M3
0
0
0
1
.
.
.
1
1
1
M1
1
0
1
0
.
.
.
1
0
1
AFC SCALING
FACTOR
1
2
3
4
.
.
.
4093
4094
4095
M2
0
1
1
0
.
.
.
0
1
1
M12
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
...
ADF7021 Data Sheet
Rev. D | Page 58 of 62
REGISTER 11—SYNC WORD DETECT REGISTER
Figure 73. Register 11—Sync Word Detect Register Map
REGISTER 12—SWD/THRESHOLD SETUP REGISTER
Figure 74. Register 12—SWD/Threshold Setup Register Map
Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking
the AFC and AGC loops when using linear or correlator demodulation.
05876-041
PL2
0
0
1
1
PL1
0
1
0
1
SYNC BYTE
LENGTH
12 BITS
16 BITS
20 BITS
24 BITS
MT2
0
0
1
1
MT1
0
1
0
1
MATCHING
TOLERANCE
ACCEPT 0 ERRORS
ACCEPT 1 ERROR
ACCEPT 2 ERRORS
ACCEPT 3 ERRORS
SYNC_BYTE_SEQUENCE
CONTROL
BITS
SYNC_BYTE_
LENGTH
MATCHING_
TOLERANCE
MT2
SB1
SB2
SB3
SB4
SB5
SB6
SB7
SB8
SB9
SB10
SB11
SB12
SB13
SB14
SB15
SB16
SB17
SB18
SB19
SB20
SB21
SB22
SB23
SB24
MT1
C2 (1)
C1 (1)
C3 (0)
C4 (1)
PL1
PL2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
DATA_PACKET_LENGTH
CONTROL
BITS
LOCK_
THRESHOLD_
MODE
SWD_MODE
IL2
IL1
C2 (0)
C1 (0)
C3 (1)
C4 (1)
LM1
LM2
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DB7
DB6
DB5
DB4
DB1
DB0
DB2
DB3
LOCK THRESHOLD MODE
0 THRESHOLD FREE RUNNING
1 LOCK THRESHOLD AFTER NEXT SYNCWORD
2 LOCK THRESHOLD AFTER NEXT SYNCWORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 LOCK THRESHOLD
DATA PACKET LENGTH
0 INVALID
1 1 BYTE
... ...
255 255 BYTES
SWD MODE
0 SWD PIN LOW
1 SWD PIN HIGH AFTER NEXT SYNCWORD
2 SWD PIN HIGH AFTER NEXT SYNCWORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 INTERRUPT PIN HIGH
0
5876-042
Data Sheet ADF7021
Rev. D | Page 59 of 62
REGISTER 13—3FSK/4FSK DEMOD REGISTER
Refer to the Receiver Setup section for information about programming these settings.
Figure 75. Register 13—3FSK/4FSK Demod Register Map
05876-043
3FSK_CDR_THRESHOLD
VITERBI_
PATH_
MEMORY
3FSK/4FSK_
SLICER_THRESHOLD
CONTROL
BITS
3FSK_VITERBI_
DETECTOR
PHASE_
CORRECTION
ST4
ST5
ST6
ST7
VD1
PC1
VM1
VM2
VT1
VT2
VT3
VT4
VT5
VT6
VT7
ST3
C2 (0)
C1 (1)
C3 (1)
C4 (1)
ST1
ST2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB1
DB0
DB2
DB3
3FSK_PREAMBLE_
TIME_VALIDATE
PTV1
PTV2
PTV3
PTV4
DB24
DB23
DB22
DB25
4 BITS
0
0
1
1
VM2
VITERBI PATH
MEMORY
VM1
0
1
0
1
6 BITS
8 BITS
32 BITS
PHASE
CORRECTION
0 DISABLED
1 ENABLED
PC1
3FSK VITERBI
DETECTOR
0 DISABLED
1 ENABLED
VD1
ST3
0
0
0
.
.
1
ST1
1
0
1
.
.
1
SLICER
THRESHOLD
1
2
3
.
.
ST2
0
1
1
.
.
1
ST7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
00
0... 0OFF
VT3
0
0
0
.
.
1
VT1
1
0
1
.
.
1
3FSK CDR
THRESHOLD
1
2
3
.
.
VT2
0
1
1
.
.
1
VT7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
00
0 ... 0OFF
PTV3
0
0
0
.
.
1
PTV1
1
0
1
.
.
1
3FSK PREMABLE
TIME VALIDATE
1
2
3
.
.
PTV2
0
1
1
.
.
1
PTV4
0
0
0
.
.
115
00
000
ADF7021 Data Sheet
Rev. D | Page 60 of 62
REGISTER 14—TEST DAC REGISTER
Figure 76. Register 14—Test DAC Register Map
The demodulator tuning parameters, PULSE_EXTENSION,
ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can only be
enabled by setting R15_DB[4:7] to 0x9.
Using the Test DAC to Implement Analog FM DEMOD
and Measuring SNR
The test DAC allows the post demodulator filter out for both
linear and correlator demodulators to be viewed externally. The
test DAC also takes the 16-bit filter output and converts it to a
high frequency, single-bit output using a second-order, error
feedback Σ-Δ converter. The output can be viewed on the SWD
pin. This signal, when filtered appropriately, can then be used to
do the following:
Monitor the signals at the FSK post demodulator filter
output. This allows the demodulator output SNR to be
measured. Eye diagrams of the received bit stream can also
be constructed to measure the received signal quality.
Provide analog FM demodulation.
While the correlators and filters are clocked by DEMOD CLK,
CDR CLK clocks the test DAC. Note that although the test
DAC functions in regular user mode, the best performance is
achieved when the CDR_CLK is increased to or above the
frequency of DEMOD CLK. The CDR block does not function
when this condition exists.
Programming Register 14 enables the test DAC. Both the
linear and correlator/demodulator outputs can be multiplexed
into the DAC.
Register 14 allows a fixed offset term to be removed from the
signal (to remove the IF component in the ddt case). It also has
a signal gain term to allow the usage of the maximum dynamic
range of the DAC.
TEST_DAC_GAIN TEST DAC OFFSET
TEST
TDAC EN
ED_PEAK_
RESPONSE
ED_LEAK_
FACTOR
PULSE_
EXTENSION
ADDRESS
BITS
TG3
TG2
ER2
TO4
TO5
TO6
TO7
TO11
TO12
TO14
TO15
TO16
TG1
TO13
TO8
TO9
TO10
TO3
TO2
EF1
EF2
C2 (1)
C1 (0)
C3 (1)
C4 (1)
TE1
TO1
ER1
EF3
PE1
PE2
TG4
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
PULSE EXTENSION
0
1
2
3
NO PULSE EXTENSION
EXTENDED BY 1
EXTENDED BY 2
EXTENDED BY 3
ED PEAK RESPONSE
0
1
2
3
FULL RESPONSE TO PEAK
0.5 RESPONSE TO PEAK
0.25 RESPONSE TO PEAK
0.125 RESPONSE TO PEAK
TEST DAC GAIN
0
1
...
15
NO GAIN
× 2^1
...
× 2^15
ED LEAK FACTOR
0
1
2
3
4
5
6
7
LEAKAGE =
2^–8
2^–9
2^–10
2^–11
2^–12
2^–13
2^–14
2^–15
05876-044
Data Sheet ADF7021
Rev. D | Page 61 of 62
REGISTER 15—TEST MODE REGISTER
Figure 77. Register 15—Test Mode Register Map
05876-045
Rx_TEST_
MODES
Tx_TEST_
MODES
Σ-∆_TEST_
MODES
PFD/CP_TEST_
MODES
PLL_TEST_
MODES
ANALOG_TEST_
MODES CLK_-MUX
FORCE_LD
HIGH
REG 1_PD
CAL_
OVERRIDE
ADDRESS
BITS
PM4
PM3
AM3
TM1
TM2
TM3
SD1
PC2
PC3
CM2
CM3
PM1
PM2
CM1
SD2
SD3
PC1
RT4
RT3
AM4
FH1
RD1
CO2
CO1
C2 (1)
C1 (1)
C3 (1)
C4 (1)
RT1
RT2
AM2
AM1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
ANALOG TEST MODES
0 BAND GAP VOLTGE
140µA CURRENT FROM REG4
2 FILTER I CHANNEL: STAGE 1
3 FILTER I CHANNEL: STAGE 2
4 FILTER I CHANNEL: STAGE 1
5 FILTER Q CHANNEL: STAGE 1
6 FILTER Q CHANNEL: STAGE 2
7 FILTER Q CHANNEL: STAGE 1
8 ADC REFERENCE VOLTAGE
9 BIAS CURRENT FROM RSSI 5µA
10 FILTER COARSE CAL OSCILLATOR O/P
11 ANALOG RSSI I CHANNEL
12 OSET LOOP +VE FBACK V (I CH)
13 SUMMED O/P OF RSSI RECTIFIER+
14 SUMMED O/P OF RSSI RECTIFIER–
15 BIAS CURRENT FROM BB FILTER
Rx TEST MODES
0NORMAL
1 SCLK, SDATA -> I, Q
2 REVERSE I,Q
3
LINEAR SLICER ON RXDATA
4
CORRELATOR SLICER ON TxRxDATA
ADDITIONAL FILTERING ON I, Q
ENVELOPE DETECTOR WATCHDOG DISABLED
RESERVED
ENABLE REG 14 DEMOD PARAMETERS
PROHIBIT CALACTIVE
ENABLE DEMOD DURING CAL
FORCE CALACTIVE
5
6
I,Q TO TxRxCLK, TxRxDATA
7
8
9
10
11
12
POWER DOWN DDT AND ED IN T/4 MODE
13
14
15
Tx TEST MODES
0
Tx CARRIER ONLY
1
Tx +VE TONE ONLY
2
Tx –VE TONE ONLY
3
Tx "1010" PATTERN
4
Tx PN9 DATA, AT PROGRAMED RATE
5
Tx SYNC BYTE REPEATEDLY
6
Σ-∆TEST MODES
0 DEFAULT, 3RD ORDER SD, NO DITHER
1 1ST ORDER SD
2 2ND ORDER SD
3 DITHER TO FIRST STAGE
4 DITHER TO SECOND STAGE
5 DITHER TO THIRD STAGE
6DITHER×8
7DITHER×32
PLL TEST MODES
0 NORMAL OPERATION
1RDIV
2NDIV
3 RCNTR/2 ON MUXOUT
4 NCNTR/2 ON MUXOUT
5 ACNTR TO MUXOUT
6 PFD PUMP UP TO MUXOUT
7 PFD PUMP DN TO MUXOUT
8 SDATA TO MUXOUT (OR SREAD?)
9 ANALOG LOCK DETECT ON MUXOUT
10 END OF COARSE CAL ON MUXOUT
11 END OF FINE CAL ON MUXOUT
12
13 TEST MUX SELECTS DATA
14 LOCK DETECT PERCISION
15 RESERVED
PFD/CP TEST MODES
0 DEFAULT, NO BLEED
1 (+VE) CONSTANT BLEED
2 (–VE) CONSTANT BLEED
3 (–VE) PULSED BLEED
4 (–VE) PULSE BLD, DELAY UP?
5 CPPUMPUP
6CPTRI-STATE
7 CPPUMPDN
CLK MUXES on CLKOUT pin
0
1
2
3
4
5
6
7
CAL OVERRIDE
0 AUTO CAL
1 OVERRIDE GAIN
2 OVERRIDE BW
3 OVERRIDE BW AND GAIN
FORCE LD HIGH
0NORMAL
1 FORCE
REG1 PD
0NORMAL
1PWRDWN
SDATA TO CDR
FORCE NEW PRESCALER CONFIG.
FOR ALL N
NORMAL OPERATION
NORMAL, NO OUTPUT
DEMOD CLK
CDR CLK
SEQ CLK
BB OFFSET CLK
SIGMA DELTA CLK
ADC CLK
TxRxCLK
3FSK SLICER ON TxRxDATA
ADF7021 Data Sheet
Rev. D | Page 62 of 62
OUTLINE DIMENSIONS
Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description2 Package Option
ADF7021BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-5
ADF7021BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-5
ADF7021BCPZ-RL7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-5
EVAL-ADF70XXMBZ2 Mother Board
EVAL-ADF7021DBJZ 426 MHz to 429 MHz Daughter Board
EVAL-ADF7021DBZ2 860 MHz to 870 MHz Daughter Board
EVAL-ADF7021DBZ3 431 MHz to 470 MHz Daughter Board
EVAL-ADF7021DBZ5 80 MHz to 650 MHz Daughter Board
EVAL-ADF7021DBZ6 608 MHz to 614 MHz Daughter Board
EVAL-ADF7021DB9Z 169 MHz Daughter Board
1 Z = RoHS Compliant Part.
2 Maximum ordering quantity for all daughter boards is three. EVAL-ADF70XXMBZ2 is the required mother board for the daughter boards.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN1
INDICATOR
4.25
4.10 SQ
3.95
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 MIN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
08-16-2010-B
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05876-0-9/16(D)
