SST39VF1601C/SST39VF1602C 16 Mbit (x16) Multi-Purpose Flash Plus The SST39VF1601C / SST39VF1602C devices are 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF1601C / SST39VF1602C write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. 1.0 FEATURES * Organized as 1M x16: SST39VF1601C/1602C * Single Voltage Read and Write Operations - 2.7-3.6V * Superior Reliability - Endurance: 100,000 Cycles (Typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 9 mA (typical) - Standby Current: 3 A (typical) - Auto Low Power Mode: 3 A (typical) * Hardware Block-Protection/WP# Input Pin - Top Block-Protection (top 8 KWord) - Bottom Block-Protection (bottom 8 KWord) * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Flexible block architecture; one 8-, two 4-, one 16-, and thirty one 32-KWord blocks * Chip-Erase Capability * Erase-Suspend/Erase-Resume Capabilities * Hardware Reset Pin (RST#) * Latched Address and Data * Security-ID Feature - SST: 128 bits; User: 128 words * Fast Read Access Time: - 70 ns * Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) - Word-Program Time: 7 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bits 2015-2018 Microchip Technology Inc. * * * * - Data# Polling - Ready/Busy# Pin CMOS I/O Compatibility JEDEC Standard - Flash EEPROM Pinouts and command sets Packages Available - 48-lead TSOP (12mm x 20mm) - 48-ball TFBGA (6mm x 8mm) - 48-ball WFBGA (4mm x 6mm) All devices are RoHS compliant 2.0 PRODUCT DESCRIPTION The SST39VF1601C and SST39VF1602C devices are 1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF160xC writes (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39VF1601C/1602C devices provide a typical Word-Program time of 7 sec. These devices use Toggle Bit, Data# Polling, or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF1601C/1602C devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during DS20005018B-page 1 SST39VF1601C/SST39VF1602C Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF1601C/1602C are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 4-1, 4-2, and 4-3 for pin assignments. TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2015-2018 Microchip Technology Inc. DS20005018B-page 2 SST39VF1601C/SST39VF1602C 3.0 BLOCK DIAGRAM X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# RY/BY# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 1380 B1.0 FIGURE 3-1: FUNCTIONAL BLOCK DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 3 SST39VF1601C/SST39VF1602C 4.0 PIN ASSIGNMENTS A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RST# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1380 48-tsop P01.0 FIGURE 4-1: PIN ASSIGNMENTS FOR 48-LEAD TSOP 2015-2018 Microchip Technology Inc. DS20005018B-page 4 SST39VF1601C/SST39VF1602C TOP VIEW (balls facing down) SST39VF1601C/1602C 6 5 A13 A12 A14 A15 A16 NC DQ15 VSS A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# NC A19 DQ5 DQ12 VDD DQ4 RY/BY# WP# A18 NC DQ2 DQ10 DQ11 DQ3 A9 4 3 2 1 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 1380 48-tfbga B3K P02.0 FIGURE 4-2: PIN ASSIGNMENTS FOR 48-BALL TFBGA TOP VIEW (balls facing down) SST39WF160xC 6 5 4 3 2 1 A2 A4 A6 A17 A1 A3 A7 WP# A0 A5 A18 NC NC WE# RST# A9 A11 RY/BY# A10 A13 A14 A8 A12 A15 CE# DQ8 DQ10 VSS OE# DQ9 A19 DQ4 DQ11 A16 NC DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS A B C D E F G H J K L 1380 48-wfbga MAQ P03.0 FIGURE 4-3: PIN ASSIGNMENTS FOR 48-BALL WFBGA 2015-2018 Microchip Technology Inc. DS20005018B-page 5 SST39VF1601C/SST39VF1602C TABLE 4-1: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. To provide power supply voltage: 2.7-3.6V VDD Power Supply VSS Ground NC No Connection Unconnected pins. RY/BY# Ready/Busy# To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. 1. AMS = Most significant address AMS = A19 2015-2018 Microchip Technology Inc. DS20005018B-page 6 SST39VF1601C/SST39VF1602C TABLE 4-2: TOP/BOTTOM BOOT BLOCK ADDRESS Top Boot Block Address SST39VF1602C # Size (KWord) Bottom Boot Block Address SST39VF1601C Address Range # Size (KWord) Address Range 34 8 FE000H-FFFFFH 34 32 F8000H-FFFFFH 33 4 FD000H-FDFFFH 33 32 F0000H-F7FFFH 32 4 FC000H-FCFFFH 32 32 E8000H-EFFFFH 31 16 F8000H-FBFFFH 31 32 E0000H-E7FFFH 30 32 F0000H-F7FFFH 30 32 D8000H-DFFFFH 29 32 E8000H-EFFFFH 29 32 D0000H-D7FFFH 28 32 E0000H-E7FFFH 28 32 C8000H-CFFFFH 27 32 D8000H-DFFFFH 27 32 C0000H-C7FFFH 26 32 D0000H-D7FFFH 26 32 B8000H-BFFFFH 25 32 C8000H-CFFFFH 25 32 B0000H-B7FFFH 24 32 C0000H-C7FFFH 24 32 A8000H-AFFFFH 23 32 B8000H-BFFFFH 23 32 A0000H-A7FFFH 22 32 B0000H-B7FFFH 22 32 98000H-9FFFFH 21 32 A8000H-AFFFFH 21 32 90000H-97FFFH 20 32 A0000H-A7FFFH 20 32 88000H-8FFFFH 19 32 98000H-9FFFFH 19 32 80000H-87FFFH 18 32 90000H-97FFFH 18 32 78000H-7FFFFH 17 32 88000H-8FFFFH 17 32 70000H-77FFFH 16 32 80000H-87FFFH 16 32 68000H-6FFFFH 15 32 78000H-7FFFFH 15 32 60000H-67FFFH 14 32 70000H-77FFFH 14 32 58000H-5FFFFH 13 32 68000H-6FFFFH 13 32 50000H-57FFFH 12 32 60000H-67FFFH 12 32 48000H-4FFFFH 11 32 58000H-5FFFFH 11 32 40000H-47FFFH 10 32 50000H-57FFFH 10 32 38000H-3FFFFH 9 32 48000H-4FFFFH 9 32 30000H-37FFFH 8 32 40000H-47FFFH 8 32 28000H-2FFFFH 7 32 38000H-3FFFFH 7 32 20000H-27FFFH 6 32 30000H-37FFFH 6 32 18000H-1FFFFH 5 32 28000H-2FFFFH 5 32 10000H-17FFFH 4 32 20000H-27FFFH 4 32 08000H-0FFFFH 3 32 18000H-1FFFFH 3 16 04000H-07FFFH 2 32 10000H-17FFFH 2 4 03000H-03FFFH 1 32 08000H-0FFFFH 1 4 02000H-02FFFH 0 32 00000H-07FFFH 0 8 00000H-01FFFH 2015-2018 Microchip Technology Inc. DS20005018B-page 7 SST39VF1601C/SST39VF1602C 5.0 DEVICE OPERATION Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF1601C/1602C also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. 5.1 Read The Read operation of the SST39VF1601C/1602C is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 8-1). 5.2 Word-Program Operation The SST39VF1601C/1602C are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figures 8-2 and 8-3 for WE# and CE# controlled Program operation timing diagrams and Figure 8-17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued 2015-2018 Microchip Technology Inc. during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. 5.3 Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or blockby-block) basis. The SST39VF1601C/1602C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on non-uniform block sizes--thirty-one 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks. See Figure 7-1 for top and bottom boot device block addresses. The Sector-Erase operation is initiated by executing a six-byte command sequence with SectorErase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with BlockErase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 8-7 and 8-8 for timing waveforms and Figure 8-21 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. 5.4 Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at `1'. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. DS20005018B-page 8 SST39VF1601C/SST39VF1602C 5.5 Chip-Erase Operation an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/ BY# status is valid. The SST39VF1601C/1602C provide a Chip-Erase operation, which allows the user to erase the entire memory array to the `1' state. This is useful when the entire device must be quickly erased. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is still in progress. When RY/BY# is high (Ready), the devices may be read or left in Standby mode. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6-2 for the command sequence, Figure 8-6 for timing diagram, and Figure 821 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. 5.6 5.8 Data# Polling (DQ7) When the SST39VF1601C/1602C are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or ChipErase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8-4 for Data# Polling timing diagram and Figure 8-18 for a flowchart. Write Operation Status Detection The SST39VF1601C/1602C provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. 5.9 Toggle Bits (DQ6 and DQ2) The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `1's and `0's, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or ChipErase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to `1' if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. 5.7 An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 5-1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 8-5 for Toggle Bit timing diagram and Figure 818 for a flowchart. Ready/Busy# (RY/BY#) The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via TABLE 5-1: WRITE OPERATION STATUS Status Normal Operation Standard Program Standard Erase 2015-2018 Microchip Technology Inc. DQ7 DQ6 DQ2 RY/BY# DQ7# Toggle No Toggle 0 0 Toggle Toggle 0 DS20005018B-page 9 SST39VF1601C/SST39VF1602C TABLE 5-1: WRITE OPERATION STATUS Status Erase-Suspend Mode DQ7 DQ6 DQ2 RY/BY# Read from EraseSuspended Sector/Block 1 1 Toggle 1 Read from Non-EraseSuspended Sector/Block Data Data Data 1 Program DQ7# Toggle N/A 0 NOTE: DQ7 and DQ2 require a valid address when reading status information. 5.10 Data Protection The SST39VF1601C/1602C provide both hardware and software features to protect nonvolatile data from inadvertent writes. 5.11 Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. 5.12 Hardware Block Protection The SST39VF1602C supports top hardware block protection, which protects the top 8 KWord block of the device. The SST39VF1601C supports bottom hardware block protection, which protects the bottom 8KWord block of the device. The Boot Block address ranges are described in Table 5-2. Program and Erase operations are prevented on the 8 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. TABLE 5-2: BOOT BLOCK ADDRESS RANGES Product Address Range Bottom Boot Block SST39VF1601C 00000H - 01FFFH Top Boot Block SST39VF1602C FE000H - FFFFFH 0 5.13 Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 8-13). The Erase or Program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. 5.14 Software Data Protection (SDP) The SST39VF1601C/1602C provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal pro- 2015-2018 Microchip Technology Inc. tection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6-2 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. 5.15 Common Flash Memory Interface (CFI) The SST39VF1601C/1602C also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the Address DS20005018B-page 10 SST39VF1601C/SST39VF1602C and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 6-3 through 6-5. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. 5.16 operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6-2 for software operation, Figure 8-9 for the Software ID Entry and Read timing diagram and Figure 8-19 for the Software ID Entry command sequence flowchart. Product Identification The Product Identification mode identifies the devices as the SST39VF1601C, SST39VF1602C, and manufacturer as SST. This mode may be accessed software TABLE 5-3: PRODUCT IDENTIFICATION Address Data 0000H BFH SST39VF1601C 0001H 234FH SST39VF1602C 0001H 234EH Manufacturer's ID Device ID 5.17 Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 6-2 for software command codes, Figure 811 for timing waveform, and Figure 8-20 for flowcharts. 5.18 The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6-2 for more details. Security ID The SST39VF1601C/1602C devices offer a 136 Word Security ID space. The Secure ID space is divided into two segments--one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment, with a 128 word space, is left unprogrammed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. 2015-2018 Microchip Technology Inc. DS20005018B-page 11 SST39VF1601C/SST39VF1602C 6.0 OPERATIONS TABLE 6-1: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIH VIL 1 Erase VIL Standby VIH X X VIL X VIL Write Inhibit X Sector or block address, XXH for ChipErase X High Z X X High Z/ DOUT X X VIH High Z/ DOUT X VIL VIH Product Identification Software Mode See Table 6-2 1. X can be VIL or VIH, but no other value. TABLE 6-2: Command Sequence SOFTWARE COMMAND SEQUENCE 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle 2 Addr1 3rd Bus Write Cycle 4th Bus Write Cycle Data Addr Data Addr 2 1 2 1 5th Bus Write Cycle Data2 Addr1 Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Data Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 6th Bus Write Cycle Data Addr Data 55H SAX4 50H 30H 10H 2 1 Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX4 Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H Erase-Suspend XXXH B0H Erase-Resume XXXH 30H Query Sec ID5 555H AAH 2AAH 55H 555H 88H User Security ID Word-Program 555H AAH 2AAH 55H 555H A5H WA6 Data User Security ID Program LockOut 555H AAH 2AAH 55H 555H 85H XXH6 0000 H Software ID Entry7,8 555H AAH 2AAH 55H 555H 90H CFI Query Entry 555H AAH 2AAH 55H 555H 98H CFI Query Entry 55H 98H Software ID Exit9,10 /CFI Exit/Sec ID Exit 555H AAH 2AAH 55H 555H F0H Software ID Exit9,10 /CFI Exit/Sec ID Exit XXH F0H 2 1. 2. 3. 4. Address format A10-A0 (Hex). Addresses A11-A19 can be VIL or VIH, but no other value, for Command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence WA = Program Word address SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address; AMS = A19 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000008H to 000087H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 2015-2018 Microchip Technology Inc. DS20005018B-page 12 SST39VF1601C/SST39VF1602C 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF1601C Device ID = 234FH, is read with A0 = 1, SST39VF1602C Device ID = 234EH, is read with A0 = 1, AMS = Most significant address; AMS = A19 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed `0' bits cannot be reversed to `1'). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H. TABLE 6-3: CFI QUERY IDENTIFICATION STRING1 Address Data 10H 0051H 11H 0052H 12H 0059H 13H 0002H 14H 0000H 15H 0000H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) 1. Refer to CFI publication 100 for more details. TABLE 6-4: SYSTEM INTERFACE INFORMATION Address Data 1BH 0027H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0003H Typical time out for Word-Program 2N s (23 = 8 s) 20H 0000H Typical time out for min. size buffer program 2N s (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 s) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) TABLE 6-5: DEVICE GEOMETRY INFORMATION Address Data 27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H 2BH 0000H 2CH 0005H Data Maximum number of byte in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device 2015-2018 Microchip Technology Inc. DS20005018B-page 13 SST39VF1601C/SST39VF1602C TABLE 6-5: DEVICE GEOMETRY INFORMATION Address Data 2DH 0000H 2EH 0000H 2FH 0040H 30H 0000H 31H 0001H 32H 0000H 33H 0020H 34H 0000H 35H 0000H 36H 0000H 37H 0080H 38H 0000H 39H 001EH 3AH 0000H 3BH 0000H 3CH 0001H Data Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information 2015-2018 Microchip Technology Inc. DS20005018B-page 14 SST39VF1601C/SST39VF1602C 7.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. TABLE 7-1: AC CONDITIONS OF TEST1 Input Rise/Fall Time Output Load 5ns CL = 30 pF 1. See Figures 8-15 and 8-16 TABLE 7-2: OPERATING RANGE Range Commercial Industrial 7.1 Ambient Temp VDD 0C to +70C 2.7-3.6V -40C to +85C 2.7-3.6V Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. TPU-READ > 100 s VDD min VDD 0V RESET# VIH TRHR > 50ns CE# 1380 F24.0 FIGURE 7-1: POWER-UP DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 15 SST39VF1601C/SST39VF1602C TABLE 7-3: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1 Limits Symbol Parameter IDD Min Max Units Test Conditions Address input=VILT/VIHT2, at f=5 MHz, VDD=VDD Max Power Supply Current Read3 18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 20 A CE#=VIHC, VDD=VDD Max IALP Auto Low Power 20 A CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# 10 A WP#=GND to VDD or RST#=GND to VDD ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage 0.2 VDD-0.2 V VDD=VDD Max V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 8-15 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. TABLE 7-4: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Program/Erase Operation 100 s 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7-5: Parameter CI/O 1 CIN1 CAPACITANCE (TA = 25C, F=1 MHZ, OTHER PINS OPEN) Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7-6: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. 2015-2018 Microchip Technology Inc. DS20005018B-page 16 SST39VF1601C/SST39VF1602C 8.0 AC CHARACTERISTICS TABLE 8-1: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol Parameter TRC Read Cycle Time Min TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns 1 CE# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCLZ Max Units 70 ns ns ns 1 CE# High to High-Z Output 20 ns TOHZ1 OE# High to High-Z Output 20 ns TCHZ TOH 1 0 ns TRP1 Output Hold from Address Change RST# Pulse Width 500 ns TRHR1 TRY1,2 RST# High before Read 50 ns RST# Pin Low to Read Mode 20 s 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to ChipErase operations. TABLE 8-2: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 TIDA1 Software ID Access and Exit Time TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms TBY1,2 RY/BY# Delay Time TBR 1 Bus Recovery Time 10 Units s ns 150 90 ns ns 0 s 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. 2015-2018 Microchip Technology Inc. DS20005018B-page 17 SST39VF1601C/SST39VF1602C TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TOH TCLZ HIGH-Z HIGH-Z DQ15-0 DATA VALID DATA VALID 1380 F03.0 Note: AMS = Most significant address FIGURE 8-1: READ CYCLE TIMING DIAGRAM TBP ADDRESSES 555 2AA 555 ADDR TAH TWP WE# TWPH TAS OE# TCH CE# TCS TBY TBR RY/BY# TDS DQ15-0 XXAA XX55 XXA0 TDH DATA WORD (ADDR/DATA) VALID 1380 F25.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 8-2: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 18 SST39VF1601C/SST39VF1602C TBP 555 ADDRESSES 2AA 555 ADDR TAH TCP CE# TAS TCPH OE# TCH WE# TCS TBY TBR RY/BY# TDS DQ15-0 XXAA XX55 XXA0 TDH DATA VALID WORD (ADDR/DATA) 1380 F26.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 8-3: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A19-0 TCE CE# TOEH TOES OE# TOE WE# TBY RY/BY# DQ7 DATA DATA# DATA# DATA 1380 F27.0 FIGURE 8-4: DATA# POLLING TIMING DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 19 SST39VF1601C/SST39VF1602C ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1380 F07.0 Note: AMS = Most significant address FIGURE 8-5: TOGGLE BITS TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 555 2AA 555 555 2AA 555 CE# OE# TOEH WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 1380 F31.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 8-2). WP# must be held in proper logic state (VIH) 1s prior to and 1s after the command sequence. FIGURE 8-6: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 20 SST39VF1601C/SST39VF1602C TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 555 2AA 555 555 2AA BAX CE# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 1380 F32.0 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 8-2). BAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. FIGURE 8-7: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 555 2AA 555 555 2AA SAX CE# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1380 F28.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 8-2). SAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. FIGURE 8-8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM 2015-2018 Microchip Technology Inc. DS20005018B-page 21 SST39VF1601C/SST39VF1602C Three-Byte Sequence for Software ID Entry 555 ADDRESS 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BF Device ID 1380 F11.0 Note: Device ID = 234BH for SST39VF1601C and 234AH for SST39VF1602C. WP# must be held in proper logic state (VIL or VIH) 1s after the command sequence. X can VIL or VIH but no other value. FIGURE 8-9: SOFTWARE ID ENTRY AND READ Three-Byte Sequence for CFI Query Entry ADDRESS 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX98 SW0 SW1 SW2 1380 F12.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s after the command sequence. X can VIL or VIH but no other value. FIGURE 8-10: CFI QUERY ENTRY AND READ 2015-2018 Microchip Technology Inc. DS20005018B-page 22 SST39VF1601C/SST39VF1602C THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS DQ15-0 555 2AA XXAA 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1380 F13.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can VIL or VIH but no other value. FIGURE 8-11: SOFTWARE ID EXIT/CFI EXIT THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1380 F20.0 Note: AMS = Most significant address AMS = A19 WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can VIL or VIH but no other value. FIGURE 8-12: SEC ID ENTRY 2015-2018 Microchip Technology Inc. DS20005018B-page 23 SST39VF1601C/SST39VF1602C RY/BY# 0V TRP RST# TRHR CE#/OE# 1380 F29.0 FIGURE 8-13: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) TRY RY/BY# TRP RST# CE# TBR OE# 1380 F30.0 FIGURE 8-14: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1380F14.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic `1' and VILT (0.1 VDD) for a logic `0'. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 8-15: AC INPUT/OUTPUT REFERENCE WAVEFORMS 2015-2018 Microchip Technology Inc. DS20005018B-page 24 SST39VF1601C/SST39VF1602C TO TESTER TO DUT CL 1380 F15.0 FIGURE 8-16: A TEST LOAD EXAMPLE Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed X can be VIL or VIH, but no other value 1380 F16.0 FIGURE 8-17: WORD-PROGRAM ALGORITHM 2015-2018 Microchip Technology Inc. DS20005018B-page 25 SST39VF1601C/SST39VF1602C Internal Timer Toggle Bit Data# Polling RY/BY# Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read RY/BY# Read same word Program/Erase Completed No Is DQ7 = true data? No Is RY/BY# = 1? Yes Yes No Does DQ6 match? Program/Erase Completed Program/Erase Completed Yes Program/Erase Completed 1380 F17.1 FIGURE 8-18: WAIT OPTIONS 2015-2018 Microchip Technology Inc. DS20005018B-page 26 SST39VF1601C/SST39VF1602C CFI Query Entry Command Sequence Sec ID Query Entry Command Sequence Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H Load data: XX98H Address: 55H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Wait TIDA Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX98H Address: 55H Read CFI data Load data: XX88H Address: 555H Load data: XX90H Address: 555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Sec ID Read Software ID X can be VIL or VIH, but no other value 1380 F21.0 FIGURE 8-19: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS 2015-2018 Microchip Technology Inc. DS20005018B-page 27 SST39VF1601C/SST39VF1602C Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAH Wait TIDA Load data: XXF0H Address: 555H Return to normal operation Wait TIDA Return to normal operation X can be VIL or VIH, but no other value 1380 F18.0 FIGURE 8-20: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS 2015-2018 Microchip Technology Inc. DS20005018B-page 28 SST39VF1601C/SST39VF1602C Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX50H Address: SAX Load data: XX30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH X can be VIL or VIH, but no other value 1380 F19.0 FIGURE 8-21: ERASE COMMAND SEQUENCE 2015-2018 Microchip Technology Inc. DS20005018B-page 29 SST39VF1601C/SST39VF1602C Product Ordering Information SST 39 XX VF XX 1601C XXXXX - 70 XX - 4I XX - EKE XXX Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Q = 48 balls (66 possible positions) Package Type E = TSOP (type1, die up, 12mm x 20mm) B3 = TFBGA (6mm x 8mm, 0.8mm pitch) MA = WFBGA (4mm x 6mm, 0.5mm pitch) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 160 = 16 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash 1.Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". 8.0.1 VALID COMBINATIONS FOR SST39VF1601C SST39VF1601C-70-4C-EKE SST39VF1601C-70-4C-B3KE SST39VF1601C-70-4C-MAQE SST39VF1601C-70-4I-EKE SST39VF1601C-70-4I-B3KE SST39VF1601C-70-4I-MAQE 8.0.2 VALID COMBINATIONS FOR SST39VF1602C SST39VF1602C-70-4C-EKE SST39VF1602C-70-4C-B3KE SST39VF1602C-70-4C-MAQE SST39VF1602C-70-4I-EKE SST39VF1602C-70-4I-B3KE SST39VF1602C-70-4I-MAQE Note: Valid combinations are those products in mass production or will be in mass production. Consult your Microchip sales representative to confirm availability of valid combinations and to determine availability of new combinations 2015-2018 Microchip Technology Inc. DS20005018B-page 30 SST39VF1601C/SST39VF1602C 9.0 PACKAGING DIAGRAMS 2015-2018 Microchip Technology Inc. DS20005018B-page 31 SST39VF1601C/SST39VF1602C 2015-2018 Microchip Technology Inc. DS20005018B-page 32 SST39VF1601C/SST39VF1602C 48-Ball Thin Profile Fine Pitch Ball Grid Array (CD) - 6x8 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C D A B (DATUM B) 6 5 4 E 3 2 2X E/4 1 0.15 C A B C D E F G H (DATUM A) NOTE 1 D/4 TOP VIEW DETAIL A A SEATING PLANE C A1 SIDE VIEW D1 eD eD/2 eE 1 2 3 E1 4 5 eE/2 6 DETAIL B A B C D E F G H BOTTOM VIEW Microchip Technology Drawing C04-168C Sheet 1 of 2 2015-2018 Microchip Technology Inc. DS20005018B-page 33 SST39VF1601C/SST39VF1602C 48-Ball Thin Profile Fine Pitch Ball Grid Array (CD) - 6x8 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 0.12 C C DETAIL A nX Ob 0.15 0.08 C A B C DETAIL B Units Dimension Limits n Number of Solder Balls eD Solder Ball X-Pitch eE Solder Ball Y-Pitch A Overall Height Ball Height A1 D Overall Length D1 Overall Solder Ball X-Pitch E Overall Width Overall Solder Ball Y-Pitch E1 b Solder Ball Diameter MIN 1.00 0.30 0.40 MILLIMETERS NOM 48 0.80 BSC 0.80 BSC 1.10 0.35 8.00 BSC 5.60 BSC 6.00 BSC 4.00 BSC 0.45 MAX 1.20 0.40 0.50 Notes: 1. Ball A1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 3. Ball interface to package body: 0.38mm nominal diameter. Microchip Technology Drawing C04-168C Sheet 2 of 2 2015-2018 Microchip Technology Inc. DS20005018B-page 34 SST39VF1601C/SST39VF1602C 48-ball, Very, Very Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6 mm 48-wfbga-MAQ-4x6-32mic-2. Note: 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger and bottom side A1 indicator is triangle at corner. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. Ball opening size is 0.29 mm ( 0.05 mm) 2015-2018 Microchip Technology Inc. DS20005018B-page 35 SST39VF1601C/SST39VF1602C TABLE 9-1: REVISION HISTORY Number Description Date 00 * Initial release Apr 2008 01 * * Corrected typo in Hardware Block Protection on page 4 Corrected typo in table title, Table 5 page 8 Sep 2008 02 * Changed 1V per 100 s to 1V per 100 ms in Power Up Specifications on page 12 Jan 2009 03 * * Changed from Preliminary Specification to Data Sheet Clarified RY/BY# pin timing by updating Features, Figures 8-2, 8-3, 8-4, 8-6, 8-7, 8-8, 8-13, 8-14, and 8-18, and Tables 5-1 and 8-2. Aug 2009 04 * * Added information for MAQE package Updated SST address information on page 33 May 2010 A * * * Applied new document format Released document under letter revision system Updated spec number S71380 to DS-25018 May 2011 B * * * Applied new document format Corrected Figure 8-3 Updated TSOP and TFBGA package drawings May 2018 2015-2018 Microchip Technology Inc. DS20005018B-page 36 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, InterChip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2971-5 == ISO/TS 16949 == 2018 Microchip Technology Inc. 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