2015-2018 Microchip Technology Inc. DS20005018B-page 1
1.0 FEATURES
• Organized as 1M x16: SST39VF1601C/1602C
• Single Voltage Read and Write Operations
- 2.7-3.6V
• Superior Reliability
- Endurance: 100,000 Cycles (Typical)
- Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5
MHz)
- Active Current: 9 mA (typical)
- Standby Current: 3 µA (typical)
- Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
- Top Block-Protection (top 8 KWord)
- Bottom Block-Protection (bottom 8 KWord)
• Sector-Erase Capability
- Uniform 2 KWord sectors
• Block-Erase Capability
- Flexible block architecture; one 8-, two 4-, one
16-, and thirty one 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• Security-ID Feature
- SST: 128 bits; User: 128 words
• Fast Read Access Time:
- 70 ns
• Fast Erase and Word-Program:
- Sector-Erase Time: 18 ms (typical)
- Block-Erase Time: 18 ms (typical)
- Chip-Erase Time: 40 ms (typical)
- Word-Program Time: 7 µs (typical)
• Automatic Write Timing
- Internal VPP Generation
•End-of-Write Detection
- Toggle Bits
- Data# Polling
- Ready/Busy# Pin
• CMOS I/O Compatibility
• JEDEC Standard
- Flash EEPROM Pinouts and command sets
• Packages Available
- 48-lead TSOP (12mm x 20mm)
- 48-ball TFBGA (6mm x 8mm)
- 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
2.0 PRODUCT DESCRIPTION
The SST39VF1601C and SST39VF1602C devices are
1M x16 CMOS Multi-Purpose Flash Plus (MPF+) man-
ufactured with SST proprietary, high performance
CMOS SuperFlash technology. The split-gate cell
design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alter-
nate approaches. The SST39VF160xC writes (Pro-
gram or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pinouts for x16
memories.
Featuring high performance Word-Program, the
SST39VF1601C/1602C devices provide a typical
Word-Program time of 7 µsec. These devices use Tog-
gle Bit, Data# Polling, or the RY/BY# pin to indicate the
completion of Program operation. To protect against
inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applica-
tions, these devices are offered with a guaranteed
typical endurance of 100,000 cycles. Data retention is
rated at greater than 100 years.
The SST39VF1601C/1602C devices are suited for
applications that require convenient and economical
updating of program, configuration, or data memory.
For all system applications, they significantly improve
performance and reliability, while lowering power
consumption. They inherently use less energy during
The SST3 9VF1601C / SST3 9VF1602C devices are 1M x16 CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS
SuperFlash technol ogy. The spl it-ga te cell design and thick-oxide tunnelin g injec-
tor attain better reliability and manufacturability compared with alternate
appro aches. The SST39VF1601C / SST39VF1602C write (Program or Erase)
with a 2.7-3.6V power suppl y. These devices conform to JEDE C st andard pin-
outs for x16 memorie s .
SST39VF1601C/SST39VF1602C
16 Mbit (x16) Multi-Purpose Flash Plus
2015-2018 Microchip Technology Inc. DS20005018B-page 2
SST39VF1601C/SST39VF1602C
Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash technolo-
gies. These devices also improve flexibility while
lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies, whose Erase and Program times increase
with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF1601C/1602C are offered in 48-lead TSOP,
48-ball TFBGA, and 48-ball WFBGA packages. See
Figures 4-1, 4-2, and 4-3 for pin assignments.
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2015-2018 Microchip Technology Inc. DS20005018B-page 3
SST39VF1601C/SST39VF1602C
3.0 BLOCK DIAGRAM
FIGURE 3-1: FUNCTIONAL BLOCK DIAGRAM
Y-Decoder
I/O Buffers and Data Latches
1380 B1.0
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
RY/BY#
2015-2018 Microchip Technology Inc. DS20005018B-page 4
SST39VF1601C/SST39VF1602C
4.0 PIN ASSIGNMENTS
FIGURE 4-1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1380 48-tsop P01.0
Standard Pinout
Top Vie w
Die Up
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
2015-2018 Microchip Technology Inc. DS20005018B-page 5
SST39VF1601C/SST39VF1602C
FIGURE 4-2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
FIGURE 4-3: PIN ASSIGNMENTS FOR 48-BALL WFBGA
A13
A9
WE#
RY/BY#
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
NC
A18
A6
A2
A15
A11
A19
NC
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
1380 48-tfbga B3K P02
.0
SST39VF1601C/1602C
TOP VIEW (balls facing down)
6
5
4
3
2
1
A B C D E F G H
A2
A1
A0
CE#
VSS
A4
A3
A5
DQ8
OE#
DQ0
A6
A7
A18
DQ10
DQ9
DQ1
A17
WP#
A19
DQ2
NC
DQ3
NC
VDD
WE#
DQ12
RST#
RY/BY#
NC
DQ13
A9
A10
A8
DQ4
DQ5
DQ14
A11
A13
A12
DQ11
DQ6
DQ15
A14
A15
A16
DQ7
VSS
TOP VIEW (balls facing down)
A B C D E F G H J K L
6
5
4
3
2
1
1380 48-wfbga MAQ P03.0
SST39WF160xC
2015-2018 Microchip Technology Inc. DS20005018B-page 6
SST39VF1601C/SST39VF1602C
TABLE 4-1: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0
1. AMS = Most significant address
AMS = A19
Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
RY/BY# Ready/Busy# To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
2015-2018 Microchip Technology Inc. DS20005018B-page 7
SST39VF1601C/SST39VF1602C
TABLE 4-2: TOP/BOTTOM BOOT BLOCK ADDRESS
Top Boot Block Address SST39VF1602C Bottom Boot Block Address SST39VF1601C
#Size
(KWord) Address Range # Size
(KWord) Address Range
34 8 FE000H-FFFFFH 34 32 F8000H-FFFFFH
33 4 FD000H-FDFFFH 33 32 F0000H-F7FFFH
32 4 FC000H-FCFFFH 32 32 E8000H-EFFFFH
31 16 F8000H-FBFFFH 31 32 E0000H-E7FFFH
30 32 F0000H-F7FFFH 30 32 D8000H-DFFFFH
29 32 E8000H-EFFFFH 29 32 D0000H-D7FFFH
28 32 E0000H-E7FFFH 28 32 C8000H-CFFFFH
27 32 D8000H-DFFFFH 27 32 C0000H-C7FFFH
26 32 D0000H-D7FFFH 26 32 B8000H-BFFFFH
25 32 C8000H-CFFFFH 25 32 B0000H-B7FFFH
24 32 C0000H-C7FFFH 24 32 A8000H-AFFFFH
23 32 B8000H-BFFFFH 23 32 A0000H-A7FFFH
22 32 B0000H-B7FFFH 22 32 98000H-9FFFFH
21 32 A8000H-AFFFFH 21 32 90000H-97FFFH
20 32 A0000H-A7FFFH 20 32 88000H-8FFFFH
19 32 98000H-9FFFFH 19 32 80000H-87FFFH
18 32 90000H-97FFFH 18 32 78000H-7FFFFH
17 32 88000H-8FFFFH 17 32 70000H-77FFFH
16 32 80000H-87FFFH 16 32 68000H-6FFFFH
15 32 78000H-7FFFFH 15 32 60000H-67FFFH
14 32 70000H-77FFFH 14 32 58000H-5FFFFH
13 32 68000H-6FFFFH 13 32 50000H-57FFFH
12 32 60000H-67FFFH 12 32 48000H-4FFFFH
11 32 58000H-5FFFFH 11 32 40000H-47FFFH
10 32 50000H-57FFFH 10 32 38000H-3FFFFH
9 32 48000H-4FFFFH 9 32 30000H-37FFFH
8 32 40000H-47FFFH 8 32 28000H-2FFFFH
7 32 38000H-3FFFFH 7 32 20000H-27FFFH
6 32 30000H-37FFFH 6 32 18000H-1FFFFH
5 32 28000H-2FFFFH 5 32 10000H-17FFFH
4 32 20000H-27FFFH 4 32 08000H-0FFFFH
3 32 18000H-1FFFFH 3 16 04000H-07FFFH
2 32 10000H-17FFFH 2 4 03000H-03FFFH
1 32 08000H-0FFFFH 1 4 02000H-02FFFH
0 32 00000H-07FFFH 0 8 00000H-01FFFH
2015-2018 Microchip Technology Inc. DS20005018B-page 8
SST39VF1601C/SST39VF1602C
5.0 DEVICE OPERATION
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write
sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched
on the falling edge of WE# or CE#, whichever occurs
last. The data bus is latched on the rising edge of WE#
or CE#, whichever occurs first.
The SST39VF1601C/1602C also have the Auto Low
Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read
operation. This reduces the IDD active read current
from typically 9 mA to typically 3 µA. The Auto Low
Power mode reduces the typical IDD active read current
to the range of 2 mA/MHz of Read cycle time. The
device exits the Auto Low Power mode with any
address transition or control signal transition used to
initiate another Read cycle, with no access time pen-
alty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
5.1 Read
The Read operation of the SST39VF1601C/1602C is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle tim-
ing diagram for further details (Figure 8-1).
5.2 Word-Program Operation
The SST39VF1601C/1602C are programmed on a
word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Pro-
gram operation is accomplished in three steps. The first
step is the three-byte load sequence for Software Data
Protection. The second step is to load word address
and word data. During the Word-Program operation,
the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, which-
ever occurs first. The third step is the internal Program
operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within
10 µs. See Figures 8-2 and 8-3 for WE# and CE# con-
trolled Program operation timing diagrams and Figure
8-17 for flowcharts. During the Program operation, the
only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free
to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
During the command sequence, WP# should be stati-
cally held high or low.
5.3 Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the sys-
tem to erase the device on a sector-by-sector (or block-
by-block) basis. The SST39VF1601C/1602C offer both
Sector-Erase and Block-Erase mode.
The sector architecture is based on a uniform sector
size of 2 KWord. The Block-Erase mode is based on
non-uniform block sizes—thirty-one 32 KWord, one 16
KWord, two 4 KWord, and one 8 KWord blocks. See
Figure 7-1 for top and bottom boot device block
addresses. The Sector-Erase operation is initiated by
executing a six-byte command sequence with Sector-
Erase command (50H) and sector address (SA) in the
last bus cycle. The Block-Erase operation is initiated by
executing a six-byte command sequence with Block-
Erase command (30H) and block address (BA) in the
last bus cycle. The sector or block address is latched
on the falling edge of the sixth WE# pulse, while the
command (30H or 50H) is latched on the rising edge of
the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling
or Toggle Bit methods. See Figures 8-7 and 8-8 for tim-
ing waveforms and Figure 8-21 for the flowchart. Any
commands issued during the Sector- or Block-Erase
operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be
ignored. During the command sequence, WP# should
be statically held high or low.
5.4 Erase-Suspend/Erase-Resume
Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to
be read from any memory location, or program data
into any sector/block that is not suspended for an Erase
operation. The operation is executed by issuing one
byte command sequence with Erase-Suspend com-
mand (B0H). The device automatically enters read
mode typically within 20 µs after the Erase-Suspend
command had been issued. Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within
erase-suspended sectors/blocks will output DQ2 tog-
gling and DQ6 at ‘1’. While in Erase-Suspend mode, a
Word-Program operation is allowed except for the sec-
tor or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation
which has been suspended the system must issue
Erase Resume command. The operation is executed
by issuing one byte command sequence with Erase
Resume command (30H) at any address in the last
Byte sequence.
2015-2018 Microchip Technology Inc. DS20005018B-page 9
SST39VF1601C/SST39VF1602C
5.5 Chip-Erase Operation
The SST39VF1601C/1602C provide a Chip-Erase oper-
ation, which allows the user to erase the entire memory
array to the ‘1’ state. This is useful when the entire
device must be quickly erased.
The Chip-Erase operation is initiated by executing a
six-byte command sequence with Chip-Erase com-
mand (10H) at address 555H in the last byte sequence.
The Erase operation begins with the rising edge of the
sixth WE# or CE#, whichever occurs first. During the
Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 6-2 for the command
sequence, Figure 8-6 for timing diagram, and Figure 8-
21 for the flowchart. Any commands issued during the
Chip-Erase operation are ignored. When WP# is low,
any attempt to Chip-Erase will be ignored. During the
command sequence, WP# should be statically held
high or low.
5.6 Write Operation Status Detection
The SST39VF1601C/1602C provide two software
means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle
time. The software detection includes two status bits:
Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-
Write detection mode is enabled after the rising edge of
WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data
may appear to conflict with either DQ7 or DQ6. In order
to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to
read the accessed location an additional two (2) times.
If both reads are valid, then the device has completed
the Write cycle, otherwise the rejection is valid.
5.7 Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output
signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it
allows several devices to be tied in parallel to VDD via
an external pull-up resistor. After the rising edge of the
final WE# pulse in the command sequence, the RY/
BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is still in progress. When
RY/BY# is high (Ready), the devices may be read or
left in Standby mode.
5.8 Data# Polling (DQ7)
When the SST39VF1601C/1602C are in the internal
Program operation, any attempt to read DQ7 will pro-
duce the complement of the true data. Once the Pro-
gram operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will
produce a ‘0’. Once the internal Erase operation is
completed, DQ7 will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector-, Block- or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 8-4 for Data#
Polling timing diagram and Figure 8-18 for a flowchart.
5.9 Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any
consecutive attempts to read DQ6 will produce alternat-
ing ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When
the internal Program or Erase operation is completed,
the DQ6 bit will stop toggling. The device is then ready
for the next operation. For Sector-, Block-, or Chip-
Erase, the toggle bit (DQ6) is valid after the rising edge
of sixth WE# (or CE#) pulse. DQ6 will be set to ‘1’ if a
Read operation is attempted on an Erase-Suspended
Sector/Block. If Program operation is initiated in a sec-
tor/block not selected in Erase-Suspend mode, DQ6
will toggle.
An additional Toggle Bit is available on DQ2, which can
be used in conjunction with DQ6 to check whether a
particular sector is being actively erased or erase-sus-
pended. Table 5-1 shows detailed status bits informa-
tion. The Toggle Bit (DQ2) is valid after the rising edge
of the last WE# (or CE#) pulse of Write operation. See
Figure 8-5 for Toggle Bit timing diagram and Figure 8-
18 for a flowchart.
TABLE 5-1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2RY/BY#
Normal Operation Standard Program DQ7# Toggle No Toggle 0
Standard Erase 0 Toggle Toggle 0
2015-2018 Microchip Technology Inc. DS20005018B-page 10
SST39VF1601C/SST39VF1602C
NOTE: DQ7 and DQ2 require a valid address when reading status information.
5.10 Data Protection
The SST39VF1601C/1602C provide both hardware and
software features to protect nonvolatile data from inad-
vertent writes.
5.11 Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less
than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inad-
vertent writes during power-up or power-down.
5.12 Hardware Block Protection
The SST39VF1602C supports top hardware block pro-
tection, which protects the top 8 KWord block of the
device. The SST39VF1601C supports bottom hard-
ware block protection, which protects the bottom
8KWord block of the device. The Boot Block address
ranges are described in Tabl e 5-2 . Program and Erase
operations are prevented on the 8 KWord when WP# is
low. If WP# is left floating, it is internally held high via a
pull-up resistor, and the Boot Block is unprotected,
enabling Program and Erase operations on that block.
5.13 Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting
the device to read array data. When the RST# pin is
held low for at least TRP, any in-progress operation will
terminate and return to Read mode. When no internal
Program/Erase operation is in progress, a minimum
period of TRHR is required after RST# is driven high
before a valid Read can take place (see Figure 8-13).
The Erase or Program operation that has been inter-
rupted needs to be re-initiated after the device resumes
normal operation mode to ensure data integrity.
5.14 Software Data Protection (SDP)
The SST39VF1601C/1602C provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of the three-
byte sequence. The three-byte load sequence is used
to initiate the Program operation, providing optimal pro-
tection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase oper-
ation requires the inclusion of six-byte sequence.
These devices are shipped with the Software Data Pro-
tection permanently enabled. See Table 6-2 for the
specific software command codes. During SDP com-
mand sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value, during any
SDP command sequence.
5.15 Common Flash Memory Interface
(CFI)
The SST39VF1601C/1602C also contain the CFI infor-
mation to describe the characteristics of the device. In
order to enter the CFI Query mode, the system writes
a three-byte sequence, same as product ID entry com-
mand with 98H (CFI Query command) to address 555H
in the last byte sequence. Additionally, the system can
use the one-byte sequence with 55H on the Address
Erase-Suspend Mode Read from Erase-
Suspended Sector/Block
11Toggle1
Read from Non-Erase-
Suspended Sector/Block
Data Data Data 1
Program DQ7# Toggle N/A 0
TABLE 5-1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2RY/BY#
TABLE 5-2: BOOT BLOCK ADDRESS RANGES
Product Address Range
Bottom Boot Block
SST39VF1601C 00000H - 01FFFH
Top Boot Block
SST39VF1602C FE000H - FFFFFH
0
2015-2018 Microchip Technology Inc. DS20005018B-page 11
SST39VF1601C/SST39VF1602C
and 89H on the Data Bus to enter the CFI Query mode.
Once the device enters the CFI Query mode, the sys-
tem can read CFI data at the addresses given in Tables
6-3 through 6-5. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
5.16 Product Identification
The Product Identification mode identifies the devices
as the SST39VF1601C, SST39VF1602C, and manu-
facturer as SST. This mode may be accessed software
operations. Users may use the Software Product Iden-
tification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the
same socket. For details, see Table 6-2 for software
operation, Figure 8-9 for the Software ID Entry and
Read timing diagram and Figure 8-19 for the Software
ID Entry command sequence flowchart.
5.17 Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Soft-
ware Product Identification mode must be exited. Exit
is accomplished by issuing the Software ID Exit com-
mand sequence, which returns the device to the Read
mode. This command may also be used to reset the
device to the Read mode after any inadvertent tran-
sient condition that apparently causes the device to
behave abnormally, e.g., not read correctly. Please
note that the Software ID Exit/CFI Exit command is
ignored during an internal Program or Erase operation.
See Table 6-2 for software command codes, Figure 8-
11 for timing waveform, and Figure 8-20 for flowcharts.
5.18 Security ID
The SST39VF1601C/1602C devices offer a 136 Word
Security ID space. The Secure ID space is divided into
two segments—one factory programmed segment and
one user programmed segment. The first segment is
programmed and locked at SST with a random 128-bit
number. The user segment, with a 128 word space, is
left unprogrammed for the customer to program as
desired.
To program the user segment of the Security ID, the
user must use the Security ID Word-Program com-
mand. To detect end-of-write for the SEC ID, read the
toggle bits. Do not use Data# Polling. Once this is com-
plete, the Sec ID should be locked using the User Sec
ID Program Lock-Out. This disables any future corrup-
tion of this space. Note that regardless of whether or
not the Sec ID is locked, neither Sec ID segment can
be erased.
The Secure ID space can be queried by executing a
three-byte command sequence with Enter Sec ID com-
mand (88H) at address 555H in the last byte sequence.
To exit this mode, the Exit Sec ID command should be
executed. Refer to Table 6-2 for more details.
TABLE 5-3: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39VF1601C 0001H 234FH
SST39VF1602C 0001H 234EH
2015-2018 Microchip Technology Inc. DS20005018B-page 12
SST39VF1601C/SST39VF1602C
6.0 OPERATIONS
TABLE 6-1: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector or block address, XXH for Chip-
Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 6-2
TABLE 6-2: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
1. Address format A10-A0 (Hex). Addresses A11-A19 can be VIL or VIH, but no other value, for Command sequence.
Data
2
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
Addr1
Data
2
Addr
1
Data
2
Addr
1Data2Addr1
Data
2
Addr
1
Data
2
Word-Program 555H AAH 2AAH 55H 555H A0H WA3
3. WA = Program Word address
Data
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX4
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address; AMS = A19
50H
Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Erase-Suspend XXXH B0H
Erase-Resume XXXH 30H
Query Sec ID5
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
555H AAH 2AAH 55H 555H 88H
User Security ID
Word-Program
555H AAH 2AAH 55H 555H A5H WA6Data
User Security ID
Program Lock-
Out
555H AAH 2AAH 55H 555H 85H XXH60000
H
Software ID
Entry7,8 555H AAH 2AAH 55H 555H 90H
CFI Query Entry 555H AAH 2AAH 55H 555H 98H
CFI Query Entry 55H 98H
Software ID
Exit9,10
/CFI Exit/Sec ID
Exit
555H AAH 2AAH 55H 555H F0H
Software ID
Exit9,10
/CFI Exit/Sec ID
Exit
XXH F0H
2015-2018 Microchip Technology Inc. DS20005018B-page 13
SST39VF1601C/SST39VF1602C
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1601C Device ID = 234FH, is read with A0 = 1, SST39VF1602C Device ID = 234EH, is read with A0 = 1,
AMS = Most significant address; AMS = A19
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are
from 000000H-000007H and 000008H-000087H.
TABLE 6-3: CFI QUERY IDENTIFICATION STRING1
Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0002H Primary OEM command set
14H 0000H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
1. Refer to CFI publication 100 for more details.
TABLE 6-4: SYSTEM INTERFACE INFORMATION
Address Data Data
1BH 0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
TABLE 6-5: DEVICE GEOMETRY INFORMATION
Address Data Data
27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0005H Number of Erase Sector/Block sizes supported by device
2015-2018 Microchip Technology Inc. DS20005018B-page 14
SST39VF1601C/SST39VF1602C
2DH 0000H Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100)
2EH 0000H
2FH 0040H
30H 0000H
31H 0001H Erase Block Region 2 Information
32H 0000H
33H 0020H
34H 0000H
35H 0000H Erase Block Region 3 Information
36H 0000H
37H 0080H
38H 0000H
39H 001EH Erase Block Region 4 Information
3AH 0000H
3BH 0000H
3CH 0001H
TABLE 6-5: DEVICE GEOMETRY INFORMATION
Address Data Data
2015-2018 Microchip Technology Inc. DS20005018B-page 15
SST39VF1601C/SST39VF1602C
7.0 ELECTRICAL SPECIFICATIONS
7.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0V
to 3V in less than 300 ms). If the VDD ramp rate is
slower than 1V per 100 ms, a hardware reset is
required. The recommended VDD power-up to RESET#
high time should be greater than 100 µs to ensure a
proper reset.
FIGURE 7-1: POWER-UP DIAGRAM
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these conditions or conditions greater than those defined in the operational sec-
tions of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect
device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
TABLE 7-1: AC CONDITIONS OF TEST1
1. See Figures 8-15 and 8-16
Input Rise/Fall Time Output Load
5ns CL = 30 pF
TABLE 7-2: OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
1380 F24.0
VDD
RESET#
CE#
TPU-READ > 100 µs
VDD min
0V
VIH
TRHR > 50ns
2015-2018 Microchip Technology Inc. DS20005018B-page 16
SST39VF1601C/SST39VF1602C
TABLE 7-3: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
2. See Figure 8-15
Read3
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
18 mA CE#=VIL, OE#=WE#=VIH, all I/Os
open
Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current
on WP# pin and RST#
10 µA WP#=GND to VDD or RST#=GND to
VDD
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
TABLE 7-4: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
TABLE 7-5: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
TABLE 7-6: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating
would result in a higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
2015-2018 Microchip Technology Inc. DS20005018B-page 17
SST39VF1601C/SST39VF1602C
8.0 AC CHARACTERISTICS
TABLE 8-1: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol Parameter Min Max Units
TRC Read Cycle Time 70 ns
TCE Chip Enable Access Time 70 ns
TAA Address Access Time 70 ns
TOE Output Enable Access Time 35 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 ns
TOLZ1OE# Low to Active Output 0 ns
TCHZ1CE# High to High-Z Output 20 ns
TOHZ1OE# High to High-Z Output 20 ns
TOH1Output Hold from Address Change 0 ns
TRP1RST# Pulse Width 500 ns
TRHR1RST# High before Read 50 ns
TRY1,2
2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-
Erase operations.
RST# Pin Low to Read Mode 20 µs
TABLE 8-2: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
TBY1,2
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
RY/BY# Delay Time 90 ns
TBR1Bus Recovery Time 0 µs
2015-2018 Microchip Technology Inc. DS20005018B-page 18
SST39VF1601C/SST39VF1602C
FIGURE 8-1: READ CYCLE TIMING DIAGRAM
FIGURE 8-2: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1380 F03.0
ADDRESS AMS-0
DQ15-0
WE#
OE#
CE#
TCE
TRC TAA
TOE
TOLZ
VIH
HIGH-Z TCLZ TOH TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
Note: AMS = Most significant address
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
2015-2018 Microchip Technology Inc. DS20005018B-page 19
SST39VF1601C/SST39VF1602C
FIGURE 8-3: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
FIGURE 8-4: DATA# POLLING TIMING DIAGRAM
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
1380 F26.0
ADDRESSES
DQ
15-0
WE#
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
WORD
(ADDR/DATA)
OE#
CE#
RY/ BY#
VALID
T
DH
T
CPH
T
AS
T
CH
T
CS
T
AH
T
CP
T
DS
T
BY
T
BR
T
BP
1380 F27.0
ADDRESS A19-0
DQ7DATA
WE#
OE#
CE#
RY/BY#
DATA# DATA# DATA
TOES
TOEH
TBY
TCE
TOE
2015-2018 Microchip Technology Inc. DS20005018B-page 20
SST39VF1601C/SST39VF1602C
FIGURE 8-5: TOGGLE BITS TIMING DIAGRAM
FIGURE 8-6: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
1380 F07.0
ADDRESS A
MS-0
DQ
6
and DQ
2
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
1380 F31.0
A
DDRESSES
DQ15-0
WE#
555 2AA 2AA555 555
XX55 XX10
XX55XXAA XX80 XXAA
555
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR CHIP-ERASE
TOEH
T
SCE
TBY TBR
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as
long as minimum timings are met. (See Table 8-2).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
2015-2018 Microchip Technology Inc. DS20005018B-page 21
SST39VF1601C/SST39VF1602C
FIGURE 8-7: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
FIGURE 8-8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1380 F32.0
ADDRESSES
DQ15-0
WE#
555 2AA 2AA555 555
XX55 XX30
XX55XXAA XX80 XXAA
BAX
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR BLOCK-ERASE
TWP
TBE
TBY TBR
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 8-2).
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
1380 F28.0
A
DDRESSES
DQ
15-0
WE#
555 2AA 2AA555 555
XX55 XX50
XX55XXAA XX80 XXAA
SA
X
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR SECTOR-ERASE
T
WP
T
SE
T
BY
T
BR
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 8-2).
SAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
2015-2018 Microchip Technology Inc. DS20005018B-page 22
SST39VF1601C/SST39VF1602C
FIGURE 8-9: SOFTWARE ID ENTRY AND READ
FIGURE 8-10: CFI QUERY ENTRY AND READ
1380 F11
.0
A
DDRESS
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555 0000 0001
OE#
CE#
Three-Byte Sequence for Software ID Entry
TWP
TWPH TAA
00BF Device IDXX55XXAA XX90
Note: Device ID = 234BH for SST39VF1601C and 234AH for SST39VF1602C.
WP# must be held in proper logic state (VIL or VIH) 1µs after the command sequence.
X can VIL or VIH but no other value.
1380 F12.0
ADDRESS
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
Three-Byte Sequence for CFI Query Entry
TWP
TWPH TAA
XX55XXAA XX98
Note: WP# must be held in proper logic state (VIL or VIH) 1µs after the command sequence.
X can VIL or VIH but no other value.
2015-2018 Microchip Technology Inc. DS20005018B-page 23
SST39VF1601C/SST39VF1602C
FIGURE 8-11: SOFTWARE ID EXIT/CFI EXIT
FIGURE 8-12: SEC ID ENTRY
1380 F13
.0
A
DDRESS
DQ15-0
TIDA
TWP
TWHP
WE#
SW0 SW1 SW2
555 2AA 555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
XXAA XX55 XXF0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can VIL or VIH but no other value.
1380 F20.0
ADDRESS AMS-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
TWP
TWPH TAA
XX55XXAA XX88
Note: AMS = Most significant address
AMS = A19
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can VIL or VIH but no other value.
2015-2018 Microchip Technology Inc. DS20005018B-page 24
SST39VF1601C/SST39VF1602C
FIGURE 8-13: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
FIGURE 8-14: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)
FIGURE 8-15: AC INPUT/OUTPUT REFERENCE WAVEFORMS
1380 F29.0
RY/BY#
0V
RST#
CE#/OE#
TRP
TRHR
1380 F30.0
R
Y/BY#
CE#
OE#
TRP
T
RY
TBR
RST#
1380F14.0
REFERENCE POINTS OUTPUTINPUT VIT
V
IHT
VILT
VOT
AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Mea-
surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise
and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
2015-2018 Microchip Technology Inc. DS20005018B-page 25
SST39VF1601C/SST39VF1602C
FIGURE 8-16: A TEST LOAD EXAMPLE
FIGURE 8-17: WORD-PROGRAM ALGORITHM
1380 F15
.0
T O TESTER
T
O DUT
C
L
1380 F16.0
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load W ord
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
X can be VIL or VIH, but no other value
2015-2018 Microchip Technology Inc. DS20005018B-page 26
SST39VF1601C/SST39VF1602C
FIGURE 8-18: WAIT OPTIONS
1380 F17.1
W ait TBP,
TSCE, TSE
or TBE
Program/Erase
Initiated
Internal Timer Toggle Bit
Yes
Yes
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
word
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read word
Is DQ7 =
true data?
Read DQ7
Program/Erase
Initiated
Program/Erase
Initiated
Yes
No
RY/BY#
Is
RY/BY# = 1?
Read RY/BY#
Program/Erase
Initiated
Program/Erase
Completed
2015-2018 Microchip Technology Inc. DS20005018B-page 27
SST39VF1601C/SST39VF1602C
FIGURE 8-19: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS
1380 F21.0
Load data: XXAAH
Address: 555H
Software Product ID Ent
ry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
W ait TIDA
Read Software ID
Load data: XXAAH
Address: 555H
CFI Query Entry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX98H
Address: 55H
W ait TIDA
Read CFI data
Load data: XXAAH
Address: 555H
Sec ID Query Entry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX88H
Address: 555H
W ait TIDA
Read Sec ID
X can be VIL or VIH, but no other value
Load data: XX98H
Address: 55H
W ait TIDA
Read CFI data
2015-2018 Microchip Technology Inc. DS20005018B-page 28
SST39VF1601C/SST39VF1602C
FIGURE 8-20: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS
1380 F18.0
Load data: XXAAH
Address: 555H
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XXF0H
Address: 555H
Load data: XXF0H
Address: XXH
Return to normal
operation
W ait TIDA
W ait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
2015-2018 Microchip Technology Inc. DS20005018B-page 29
SST39VF1601C/SST39VF1602C
FIGURE 8-21: ERASE COMMAND SEQUENCE
1380 F19.0
Load data: XXAAH
Address: 555H
Chip-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XXAAH
Address: 555H
W ait TSCE
Chip erased
to FFFFH
Load data: XXAAH
Address: 555H
Sector-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX50H
Address: SAX
Load data: XXAAH
Address: 555H
W ait TSE
Sector erased
to FFFFH
Load data: XXAAH
Address: 555H
Block-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX30H
Address: BAX
Load data: XXAAH
Address: 555H
W ait TBE
Block erased
to FFFFH
X can be VIL or VIH, but no other value
2015-2018 Microchip Technology Inc. DS20005018B-page 30
SST39VF1601C/SST39VF1602C
Product Ordering Information
8.0.1 VALID COMBINATIONS FOR SST39VF1601C
8.0.2 VALID COMBINATIONS FOR SST39VF1602C
Note: Valid combinations are those products in mass production or will be in mass production. Consult your
Microchip sales representative to confirm availability of valid combinations and to determine availability of
new combinations
SST39VF1601C-70-4C-EKE SST39VF1601C-70-4C-B3KE SST39VF1601C-70-4C-MAQE
SST39VF1601C-70-4I-EKE SST39VF1601C-70-4I-B3KE SST39VF1601C-70-4I-MAQE
SST39VF1602C-70-4C-EKE SST39VF1602C-70-4C-B3KE SST39VF1602C-70-4C-MAQE
SST39VF1602C-70-4I-EKE SST39VF1602C-70-4I-B3KE SST39VF1602C-70-4I-MAQE
SST 39 VF 1601C - 70 - 4I - EKE
XX XXXXXXX-XX-XX-XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Q = 48 balls (66 possible positions)
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
MA = WFBGA (4mm x 6mm, 0.5mm
pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1.Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compli-
ant”.
2015-2018 Microchip Technology Inc. DS20005018B-page 31
SST39VF1601C/SST39VF1602C
9.0 PACKAGING DIAGRAMS
2015-2018 Microchip Technology Inc. DS20005018B-page 32
SST39VF1601C/SST39VF1602C
2015-2018 Microchip Technology Inc. DS20005018B-page 33
SST39VF1601C/SST39VF1602C
B
A
Microchip Technology Drawing C04-168C Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
A
D
E
E/4
D/4
(DATUM B)
0.15 C
0.15 C
2X
2X
D1
eD
E1
eE
eD/2
eE/2
BOTTOM VIEW
DETAIL B
DETAIL A
TOP VIEW
SIDE VIEW
ABCDEFGH
6
5
4
3
2
1
1
2
3
4
5
6
ABCDEFGH (DATUM A)
C
SEATING
PLANE
48-Ball Thin Profile Fine Pitch Ball Grid Array (CD) - 6x8 mm Body [TFBGA]
A1
NOTE 1
2015-2018 Microchip Technology Inc. DS20005018B-page 34
SST39VF1601C/SST39VF1602C
Microchip Technology Drawing C04-168C Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
nX Øb
0.15 C A B
0.08 C
C
0.12 C
DETAIL A
DETAIL B
0.20 C
48-Ball Thin Profile Fine Pitch Ball Grid Array (CD) - 6x8 mm Body [TFBGA]
Number of Solder Balls
Overall Height
Solder Ball Diameter
Overall Length
Overall Width
Overall Solder Ball X-Pitch
Overall Solder Ball Y-Pitch
Solder Ball Y-Pitch
Ball Height
Units
Dimension Limits
A1
A
b
E
D1
E1
eE
D
n
0.80 BSC
0.40
1.00
0.30
0.45
6.00 BSC
4.00 BSC
5.60 BSC
1.10
0.35
8.00 BSC
MILLIMETERS
MIN NOM
48
0.50
1.20
0.40
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
Notes:
Ball A1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
Solder Ball X-Pitch eD 0.80 BSC
3. Ball interface to package body: 0.38mm nominal diameter.
2015-2018 Microchip Technology Inc. DS20005018B-page 35
SST39VF1601C/SST39VF1602C
48-ball, Very, Very Thin-Profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6 mm
48-wfbga-MAQ-4x6-32mic-2.
Note:
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm (± 0.05 mm)
2015-2018 Microchip Technology Inc. DS20005018B-page 36
SST39VF1601C/SST39VF1602C
TABLE 9-1: REVISION HISTORY
Number Description Date
00 •Initial release Apr 2008
01 •Corrected typo in Hardware Block Protection on page 4
•Corrected typo in table title, Table 5 page 8
Sep 2008
02 •Changed 1V per 100 µs to 1V per 100 ms in Power Up Specifications
on page 12
Jan 2009
03 •Changed from Preliminary Specification to Data Sheet
•Clarified RY/BY# pin timing by updating Features, Figures 8-2, 8-3, 8-4,
8-6, 8-7, 8-8, 8-13, 8-14, and 8-18, and Tables 5-1 and 8-2.
Aug 2009
04 •Added information for MAQE package
•Updated SST address information on page 33
May 2010
A•Applied new document format
•Released document under letter revision system
•Updated spec number S71380 to DS-25018
May 2011
B•Applied new document format
•Corrected Figure 8-3
•Updated TSOP and TFBGA package drawings
May 2018
2018 Microchip Technology Inc. DS20005018B-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2971-5
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece ived IS O/T S-16 94 9:20 09 certificat i on for its worl dwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005018B-page 38 2017 Microchip Technology Inc.
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10/25/17