HYMP564U72CP8-Y5 - SK Hynix

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5 / Sep 2008 1

240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb C ver.

This Hynix unbuff ered Dual In-Line Memory Module ( DIMM) series consists of 512Mb C ver. DDR2 SDRAMs

in Fine Ball Grid Array (F BGA) packages on a 240pin glass-epo xy substrate. This Hynix 512Mb C ver. based

DDR2 Unbuffered DIMM series pr ovide a high performance 8 byte interf ace in 133.35mm width form f actor

of industry standard. It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Part Name Density Organization # of

DRAMs # of

ranks Materials ECC

HYMP532U64CP6-E3/C4/Y5 256MB 32Mx64 4 1 Lead free None

HYMP564U64CP8-E3/C4/Y5 512MB 64Mx64 8 1 Lead free None

HYMP564U72CP8-E3/C4/Y5 512MB 64Mx72 9 1 Lead free ECC

HYMP512U64CP8-E3/C4/Y5 1GB 128Mx64 16 2 Lead free None

HYMP512U72CP8-E3/C4/Y5 1GB 128Mx72 18 2 Lead free ECC

• JEDEC standard Double Data Rate2 Synchro-

nous DRAMs (DDR2 SDRAMs) with 1.8V +/-

0.1V Power Supply

• All inputs and outputs are compatible with

SSTL_1.8 interface

•4 Bank architecture

•Posted CAS

• Programmable CAS Latency 3, 4, 5, 6

• OCD (Off-Chip Driver Impedance Adjustment)

• ODT (On-Die Termination)

• Fully differential clock operations (CK & CK)

• Programmable Burst Length 4 / 8 with both

sequential and interleave mode

• Auto refresh and self refresh supported

• Partial Array Self Refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60ball FBGA(64Mx8),

84ball FBGA(32Mx16)

•133.35 x 30.00 mm form factor

• Lead-free Products are RoHS compliant

Rev. 0.5 / Sep 2008 2

1240pin DDR2 SDRAM Unbuffered DIMMs

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

E3

(DDR2-400) C4

(DDR2-533) Y5

(DDR2-667) S5

(DDR2-800) S6

(DDR2-800) Unit

Speed @CL3 400 533 400 400 -Mbps

Speed @CL4 533 533 533 533 533 Mbps

Speed @CL5 - - 667 800 667 Mbps

Speed @CL6 - - - 800 800 Mbps

CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 5-5-5 6-6-6 tCK

Density Organization Ranks SDRAMs # of

DRAMs # of row/bank/co lumn Address Refresh

Method

256MB 32M x 64 1 32Mb x 16 4 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

512MB 64M x 64 1 64Mb x 8 8 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

512MB 64M x 72 1 64Mb x 8 9 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

1GB 128M x 64 2 64Mb x 8 16 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

1GB 128M x 72 2 64Mb x 8 18 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

Rev. 0.5 / Sep 2008 3

1240pin DDR2 SDRAM Unbuffered DIMMs

Input/Output Functional Description

Symbol Type Polarity Pin Description

CK[2:0], CK[2:0] SSTL Differential

Crossing

CK and /CK are differential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sam-

pled on the crossing of positive edge of CK and negative edge of /CK. Output (read) data

is reference to the crossing of CK and /CK (Both directions of crossing)

CKE[1:0] SSTL Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self

Refresh mode.

S[1:0] SSTL Active Low

Enables the associated DDR2 SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1

RAS, CAS,

WE SSTL Active Low /RAS,/CAS and /WE(ALONG WITH S) define the command being entered.

ODT[1:0] SSTL Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

Vref Supply Reference voltage for SSTL18 inputs

VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity.

For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as

VDD pins.

BA[2:0] SSTL - Selects which DDR2 SDRAM internal bank of four or eight is activated.

A[9:0], A10/AP,

A[13:11] SSTL -

During a Bank Activate command cycle, Address input defines the row

address(RA0~RA15)

During a Read or Write command cycle, Address input defines the column address when

sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to

the column address, AP is used to invoke autoprecharge operation at the end of the burst

read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the

bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-

mand cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to pre-

charge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn

inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

DQ[63:0],

CB[7:0] SSTL - Data and Check Bit Input/Output pins.

DM[8:0] SSTL Active High

DM is an input mask signal for write data. Input data is masked when DM is sampled High

coincident with that input data during a write access. DM is sampled on both edges of

DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-

ing.

VDD,VSS Supply Power and ground for the DDR2 SDRAM input buffers, and core log ic. VDD and VDDQ

pins are tied to VDD/VDDQ planes on these modules.

DQS[8:0],

DQS[8:0] SSTL Differential

crossing

Data strobe for input and output data. For Rawcards using x16 organized DRAMs,

DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of

the DRAM

SA[2:0] - These signals are tied at the system planar to either VSS or VDD to configure the serial

SPD EEPROM.

SDA - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister

must be connected to VDD to act as a pull up.

SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from SCL to VDD to act as a pull up on the system board.

VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power

plane. EEPROM supply is operable from 1.7V to 3.6V.

Rev. 0.5 / Sep 2008 4

1240pin DDR2 SDRAM Unbuffered DIMMs

PIN CONFIGURATION

PIN ASSIGNMENT

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1 VREF 41 VSS 81 DQ33 121 VSS 161 NC(CB4)* 201 VSS

2 VSS 42 NC(CB0)* 82 VSS 122 DQ4 162 NC(CB5)* 202 DM4

3 DQ0 43 NC(CB1)* 83 DQS4 123 DQ5 163 VSS 203 NC

4 DQ1 44 VSS 84 DQS4 124 VSS 164 NC(DM8)* 204 VSS

5 VSS 45 NC(DQS8)* 85 VSS 125 DM0 165 NC 205 DQ38

6DQS

0 46 NC(DQS8)* 86 DQ34 126 NC 166 VSS 206 DQ39

7 DQS0 47 VSS 87 DQ35 127 VSS 167 NC(CB6)* 207 VSS

8 VSS 48 NC(CB2)* 88 VSS 128 DQ6 168 NC(CB7)* 208 DQ44

9 DQ2 49 NC(CB3)* 89 DQ40 129 DQ7 169 VSS 209 DQ45

10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS

11 VSS 51 VDDQ 91 VSS 131 DQ12 171 CKE1 211 DM5

12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 NC

13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15 213 VSS

14 VSS 54 BA2 94 VSS 134 DM1 174 A14 214 DQ46

15 DQS1 55 NC 95 DQ42 135 NC 175 VDDQ 215 DQ47

16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS

17 VSS 57 A11 97 VSS 137 CK1 177 A9 217 DQ52

18 NC 58 A7 98 DQ48 138 CK1 178 VDD 218 DQ53

19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS

20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 CK2

21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 CK2

22 DQ11 62 VDDQ 102 NC,TEST1142 VSS 182 A3 222 VSS

1 pin

Front Side

64 pin 65 pin 120 pin

121 pin

Back Side

184 pin 185 pin 240 pin

* The pin names in parenthesizes are applied to DIMM with ECC only.

Rev. 0.5 / Sep 2008 5

1240pin DDR2 SDRAM Unbuffered DIMMs

PIN ASSIGNMENT(Continued)

*NC = No connect

Notes:

1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs).

2. NC Pins should not be connected to anything, including bussing within the NC group.

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6

24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC

25 DQ17 65 VSS 105 DQS6 145 VSS 185 CK0 225 VSS

26 VSS 66 VSS 106 VSS 146 DM2 186 CK0 226 DQ54

27 DQS2 67 VDD 107 DQ50 147 NC 187 VDD 227 DQ55

28 DQS2 68 NC 108 DQ51 148 VSS 188 A0 228 VSS

29 VSS 69 VDD 109 VSS 149 DQ22 189 VDD 229 DQ60

30 DQ18 70 A10/AP 110 DQ56 150 DQ23 190 BA1 230 DQ61

31 DQ19 71 BA0 111 DQ57 151 VSS 191 VDDQ 231 VSS

32 VSS 72 VDDQ 112 VSS 152 DQ28 192 RAS 232 DM7

33 DQ24 73 WE 113 DQS7 153 DQ29 193 S0 233 NC

34 DQ25 74 CAS 114 DQS7 154 VSS 194 VDDQ 234 VSS

35 VSS 75 VDDQ 115 VSS 155 DM3 195 ODT0 235 DQ62

36 DQS376 S1 116 DQ58 156 NC 196 A13 236 DQ63

37 DQS3 77 ODT1 117 DQ59 157 VSS 197 VDD 237 VSS

38 VSS 78 VDDQ 118 VSS 158 DQ30 198 VSS 238 VDDSPD

39 DQ26 79 VSS 119 SDA 159 DQ31 199 DQ36 239 SA0

40 DQ27 80 DQ32 120 SCL 160 VSS 200 DQ37 240 SA1

Rev. 0.5 / Sep 2008 6

1240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM

256MB(32Mbx64): HYMP532U64CP6

/S0

/DQS0

DM0

DQS0

D0

DQ0 I/ O 0

DQ1 I/ O 1

DQ2 I/ O 2

DQ3 I/ O 3

DQ4 I/ O 4

DQ5 I/ O 5

DQ6 I/ O 6

I/ O 7

DQ7

/DQS1

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

/CS

/LDQS

LDQS

LDM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

/DQS2

DM2

DQS2

D1

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/DQS3

DM3

DQS3

/CS

/LDQS

LDQS

LDM

/DQS4

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

/DQS5

DM5

DQS5

D2

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/CS

/LDQS

LDQS

LDM

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

/DQS7

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

D3

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/CS

/LDQS

LDQS

LDM

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

/DQS6

DM6

DQS6

BA0-BA 1

A0-A13

/RAS

/CAS

SDRAM S D0-D3

CKE0

/WE

ODT0

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

/UDQS

UDQS

UDM

I/ O 8

I/ O 9

I/ O 1 0

I/ O 1 1

I/ O 1 2

I/ O 1 3

I/ O 1 4

I/ O 15

/UDQS

UDQS

UDM I/ O 8

I/ O 9

I/ O 1 0

I/ O 1 1

I/ O 1 2

I/ O 1 3

I/ O 1 4

I/ O 15

/UDQS

UDQS

UDM

I/ O 8

I/ O 9

I/ O 1 0

I/ O 1 1

I/ O 1 2

I/ O 1 3

I/ O 1 4

I/ O 15

/UDQS

UDQS

UDM

SDRAM S D0-D3

VDD

SPD

VREF

VDD/VDDQ

VSS

Serial PD

DO-D3

Notes:

1. DQ ,DM ,DQ S,/D QS resistors : 22 Ω +/- 5 %.

2. Bax,Ax,/RAS,/CAS ,/W E resistors : 10 Ω +/- 5 %.

SCL SDA

A0 A1

WP Serial PD

SCL

SA0 SA1 SA2

A1

Clock Signal Loads

CK0, /CK0

CK1, /CK1 NC

2

CK2, /CK2 2

Clock Input SDRAMs

Rev. 0.5 / Sep 2008 7

1240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM

512MB(64Mbx64): HYMP564U64CP8

/S0

/DQS0

DM0

DQS0

D0

/CS DQS /DQS

DM

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/O 7

DQ7

/DQS1

DM1

DQS1

D1

/CS DQS /DQS

DM

DQ8 I/O 0

DQ9 I/O 1

DQ10 I/O 2

DQ11 I/O 3

DQ12 I/O 4

DQ13 I/O 5

DQ14 I/O 6

I/O 7

DQ15

/DQS2

DM2

DQS2

D2

/CS DQS /DQS

DM

DQ16 I/O 0

DQ17 I/O 1

DQ18 I/O 2

DQ19 I/O 3

DQ20 I/O 4

DQ21 I/O 5

DQ22 I/O 6

I/O 7

DQ23

/DQS3

DM3

DQS3

D3

/CS DQS /DQS

DM

DQ24 I/O 0

DQ25 I/O 1

DQ26 I/O 2

DQ27 I/O 3

DQ28 I/O 4

DQ29 I/O 5

DQ30 I/O 6

I/O 7

DQ31

/DQS4

DM4

DQS4

D4

/CS DQS /DQS

DM

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/O 7

DQ39

/DQS5

DM5

DQS5

D5

/CS DQS /DQS

DM

DQ40 I/O 0

DQ41 I/O 1

DQ42 I/O 2

DQ43 I/O 3

DQ44 I/O 4

DQ45 I/O 5

DQ46 I/O 6

I/O 7

DQ47

/DQS6

DM6

DQS6

D6

/CS DQS /DQS

DM

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/O 7

DQ55

/DQS7

DM7

DQS7

D7

/CS DQS /DQS

DM

DQ56 I/O 0

DQ57 I/O 1

DQ58 I/O 2

DQ59 I/O 3

DQ60 I/O 4

DQ61 I/O 5

DQ62 I/O 6

I/O 7

DQ63

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D7

BA0-BA1

A0-A13

/RAS

/CAS

SDRAMS D0-7

CKE0

/WE

ODT0

SDRAMS D0-7

SCL SDA

A0 A1

WP Seri al PD

SCL

SA0 SA1 SA2

A1

Notes:

1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.

2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %.

Clock Signal Loads

CK0, /CK0

CK1, /CK1 2

3

CK2, /CK2 3

Clock Input SDRAMs

Rev. 0.5 / Sep 2008 8

1240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM

512MB(64Mbx72): HYMP564U72CP8

/S0

/DQS0

DM0

DQS0

D0

/CS DQ S /DQS

DM

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/O 7

DQ7

/DQS1

DM1

DQS1

D1

/CS DQ S /DQS

DM

DQ8 I/O 0

DQ9 I/O 1

DQ10 I/O 2

DQ11 I/O 3

DQ12 I/O 4

DQ13 I/O 5

DQ14 I/O 6

I/O 7

DQ15

/DQS2

DM2

DQS2

D2

/CS DQ S /DQS

DM

DQ16 I/O 0

DQ17 I/O 1

DQ18 I/O 2

DQ19 I/O 3

DQ20 I/O 4

DQ21 I/O 5

DQ22 I/O 6

I/O 7

DQ23

/DQS3

DM3

DQS3

D3

/CS DQ S /DQS

DM

DQ24 I/O 0

DQ25 I/O 1

DQ26 I/O 2

DQ27 I/O 3

DQ28 I/O 4

DQ29 I/O 5

DQ30 I/O 6

I/O 7

DQ31

/DQS8

DM8

DQS8

D8

/CS DQ S /DQS

DM

CB0 I/O 0

CB1 I/O 1

CB2 I/O 2

CB3 I/O 3

CB4 I/O 4

CB5 I/O 5

CB6 I/O 6

I/O 7

CB7

/DQS4

DM4

DQS4

D4

/CS DQS /D QS

DM

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/O 7

DQ39

/DQS5

DM5

DQS5

D5

/CS DQS /D QS

DM

DQ40 I/O 0

DQ41 I/O 1

DQ42 I/O 2

DQ43 I/O 3

DQ44 I/O 4

DQ45 I/O 5

DQ46 I/O 6

I/O 7

DQ47

/DQS6

DM6

DQS6

D6

/CS DQS /DQS

DM

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/O 7

DQ55

/DQS7

DM7

DQS7

D7

/CS DQS /D QS

DM

DQ56 I/O 0

DQ57 I/O 1

DQ58 I/O 2

DQ59 I/O 3

DQ60 I/O 4

DQ61 I/O 5

DQ62 I/O 6

I/O 7

DQ63

A1

SCL SDA

A0 A1

WP Serial PD

SCL

SA0 SA1 SA2

A1

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D8

BA0-BA1

A0-A13

/RAS

/CAS

SDR AM S D0 -7,D 8

CKE0

/WE

ODT0

SDR AM S D0 -7,D 8

SDRAMS D0-7,D8

SDR AM S D0 -7,D 8

SDRAMS D0-7,D8

Notes:

1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.

2. Bax,Ax,/RAS,/CAS,/WE resistors : 5.1 Ω +/- 5 %.

Clock Signal Loads

CK0, /CK0

CK1, /CK1 3

3

CK2, /CK2 3

Clock Input SDRAMs

Rev. 0.5 / Sep 2008 9

1240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx64): HYMP512U64CP8

/S0

/DQS0

DM0

DQS0

D0

/

DQ0 I/ O 0

DQ1 I/ O 1

DQ2 I/ O 2

DQ3 I/ O 3

DQ4 I/ O 4

DQ5 I/ O 5

DQ6 I/ O 6

I/ O 7

DQ7

/DQS1

DM1

DQS1

D1

DQ8 I/ O 0

DQ9 I/ O 1

DQ10 I/ O 2

DQ11 I/ O 3

DQ12 I/ O 4

DQ13 I/ O 5

DQ14 I/ O 6

I/ O 7

DQ15

/DQS2

DM2

DQS2

D2

DQ16 I/ O 0

DQ17 I/ O 1

DQ18 I/ O 2

DQ19 I/ O 3

DQ20 I/ O 4

DQ21 I/ O 5

DQ22 I/ O 6

I/ O 7

DQ23

/DQS3

DM3

DQS3

D3

DQ24 I/ O 0

DQ25 I/ O 1

DQ26 I/ O 2

DQ27 I/ O 3

DQ28 I/ O 4

DQ29 I/ O 5

DQ30 I/ O 6

I/ O 7

DQ31

D8

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D9

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D10

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D11

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D12

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D15

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/DQS4

DM4

DQS4

D4

DQ32 I/ O 0

DQ33 I/ O 1

DQ34 I/ O 2

DQ35 I/ O 3

DQ36 I/ O 4

DQ37 I/ O 5

DQ38 I/ O 6

I/O 7

DQ39

/DQS5

DM5

DQS5

D5

DQ40 I/ O 0

DQ41 I/ O 1

DQ42 I/ O 2

DQ43 I/ O 3

DQ44 I/ O 4

DQ45 I/ O 5

DQ46 I/ O 6

I/O 7

DQ47

/DQS6

DM6

DQS6

D6

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/ O 7

DQ55

/DQS7

DM7

DQS7

D7

DQ56 I/ O 0

DQ57 I/ O 1

DQ58 I/ O 2

DQ59 I/ O 3

DQ60 I/ O 4

DQ61 I/ O 5

DQ62 I/ O 6

I/O 7

DQ63

D14

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D13

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/S1

SCL SDA

A0 A1

WP Serial PD

SCL

SA0 SA1 SA2

A1

BA0-BA1

A0-A15

/RAS

/CAS

SDRAMS D0-D15

CKE0

/WE

CKE1

ODT0

ODT1

SDRAMS D0-D15

SDRAMS D0-D7

SDRAMS D8-D15

SDRAMS D0-D15

SDRAMS D 0 -D7

SDRAMS D8-D15

/CS DQS /DQS

DM /CS DQS /DQS

DM

/CS DQS /DQS

DM

/CS D QS /DQS

DM

/CS D QS /DQS

DM /CS DQS /DQS

DM

/CS DQS /DQ S

DM /CS DQ S /DQS

DM

/CS DQ S /DQS

DM

/CS DQS /DQ S

DM

/CS D QS /DQS

DM /CS DQS /DQS

DM

/CS DQ S /DQS

DM

/CS D QS /DQS

DM

Notes:

1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.

2. Bax,Ax,/R A S,/CAS ,/WE re sisto rs : 7.5 Ω +/- 5 %.

4

6

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D15

Clock Signal Loads

CK0, /CK0

CK1, /CK1 4

6

CK2, /CK2 6

Clock Input SDRAMs

Rev. 0.5 / Sep 2008 10

1240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx72): HYMP512U72CP8

/S0

/DQS0

DM0

DQS0

D0

/ CS DQS /DQS

DM

DQ0 I/ O 0

DQ1 I/ O 1

DQ2 I/ O 2

DQ3 I/ O 3

DQ4 I/ O 4

DQ5 I/ O 5

DQ6 I/ O 6

I/ O 7

DQ7

/DQS1

DM1

DQS1

D1

/ CS DQS /DQS

DM

DQ8 I/ O 0

DQ9 I/ O 1

DQ10 I/ O 2

DQ11 I/ O 3

DQ12 I/ O 4

DQ13 I/ O 5

DQ14 I/ O 6

I/ O 7

DQ15

/DQS2

DM2

DQS2

D2

/ CS DQS /DQS

DQ16 I/ O 0

DQ17 I/ O 1

DQ18 I/ O 2

DQ19 I/ O 3

DQ20 I/ O 4

DQ21 I/ O 5

DQ22 I/ O 6

I/ O 7

DQ23

/DQS3

DM3

DQS3

D3

/ CS DQS /DQS

DM

DQ24 I/ O 0

DQ25 I/ O 1

DQ26 I/ O 2

DQ27 I/ O 3

DQ28 I/ O 4

DQ29 I/ O 5

DQ30 I/ O 6

I/ O 7

DQ31

/DQS8

DM8

DQS8

D8

/ CS DQS /DQS

DM

CB0 I/ O 0

CB1 I/ O 1

CB2 I/ O 2

CB3 I/ O 3

CB4 I/ O 4

CB5 I/ O 5

CB6 I/ O 6

I/ O 7

CB7

D9

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D10

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D11

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D12

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D17

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D13

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D16

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/DQS4

DM4

DQS4

D4

/ CS DQS /DQS

DM

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/ O 7

DQ39

/DQS5

DM5

DQS5

D5

/ CS DQS /DQS

DM

DQ40 I/O 0

DQ41 I/O 1

DQ42 I/O 2

DQ43 I/O 3

DQ44 I/O 4

DQ45 I/O 5

DQ46 I/O 6

I/ O 7

DQ47

/DQS6

DM6

DQS6

D6

/ CS DQS /DQS

DM

DQ48 I/ O 0

DQ49 I/ O 1

DQ50 I/ O 2

DQ51 I/ O 3

DQ52 I/ O 4

DQ53 I/ O 5

DQ54 I/ O 6

I/ O 7

DQ55

/DQS7

DM7

DQS7

D7

/ CS DQS /DQS

DM

DQ56 I/O 0

DQ57 I/O 1

DQ58 I/O 2

DQ59 I/O 3

DQ60 I/O 4

DQ61 I/O 5

DQ62 I/O 6

I/ O 7

DQ63

D15

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D14

/ CS DQS /DQS

DM

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/S1

SCL

SDA

A0 A1

WP Serial PD

SCL

SA0 SA1

SA2

A1

BA0-BA1

A0-A13

/RAS

/CAS

SDRAMS D0-D17

CKE0

/WE

CKE1

ODT0

ODT1

SDRAMS D0-D17

SDRAMS D0-D8

SDRAM S D9-D17

SDRAMS D0-D17

SDRAM S D0-D17

SDRAM S D0-D8

SDRAMS D9-D17

Notes:

1 . DQ,DM,DQS ,/DQ S res is to rs : 2 2 Ω +/- 5 % .

2 . Ba x ,A x ,/R A S ,/C A S ,/WE re sis to rs : 7 .5 Ω +/- 5 %.

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D17

Clock Signal Loads

CK0, /CK0

CK1, /CK1

6

CK2, /CK2

6

Clock Input

SDRAMs

Rev. 0.5 / Sep 2008 11

1240pin DDR2 SDRAM Unbuffered DIMMs

ABSOLUTE MAXIMUM RATINGS

Note:

1. S tress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device

functional operation at or above th e conditions indicated is not implied. Exposure to absolute maximum rating con

ditions for extended periods may affect reliablility.

OPERATING CONDITIONS

Notes:

1. Up to 9850 ft.

2. If the DRAM case te mp e rature is Above 85oC, the Auto-Refresh command interval has to be reduced to

tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.

DC OPERATING CONDITIONS (SSTL_1.8)

Notes:

1. VDDQ must be less than or equal to VDD.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF(dc)

3. VTT of transmitting device must track VREF of receiving device.

Parameter Symbol Value Unit Note

Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1

Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1

Voltage on any pin relative to Vss VIN, VOUT - 0.5 V ~ 2.3 V V 1

Storage Temperature TSTG -50 ~ +100 oC1

Storage Humidity (without condensation) HSTG 5 to 95 % 1

Parameter Symbol Rating Units Notes

DIMM Operating temperature (ambient) TOPR 0 ~ +55 oC

DIMM Barometric Pressure (operating & storage) PBAR 105 to 69 K Pascal 1

DRAM Component Case Temperature Range TCASE 0 ~+95 oC2

Parameter Symbol Min Max Unit Note

Power Supply Voltage VDD 1.7 1.9 V

VDDQ 1.7 1.9 V 1

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage VTT VREF-0.04 VREF+0.04 V3

Input leakage current; any input 0V VIN

VDD; all other balls not under test = 0V) II-2 2 uA

Output leakage curre nt; 0V VOUT V DDQ;

DQ and ODT disabled IOZ -5 5 uA

Rev. 0.5 / Sep 2008 12

1240pin DDR2 SDRAM Unbuffered DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VREF level appl ied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for fallin g edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions

and VIH (ac) to VIL (ac) on the negative transitions.

Parameter Symbol Min Max Unit Note

Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Parameter Symbol DDR2 400, 533 DDR2 667, 800 Unit Note

Min Max Min Max

AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V

AC Input logic Low VIL(AC) -V

REF - 0.250 - VREF - 0.200 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal mini mu m sl ew rat e 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

< Figure: AC Input Test Signal Waveform >

V

SWING(MAX)

delta TR

delta TF

V

REF

-

VIL

(ac)

max

delta TF

Falling Slew = Rising Slew = V

IH(ac)

min - V

REF

delta TR

Rev. 0.5 / Sep 2008 13

1240pin DDR2 SDRAM Unbuffered DIMMs

Differential Input AC logic Level

Notes:

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,

LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as

CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.

The minimum value is equal to VIH(DC) - VIL(DC).

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal

(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to V IH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.

DIFFERENTIAL AC OUTPUT PARAMETERS

Note:

1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected

to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.

Symbol Parameter Min. Max. Units Note

VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

Symbol Parameter Min. Max. Units Note

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

VDDQ

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal levels >

Rev. 0.5 / Sep 2008 14

1240pin DDR2 SDRAM Unbuffered DIMMs

OUTPUT BUFFER LEVELS

OUTPUT AC TEST CONDITIONS

Note:

1. The VDDQ of the device under test is referenced.

OUTPUT DC CURRENT DRIVE

Notes:

1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and

VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device

drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an

SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm

load line to define a convenient driver current for me asurement.

Symbol Parameter SSTL_18 Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

Rev. 0.5 / Sep 2008 15

1240pin DDR2 SDRAM Unbuffered DIMMs

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz)

256MB: HYMP532U64CP6

512MB: HYMP564U64CP8

512MB: HYMP564U72CP8

1GB: HYMP512U64CP8

1GB: HYMP512U72CP8

Notes:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Pin Symbol Min Max Unit

CK, CK CCK 18 22 pF

CKE, ODT,CS CI1 57 63 pF

Address, RAS, CAS, WE CI2 42 48 pF

DQ, DM, DQS, DQS CIO 7 9 pF

Pin Symbol Min Max Unit

CK, CK CCK 22 30 pF

CKE, ODT,CS CI1 62 84 pF

Address, RAS, CAS, WE CI2 42 64 pF

DQ, DM, DQS, DQS CIO 6 9 pF

Pin Symbol Min Max Unit

CK, CK CCK 22 30 pF

CKE, ODT,CS CI1 63 85 pF

Address, RAS, CAS, WE CI2 43 66 pF

DQ, DM, DQS, DQS CIO 6 9 pF

Pin Symbol Min Max Unit

CK, CK CCK 22 35 pF

CKE, ODT,CS CI1 64 87 pF

Address, RAS, CAS, WE CI2 50 88 pF

DQ, DM, DQS, DQS CIO 8 13 pF

Pin Symbol Min Max Unit

CK, CK CCK 23 35 pF

CKE, ODT,CS CI1 65 89 pF

Address, RAS, CAS, WE CI2 52 92 pF

DQ, DM, DQS, DQS CIO 9 13 pF

Rev. 0.5 / Sep 2008 16

1240pin DDR2 SDRAM Unbuffered DIMMs

IDD SPECIFICATIONS(TCASE: 0 to 95oC)

256MB, 32M x 64 U-DIMM: HYMP532U64CP6

512MB, 64M x 64 U - DIMM: HYMP564U64CP8

Note: 1. IDD6 current values are guaranteed up to Tcase of 85℃ max.

Symbol DDR2 400 DDR2 53 3 DDR2 667 Unit note

IDD0 400 400 440 mA

IDD1 440 440 480 mA

IDD2P 32 32 32 mA

IDD2Q 120 120 160 mA

IDD2N 120 160 160 mA

IDD3P(F) 120 120 120 mA

IDD3P(S) 48 48 48 mA

IDD3N 160 200 200 mA

IDD4W 520 680 800 mA

IDD4R 440 600 680 mA

IDD5B 600 600 640 mA

IDD6 32 32 32 mA 1

IDD7 1280 1280 1280 mA

Symbol DDR2 400 DDR2 533 DDR2 667 DDR2 800 Unit note

IDD0 640 640 720 800 mA

IDD1 640 720 720 800 mA

IDD2P 64 64 64 64 mA

IDD2Q 240 240 320 320 mA

IDD2N 240 320 320 400 mA

IDD3P(F) 240 240 240 280 mA

IDD3P(S) 96 96 96 96 mA

IDD3N 320 400 400 480 mA

IDD4W 800 1040 1200 1440 mA

IDD4R 720 880 1120 1280 mA

IDD5B 1200 1200 1280 1320 mA

IDD6 64 64 64 64 mA 1

IDD7 1680 1680 1760 1840 mA

Rev. 0.5 / Sep 2008 17

1240pin DDR2 SDRAM Unbuffered DIMMs

512MB, 64M x 72 ECC U - DIMM: HYMP564U72CP8

1GB, 128M x 64 U - DIMM: HYMP512U64CP8

Note: 1. IDD6 current value s are guaranteed up to Tcase of 85℃ max.

Symbol DDR2 400 DDR2 533 DDR2 667 DDR2 800 Unit note

IDD0 720 720 810 900 mA

IDD1 720 810 810 900 mA

IDD2P 72 72 72 72 mA

IDD2Q 270 270 360 360 mA

IDD2N 270 360 360 450 mA

IDD3P(F) 270 270 270 315 mA

IDD3P(S) 108 108 108 108 mA

IDD3N 360 450 450 540 mA

IDD4W 900 1170 1350 1620 mA

IDD4R 810 990 1260 1440 mA

IDD5B 1350 1350 1440 1485 mA

IDD6 72 72 72 72 mA 1

IDD7 1890 1890 1980 2070 mA

Symbol DDR2 400 DDR2 533 DDR2 667 DDR2 800 Unit note

IDD0 960 1040 1120 1280 mA

IDD1 960 1120 1120 1280 mA

IDD2P 128 128 128 128 mA

IDD2Q 480 480 640 640 mA

IDD2N 480 640 640 800 mA

IDD3P(F) 480 480 480 560 mA

IDD3P(S) 192 192 192 192 mA

IDD3N 640 800 800 960 mA

IDD4W 1120 1440 1600 1920 mA

IDD4R 1040 1280 1520 1760 mA

IDD5B 1520 1600 1680 1800 mA

IDD6 128 128 128 128 mA 1

IDD7 2000 2080 2160 2320 mA

Rev. 0.5 / Sep 2008 18

1240pin DDR2 SDRAM Unbuffered DIMMs

1GB, 128M x 72 ECC U - DIMM: HYMP512U72CP8

Note: 1. IDD6 current value s are guaranteed up to Tcase of 85℃ max.

Symbol DDR2 400 DDR2 533 DDR2 667 DDR2 800 Unit note

IDD0 1080 1170 1260 1440 mA

IDD1 1080 1260 1260 1440 mA

IDD2P 144 144 144 144 mA

IDD2Q 540 540 720 720 mA

IDD2N 540 720 720 900 mA

IDD3P(F) 540 540 540 630 mA

IDD3P(S) 216 216 216 216 mA

IDD3N 720 900 900 1080 mA

IDD4W 1260 1620 1800 2160 mA

IDD4R 1170 1440 1710 1980 mA

IDD5B 1710 1800 1890 2025 mA

IDD6 144 144 144 144 mA 1

IDD7 2250 2340 2430 2610 mA

Rev. 0.5 / Sep 2008 19

1240pin DDR2 SDRAM Unbuffered DIMMs

IDD MEASUREMENT CONDITIONS

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQ S, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met

with all combinations of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin ≤ VILAC (max)

HIGH is defined as Vin ≥ VIHAC (min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control sig-

nals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not

including masks or strobes.

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin

(IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus

inputs are SWITCHING mA

IDD1 Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK =

tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between

valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA

IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK (IDD);CKE is HIG H, CS is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is

LOW; Other control and address bus inputs are STABLE; Data bus inputs

are FLOATING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP =tRP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING mA

IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =

tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = 0; tCK = tCK(IDD), tRAS = tRASmax (IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid

commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA

IDD5B Burst refresh current ; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6

current values are guaranteed up to Tcase of 85℃ max.

Normal mA

Low Power

IDD7

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL

= tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is

HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-

tern is same as IDD4R; - Refer to the following page for detailed timing conditions

mA

Rev. 0.5 / Sep 2008 20

1240pin DDR2 SDRAM Unbuffered DIMMs

Electrical Characteristics & AC Timings

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

AC Timing Parameters by Speed Grade

Speed DDR2-800 DDR2-800 DDR2-667 DDR2-667 DDR2-533 DDR2-400 Unit

Bin (CL-tR CD-tRP ) 5-5-5 6-6-6 4-4-4 5-5-5 3-3-3 4-4-4

Parameter min min min min min min

CAS Latency 564535

ns

tRCD 12.5 15 12 15 11.25 15 ns

tRP 12.5 15 12 15 11.25 15 ns

tRAS 45 45 45 45 45 40 ns

tRC 57.25 60 57 60 56.25 55 ns

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Data-Out edge to Cl ock edge Skew tAC -600 +600 -500 500 ps

DQS-Out edge to Clock edge Skew tDQSCK -500 +500 -500 450 ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK

Clock Half Period tHP min(tCL,tCH) -min

(tCL, tCH) -ns

System Clock Cycle Time tCK 5000 8000 3750 8000 ps

DQ and DM input setup time(differential strobe) tDS 150 - 100 -ps 1

DQ and DM input hold time(differential strobe) tDH 275 - 225 -ps 1

DQ and DM input setup time(single ended strobe) tDS1 25 --25-ps 1

DQ and DM input hold time(single ended strobe) tDH1 25 --25-ps 1

Control & Address input Pulse Width for each input tIPW 0.6 -0.6 - tCK

DQ and DM input pulse width for each inp ut tDIPW 0.35 -0.35 - tCK

Data-out high-impedance window from CK, /CK tHZ -tAC max

-tAC max

ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps

DQ hold skew factor tQHS - 450 - 400 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated clock edge tDQSS -0.25 + 0.25 -0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

Rev. 0.5 / Sep 2008 21

1240pin DDR2 SDRAM Unbuffered DIMMs

- continued -

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Address and control input setup ti me tIS 350 -250-ps

Address and control input hold time tIH 475 -375-ps

Read pre amble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamb le tRPST 0.4 0.6 0.4 0.6 tCK

Auto-Refresh to Active/Auto-Refresh command

period tRFC 105 -105 -ns

Row Active to Row Active Delay for 1KB page size tRRD 7.5 -7.5 - ns

Row Active to Row Active Delay for 2KB page size tRRD 10 -10 - ns

Four Activate Window for 1KB page size tFAW 37.5 -37.5 - ns

Four Activate Window for 2KB page size tFAW 50 -50 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto Precharge Write Recovery + Precharge Time tDAL WR+tRP -tWR + tRP - tCK

Write to Read Command Delay tWTR 10 -7.5-ns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refre sh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refre sh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to an y non-read

command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 3 3 tCK

ODT turn-on delay tAOND 2222

tCK

ODT turn-on tAON tAC (min) tAC(max)+1 tAC (min) t AC(max)+1 ns

ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC(min)+2 2tCK+tAC(m

ax)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC (min) tAC(max)+0

.6 tAC (min) tAC (max)+

0.6 ns

ODT turn-off (Power-Down mode) tAOFPD 2.5 2.5 tAC(min)+2 2.5tCK+tAC(

max)+1 ns

Rev. 0.5 / Sep 2008 22

1240pin DDR2 SDRAM Unbuffered DIMMs

- continued -

Notes:

1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS12[8,16]21CFP).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

ODT to power down entry latency tANPD tAC (min) tAC(max)+0.

63tCK

ODT power down exit latency tAXPD tAC(min)+2 2.5tCK+

tAC(max)+1 8tCK

OCD drive mode output delay tOIT 3012

ns

Minimum time clocks remains ON after

CKE asynchronously drops LOW tDelay 8 tIS + tCK + tIH ns

Average periodic Refresh Interval tREFI -7.8-7.8us 2

tREFI -3.9 -3.9 us 3

Rev. 0.5 / Sep 2008 23

1240pin DDR2 SDRAM Unbuffered DIMMs

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

DQ output access time from CK/CK tAC -450 +450 -400 +400 ps

DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL,

tCH) -min(tCL,

tCH) -ps

Clock cycle time, CL=x tCK 3000 8000 2500 ps

DQ and DM inpu t setup time

(differen t ial strobe ) tDS 100 - 50 -ps 1

DQ and DM input hold time

(differen t ial strobe ) tDH 175 - 125 -ps 1

Control & Addres s input puls e width f or eac h

input tIPW 0.6 - 0.6 -tCK

DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 -tCK

Data-out high-impe dan ce time from CK/CK tHZ - tAC max - tAC max ps

DQS low-impedance time from CK/C K tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ

signals tDQSQ - 240 -200ps

DQ hold skew factor tQHS - 340 -300ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated

clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set com mand cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Address and control input setup time tIS 200 - 175 -ps

Address and control input hold time tIH 275 - 250 -ps

Read pr eambl e tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Activate to precharge command tRAS 45 70000 45 70000 ns

Active to active command period for 1KB

page size products tRRD 7.5 -7.5-ns

Active to active command period for 2KB

page size products tRRD 10 -10-ns

Four Active Window for 1KB page size

products tFAW 37.5 -35 -ns

Four Active Window for 2KB page size

products tFAW 50 -45 -ns

Rev. 0.5 / Sep 2008 24

1240pin DDR2 SDRAM Unbuffered DIMMs

- continued -

Notes:

1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS12[8,16]21CFP).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto precharge write recovery + precharge

time tDAL WR+tRP -WR+tRP -tCK

Internal write to read command delay tWTR 7.5 -7.5-ns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge powe r down to any non-read

command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 7 - AL 8 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 33tCK

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC (min) tAC (max)

+0.7 tAC (min) tAC (max)

+0.7 ns

ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC (min)

+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC (min) tAC (max)+

0.6 tAC (min) tAC (max)

+0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC (min)

+2 2.5tCK+

tAC(max)+1 tAC (min)

+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS + tCK +

tIH tIS + tCK

+ tIH ns

Average periodic Refresh Interval tREFI - 7.8 - 7.8 us 2

tREFI -3.9 -3.9 us 3

Rev. 0.5 / Sep 2008 25

1240pin DDR2 SDRAM Unbuffered DIMMs

PACKAGE OUTLINE

32Mx64 - HYMP532U64CP6

N o te) A ll d im e n sio ns a re in millim e ters u nle ss o the rw ise s tate d.

Front

30.

0

4.0±0.1

133.35

63.0

5.17

55.17

5

55.0

5.

0

Back

0.8 ± 0.05

1.

0

0.20

Detail of

Contacts A

2.50 ±

0.20

Detail of

Contacts B

2.50

1.50±

0.10

3.80

5.00

Detail-A Detail-B

Side

3.18 m ax

(Fron

t)

1.27 ±

0.10

3.

03.

0

10.

0

17.80

128.95

(2)

2.5

Rev. 0.5 / Sep 2008 26

1240pin DDR2 SDRAM Unbuffered DIMMs

PACKAGE OUTLINE

64Mx 64 - HYMP564U64CP8

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Deta il of Contacts A

2.50

± 0.20

Detail of Contacts B

2.50

1.50± 0.10

3.80

5.00

3.0 3.0

10.0

17.80

Detail-A Detail-B

No te ) A ll d ime nsio n s a re in m illime te rs u n le ss o therwis e st a te d.

Side

2.7 max

(Front)

1.27 ± 0.10

128.95

(2)

2.5

Rev. 0.5 / Sep 2008 27

1240pin DDR2 SDRAM Unbuffered DIMMs

PACKAGE OUTLINE

64Mx 72 - HYMP564U72CP8

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Detail of Contacts A

2.50

± 0.20

Detail of Contac ts B

2.50

1.50

± 0.10

3.80

5.00

3.0 3.0

10.0

17.80

Detail-A Detail-B

No te) A ll d imensio n s a re in mi llime te rs u nles s otherw i s e s ta te d.

Side

2.7 max

(Front)

1.27 ± 0.10

128.95

(2)

2.5

Rev. 0.5 / Sep 2008 28

1240pin DDR2 SDRAM Unbuffered DIMMs

PACKAGE OUTLINE

128Mx 64 - HYMP512U64CP8

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Deta il o f Co nta c ts A

2.50

± 0.20

Deta il of C o n ta c ts B

2.50

1.50± 0.10

3.80

5.00

Side

4.00 max.

1.27 ± 0.10

3.0 3.0

10.0

17.80

Detail-A Detail-B

Note) All dimensions are in millimeters unless otherwise stated.

128.95

(2)

2.5

Rev. 0.5 / Sep 2008 29

1240pin DDR2 SDRAM Unbuffered DIMMs

PACKAGE OUTLINE

128Mx 72 - HYMP512U72CP8

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Deta il of C o ntacts A

2.50 ± 0.20

Detail of Co n tac ts B

2.50

1.50± 0.10

3.80

5.00

Side

4.00 max.

1.27 ± 0.10

3.0 3.0

10.0

17.80

Detail-A Detail-B

Note) A ll dimensions are in millimeters u n le ss o the rwise sta te d.

128.95

(2)

2.5

Rev. 0.5 / Sep 2008 30

1240pin DDR2 SDRAM Unbuffered DIMMs

REVISION HISTORY

Revision History Date Remark

0.1 First Version Release Aug. 2006

0.2 Updated IDD3P-S value Aug. 2006

0.3 Added Guide Holes to DIMM Outline Dec. 2006

0.4 Added S6 Speed Bin May 2007

0.5 Editorial Correction Sep. 2008