Features
5V CMOS and TTL Compatible
Fast Switching
Single Event Effect (SEE) Hardened
Low Total Gate Charge
Simple Drive Requirements
Ease of Paralleling
Hermetically Sealed
Ceramic Package
Surface Mount
Light Weight
ESD Rating: Class 1C per MIL-STD-750, Method 1020
Absolute Maximum Ratings Pre-Irradiation
Parameter Units
ID @ VGS = -4.5V, TC = 25°C Continuous Drain Current -22*
A
ID @ VGS = -4.5V, TC = 100°C Continuous Drain Current -14.9
IDM Pulsed Drain Current -88
PD @TC = 25°C Maximum Power Dissipation 57 W
Linear Derating Factor 0.45 W/°C
VGS Gate-to-Source Voltage ± 10 V
EAS Single Pulse Avalanche Energy 79 mJ
IAR Avalanche Current -22 A
EAR Repetitive Avalanche Energy 5.7 mJ
dv/dt Peak Diode Recovery dv/dt -12.3 V/ns
TJ Operating Junction and -55 to + 150
TSTG Storage Temperature Range
Pckg. Mounting Surface Temp. 300 (for 5s)
Weight 1.0 (Typical) g
°C
SMD-0.5
2N7624U3
IRHLNJ797034
1 2016-11-14
Product Summary
Part Number Radiation Level RDS(on) ID
IRHLNJ797034 100 kRads(Si) 0.072 -22A*
IRHLNJ793034 300 kRads(Si) 0.072 -22A*
RADIATION HARDENED
LOGIC LEVEL POWER MOSFET
SURFACE MOUNT (SMD-0.5)
* Current is limited by package
For Footnotes refer to the page 2.
PD-97302D
Description
R
7
60V, P-CHANNEL
TECHNOLOGY
IR HiRel R7 Logic Level Power MOSFETs provide simple
solution to interfacing CMOS and TTL control circuits to
power devices in space and other radiation environments. The
threshold voltage remains within acceptable operating
limits over the full operating temperature and post radiation. This
is achieved while maintaining single event gate rupture
and single event burnout immunity.
The device is ideal when used to interface directly with
most logic gates, linear IC’s, micro-controllers, and other
device types that operate from a 3.3-5V source. It may
also be used to increase the output current of a PWM,
voltage comparator or an operational amplifier where the
logic level drive signal is available.
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Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified)
Parameter Min. Typ. Max. Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage -60 ––– ––– V VGS = 0V, ID = -250µA
BVDSS/TJ Breakdown Voltage Temp. Coefficient ––– -0.055 ––– V/°C Reference to 25°C, ID = -1.0mA
RDS(on) Static Drain-to-Source On-State ––– ––– 0.072 VGS = -4.5V, ID = -14.9A
Resistance
VGS(th) Gate Threshold Voltage -1.0 ––– -2.0 V
VGS(th)/TJ Gate Threshold Voltage Coefficient ––– 3.5 ––– mV/°C
Gfs Forward Transconductance 16 ––– ––– S VDS = -10V, ID = -14.9A
IDSS Zero Gate Voltage Drain Current ––– ––– -1.0 µA VDS = -48V, VGS = 0V
––– ––– -15 VDS = -48V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Leakage Forward ––– ––– -100 nA VGS = -10V
Gate-to-Source Leakage Reverse ––– ––– 100 VGS = 10V
QG Total Gate Charge ––– ––– 36
nC
ID = -22A
QGS Gate-to-Source Charge ––– ––– 10 VDS = -30V
QGD Gate-to-Drain (‘Miller’) Charge ––– ––– 18 VGS = -4.5V
td(on) Turn-On Delay Time ––– ––– 32
ns
VDD = -30V
tr Rise Time ––– ––– 250 ID = -22A
td(off) Turn-Off Delay Time ––– ––– 100 RG = 7.5
tf Fall Time ––– ––– 102 VGS = -5.0V
Ls +LD Total Inductance ––– 4.0 ––– nH Measured from the center of drain
pad to center of source pad
Ciss Input Capacitance ––– 2261 –––
pF
VGS = 0V
Coss Output Capacitance ––– 583 ––– VDS = -25V
Crss Reverse Transfer Capacitance ––– 91 ––– ƒ = 1.0MHz
RG Gate Resistance ––– ––– 20 ƒ = 1.0MHz,open drain
VDS = VGS, ID = -250µA
Source-Drain Diode Ratings and Characteristics
Parameter Min. Typ. Max. Units Test Conditions
IS Continuous Source Current (Body Diode) ––– ––– -22*
ISM Pulsed Source Current (Body Diode) ––– ––– -88
VSD Diode Forward Voltage ––– ––– -5.0 V TJ = 25°C,IS = -22A, VGS = 0V
trr Reverse Recovery Time ––– ––– 110 ns TJ = 25°C,IF = -22A,
Qrr Reverse Recovery Charge ––– ––– 132 nC VDD ≤-50V, di/dt = -100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
A
Footnotes:
Repetitive Rating; Pulse width limited by maximum junction temperature.
VDD = -25V, starting TJ = 25°C, L = 0.32mH, Peak IL = -22A, VGS = -10V
ISD -22A, di/dt -350A/µs, VDD -60V, TJ 150°C
Pulse width 300 µs; Duty Cycle 2%
Total Dose Irradiation with VGS Bias. -10 volt VGS applied and VDS = 0 during irradiation per MIL-STD-750, Method 1019, condition A.
Total Dose Irradiation with VDS Bias. -48 volt VDS applied and VGS = 0 during irradiation per MlL-STD-750, Method 1019, condition A.
Thermal Resistance
Parameter Min. Typ. Max. Units
RJC Junction-to-Case ––– ––– 2.2 °C/W
* Current is limited by package
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Table1. Electrical Characteristics @ Tj = 25°C, Post Total Dose Irradiation
Parameter Up to 300 kRads (Si) 1
Units Test Conditions
Min. Max.
BVDSS Drain-to-Source Breakdown Voltage -60 ––– V VGS = 0V, ID = -250µA
VGS(th) Gate Threshold Voltage -1.0 -2.0 V VDS = VGS, ID = -250µA
IGSS Gate-to-Source Leakage Forward ––– -100 nA VGS = -10V
IGSS Gate-to-Source Leakage Reverse ––– 100 nA VGS = 10V
IDSS Zero Gate Voltage Drain Current ––– -1.0 µA VDS = -48V, VGS = 0V
RDS(on) Static Drain-to-Source
On-State Resistance (TO-3) ––– 0.076 VGS = -4.5V, ID = -14.9A
RDS(on) Static Drain-to-Source
On-State Resistance (SMD-0.5) ––– 0.072 VGS = -4.5V, ID = -14.9A
VSD Diode Forward Voltage ––– -5.0 V VGS = 0V, ID = -22A
Table 2. Typical Single Event Effect Safe Operating Area
LET
(MeV/(mg/cm2))
Energy
(MeV)
Range
(µm)
VDS (V)
@VGS=0V @VGS=2V @VGS= 4V @VGS= 7V
38 ± 5% 300 ± 7.5% 38 ± 7.5% -60 -60 -60 -40
62 ± 5% 355 ± 7.5% 33 ± 7.5% -60 -60 -60 –––
85 ± 5% 380 ± 7.5% 29 ± 7.5% -60 -60 -60 –––
@VGS= 6V
-60
–––
–––
@VGS= 5V
-60
-60
–––
IR HiRel radiation hardened MOSFETs have been characterized in heavy ion environment for Single Event Effects
(SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2.
Fig a. Typical Single Event Effect, Safe Operating Area
For Footnotes, refer to the page 2.
IR HiRel Radiation Hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance
program at IR Hirel is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose
(per notes 5 and 6) using the TO-3 package. Both pre- and post-irradiation performance are tested and specified using
the same drive circuitry and test conditions in order to provide a direct comparison.
Radiation Characteristics
1 Part numbers IRHLNJ797034 and IRHLNJ793034
-70
-60
-50
-40
-30
-20
-10
0
01234567
Bias VDS (V)
Bias VGS (V)
LET=38 ± 5%
LET=62 ± 5%
LET=85 ± 5%
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Fig 2. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 1. Typical Output Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
0.1 1 10 100 1000
-VDS , Drain-to-Source Voltage (V)
1
10
100
-ID, Drain-to-Source Current (A)
20s PULSE WIDTH
Tj = 25°C
VGS
TOP -10V
-5.0V
-4.5V
-4.0V
-3.5V
-3.0V
-2.5V
BOTTOM -2.3V
-2.3V
0.1 1 10 100 1000
-VDS , Drain-to-Source Voltage (V)
1
10
100
-ID, Drain-to-Source Current (A)
20s PULSE WIDTH
Tj = 150°C
VGS
TOP -10V
-5.0V
-4.5V
-4.0V
-3.0V
-2.7V
-2.5V
BOTTOM -2.3V
-2.3V
2 2.5 3 3.5 4 4.5 5
-VGS, Gate-to-Source Voltage (V)
1
10
100
-ID, Drain-to-Source Current (A)
VDS = -25V
60s PULSE WIDTH
TJ = 150°C
TJ = 25°C
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
VGS = -4.5V
ID = -22A
2 4 6 8 10 12
-VGS, Gate -to -Source Voltage (V)
0
20
40
60
80
100
120
140
160
RDS(on), Drain-to -Source On Resistance (m)
ID = -22A
TJ = 25°C
TJ = 150°C
Fig 5. Typical On-Resistance Vs
Gate Voltage
010 20 30 40 50 60 70 80
-ID, Drain Current (A)
30
40
50
60
70
80
90
100
110
120
130
140
RDS(on), Drain-to -Source On Resistance (m)
TJ = 25°C
TJ = 150°C
Vgs = -4.5V
Fig 6. Typical On-Resistance Vs
Drain Current
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-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
-VGS(th) Gate threshold Voltage (V)
ID = -50µA
ID = -250µA
ID = -1.0mA
ID = -150mA
Fig 8. Typical Threshold Voltage Vs Temperature
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Temperature ( °C )
55
60
65
70
75
-V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
ID = -1.0mA
Fig 12. Maximum Drain Current Vs.
Case Temperature
110 100
-VDS, Drain-to-Source Voltage (V)
0
400
800
1200
1600
2000
2400
2800
3200
3600
C, Capacitance (pF)
VGS = 0V, f = 1 MHz
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
Fig 7. Typical Drain-to-Source Breakdown
Voltage Vs Temperature
0 1020304050607080
QG, Total Gate Charge (nC)
0
2
4
6
8
10
12
-VGS, Gate-to-Source Voltage (V)
VDS = -48V
VDS = -30V
VDS = -12V
ID = -22A
FOR TEST CIRCUIT
SEE FIGURE 17
0123456
-VSD , Source-to-Drain Voltage (V)
0.1
1
10
100
-ISD , Reverse Drain Current (A)
VGS = 0V
TJ = 150°C
TJ = 25°C
Fig 9. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 11. Typical Source-to-Drain Diode
Forward Voltage
25 50 75 100 125 150
TC , Case Temperature (°C)
0
5
10
15
20
25
-ID, Drain Current (A)
LIMITED BY PACKAGE
Fig 10. Typical Gate Charge Vs.
Gate-to-Source Voltage
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Fig 13. Maximum Safe Operating Area
Fig 15. Maximum Effective Transient Thermal Impedance, Junction-to-Case
110100
-VDS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
-ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1ms
10ms
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100s
DC
25 50 75 100 125 150
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
EAS , Single Pulse Avalanche Energy (mJ)
I
D
TOP -9.8A
-13.9A
BOTTOM -22A
Fig 14. Maximum Avalanche Energy
Vs. Drain Current
1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05 SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
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Fig 16a. Unclamped Inductive Test Circuit
Fig 17a. Basic Gate Charge Waveform
Fig 18b. Switching Time Waveforms
Fig 18a. Switching Time Test Circuit
Fig 16b. Unclamped Inductive Waveforms
Fig 17b. Gate Charge Test Circuit
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IR HiRel Headquarters: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
IR HiRel Leominster: 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
IR HiRel San Jose: 2520 Junction Avenue, San Jose, California 95134, USA Tel: (408) 434-5000
Data and specifications subject to change without notice.
Case Outline and Dimensions — SMD-0.5
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IMPORTANT NOTICE
The information given in this document shall be in no event regarded as guarantee of conditions or characteristic. The
data contained herein is a characterization of the component based on internal standards and is intended to
demonstrate and provide guidance for typical part performance. It will require further evaluation, qualification and
analysis to determine suitability in the application environment to confirm compliance to your system requirements.
With respect to any example hints or any typical values stated herein and/or any information regarding the application of
the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without
limitation warranties on non- infringement of intellectual property rights and any third party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s product and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of any
customer’s technical departments to evaluate the suitability of the product for the intended applications and the
completeness of the product information given in this document with respect to applications.
For further information on the product, technology, delivery terms and conditions and prices, please contact your local
sales representative or go to (www.infineon.com/hirel).
WARNING
Due to technical requirements products may contain dangerous substances. For information on the types in question,
please contact your nearest Infineon Technologies office.
