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MOS INTEGRATED CIRCUIT
μ
PD431000A
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
DATA SHEET
Document No. M11657EJDV0DS00 (13th edition)
Date Published November 2008
Printed in Japan
1990, 1993, 1995
Description
The
μ
PD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The
μ
PD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In
addition to this, A and B versions are low voltage operations.
The
μ
PD431000A is packed in 32-pin PLASTIC DIP, 32-pin PLASTIC SOP and 32-pin PLASTIC TSOP (I) (8 × 13.4
mm) and (8 × 20 mm).
Features
• 131,072 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Operating ambient temperature: TA = 0 to 70 °C
• Low VCC data retention: 2.0 V (MIN.)
• Output Enable input for easy application
• Two Chip Enable inputs: /CE1, CE2
Part number Access time Operating supply Operating ambient Supply current
ns (MAX.) voltage temperature At operating At standby At data retention
V °C mA (MAX.)
μ
A (MAX.)
μ
A (MAX.) Note1
μ
PD431000A-xxL 70, 85 4.5 to 5.5 0 to 70 70 100 15
μ
PD431000A-xxLL 20 3
μ
PD431000A-Axx 70 Note2, 100 3.0 to 5.5 35 Note3 13 Note5
μ
PD431000A-Bxx 70 Note2, 100, 120, 150 2.7 to 5.5 30 Note4 11 Note6
Notes 1. TA ≤ 40 °C
2. VCC = 4.5 to 5.5 V
3. 70 mA (VCC > 3.6 V)
4. 70 mA (VCC > 3.3 V)
5. 20
μ
A (VCC > 3.6 V)
6. 20
μ
A (VCC > 3.3 V)
Data Sheet M11657EJDV0DS
2
μ
PD431000A
Ordering Information (1/2)
Part number Package Access time Operating supply Operating ambient Remark
ns (MAX.) voltage temperature
V °C
μ
PD431000ACZ-70L 32-pin PLASTIC DIP 70 4.5 to 5.5 0 to 70 L version
μ
PD431000ACZ-85L (15.24mm (600)) 85
μ
PD431000ACZ-70LL 70 LL version
μ
PD431000ACZ-85LL 85
μ
PD431000AGW-70L 32-pin PLASTIC SOP 70 4.5 to 5.5 L version
μ
PD431000AGW-85L (13.34 mm (525)) 85
μ
PD431000AGW-70LL 70 LL version
μ
PD431000AGW-85LL 85
μ
PD431000AGW-A10 100 3.0 to 5.5 A version
μ
PD431000AGW-B12 120 2.7 to 5.5 B version
μ
PD431000AGW-B15 150
μ
PD431000AGZ-70LL-KJH
32-pin PLASTIC TSOP(I) 70 4.5 to 5.5 LL version
μ
PD431000AGZ-B15-KJH (8x20) (Normal bent) 150 2.7 to 5.5 B version
μ
PD431000AGZ-70LL-KKH 32-pin PLASTIC TSOP(I) 70 4.5 to 5.5 LL version
(8x20) (Reverse bent)
μ
PD431000AGU-B10-9JH 32-pin PLASTIC TSOP(I) 100 2.7 to 5.5 B version
μ
PD431000AGU-B12-9JH (8x13.4) (Normal bent) 120
μ
PD431000AGU-B15-9JH 150
μ
PD431000AGU-B10-9KH 32-pin PLASTIC TSOP(I) 100
(8x13.4) (Reverse bent)
Data Sheet M11657EJDV0DS 3
μ
PD431000A
(2/2)
Part number Package Access time Operating supply Operating ambient Remark
ns (MAX.) voltage temperature
V °C
μ
PD431000AGW-70L-A 32-pin PLASTIC SOP 70 4.5 to 5.5 0 to 70 L version
μ
PD431000AGW-85L-A (13.34 mm (525)) 85
μ
PD431000AGW-70LL-A 70 LL version
μ
PD431000AGW-85LL-A 85
μ
PD431000AGW-A10-A 100 3.0 to 5.5 A version
μ
PD431000AGW-B12-A 120 2.7 to 5.5 B version
μ
PD431000AGW-B15-A 150
μ
PD431000AGZ-70LL-KJH-A
32-pin PLASTIC TSOP(I) 70 4.5 to 5.5 LL version
μ
PD431000AGZ-B10-KJH-A
(8x20) (Normal bent) 100 2.7 to 5.5 B version
μ
PD431000AGZ-70LL-KKH-A 32-pin PLASTIC TSOP(I) 70 4.5 to 5.5 LL version
(8x20) (Reverse bent)
μ
PD431000AGU-B10-9JH-A 32-pin PLASTIC TSOP(I) 100 2.7 to 5.5 B version
μ
PD431000AGU-B12-9JH-A (8x13.4) (Normal bent) 120
μ
PD431000AGU-B15-9JH-A 150
μ
PD431000AGU-B10-9KH-A 32-pin PLASTIC TSOP(I) 100
(8x13.4) (Reverse bent)
Remark Products with -A at the end of the part number are lead-free products.
Data Sheet M11657EJDV0DS
4
μ
PD431000A
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-pin PLASTIC DIP (15.24 mm (600))
[
μ
PD431000ACZ-xxL]
[
μ
PD431000ACZ-xxLL]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
VCC
A15
CE2
/WE
A13
A8
A9
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJDV0DS 5
μ
PD431000A
32-pin PLASTIC SOP (13.34 mm (525))
[
μ
PD431000AGW-xxL]
[
μ
PD431000AGW-xxLL]
[
μ
PD431000AGW-Axx]
[
μ
PD431000AGW-Bxx]
[
μ
PD431000AGW-xxL-A]
[
μ
PD431000AGW-xxLL-A]
[
μ
PD431000AGW-Axx-A]
[
μ
PD431000AGW-Bxx-A]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
V
CC
A15
CE2
/WE
A13
A8
A9
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJDV0DS
6
μ
PD431000A
32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
[
μ
PD431000AGZ-xxLL-KJH]
[
μ
PD431000AGZ-Bxx-KJH]
[
μ
PD431000AGZ-xxLL-KJH-A]
[
μ
PD431000AGZ-Bxx-KJH-A]
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
[
μ
PD431000AGZ-xxLL-KKH]
[
μ
PD431000AGZ-xxLL-KKH-A]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A0 - A16 : Address inputs /OE : Output Enable
I/O1 - I/O8 : Data inputs / outputs VCC : Power supply
/CE1, CE2 : Chip Enable 1, 2 GND : Ground
/WE : Write Enable NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJDV0DS 7
μ
PD431000A
32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
[
μ
PD431000AGU-Bxx-9JH]
[
μ
PD431000AGU-Bxx-9JH-A]
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
[
μ
PD431000AGU-Bxx-9KH]
[
μ
PD431000AGU-Bxx-9KH-A]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A0 - A16 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
NC : No connection
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11657EJDV0DS
8
μ
PD431000A
Block Diagram
Address buffer
Address
buffer Row
decoder Memory cell array
1,048,576 bits
Input data
controller
A0
A16
Sense amplifier /
Switching circuit
Column decoder
/CE1
/WE
/OE
CE2
Output data
controller
V
CC
GND
I/O1
I/O8
Truth Table
/CE1 CE2 /OE /WE Mode I/O Supply current
H × × × Not selected High impedance ISB
× L × ×
L H H H Output disable ICCA
L H L H Read DOUT
L H × L Write DIN
Remark × : VIH or VIL
Data Sheet M11657EJDV0DS 9
μ
PD431000A
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.5 Note to +7.0 V
Input / Output voltage VT –0.5 Note to VCC + 0.5 V
Operating ambient temperature TA 0 to 70 °C
Storage temperature Tstg –55 to +125 °C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition
μ
PD431000A-xxL
μ
PD431000A-Axx
μ
PD431000A-Bxx Unit
μ
PD431000A-xxLL
MIN. MAX. MIN. MAX. MIN. MAX.
Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V
High level input voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V
Low level input voltage VIL –0.3
Note +0.8 –0.3
Note +0.5 –0.3
Note +0.5 V
Operating ambient temperature TA 0 70 0 70 0 70 °C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input / Output capacitance CI/O VI/O = 0 V 10 pF
Remarks 1. VIN : Input voltage
V
I/O : Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M11657EJDV0DS
10
μ
PD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol Test condition
μ
PD431000A-xxL
μ
PD431000A-xxLL
μ
PD431000A-Axx Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0
μ
A
current
I/O leakage ILO VI/O = 0 V to VCC, –1.0 +1.0 –1.0 +1.0 –1.0 +1.0
μ
A
current /CE1 = VIH or CE2 = VIL
or /WE = VIL or /OE = VIH
Operating ICCA1 /CE1 = VIL, CE2 = VIH, 40 70 40 70 40 70 mA
supply current II/O = 0 mA
Minimum cycle time VCC ≤ 3.6 V – – 35
ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, 15 15 15
Cycle time = ∞ VCC ≤ 3.6 V – – 8
ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10 10 10
Cycle time = 1
μ
s, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
VCC ≤ 3.6 V – – 8
Standby ISB /CE1 = VIH or CE2 = VIL 3 3 3 mA
supply current VCC ≤ 3.6 V – – 2
ISB1 /CE1 ≥ VCC − 0.2 V, 2 100 1 20 1 20
μ
A
CE2 ≥ VCC − 0.2 V VCC ≤ 3.6 V – – 0.5 13
ISB2 CE2 ≤ 0.2 V 2 100 1 20 1 20
VCC ≤ 3.6 V – – – – 0.5 13
High level VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 2.4 2.4 V
output voltage IOH = –0.5 mA – – 2.4
VOH2 IOH = –0.02 mA – – VCC–0.1
Low level VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 0.4 0.4 V
output voltage IOL = 1.0 mA – – 0.4
VOL2 IOL = 0.02 mA – – 0.1
Remarks 1. VIN : Input voltage
V
I/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
Data Sheet M11657EJDV0DS 11
μ
PD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test condition
μ
PD431000A-Bxx Unit
MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0
μ
A
I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL –1.0 +1.0
μ
A
or /WE = VIL or /OE = VIH
Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA 40 70 mA
Minimum cycle time VCC ≤ 3.3 V 30
ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, 15
Cycle time = ∞ VCC ≤ 3.3 V 7
ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10
Cycle time = 1
μ
s, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V 7
Standby supply current ISB /CE1 = VIH or CE2 = VIL 3 mA
VCC ≤ 3.3 V 2
ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1 20
μ
A
VCC ≤ 3.3 V 0.5 11
ISB2 CE2 ≤ 0.2 V 1 20
VCC ≤ 3.3 V 0.5 11
High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V
2.4 V
IOH = –0.5 mA 2.4
VOH2 IOH = –0.02 mA VCC–0.1
Low level output voltage VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 V
IOL = 1.0 mA 0.4
VOL2 IOL = 0.02 mA 0.1
Remarks 1. VIN : Input voltage
V
I/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
Data Sheet M11657EJDV0DS
12
μ
PD431000A
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
μ
PD431000A-70L,
μ
PD431000A-85L,
μ
PD431000A-70LL,
μ
PD431000A-85LL]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Test points1.5 V 1.5 V
2.2 V
0.8 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1 Figure 2
(tAA, tCO1, tCO2, tOE, tOH) (tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW)
+5 V
I/O (Output)
1.8 kΩ
5 pF
CL
990 Ω
+5 V
I/O (Output)
1.8 kΩ
100 pF
CL
990 Ω
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[
μ
PD431000A-A10,
μ
PD431000A-B10,
μ
PD431000A-B12,
μ
PD431000A-B15]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Test points1.5 V 1.5 V
2.2 V
0.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Part number Output load condition
tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW
μ
PD431000A-A10,
μ
PD431000A-B10,
μ
PD431000A-B12 1TTL + 50 pF 1TTL + 5 pF
μ
PD431000A-B15 1TTL + 100 pF 1TTL + 5 pF
Data Sheet M11657EJDV0DS 13
μ
PD431000A
Read Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition
μ
PD431000A-70
μ
PD431000A-85
μ
PD431000A-A10
μ
PD431000A-Axx
μ
PD431000A-Bxx
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 70 85 100 ns
Address access time tAA 70 85 100 ns Note
/CE1 access time tCO1 70 85 100 ns
CE2 access time tCO2 70 85 100 ns
/OE to output valid tOE 35 45 50 ns
Output hold from address change tOH 10 10 10 ns
/CE1 to output in low impedance tLZ1 10 10 10 ns
CE2 to output in low impedance tLZ2 10 10 10 ns
/OE to output in low impedance tOLZ 5 5 5 ns
/CE1 to output in high impedance tHZ1 25 30 35 ns
CE2 to output in high impedance tHZ2 25 30 35 ns
/OE to output in high impedance tOHZ 25 30 35 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/2)
Parameter Symbol VCC ≥ 2.7 V Unit Condition
μ
PD431000A-B10
μ
PD431000A-B12
μ
PD431000A-B15
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 100 120 150 ns
Address access time tAA 100 120 150 ns Note
/CE1 access time tCO1 100 120 150 ns
CE2 access time tCO2 100 120 150 ns
/OE to output valid tOE 50 60 70 ns
Output hold from address change tOH 10 10 10 ns
/CE1 to output in low impedance tLZ1 10 10 10 ns
CE2 to output in low impedance tLZ2 10 10 10 ns
/OE to output in low impedance tOLZ 5 5 5 ns
/CE1 to output in high impedance tHZ1 35 40 50 ns
CE2 to output in high impedance tHZ2 35 40 50 ns
/OE to output in high impedance tOHZ 35 40 50 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11657EJDV0DS
14
μ
PD431000A
Read Cycle Timing Chart
t
HZ2
t
RC
t
OH
t
HZ1
t
LZ2
t
CO2
t
LZ1
t
CO1
t
AA
High impedance Data out
CE2 (Input)
/CE1 (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M11657EJDV0DS 15
μ
PD431000A
Write Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V VCC ≥ 3.0 V Unit Condition
`
μ
PD431000A-70
μ
PD431000A-85
μ
PD431000A-A10
μ
PD431000A-Axx
μ
PD431000A-Bxx
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 70 85 100 ns
/CE1 to end of write tCW1 55 70 80 ns
CE2 to end of write tCW2 55 70 80 ns
Address valid to end of write tAW 55 70 80 ns
Address setup time tAS 0 0 0 ns
Write pulse width tWP 50 60 60 ns
Write recovery time tWR 5 5 0 ns
Data valid to end of write tDW 35 35 60 ns
Data hold time tDH 0 0 0 ns
/WE to output in high impedance tWHZ 25 30 35 ns Note
Output active from end of write tOW 5 5 5 ns
Note See the output load.
Remark These AC characteristics are in common regardless package types.
Write Cycle (2/2)
Parameter Symbol VCC ≥ 2.7 V Unit Condition
μ
PD431000A-B10
μ
PD431000A-B12
μ
PD431000A-B15
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 100 120 150 ns
/CE1 to end of write tCW1 80 100 120 ns
CE2 to end of write tCW2 80 100 120 ns
Address valid to end of write tAW 80 100 120 ns
Address setup time tAS 0 0 0 ns
Write pulse width tWP 60 85 100 ns
Write recovery time tWR 0 0 0 ns
Data valid to end of write tDW 60 60 80 ns
Data hold time tDH 0 0 0 ns
/WE to output in high impedance tWHZ 35 40 50 ns Note
Output active from end of write tOW 5 5 5 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11657EJDV0DS
16
μ
PD431000A
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out High
impe-
dance
High
impe-
dance
Data in Indefinite data out
Address (Input)
/CE1 (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M11657EJDV0DS 17
μ
PD431000A
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
t
AS
t
CW1
t
DW
t
DH
Data in
High impedance
Address (Input)
/CE1 (Input)
I/O (Input) High
impedance
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M11657EJDV0DS
18
μ
PD431000A
Write Cycle Timing Chart 3 (CE2 Controlled)
tWC
tAS tCW2
tDW tDH
Data in
High impedance
Address (Input)
CE2 (Input)
I/O (Input) High
impedance
/CE1 (Input)
tCW1
tAW tWP tWR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M11657EJDV0DS 19
μ
PD431000A
Low VCC Data Retention Characteristics (TA = 0 to 70 °C)
Parameter Symbol Test Condition
μ
PD431000A-xxL
μ
PD431000A-xxLL Unit
μ
PD431000A-Axx
μ
PD431000A-Bxx
MIN. TYP. MAX. MIN. TYP. MAX.
Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, 2.0 5.5 2.0 5.5 V
supply voltage CE2 ≥ VCC − 0.2 V
VCCDR2 CE2 ≤ 0.2 V 2.0 5.5 2.0 5.5
Data retention ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, 1 50 Note1 0.5 10 Note2
μ
A
supply current CE2 ≥ VCC − 0.2 V
ICCDR2 VCC = 3.0 V, CE2 ≤ 0.2 V 1 50 Note1 0.5 10 Note2
Chip deselection tCDR 0 0 ns
to data retention
mode
Operation tR 5 5 ms
recovery time
Notes 1. 15
μ
A (TA ≤ 40 °C)
2. 3
μ
A (TA ≤ 40 °C)
Data Sheet M11657EJDV0DS
20
μ
PD431000A
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CE1
/CE1 ≥ V
CC
– 0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode t
R
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
CE2
CE2 ≤ 0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode t
R
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
Data Sheet M11657EJDV0DS 21
μ
PD431000A
Package Drawings
32-PIN PLASTIC DIP (15.24mm(600))
NOTES
1. Each lead centerline is located within 0.25 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A 40.64 MAX.
B 1.27 MAX.
C 2.54 (T.P.)
D 0.50±0.10
F 1.1 MIN.
G 3.2±0.3
J 5.08 MAX.
K 15.24 (T.P.)
M 0.25
N 0.25
H 0.51 MIN.
I 4.31 MAX.
L 13.2
+0.10
−0.05
2. Item "K" to center of leads when formed parallel.
P32C-100-600A-2
R 0 - 15°
P 0.9 MIN.
32 17
116
NB
I
M
R
M
C
D
F
H
G
A
JK
L
P
Data Sheet M11657EJDV0DS
22
μ
PD431000A
32 17
116
S
32-PIN PLASTIC SOP (13.34 mm (525))
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
C0.78 MAX.
B20.61 MAX.
A
1.27 (T.P.)
E 0.15±0.05
F 2.95 MAX.
G 2.7
H 14.1±0.3
I11.3
J1.4±0.2
D 0.40+0.10
−0.05
M0.12
N0.10
L 0.8±0.2
K 0.20+0.10
−0.05
P3°+7°
−3°
P32GW-50-525A-1
K
L
G
P
DM
B
J
detail of lead end
SN
A
H
I
M
F
E
C
Data Sheet M11657EJDV0DS 23
μ
PD431000A
NOTES
32-PIN PLASTIC TSOP(I) (8x20)
ITEM MILLIMETERS
A
B
C
E
I
8.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
18.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
R
L
0.97±0.08G
L 0.5
0.10N
P 20.0±0.2
Q3°+5°
−3°
0.25R
S32GZ-50-KJH1-2
S 0.60±0.15
J 0.8±0.2
G
F
ES
Q
detail of lead end
1
16
32
17
SN
S
C
D
M
M
B
A
P
K
I J
Data Sheet M11657EJDV0DS
24
μ
PD431000A
NOTES
32-PIN PLASTIC TSOP(I) (8x20)
ITEM MILLIMETERS
A
B
C
E
I
8.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
18.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
C
R
D
M
M
G
0.97±0.08G
L 0.5
0.10N
P 20.0±0.2
Q3°+5°
−3°
0.25R
S32GZ-50-KKH1-2
S 0.60±0.15
J 0.8±0.2
B
F
E
Q
S
L
detail of lead end
1
16
32
17
S
A
SN
K
I
P
J
Data Sheet M11657EJDV0DS 25
μ
PD431000A
32-PIN PLASTIC TSOP(I) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
P32GU-50-9JH-2
B 0.45 MAX.
C 0.5 (T.P.)
detail of lead end
A 8.0±0.1
H 12.4±0.2
B
T
D 0.22±0.05
G 1.0±0.05
I 11.8±0.1
J 0.8±0.2
K
L 0.5
M 0.08
N 0.08
Q 0.1±0.05
P 13.4±0.2
S 1.2 MAX.
R3°
T 0.25
U 0.6±0.15
+5°
−3°
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
M
U
L
R
Q
S
DM
C
G
J
0.145+0.025
−0.015
1
16
32
17
S
SN
K
H
P
IA
Data Sheet M11657EJDV0DS
26
μ
PD431000A
+0.025
−0.015
32-PIN PLASTIC TSOP(I) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
P32GU-50-9KH-2
B 0.45 MAX.
C 0.5 (T.P.)
detail of lead end
A 8.0±0.1
H 12.4±0.2
T
D 0.22±0.05
G 1.0±0.05
I 11.8±0.1
J 0.8±0.2
K
L 0.5
M 0.08
N 0.08
Q 0.1±0.05
P 13.4±0.2
S 1.2 MAX.
R3°
T 0.25
U 0.6±0.15
+5°
−3°
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
U
L
R
Q
S
0.145
1
16
32
17
SN
S
B
M
DM
C
G
A
K
H
P
IJ
Data Sheet M11657EJDV0DS 27
μ
PD431000A
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
μ
PD431000A.
Types of Surface Mount Device
μ
PD431000AGW-xxL : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-xxLL : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-Axx : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-Bxx : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGZ-xxLL-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
μ
PD431000AGZ-xxLL-KKH : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
μ
PD431000AGZ-Bxx-KJH : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
μ
PD431000AGU-Bxx-9JH : 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
μ
PD431000AGU-Bxx-9KH : 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
μ
PD431000AGW-xxL-A : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-xxLL-A : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-Axx-A : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGW-Bxx-A : 32-pin PLASTIC SOP (13.34 mm (525))
μ
PD431000AGZ-xxLL-KJH-A : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
μ
PD431000AGZ-xxLL-KKH-A : 32-pin PLASTIC TSOP(I) (8x20) (Reverse bent)
μ
PD431000AGZ-Bxx-KJH-A : 32-pin PLASTIC TSOP(I) (8x20) (Normal bent)
μ
PD431000AGU-Bxx-9JH-A : 32-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
μ
PD431000AGU-Bxx-9KH-A : 32-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
Types of Through Hole Mount Device
μ
PD431000ACZ-xxL : 32-pin PLASTIC DIP (15.24 mm (600))
μ
PD431000ACZ-xxLL : 32-pin PLASTIC DIP (15.24 mm (600))
Soldering process Soldering conditions
Wave soldering (Only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or below
Partial heating method Pin temperature : 300 °C or below, Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
Data Sheet M11657EJDV0DS
28
μ
PD431000A
Revision History
Edition/ Page Type of Description
Date This Previous revision
edition edition
13th edition/ through through Modification Ordering Information revised.
Nov. 2008
Data Sheet M11657EJDV0DS 29
μ
PD431000A
[MEMO]
Data Sheet M11657EJDV0DS
30
μ
PD431000A
[MEMO]
Data Sheet M11657EJDV0DS 31
μ
PD431000A
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
μ
PD431000A
The information in this document is current as of November, 2008. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data
books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or
types are available in every country. Please check with an NEC Electronics sales representative for
availability and additional information.
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
