HIGH-D ENSITY HIGH-PERFORMANCE KZ4 0 0 G H KZ4 0 0EH CMOS GATE ARRAYS OVERVIEW With the KZ400GH/KZ400EH CMOS Series, Kawasaki LSI offers an advanced generation of 0.35 micron gate arrays and embedded arrays. The Series provides cost-effective solutions for high-speed, highly integrated, yet low voltage applications in today's networking, computer and multimedia markets. Appropriate product applications include high-speed data routers/switches, 3D graphics and video encoders/decoders. To satisfy these requirements, the KZ400GH/KZ400EH Series uses Kawasaki LSl's 0.35 m DLM, TLM or QLM process technologies and an advanced cell architecture. This achieves high density, high speed and low power dissipation--comparable to standard cell products--while maintaining the quick turnaround of gate arrays. The KZ400GH/KZ400EH Series supports complex designs of up to 2 million gates and a system clock frequency as high as 200MHz. A variety of I/O buffers are available, including LVTTL, GTL+, HSTL, SSTL, LVDS, PCI, USB, Pseudo-ECL and OSC. The KZ400GH/KZ400EH Series offers a wide selection of compilable memories such as metal-programmable RAMs and all-layer RAMs/ROMs. This helps you optimize designs, because the best compilable memory for a specific application may be chosen. Also, ASIC-DRAM is under development for graphics, image processing and networking applications which require the large capacity of memory buffers. For high-performance and fast time-to-market designs, the KZ400GH/KZ400EH Series offers various high-performance cores such as CPU (and its peripherals), JPEG, CAM (Content Addressable Memory), and analog functions (PLL, A/D Converter, D/A Converter). You can also maximize the chip-level and system-level performance for complex designs by using Kawasaki LSl's design methodology. It includes rich libraries of accurately characterized cells, timing-driven synthesis, clock distribution schemes, test insertion, and a floor planner with interaction to synthesis on industry-standard tools. KEY FEATURES * * * * * * * * * * * CORE LIBRARY 0.35 m drawn channel length (0.29 m effective) Double/triple/quadruple layer metal CMOS technologies High-density and high-performance cell architecture comparable to standard cell solutions Gate array architecture with 20 masterslices for fastest time-to-market designs Embedded arrays offered for high-speed complex designs Customized array options available for high volume designs Wide selection of I/O buffers: LVTTL, GTL+, HSTL, SSTL, LVDS, PCI, USB, PECL, OSC 3.3V or 2.5V operation voltage I/O drive: 2~24 mA Low power dissipation: 0.63 W/MHz/gate at 3.3V The KZ400GH/KZ400EH Series library offers more than 300 robust macrocells, providing a variety of high-performance synthesis options. The macrocells are composed of different sized transistors, enabling you to optimize the design for speed, power and density. The macrocells have input slew-rate-dependent loading and offset * * * * * * Propagation delay of 130 ps (2NAND power gate, F.O.= 2) Clock skew management: PLL and clock distribution methodologies Six types of metal-programmable SRAM High-density (22K bits/mm 2) all-layer SRAM up to 256K bits Testability tools such as SCANTEST, IDDQ and JTAG Design system with open I/F to various front-end platforms ISO9001 certified on manufacturing and design quality since 1994 delay, and non-linear output load-dependent delay parameters to produce accurately characterized timing. This results in the maximum performance achievable from the process technology. The core library is supplied for many industry-standard tools and HDL's, including Verilog HDL, VHDL, Synopsys, Mentor, ViewLogic and others. KZ400GH/KZ400EH CMOS SERIES I/O LIBRARY The I/Os in the KZ400GH/KZ400EH Series are powered by 3.3 or 2.5V supplies. Kawasaki LSI also provides 5V-tolerant I/Os, which can receive signals from a 5V-powered device, yet output 3.3 or 2.5V. Slew-rate controlled buffers, input with pull-up, pull-down resistors and open drain outputs are also available. The KZ400GH/ KZ400EH Series also supports high-speed and low-voltage swing I/Os such as LVTTL, GTL+, Pseudo-ECL (PECL), High-Speed Transceiver Logic (HSTL), Stub Series Terminated Logic (SSTL) and Low-Voltage Differential Signal (LVDS). For computer and peripheral applications, Kawasaki LSI support industry-standard buses with its PCI Bus I/O buffers and USB I/O buffers. MEMORIES Metal-Programmable Memory LP RAMs feature high-performance and very low-power. The total capacity of an LP RAM is 16K bits. As an application example, LP RAMs are suitable for register files. Table 1 shows the performance and specifications of HD and LP RAMs. The KZ400GH/KZ400EH Series has two types of compiled metal-programmable memory: High-Density (HD) RAM and Low-Power (LP) RAM. HD RAMs feature high performance and high density up to 7.13K bits/mm2. HD RAMs are suitable for applications that need high-performance, high-density memories. The total capacity of an HD RAM is up to 36K bits per block. Table 1 KZ400GH/KZ400EH Metal-Programmable Memories HIGH-DENSITY RAM LOW-POWER RAM TOTAL BITS 64~36K 32~36K 64~36K 32~36K 1~16K 1~16K 1-p Async. 2-p Async. 1-p Sync 2-p Sync. 1-p Async. 2-p Async. WORD 64~4K 32~4K 64~4K 32~4K 1~128 1~128 BIT 1~36 1~36 1~36 1~36 1~128 1~128 DENSITY ~7,125 bits/mm2 ~3,454 bits/mm2 ~6,890 bits/mm2 ~3,402 bits/mm2 ~3,369 bits/mm2 ~3,369 bits/mm2 ACCESS TIME 2.6ns* 3.1ns* 2.9ns* 3.2ns* 2.4ns** 2.4ns** *Access time is for 512-word x 8-bit configuration in typical condition. **Access time is for 32-word x 8-bit configuration in typical condition. All-Layer Memory In the KZ400EH Series, higher density embedded memories are generated by all-layer memory compilers. All-layer memories feature extremely high-density, large-capacity, and high-performance, while offering low-power dissipation. The largest memory capacity is 256K bits for SRAM, and 1M bit for ROM. The bit density of 22K bits/mm2 for the single-port SRAM is extremely high for an ASIC memory. These Kawasaki LSI all-layer memories are tuned for highperformance, memory-intensive applications such as image processing, ATM switches, etc. If lower power is required, an Address Transition Detection (ATD) circuit can be optionally added. ATDdetects the address transition, then starts accessing the memory. After a certain period of time, it turns off the entire memory operation to cut off the DC current and prepare for the next address transition automatically. This option is very effective for power reduction when the operating frequency is less than 100MHz in SRAMs, and less than 50MHz in ROM. Kawasaki LSI is now developing ASIC-DRAM as one of the all-layer memories offered; the size of a 256K bit block is targeted to be 60% of that of the all-layer single-port RAM, with a density of about 35K bits/mm2. A 100MHz high-speed page mode operation can be achieved. Table 2 shows the performance specifications of all-layer memories. Table 2 KZ400EH All-Layer Memories SRAM ROM DRAM*** 1-p Async. 1-p Sync. 2-p Sync. 1-p Sync. 1-p Sync. TOTAL B ITS 16~256K 16~256K 16~64K 64~1M 2K~256K *The numbers are for 512-word x 8-bit configuration in typical condition. **The numbers are row access time/column access time under worst case conditions. ***Under development WORD 16~16K 16~16K 16~4K 64~128K 1K~64K BIT 1~64 1~64 1~64 1~128 1~64 DENSITY ACCESS TIME ~22,000 bits/mm 2 3.4ns* ~22,000 bits/mm 2 2.4ns* ~8,500 bits/mm2 3.8ns* ~100,000 bits/mm2 4.1ns* 35,000 bits/mm 2 20ns (RAS)/4ns(CAS)** ARRAY ARCHITECTURE gate array, on the other hand, the size of the core cell is uniformly large to provide sufficient drive for the large fanout. Yet this results in the low gate density, as most nets have a small number of fanouts and do not require high drive. With CBA, the smaller gate load and smaller wire load significantly improves performance, power and density compared to conventional gate arrays. These features are comparable to the same generation standard cell architecture. With this optimized cell architecture, KZ400GH/KZ400EH arrays achieve a gate density of up to 9,500 usable gates/mm2. The core cell cluster of the KZ400GH/KZ400EH Series as shown in Figure 1, is based on the CMOS-CBA(R) architecture licensed by Synopsys, Inc. It consists of two different unit cells: a compute cell and a drive cell. A compute cell contains four small PMOS and four small NMOS that are optimized for building logic and memory. A drive cell contains two large PMOS and two large NMOS that provide sufficient drive for global nets or large fanout. Statistical analysis has determined that a cluster of three compute cells and one drive cell provides optimal density for many design styles. In the conventional Figure 1 CMOS-CBA Array Core Architecture Compute Section Drive Section Cluster ARRAY FAMILY Table 3 shows the 20 base arrays in the KZ400GH/KZ400EH Series. Array utilization depends on design, and typically varies from 33 to 46% in DLM (Double Layer Metal) technology, from 50 to 69% in TLM (Triple Layer Metal) technology, and from 66 to 90% in QLM (Quadruple Layer Metal). A compute cell or a drive cell is counted as a gate. Kawasaki LSI offers an option to compile and fabricate a custom sized array for high-volume designs. Table 3 KZ400GH/KZ400EH Masterslice Selection ARRAY INDEX 006 009 013 016 019 027 031 036 040 046 050 058 064 069 077 108 144 207 262 307 STANDARD 108 128 152 168 184 216 232 248 264 280 292 312 328 340 360 424 488 584 656 708 Typical design both for DLM and TLM A compute cell or a drive cell is counted as a gate. PAD COUNT (BY PAD PITCH) FINE 112 136 160 180 196 232 252 268 284 304 316 340 356 372 392 464 536 640 720 780 RAW GATES 61,500 87,600 126,700 156,800 190,100 266,300 309,100 355,200 404,500 462,400 501,300 577,600 640,000 685,600 774,400 1,081,600 1,440,000 2,073,600 2,624,400 3,069,500 DLM 28,100 38,200 52,600 63,100 74,400 99,000 112,300 126,100 140,600 157,100 167,900 190,600 211,200 226,200 255,500 356,000 475,200 684,200 866,000 1,012,900 USABLE GATES TLM QLM 42,200 55,300 57,400 76,500 78,900 105,200 94,700 126,300 111,600 148,900 148,500 198,100 168,400 224,600 189,200 252,300 210,900 281,200 235,700 314.200 251,900 335,900 288,800 381,200 320,000 422,400 342,700 452,400 387,200 511,100 540,800 713,800 720,000 950,400 1,036,800 1,368,500 1,312,200 1,732,100 1,534,700 2,025,800 KZ400GH/KZ400EH CMOS SERIES MEGAFUNCTIONS AND ANALOG FUNCTIONS Kawasaki LSI supports a number of megafunctions other than the compiled memories in the KZ400GH/KZ400EH Series. These megafunctions minimize design time and maximize performance of complex system chips. The KC80 is a very high-performance CPU core that is binary-compatible with the Zilog Z80(R). A JPEG core is also available for imaging and data compression applications. Kawasaki LSI also offers an Address Processor Core or Content Addressable Memory (CAM) for high-performance broadband network and internetworking applications. There are a number of analog functions under development for video signal processing applications, system clock management and frequency synthesis. These functions include 8 and 10-bit A/D converters, 8-bit D/A converters, operational amplifiers, comparators, Phase Locked Loops (PLL) and Voltage Controlled Oscillators (VCO). CLOCK DISTRIBUTION For maximum system performance, it is important to minimize not only board-level system clock skew, but also chip-level clock skew on a die. Kawasaki LSI provides several clocking methodologies to minimize on-chip clock skew. Clock Tree Synthesis (CTS) Clock Buffer This method is the most popular and has been well utilized in older technologies. It is simple and effective in cases where the number of clocked elements are less than a few hundred, or the clock skew requirement is not stringent. In the KZ400GH/KZ400EH Series, up to 200 flip-flops (depending on frequency) can be driven in a single stage, with special buffers for clocking. Clock Tree Synthesis is an automatic way to build a clock tree by balancing the far end delay with local buffers at the most appropriate physical location. The clock tree is synthesized with low driving inverters or buffers. Clock Tree Synthesis (CTS) is efficient when the number of clocked instances is very large or the clock skew requirement is stringent. Clock Trunk with CTS The clock trunk is a wide metal line which is connected to a special clock driver. It provides lower skew and a shorter delay than a clock buffer or CTS. In the KZ400GH/KZ400EH Series, a strong clock driver can be built with multiple special buffers for clocking, or can be configured with an I/O clock driver, which typically uses 2 to 3 I/O pads. PACKAGES Kawasaki LSI has internal ceramic packaging capabilities, enabling accelerated prototype deliveries. Subcontractors are used for most of the cost-effective plastic packages that are popular in high volume designs. Kawasaki LSI also maintains close development relationships with key vendors, ensuring that the next generation of industry standard Ball Grid Arrays (BGA) will be offered to customers whose designs exceed 300 pins. Package offerings are shown in Table 4. Table 4 KZ400GH/KZ400EH Package Selection PACKAGE Skinny DIP PQFP LQFP (1.4 mm thick body) PBGA TBGA PGA PIN COUNT 42 44 64 256 256 144 64 64 80 304 304 180 80 100 352 352 208 100 128 416 416 256 120* 144 480 480 280 128 160 576 576 144* 176 160* 208 176 208* 240* 304* 672 *Drop-in heat spreader a vailable for high power dissipation TEST METHODOLOGY To ensure a high-quality device, it is important to implement a test strategy with high fault coverage. Kawasaki LSI's test methodology for the KZ400GH/KZ400EH Series includes the following test solutions. Internal Full Scan Testing Internal Full Scan Testing is one of the most powerful test methodologies for automatic development of test vectors, achieving more than 95% stuck-at fault coverage for large synchronous designs. The Synopsys Test Compiler, which automatically performs testability rule checking, scan chain insertion and ATPG (Automatic Test Pattern Generation). IDDQ Testing IDDQ Testing is an effective methodology which detects various types of silicon defects without area or performance overhead. This methodology is supported by measuring the device's quiescent power-supply current on functional vectors selected by CM-iTest(R) from CrossCheck, a part of Duet Technologies, Inc. This test provides an easy way to improve the fault coverage of an ad-hoc test strategy. JTAG (IEEE 1149.1 Boundary Scan Testing) JTAG is supported by inserting boundary scan circuits into the system logic and providing test vectors and BSDL for the boundary scan logic. The TAP controller and associated logic is transparently inserted into the customer's netlist. Process Monitoring Process monitoring is performed by adding an AC measurement circuit into the device and measuring the AC delay. This AC measurement verifies that the device can operate at a required frequency. Fault Simulation Fault simulation is supported using the Cadence Verifault-XL simulator, which allows you to rapidly obtain fault coverage information for the applied test vectors. KZ400GH/KZ400EH CMOS SERIES DESIGN SYSTEM Kawasaki LSI's integrated top-down design flow is shown in Fig. 2. It allows you to start either with VHDL or Verilog-HDL, or from the gate-level, and choose from a wide assortment of schematic capture programs. Kawasaki LSI supports popular EDA tools, from companies such as Synopsys, Cadence, Mentor Graphics and ViewLogic. Kawasaki LSI's Design Rule Checker and Delay Calculator can read EDIF netlists. Thus you have a choice of either VSS, Verilog, QuickSim II, ViewSim, V-System or IKOS Voyager, to read the delay files generated by the Delay Calculator for gate-level simulation. An accurate delay calculation method is provided, accounting for not only output-load-dependent delay, but also input-slew-rate-dependent offset delay, input-slew-rate-dependent loading delay and interconnect delay caused by wire resistance. This advanced calculation methodology, coupled with control of the physical layout, results in the implementation of the highest performance and most accurate designs. The interfaces to these tools are industry-standard formats such as Verilog-HDL, VHDL, EDIF, SDF, PDEF and WGL, making it very easy for designers to migrate their designs to Kawasaki LSI's technologies. The design sign-off golden simulator is Verilog. Figure 2 Kawasaki LSI's Design Flow Verilog HDL,VHDL Vector RTL Functional Simulation Memory Megafunction JTAG Schematic Capture Logic Synthesis Test Synthesis Timing Analysis EDIF Delay Calculator Design Rule Checker Gate-Level Simulation Test Vector Floorplanner Fault Simulation Placement and Clock Tree Synthesis Test Program Routing Tester Verification Fabrication ELECTRICAL CHARACTERISTICS Tables 5 through 7 show the electrical characteristics of the KZ400GH/KZ400EH Series. Table 5 Recommended Operating Conditions PARAMETER Power Supply Voltage SYMBOL VDD Ambient Temperature Ta RATING 3.0~3.6 2.3~2.7 -40~+85 UNITS V V C Table 6 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage SYMBOL VDD VIN Output Current Storage Temperature IOUT TSTG RATING UNITS -0.3~+3.6 V -0.3~VDD+0.3 V 0.3~+6.3 +30 mA -55~+125 C Table 7 DC Characteristics SYMBOL PARAMETER Vih High-Input Voltage Vil Low-Input Voltage V+ VVh lih lil Voh Vol loz High-Input Voltage Low-Input Voltage Hysteresis Voltage High-Input Current Low-Input Current High-Output Voltage Low-Output Voltage 3-State Lead Current lpu lpd ldds Active Pull-Up Current Active Pull-Down Current Static Stand-By Current CONDITIONS LVTTL 5V-tolerant LVTTL 3.3V PCI LVTTL 5V-tolerant LVTTL 3.3V PCI LVTTL-Schmitt LVTTL-Schmitt LVTTL-Schmitt VIN=VDD VIN=VSS loh=-2~-24mA lol=2~24mA Voh=VSS Vol=VDD VIN=VSS VIN=VDD - *The number is design-dependent. ESDProtection:=2000V using MIL STD-883D 3015.6 and EIAJ:ED4701 C-111 B standards Lock-up immunity:300mA injection current (room temp) using JEDEC No. 17 standard Silicon Valley Office Kawasaki LSI U.S.A., Inc. 4655 Old Ironsides Drive, Suite 265 Santa Clara, CA 95054 Tel: (408) 654-0180 Fax: (408) 654-0198 Eastern Area Office Kawasaki LSI U.S.A., Inc. 501 Edgewater Drive, Suite 510 Wakefield, MA 01880 Tel: (617) 224-4201 Fax: (617) 224-2503 Kawasaki LSI's logo design registered ais trademark Kawasaki of LSI USA, Inc. All other brand, product names, and company names are trademarks registered or trademarks their ofrespective companies. Kawasaki LSI reserves the right make to changes anyproducts to and services herein any attime without notice. Kawasaki LSI does not assume any responsibility liability or arising outoftheapplicationoruseofanyproductorservicedescribedherein;nordoesthepurchase,leaseoruse product ofa orservicefromKawasakiLSIconvey license a underanypatentrights,copyrights,trademarkrights,oranyotheroftheintellectualpropertyrightsofKawasakiLSIorofthirdparties.(c)1997KawasakiLSI.Allrightsreserved.PrintedU.S.A. in 1/97. MIN. 2.0 2.0 0.5 x VDD - - - - 0.5 0.4 -10 -10 2.4 - -10 -10 -25 25 - LIMITS TYP. - - - - - - 1.8 0.9 - - - - - - - -66 66 - UNITS MAX. - - - 0.8 0.8 0.3 x VDD 2.3 - - +10 +10 - 0.4 +10 +10 -160 160 450* V V V V V V V V V A A V V A A A A A