Product Specification PE42650A SP3T High Power UltraCMOSTM RF Switch 30 MHz - 1000 MHz Product Description ig de s The PE42650A is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Features * 50 Watt P1dB compression point * 10 Watts <8:1 VSWR (Normal Operation) * 38 dB TX-RX Isolation * 2fo and 3fo < -81 dBc @10 Watts * ESD rugged to 2.0 kV HBM * No blocking capacitors required * 32-lead 5x5 mm QFN package ns The following specification defines an SP3T (single pole three throw) switch for use in cellular and other wireless applications. It has both a standard and attenuated RX mode. The PE42650A uses Peregrine's UltraCMOSTM process and also features HaRPTM technology enhancements to deliver high linearity and exceptional harmonics performance. HaRPTM technology is an innovative feature of the UltraCMOSTM process providing upgraded linearity performance. Figure 2. Package Type 32-lead 5x5 mm QFN ne w Figure 1. Functional Diagram ot fo r TX1 ESD ANT TX2 N ESD RX ESD CMOS Control Driver and ESD CTRL Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE42650A Product Specification Table 1: Electrical Specifications @ +25 C, VDD = 3.3 V (ZS = ZL = 50 ) unless otherwise noted Parameter Conditions Min Typ Max Units 30 MHz 1 GHz 0.3 0.5 dB RX Insertion Loss (Un-Attenuated State)1 RX Insertion Loss (Attenuated State)1 30 MHz 1 GHz 800 MHz 0.5 14.5 0.9 16 dB dB 0.1 dB Input Compression Point 800 MHz, 50% duty cycle Isolation (Supply Biased): TX-TX 800 MHz Isolation (Supply Biased): TX-RX Unbiased Isolation: ANT - TX, VDD, V1, V2, V3=0 V Unbiased Isolation: ANT - RX, VDD, V1, V2, V3=0 V TX Insertion Loss 1 13 45.4 dBm 30 33 dB 800 MHz 35 38 dB 800 MHz, +27 dBm 6 10 dB 800 MHz, +27 dBm 14 22 dB Un-Attenuated State, 800 MHz 22 dB Attenuated State, with external matching inductor optimized without attenuator engaged, 800 MHz 12 18 dB TX and ANT Port Return Loss1 800 MHz 20 TX, 2nd Harmonic TX, 3rd Harmonic 800 MHz @ 42.5 dBm 800 MHz @ 42.5 dBm RX IIP3 Un-Attenuated State, 800 MHz, 150 kHz tone separation Switching Time 50% of CTRL to 10/90% of RF de s ig ns 18 RX Port Return Loss1 23 dB -81 -81 -79 -79 dBc dBc 30 dBm 0.1 0.5 ms w Note: 1. The device was matched with ~4 nH inductance per RF port. RX port may not need matching inductor. Table 3. Absolute Maximum Ratings Parameter Min 30 Max 1000 Units Symbol MHz VDD dBm VI TX Input Power1 (VSWR 8:1) 40 RX Input Power 2 (VSWR 8:1) fo r Frequency Range Typ ne Table 2. Operating Ranges VDD Power Supply Voltage 27 3.2 Control Voltage Low TOP Operating temperature range (Case) 170 -40 Tj Operating junction temperature Voltage on any DC input -0.3 -65 TST Storage temperature range V TCASE Maximum case temperature 3.4 uA Tj V 0.4 V 85 C 140 C Notes: 1. Supply biased 2. Supply biased or unbiased Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE42650A in the 5x5 QFN package is MSL3. Min Max Units -0.3 dBm 1.4 N Control Voltage High 90 ot IDD Power Supply Current 3.3 Parameter/Conditions Power supply voltage Peak maximum junction temperature (10 seconds max) TX Input Power1 (VSWR 20:1, 10 seconds) TX Input Power1 (50 ) 4 VDD+ 0.3 V V 150 C 85 C 200 C 40 dBm 45 dBm RX Input Power at ANT pin2 (VSWR 20:1) 27 dBm RF Input Power on inactive ports or supply unbiased 27 dBm PD Maximum Power Dissipation from RF Insertion Loss 2.8 W VESD ESD Voltage (HBM, MIL_STD 883 Method 3015.7) 2000 V PIN Notes: 1. Supply biased 2. Supply biased or unbiased Absolute Maximum Ratings Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Electrostatic Discharge (ESD) Precautions 25 GND GND 1 24 GND TX1 2 23 TX2 GND 3 22 GND TX1 4 GND 5 GND 6 19 GND GND 7 18 GND RX 8 17 GND Exposed Ground Paddle When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance 21 TX2 Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. 10 11 12 13 14 15 16 GND N/C Vdd V3 V2 V1 N/C Table 5. Control Logic Truth Table Path V3 V2 V1 L L L Unsupported mode L L H Unsupported mode L H L ANT - TX1 L H H ANT - RX H L L ig 9 GND 20 GND ns 26 GND 27 GND 28 ANT 29 GND 30 GND 31 GND 32 GND Figure 3. Pin Configuration (Top View) de s ANT - RX Attenuated Table 4. Pin Descriptions Description 1 GND Ground 2 TX1 TX1 port 3 GND Ground w Pin Name ne Pin No. TX11 TX1 port 5-7 GND Ground 8 RX RX port 9-10 GND Ground 11 N/C No Connect 12 VDD Nominal 3.3 V supply connection 13 V3 Control H L H H H L ANT - TX2 H H H 14 V2 Control 15 V12 16 N/C N ot fo r 4 Unsupported mode Unsupported mode 17-20 GND Ground 21 TX2 TX2 port Control Do not connect 22 GND Ground 23 TX23 TX2 port 24-27 GND Ground 28 ANT Antenna Port 29-32 GND Ground Paddle GND Exposed ground paddle Note: 1. Must be tied to pin 2 2. Must be tied to V2 3. Must be tied to pin 21 Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE42650A Product Specification Evaluation Kit Figure 4. Evaluation Board Layout The PE42650A Evaluation Kit board was designed to ease customer evaluation of the PE42650A RF switch. Peregrine Specification 101-0315 ig de s ne w The RF common port (ANT) is connected through a 50 Ohm transmission line via the top SMA connector, J1. RX and TX paths are also connected through 50 Ohm transmission lines via SMA connectors. A 50 Ohm through transmission line is available via SMA connectors J8 and J9. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. An open-ended 50 Ohm transmission line is also provided at J7 for calibration if needed. ns DC power is supplied through J10, with VDD on pin 9, and GND on the entire lower row of even numbered pins. To evaluate a switch path, add or remove jumpers on V1 (pin 3), V2 (pin 5), and V3 (pin 7) using Table 5 (adding a jumper pulls the CMOS control pin low and removing it allows the on-board pull-up resistor to set the CMOS control pin high). J10 pins 1, 11, and 13 are N/C. Figure 5. Evaluation Board Schematic Peregrine Specification 102-0535 N ot fo r Narrow trace widths are used near each part to improve impedance matching. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Performance Plots Figure 8. Isolation, Tx-Tx, +25C de s ig ns Figure 6. Isolation, Tx-Tx, VDD=3.3V Figure 9. Isolation, Tx-Rx, +25C N ot fo r ne w Figure 7. Isolation, Tx-Rx, VDD=3.3V Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE42650A Product Specification Figure 13. Tx Insertion Loss, +25C Figure 11. Rx Insertion Loss Un-Attenuated, VDD=3.3V Figure 14. Rx Insertion Loss Un-Attenuated, +25C N ot fo r ne w de s ig ns Figure 10. Tx Insertion Loss, VDD=3.3V Figure 12. Rx Insertion Loss Attenuated, VDD=3.3V (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Figure 15. Rx Insertion Loss Attenuated, +25C Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Figure 18. Return Loss, +25C de s ig ns Figure 16. Return Loss, VDD=3.3V Figure 19. Tx Return Loss, +25C N ot fo r ne w Figure 17. Tx Return Loss, VDD=3.3V Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE42650A Product Specification Figure 22. Rx Return Loss Attenuated, +25C de s ig ns Figure 20. Rx Return Loss Attenuated, VDD=3.3V Figure 23. Rx Return Loss Un-Attenuated, +25C N ot fo r ne w Figure 21. Rx Return Loss Un-Attenuated, VDD=3.3V (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Thermal Data Figure 24. Power Dissipation Though the insertion loss for this part is very low, when handling high power RF signals, the part can get quite hot. 3.0 1:1 VSWR (50 OhmLoad) 2.5 Power Dissipated (W) Figure 24 shows the estimated power dissipation for a given incident RF power level. Multiple curves are presented to show the effect of poor VSWR conditions. VSWR conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. Figure 25 shows the estimated maximum junction temperature of the part for similar conditions. Min Max 15 N ot Theta JC (+85C) Typ Units C/W 20:1 VSWR (2.5 OhmLoad) 2.0 INF:1 VSWR (0 OhmLoad) Reliabil ity Limit 1.5 1.0 ns 31 32 33 34 35 de s 30 ig 0.0 36 37 38 39 40 41 42 43 44 45 46 45 46 RF Power (dBm) w Figure 25. Maximum Junction Temperature 145 Max Junction Temperature (C) Parameter fo r Table 6. Theta JC 8:1 VSWR (6.25 OhmLoad) 0.5 ne Note that both of these charts assume that the case (GND slug) temperature is held at 85C. Special consideration needs to be made in the design of the PCB to properly dissipate the heat away from the part and maintain the 85C maximum case temperature. It is recommended to use best design practices for high power QFN packages: multi-layer PCBs with thermal vias in a thermal pad soldered to the slug of the package. Special care also needs to be made to alleviate solder voiding under the part. 2:1 VSWR (25 OhmLoad) 140 135 1:1 VSWR (50 OhmLoad) 130 2:1 VSWR (25 OhmLoad) 125 8:1 VSWR (6.25 OhmLoad) 120 INF:1 VSWR (0 OhmLoad) 20:1 VSWR (2.5 OhmLoad) Reliabil ity Limit 115 110 105 100 95 90 85 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 RF Power (dBm) Document No. 70-0267-02 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE42650A Product Specification Figure 26. Package Drawing See Note below de s ig ns Note: Not for electrical connection. Corner detail is tied to paddle and should not be isolated on PCB board. N ot fo r ne w Figure 27. Tape and Reel Specs Pin 1 Top of Device Tape Feed Direction Device Orientation in Tape Table 7. Ordering Information Part Marking Description Package Shipping Method PE42650AMLI-Z Order Code 42650A Parts on Tape and Reel Green 32-lead 5x5mm QFN 3000 units / T&R PE42650AMLI 42650A Parts in Tubes or Cut Tape Green 32-lead 5x5mm QFN 73 units / Tube EK42650A-01 42650A Evaluation Kit Evaluation Kit 1 / Box (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0267-02 UltraCMOSTM RFIC Solutions PE42650A Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 ns Peregrine Semiconductor K.K., Japan ig Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 de s High-Reliability and Defense Products w Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 fo r ne Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com ot Data Sheet Identification N Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0267-02 www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11