PE42650AMLI - Peregrine Semiconductor Corp.

Document No. 70-0267-02 │www. psemi.com

Page 1 of 11

32-lead 5x5 mm QFN

Fig ur e 2. Pa ck ag e Typ e

The following specification defines an SP3T (single pole three

throw) switch for use in cellular and other wireless applications.

It has both a standard and attenuated RX mode. The

PE42650A uses Peregrine’s UltraCMOS™ process and also

features HaRP™ technology enhancements to deliver high

li near i ty and exce pti o n al har m oni cs p er for m a nc e. H aR P™

technology is an innovative feature of the UltraCMOS™

process providing upgraded linearity performance.

The PE42650A is manufactured on Peregrine’s UltraCMOS™

pro cess, a patented variation of silicon-o n-insulator (SOI )

technology on a sapphire substrate, offering the performance

of GaAs with the econom y an d i nte gr ation of co nv entional

CMOS.

Pro duct Specificat ion

SP3T High Power UltraCMOS™

RF Switch 30 MHz - 1000 MHz

Product Description

PE42650A

Features

• 50 Watt P1dB compression point

• 10 Watts <8:1 VSWR (Normal

Operation)

• 38 dB TX-RX Is olatio n

• 2fo and 3fo < -81 dBc @10 Watts

• ESD rugged to 2.0 kV HBM

• No blocking capacitors required

• 32-lead 5x5 mm QFN package

Figure 1. Functional Diagram

TX1

ANT TX2

RX

CMOS

Control Driver

and ESD

CTRL

ESD

Not for new designs

Product Specification

PE42650A

Page 2 of 11

Table 1: Electrical Specifications @ +25 °C, VDD = 3.3 V (ZS = ZL = 50 Ω ) unless oth erwi se no t ed

Table 3. Absolute Maximum Ratings

Absolute Maximum Ratings

Exceeding abs olute maxim um ratings may cause

permanent damage. Operation should be res tricted to

the limits in t he Operating Ranges t able. Oper ation

between oper ating range maxi m um and abs olute

maximum for extended periods m ay r educ e r eliability.

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4 V

VI Voltage on any DC input -0.3 VDD+

0.3 V

TST Storage temperature range -65 150 °C

TCASE Maximum case temperature 85 °C

Tj Peak m ax imu m junc tio n

temperature (10 seconds max) 200 °C

TX Input Power1

(V SWR 20:1, 10 seconds) 40 dBm

TX Input Power1 (50 Ω) 45 dBm

RX Input Power at ANT pin2

(VSWR 20:1) 27 dBm

RF Input Power on inactive ports or

supply unbi ased 27 dBm

PD Maximum Power Dissipation fro m

RF Insertion Loss 2.8 W

VESD ESD Vo ltage (HBM, MIL_STD 883

Meth od 301 5.7) 2000 V

Table 2. Operating Ranges

Parameter Min Typ Max Units

Frequency Range 30 1000 MHz

TX Input Power1 (VSWR ≤ 8:1) 40 dB m

RX Input Power2 (VSWR ≤ 8:1) 27 dBm

VDD Power Supply Voltage 3.2 3.3 3.4 V

IDD Power Supply Current 90 170 uA

Control Voltage High 1.4 V

Control Voltage Low 0.4 V

TOP Operating temperature

range (Cas e) -40 85

°C

Tj Operating junction

temperature 140 °C

Moist u re Sensitivit y Lev el

The Mois ture Sensitiv ity Level r ating for the PE42650A

in the 5x5 QF N pac kage is MSL3.

Parameter Conditions Min Typ Max Units

TX Insertion Loss1 30 MH z ≤ 1 GHz 0.3 0.5 dB

RX Insertion Loss (Un-Attenuated State)1 30 MHz ≤ 1 GHz 0.5 0.9 dB

RX Insertion Loss (Attenuated State)1 800 MHz 13 14.5 16 dB

0.1 dB Inp ut Compre ssion Point 800 MH z, 50% duty cycle 45.4 dBm

Isolation (Supply Biased): TX-TX 800 MHz 30 33 dB

Isolation (Supply Biased): TX-RX 800 MHz 35 38 dB

Unbiased Isolation: ANT - TX, VDD, V1,

V2, V3=0 V 800 MHz, +27 dBm 6 10 dB

Unbiased Isolation: ANT - RX, VDD, V1,

V2, V3=0 V 800 MHz, +27 dBm 14 22 dB

RX Port Return Loss1 Un-Attenuated State, 800 MHz 18 22 dB

Atte nuat ed S t ate, wi th ex tern al matc hi ng ind uc tor o ptimized w it hout

att en uator en gag ed, 800 MHz 12 18 dB

TX an d ANT Port Return Loss1 800 MHz 20 23 dB

TX, 2n d H arm onic

TX, 3rd Har m onic 800 MHz @ 42.5 dBm

800 MHz @ 42.5 dBm -81

-81 -79

-79 dBc

dBc

RX IIP3 Un-Attenuated State, 800 MHz, 150 kHz tone separation 30 dBm

Switching Time 50% of CTRL to 10/90% of RF 0.1 0.5 ms

Notes: 1. Supply biased

2. Supply biased or unbiased

Notes: 1. Supply biased

2. Supply biased or unbiased

Note: 1. The device was matched with ~4 nH inductance per RF port. RX port may not need matching inductor.

Not for new designs

Product Specification

PE42650A

Page 3 of 11

Table 4 . Pin Descriptions

Electrostatic Discharge (ESD) Precautions

When handling this Ultr aCM OS™ device, observ e the

same pr ec autions that you would us e with other ESD-

sensit iv e devices. Although this devic e c ontains

circ uitry t o prot ec t it from dam age due to ES D,

precautions should be t ak en to avoid exc eeding the

rating s pec ified.

Latc h-Up Avoidance

Unlike conventional CMO S dev ic es , Ultr aCMOS™

devices are immune t o latch-up.

Figure 3. Pin Configur ation (Top View)

Pin No. Pin Name Description

1 GND Ground

2 TX1 TX1 port

4 TX11 TX1 port

8 RX RX port

11 N/C No Connect

12 VDD Nominal 3.3 V supply connection

13 V3 Control

14 V2 Control

15 V12 Control

16 N/C Do not connect

21 TX2 TX2 port

23 TX23 TX2 port

28 ANT Antenna Port

Paddle GND Exposed ground paddle

3 GND Ground

5-7 GND Ground

9-10 GND Ground

17-20 GND Ground

22 GND Ground

24-27 GND Ground

29-32 GND Ground

Table 5. Control Logic Truth Table

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

GND

TX1

GND

TX1

GND

RX

GND

TX2

GND

TX2

GND

N/C

Vdd

V3

V2

V1

N/C

GND

ANT

GND

Exposed

Ground

Paddle

Path V3 V2 V1

ANT – RX Attenuated L L L

Uns up ported mo de L L H

Uns up ported mo de L H L

ANT – TX1 L H H

ANT – RX H L L

Uns up port e d mo de H L H

Uns up port e d mo de H H L

ANT – TX2 H H H

Note: 1. Must be tied to pin 2

2. Mu st be tied to V2

3. Must be tied to pi n 21

Not for new designs

Product Specification

PE42650A

Page 4 of 11

Peregr ine S pec ification 101-0315

Evaluation Kit

The PE42650A Evaluation Kit board was designed

to ease customer evaluation of the PE42650A RF

switch.

DC power is supplied through J10, with VDD on pin 9,

and GND on the entire lower row of even numbered

pins. To evaluate a switch path, add or remove

jumpers on V1 (pin 3), V2 (pin 5), and V3 (pin

7) using Table 5 (adding a jumper pulls the CMOS

control pin low and removing it allows the on-board

pull-up resistor to set the CMOS control pin

high). J10 pins 1, 11, and 13 are N/C.

The RF common port (ANT) is connected through

a 50 Ohm transmission line via the top SMA

connector, J1. RX and TX paths are also

connected through 50 Ohm transmission lines via

SMA connectors. A 50 Ohm through transmission

line is available via SMA connectors J8 and J9.

This transmission line can be used to estimate the

loss of the PCB over the environmental conditions

being evaluated. An open-ended 50 Ohm

transmission line is also provided at J7 for calibration

if needed.

Narrow trace widths are used near each part to

improve impedance matching.

Figure 4. Evaluation Board Layout

Peregr ine S pec ification 102-0535

Figure 5. Evaluation Board Schematic

Not for new designs

Product Specification

PE42650A

Page 5 of 11

Performance Plots

Figure 6. Isolation, Tx-Tx, VDD=3.3V Figure 8. Isolation, Tx-Tx, +25°C

Figure 7. Isolation, Tx-Rx, VDD=3.3V Figure 9. Isolation, Tx-Rx, +25°C

Not for new designs

Product Specification

PE42650A

Page 6 of 11

Figure 10. Tx Insertion Loss, VDD=3.3V Figure 13. Tx Insertion Loss, +25°C

Figure 11. Rx Insertion Lo ss

Un-Attenuated, VDD=3.3V Figure 14. Rx Insertion Lo ss

Un-Attenuated, +25°C

Figure 15. Rx Insertion Lo ss

Attenuated, +25°C

Figure 12. Rx Insertion Lo ss

Attenuated, VDD=3.3V

Not for new designs

Product Specification

PE42650A

Page 7 of 11

Figure 18. Re turn Loss, +25°C Figure 16. Return Loss, VDD=3.3 V

Figure 17. Tx Return Loss, VDD=3.3V Figure 19. Tx Return Loss, +25°C

Not for new designs

Product Specification

PE42650A

Page 8 of 11

Figure 20. Rx Return Loss

Attenuated, VDD=3.3V Figure 22. Rx Return Loss

Attenuated, +25°C

Figure 21. Rx Return Loss

Un-Attenuated, VDD=3.3V Figure 23. Rx Return Loss

Un-Attenuated, +25°C

Not for new designs

Product Specification

PE42650A

Page 9 of 11

Figure 24. Power Dissip ation

Figure 25. Maximum Junction Temperature

Thermal Data

Though the insertion loss for this part is very low,

when handling high power RF signals, the part can

get quite hot.

Figure 24 shows the estimated power dissipation for

a given incident RF power level. Multiple curves are

presented to show the effect of poor VSWR

conditions. VSWR conditions that present short

circuit loads to the part can cause significantly more

power dissipation than with proper matching.

Figure 25 shows the estimated maximum junction

temperature of the part for similar conditions.

Note that both of these charts assume that the case

(GND slug) temperature is held at 85C. Special

consideration needs to be made in the design of the

PCB to properly dissipate the heat away from the

part and maintain the 85C maximum case

temperature. It is recommended to use best design

practices for high power QFN packages: multi-layer

PCBs with thermal vias in a thermal pad soldered to

the slug of the package. Special care also needs to

be made to alleviate solder voiding under the part.

Table 6 . Theta JC

Parameter Min Typ Max Units

Theta JC (+85°C) 15 C/W

0.0

0.5

1. 0

1. 5

2.0

2.5

3.0

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

RF Power (dBm)

Power Dissipated (W)

1: 1 V SWR (50 Ohm Load)

2: 1 V SWR (25 Ohm Load)

8:1 VSWR (6. 25 Ohm Load)

20:1 VSWR (2.5 Ohm Load)

INF:1 VSWR (0 Ohm Load)

Rel i abi l i ty Li mi t

85

90

95

10 0

10 5

110

115

12 0

12 5

13 0

13 5

14 0

14 5

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

RF Pow er (dBm)

Max Junction Temperature (C)

1: 1 V SWR ( 50 Ohm Load)

2: 1 V SWR ( 25 Ohm Load)

8:1 VSWR (6.25 Ohm Load)

20:1 VSWR (2.5 Ohm Load)

I NF:1 VSWR (0 Ohm Load)

Reliabilit

y

Li mi t

Not for new designs

Product Specification

PE42650A

Page 10 of 11

Table 7. Ordering Information

Figure 26. Package Drawing

Figure 27. Tap e and Reel Specs

Note: Not for electrical connection.

Corner detai l is ti ed to pad dl e and

shou ld not be is ol ated on PCB boar d.

See Note

below

Or der Code Par t Marking Description Package Shi pping Method

PE42650AMLI-Z 42650A Parts on Tape and Reel Green 32-lead 5x5mm QFN 3000 units / T&R

PE42650AMLI 42650A Parts in Tubes or Cut Tape Green 32-lead 5x5mm QFN 73 units / Tube

EK42650A-01 42650A Evaluation Kit Evaluation Kit 1 / Box

Device Orientation in Tape

Top of

Device

Pin 1

Tape Feed Dire c tion

Not for new designs

Product Specification

PE42650A

Page 11 of 11

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Q uatre Vent s

F-92380 Garches , France

Tel: +33-1-4741-9173

Fax : +33-1 -4741 -917 3

For a list of representatives in your area, please r efer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The dat a

sheet contains design target specificat ions for pr oduct

development. Specif ications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminar y data. Additional data

may be added at a later date. Peregrine reserves t he right

to change specifications at any time without notice in order

to supply t he best possible product.

Product Specification

The data sheet con tains final data. In the event Peregrine

dec ide s to cha nge the spe c ific ations, Pereg rine will not ify

customers of t he intended changes by is s u ing a DCN

(Document Change Notice).

The information in this data sheet is believed t o be reliable.

Howeve r, Peregrine assume s no liabilit y for the use of this

information. Use shall be entir ely at the user’s own risk.

No patent rights or licenses to any circuits descr ibed in t his

data sheet are implied or granted to any third party.

Peregrine’s pr oducts are not designed or int ended for use in

devices or systems intended for surgical implant, or in other

applications intended t o support or sustain life, or in any

application in which the failure of t he Per egrine product could

create a situation in which personal injury or death might occur.

Peregr ine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The Peregrine name, logo, and UTSi are registered t r ademarks

and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks

of Peregrine Semiconductor Corp.

High-Reliability and Defense Products

Americas

San Diego, CA, USA

Phone: 858- 731-9475

Fax: 848-731-9499

Europe/Asia-Pacific

Aix-En-Provence Cedex 3, France

Phone: +33- 4- 4239-3361

Fax: +33-4-4239-7227

Peregri ne Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, 210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-943 Sout h Korea

Tel: +82-31-728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teiko k u Hote l Tower 10B-6

1- 1-1 Uchisa iwai-c ho, Chiy o da- k u

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Not for new designs