PRELIMINARY
FEMTOCLOCKSTM
SAS/SATA CLOCK GENERATOR
ICS844441I
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 1
ICS844441AGI REV. A JULY 17, 2008
General Description
The ICS844441I is a low jitter, high performance
clock generator and a member of the FemtoClocks™
family of silicon timing products. The ICS844441I is
designed for use in applications using the SAS and
SATA interconnect. The ICS844441I uses an
external, 25MHz, parallel resonant crystal to generate four
selectable output frequencies: 75MHz, 100MHz, 150MHz, and
300MHz. This silicon based approach provides excellent
frequency stability and reliability. The ICS844441I features down
and center spread spectrum (SSC) clocking techniques.
Applications
•SAS/SATA Host Bus Adapters
•SATA Port Multipliers
•SAS I/O Controllers
•TapeDrive and HDD Array Controllers
•SAS Edge and Fanout Expanders
•HDDs and TapeDrives
•Disk Storage Enterprise
Features
•Designed for use in SAS, SAS-2, and SATA systems
•Center (±0.25%) Spread Spectrum Clocking (SSC)
•Down (-0.23% or -0.5%) SSC
•Better frequency stability than SAW oscillators
•One differential 2.5V LVDS output
•Crystal oscillator interface designed for 25MHz
(CL = 18pF) frequency
•External fundamental crystal frequency ensures high reliability
and low aging
•Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
•Output frequency is tunable with external capacitors
•RMS phase jitter: 1.33ps (typical)
•2.5V operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
Block Diagrams
FemtoClock™
PLL
OSC
nPLL_SEL
1
0
25MHz
XTAL
XTAL_IN
XTAL_OUT
00 = 75MHz
01 = 100MHz
10 = 150MHz (default)
11 = 300MHz
Q
nQ
SSC_SEL(1:0)
F_SEL(1:0)
Clock Output
Control Logic
16-Lead TSSOP
FemtoClock™
PLL
OSC
25MHz
XTAL
XTAL_IN
XTAL_OUT
00 = SSC Off
01 = 0.5% Down-spread
10 = 0.23% Down-spread
11 = 0.5% Center-spread
Q
nQ
SSC_SEL(1:0) SSC Output
Control Logic
8-Lead SOIC
Pulldown
Pullup:Pulldown
Pulldown:Pulldown
Pulldown:Pulldown
Pin Assignment
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
SSC_SEL0
XTAL_IN
XTAL_OUT
GND F_SEL1
nPLL_SEL
nQ
Q
VDD
F_SEL0
VDD
SSC_SEL1
GND
nc
nc
ICS844441I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
1
2
3
4
8
7
6
5VDD
XTAL_OUT
XTAL_IN
SSC_SEL0
GND
Q
nQ
SSC_SEL1
ICS844441I
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 2
ICS844441AGI REV. A JULY 17, 2008
Table 1. Pin Descriptions
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. SSC_SEL[1:0] Function Table Table 3B. F_SEL[1:0] Function Table
Name Type Description
XTAL_OUT,
XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC_SEL0,
SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels.
Q, nQ Output Differential clock outputs. LVDS interface levels.
GND Power Power supply ground.
VDD Power Power supply pin.
nc Unused No connect.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLDOWN Input Pulldown Resistor 51 kΩ
RPULLUP Input Pullup Resistor 51 kΩ
Inputs
ModeSSC_SEL1 SSC_SEL0
0 (default) 0 (default) SSC Off
0 1 0.5% Down-spread
1 0 0.23% Down-spread
1 1 0.5% Center-spread
Inputs Output Frequency
(MHz)F_SEL1 F_SEL0
00 75
01 100
1 (default) 0 (default) 150
11 300
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 3
ICS844441AGI REV. A JULY 17, 2008
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics,VDD = 2.5V ± 5%, TA = -40°C to 85°C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
16 Lead TSSOP
8 Lead SOIC
92.4°C/W (0 mps)
96.0°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Power Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 45 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 1.7 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.7 V
IIH
Input
High Current
F_SEL1 VDD = VIN = 2.5V 5 µA
SSC_SEL[0:1],
F_SEL0, nPLL_SEL VDD = VIN = 2.5V 150 µA
IIL
Input
Low Current
F_SEL1 VDD = 2.5V, VIN = 0V -150 µA
SSC_SEL[0:1],
F_SEL0, nPLL_SEL VDD = 2.5V, VIN = 0V -5 µA
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 4
ICS844441AGI REV. A JULY 17, 2008
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
Table 4C. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Table 4D. Crystal Characteristics
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Using a 25MHz, 18pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plot.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 350 mV
∆VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.25 V
∆VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50 Ohm
Shunt Capacitance 7pF
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency
F_SEL(1:0) = 00 75 MHz
F_SEL(1:0) = 01 100 MHz
F_SEL(1:0) = 10 150 MHz
F_SEL(1:0) = 11 300 MHz
tjit(Ø) RMS Phase Jitter
(Random); NOTE 1
75MHz,
Integration Range: 12kHz – 20MHz 1.33 ps
100MHz,
Integration Range: 12kHz – 20MHz 1.53 ps
150MHz,
Integration Range: 12kHz – 20MHz ps
300MHz,
Integration Range: 12kHz – 20MHz ps
tR / tFOutput Rise/Fall Time 20% to 80% 400 ps
odc Output Duty Cycle 50 %
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 5
ICS844441AGI REV. A JULY 17, 2008
Typical Phase Noise at 100MHz
NOTE: Measured on Aeroflex PN9000
Noise Power dBc
Hz
Raw Phase Noise Data
➝
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.53ps (typical)
Offset Frequency (Hz)
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 6
ICS844441AGI REV. A JULY 17, 2008
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
Parameter Measurement Information
2.5V LVDS Output Load AC Test Circuit
Output Rise/Fall Time
Offset Voltage Setup
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
SCOPE
Qx
nQx
LVDS
2.5V±5%
POWER SUPPLY
+–
Float GND
VDD
V
OS
20%
80% 80%
20%
t
R
t
F
V
OD
GND
nQ
Q
out
out
LVDS
DC Input
➤
➤
➤
VOS/∆ VOS
VDD
Phase Noise Mas
k
Offset Frequency
f1f2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
nQ
Q
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 7
ICS844441AGI REV. A JULY 17, 2008
Application Information
Crystal Input Interface
The ICS844441I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
Figure 1. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27p
C2
27p
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50Ω0.1µf
R1
R2
V
CC
V
CC
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 8
ICS844441AGI REV. A JULY 17, 2008
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
2.5V LVDS Driver Termination
Figure 3 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LVDS driver,
it is recommended to terminate the unused outputs.
Figure 3. Typical LVDS Driver Termination
2.5V
LVDS Driver
R1
100Ω
–
+
2.5V 50Ω
50Ω
100Ω Differential Transmission Line
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 9
ICS844441AGI REV. A JULY 17, 2008
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844441I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844441I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 45mA = 118.125mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.118W * 96°C/W = 96.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (single layer or
multi-layer).
Table 6A. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 85.9°C/W
θJA vs. Air Flow
Linear Feet per Second 0200500
Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 10
ICS844441AGI REV. A JULY 17, 2008
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
Reliability Information
Table 7A. θJA vs. Air Flow Table for a 16 Lead TSSOP
Table 7B. θJA vs. Air Flow Table for a 8 Lead SOIC
Transistor Count
The transistor count for ICS844441I is: 6431
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 85.9°C/W
θJA vs. Air Flow
Linear Feet per Second 0200500
Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 11
ICS844441AGI REV. A JULY 17, 2008
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 8A. Package Dimensions for 16 Lead TSSOP
Reference Document: JEDEC Publication 95, MO-153
Package Outline - M Suffix for 8 Lead SOIC
Table 8B. Package Dimensions for 8 Lead SOIC
Reference Document: JEDEC Publication 95, MS-012
All Dimensions in Millimeters
Symbol Minimum Maximum
N16
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D4.90 5.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
α0° 8°
aaa 0.10
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.35 1.75
A1 0.10 0.25
B0.33 0.51
C0.19 0.25
D4.80 5.00
E3.80 4.00
e1.27 Basic
H5.80 6.20
h0.25 0.50
L0.40 1.27
α0° 8°
IDT™ / ICS™
SAS/SATA CLOCK GENERATOR 12
ICS844441AGI REV. A JULY 17, 2008
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
Ordering Information
Table 9. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Table 10. Additional Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
844441AGI TBD 16 Lead TSSOP Tube -40°C to 85°C
844441AGIT TBD 16 Lead TSSOP 2500 Tape & Reel -40°C to 85°C
844441AGILF 44441AIL 16 Lead “Lead-Free” TSSOP Tube -40°C to 85°C
844441AGILFT 44441AIL 16 Lead “Lead-Free” TSSOP 2500 Tape & Reel -40°C to 85°C
844441AMI-75 TBD 8 Lead SOIC Tube -40°C to 85°C
844441AMI-75T TBD 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-75LF TBD 8 Lead “Lead-Free” SOIC Tube -40°C to 85°C
844441AMI-75LFT TBD 8 Lead “Lead-Free” SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-100 TBD 8 Lead SOIC Tube -40°C to 85°C
844441AMI-100T TBD 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-100LF TBD 8 Lead “Lead-Free” SOIC Tube -40°C to 85°C
844441AMI-100LFT TBD 8 Lead “Lead-Free” SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-150 TBD 8 Lead SOIC Tube -40°C to 85°C
844441AMI-150T TBD 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-150LF TBD 8 Lead “Lead-Free” SOIC Tube -40°C to 85°C
844441AMI-150LFT TBD 8 Lead “Lead-Free” SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-300 TBD 8 Lead SOIC Tube -40°C to 85°C
844441AMI-300T TBD 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C
844441AMI-300LF TBD 8 Lead “Lead-Free” SOIC Tube -40°C to 85°C
844441AMI-300LFT TBD 8 Lead “Lead-Free” SOIC 2500 Tape & Reel -40°C to 85°C
Part/Order Number Package Output Frequency (MHz)
844441AGI 16 TSSOP 75, 100, 150, 300
844441AMI-75 8 SOIC 75
844441AMI-100 8 SOIC 100
844441AMI-150 8 SOIC 150
844441AMI-300 8 SOIC 300
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR PRELIMINARY
www.IDT.com
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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Fax: 408-284-2775
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Technical Support
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+480-763-2056
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Contact Information:
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