DM74LS126ANX - Fairchild Semiconductor

August 1986

Revised March 2000

DM74LS126A Quad 3-STATE Buffer

DM74LS126A

Quad 3-STATE Buffer

General Descript ion

This device contains four independent gates each of which

performs a non-inverti ng buffer fun ction. The o utputs have

the 3-STATE feature. When enabled, the outputs exhibit

the low impe dance char acteristics of a sta ndard LS output

with additional drive capability to permit the driving of bus

lines without external resistors. When disabled, both the

output transistors are turned OFF presenting a high-imped-

ance state to the bus line. Thus th e output will act neith er

as a sign ific an t loa d n or as a d river. To min imi ze the po ssi-

bility that two out puts will att empt t o ta ke a co mm on bus to

opposite logic levels, the disable time is shorter than the

enable time of the outputs.

Ordering Code:

Devices also available in Tape and Reel. Speci fy by appending the s uffix let t er “X” to the orderin g c ode.

Connection Diagram Function Table

Y = A

H = HIGH Lo gic Level

L = LOW Lo gic Level

X = Either LOW or HIGH Logic Level

Hi-Z = 3-STATE (Outputs are disabled)

Order Number Package Number Package Description

DM74LS126AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS126AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Output

ACY

LHL

HHH

X L Hi-Z

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DM74LS126A

Absolute Maximum Ratings (N o te 1) Note 1: Th e “Absolut e Maximum R atings” are th ose values be yond which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at t he abso lute maximu m rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typic als are at VCC = 5V, TA = 25°C.

Note 3: Not more than one o utput should be shorted at a time, and the duration sh ould not exceed one second.

Switching Characteri stics

VCC = 5V, TA = 25°C

Note 4: CL = 5pF.

Supply Voltage 7V

Input Vo ltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −2.6 mA

IOL LOW Level Output Current 24 mA

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, I OH = Max 2.4 V

Output Voltage VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 12 mA, VCC = Min 0.25 0.4

IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA

IIH HIGH Level Input Curre nt VCC = Max, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOZH Off-State Output Current with VCC = Max, VO = 2.4V 20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.4V −20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICC Supply Current VCC = Max 12 22 mA

RL = 667Ω

Symbol Parameter CL = 50 pF CL = 150 pF Units

Min Max Min Max

tPLH Propagation Delay Time LOW-to-HIGH Level Output 15 21 ns

tPHL Propagation Delay Time HIGH-to-LOW Level Output 18 22 ns

tPZH Output Enable Time to HIGH Level Output 30 36 ns

tPZL Output Enable Time to LOW Level Output 30 42 ns

tPHZ Output Disable Time from HIGH Level Output (Note 4) 25 ns

tPLZ Output Disable Time from LOW Level Output (Note 4) 25 ns

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DM74LS126A

Physical Dim ensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

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DM74LS126A Quad 3-STATE Buffer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of any c ircuitry described, no circuit pate nt licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.