3 MSPS,10-/12-Bit
ADCs in 8-Lead TSOT
AD7273/AD7274
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Throughput rate: 3 MSPS
Specified for VDD of 2.35 V to 3.6 V
Power consumption
11.4 mW at 3 MSPS with 3 V supplies
Wide input bandwidth
70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typ
8-lead TSOT package
8-lead MSOP package
GENERAL DESCRIPTION
The AD7273/AD7274 are 10-/12-bit, high speed, low power,
successive approximation ADCs, respectively. The parts operate
from a single 2.35 V to 3.6 V power supply and feature
throughput rates of up to 3 MSPS. Each part contains a low
noise, wide bandwidth track-and-hold amplifier that can handle
input frequencies in excess of 55 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. The conversion rate is determined by the SCLK. There
are no pipeline delays associated with these parts.
The AD7273/AD7274 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the parts is applied externally and can be in
the range of 1.4 V to VDD. This allows the widest dynamic input
range to the ADC.
FUNCTIONAL BLOCK DIAGRAM
T/H
CONTROL
LOGIC
10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
DGND
V
DD
AD7273/AD7274
V
IN
AGND
SCLK
SDATA
CS
V
REF
04973-001
Figure 1.
Table 1.
Part Number Resolution Package
AD7273110 8-lead MSOP 8-Lead TSOT
AD7274112 8-lead MSOP 8-Lead TSOT
AD7276 12 8-lead MSOP 6-Lead TSOT
AD7277 10 8-lead MSOP 6-Lead TSOT
AD7278 8 8-lead MSOP 6-Lead TSOT
1 Parts contain external reference pin.
PRODUCT HIGHLIGHTS
1. 3 MSPS ADCs in an 8-lead TSOT package.
2. High throughput with low power consumption.
3. Flexible power/serial clock speed management.
Allows maximum power efficiency at low throughput rates.
4. Reference can be driven up to the power supply.
5. No pipeline delay.
6. The parts feature a standard successive approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
AD7273/AD7274
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7274 Specifications................................................................. 3
AD7273 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Timing Examples.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Ter mi nol o g y .................................................................................... 14
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
ADC Transfer Function............................................................. 15
Typical Connection Diagram ....................................................... 16
Analog Input ............................................................................... 16
Digital Inputs .............................................................................. 16
Modes of Operation ....................................................................... 17
Normal Mode.............................................................................. 17
Partial Power-Down Mode ....................................................... 17
Full Power-Down Mode ............................................................ 17
Power-Up Times......................................................................... 18
Power vs. Throughput Rate....................................................... 20
Serial Interface ................................................................................ 21
Microprocessor Interfacing....................................................... 23
Application Hints ........................................................................... 24
Grounding and Layout .............................................................. 24
Evaluating the AD7273/AD7274 Performance......................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
9/05—Revision 0: Initial Version
AD7273/AD7274
Rev. 0 | Page 3 of 28
SPECIFICATIONS
AD7274 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter B Grade1Unit2Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 1 MHz sine wave
Signal-to-Noise + Distortion (SINAD)368 dB min
Signal-to-Noise Ratio (SNR) 69.5 dB min
Total Harmonic Distortion (THD)3 −73 dB max
−78 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −80 dB typ
Intermodulation Distortion (IMD)
Second-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz
Third-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz
Aperture Delay 5 ns typ
Aperture Jitter 18 ps typ
Full Power Bandwidth 55 MHz typ @ 3 dB
8 MHz typ @ 0.1 dB
Power Supply Rejection Ratio (PSRR) 82 dB typ
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity3±1 LSB max
Differential Nonlinearity3±1 LSB max Guaranteed no missed codes to 12 bits
Offset Error3±3 LSB max
Gain Error3±3.5 LSB max
Total Unadjusted Error (TUE)3±3.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to VREF V
DC Leakage Current ±1 μA max −40°C to +85°C
±5.5 μA max 85°C to 125°C
Input Capacitance 42 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT
VREF Input Voltage Range 1.4 to VDD V min/V max
DC leakage Current ±1 μA max
Input Capacitance 20 pF typ
Input Impedance 32 Ω typ
LOGIC INPUTS
Input High Voltage, VINH 1.7 V min 2.35 V ≤ VDD ≤ 2.7 V
2 V min 2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VINL 0.7 V max 2.35 V ≤ VDD < 2.7 V
0.8 V max 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN42 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
Output Low Voltage, VOL 0.2 V max ISINK = 200 μA
Floating-State Leakage Current ±2.5 μA max
Floating-State Output Capacitance44.5 pF max
Output Coding Straight (natural) binary
AD7273/AD7274
Rev. 0 | Page 4 of 28
Parameter B Grade1Unit2Test Conditions/Comments
CONVERSION RATE
Conversion Time 291 ns max 14 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Time360 ns max
Throughput Rate 3 MSPS max See the Serial Interface section
POWER RQUIREMENTS
VDD 2.35/3.6 V min/V max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 1 mA typ VDD = 3 V, SCLK on or off
Normal Mode (Operational) 5 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
3.8 mA typ VDD = 3 V
Partial Power-Down Mode (Static) 34 μA typ
Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA
10 μA max 85°C to 125°C
Power Dissipation5
Normal Mode (Operational) 18 mW max VDD = 3.6 V , fSAMPLE = 3 MSPS
11.4 mW typ VDD = 3 V
Partial Power-Down 102 μW max VDD = 3 V
Full Power-Down 7.2 μW max VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
AD7273/AD7274
Rev. 0 | Page 5 of 28
AD7273 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter B Grade1Unit2Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 1 MHz sine wave
Signal-to-Noise + Distortion (SINAD)361 dB min
Total Harmonic Distortion (THD)3 −72 dB max
−77 dB typ
Peak Harmonic or Spurious Noise (SFDR)3 −80 dB typ
Intermodulation Distortion (IMD)
Second-Order Terms −81 dB typ fa = 1 MHz, fb = 0.97 MHz
Third-Order Terms −81 dB typ fa = 1 MHz, fb = 0.97 MHz
Aperture Delay 5 ns typ
Aperture Jitter 18 ps typ
Full Power Bandwidth 74 MHz typ @ 3 dB
10 MHz typ @ 0.1 dB
Power Supply Rejection Ratio (PSRR) 82 dB typ
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity3±0.5 LSB max
Differential Nonlinearity3±0.5 LSB max Guaranteed no missed codes to 10 bits
Offset Error3±1 LSB max
Gain Error3±1.5 LSB max
Total Unadjusted Error (TUE)3±2.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to VREF V
DC Leakage Current ±1 μA max −40°C to +85°C
±5.5 μA max 85°C to 125°C
Input Capacitance 42 pF typ When in track
10 pF typ When in hold
REFERENCE INPUT
VREF Input Voltage Range 1.4 to VDD V min/V max
DC leakage Current ±1 μA max
Input Capacitance 20 pF typ
Input Impedance 32 Ω typ
LOGIC INPUTS
Input High Voltage, VINH 1.7 V min 2.35 V ≤ VDD ≤ 2.7 V
2 V min 2.7 V < VDD ≤ 3.6 V
Input Low Voltage, VIN 0.7 V max 2.35 V ≤ VDD< 2.7 V
0.8 V max 2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN42 pF max
LOGIC OUTPUTS
Output High Voltage, VOH VDD − 0.2 V min ISOURCE = 200 μA; VDD = 2.35 V to 3.6 V
Output Low Voltage, VOL 0.2 V max ISINK = 200 μA
Floating-State Leakage Current ±2.5 μA max
Floating-State Output Capacitance44.5 pF max
Output Coding Straight (natural) binary
CONVERSION RATE
Conversion Time 250 ns max 12 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Time360 ns max
Throughput Rate 3.45 MSPS max See the Serial Interface section
AD7273/AD7274
Rev. 0 | Page 6 of 28
Parameter B Grade1Unit2Test Conditions/Comments
POWER RQUIREMENTS
VDD 2.35/3.6 V min/V max
IDD Digital I/Ps = 0 V or VDD
Normal Mode (Static) 0.6 mA typ VDD = 3 V, SCLK on or off
Normal Mode (Operational) 5 mA max VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
3.2 mA typ VDD = 3 V
Partial Power-Down Mode (Static) 34 μA typ
Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA
10 μA max 85°C to 125°C
Power Dissipation5
Normal Mode (Operational) 18 mW max VDD = 3.6 V , fSAMPLE = 3 MSPS
9.6 mW typ VDD = 3 V
Partial Power-Down 102 μW max VDD = 3 V
Full Power-Down 7.2 μW max VDD = 3.6 V, −40°C to +85°C
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
AD7273/AD7274
Rev. 0 | Page 7 of 28
TIMING SPECIFICATIONS
VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals
are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 4.
Parameter
Limit at TMIN, TMAX
AD7273/AD7274 Unit Description
fSCLK2500 kHz min3
48 MHz max
tCONVERT 14 × tSCLK AD7274
12 × tSCLK AD7273
tQUIET 4 ns min
Minimum quiet time required between bus relinquish and start of
next conversion
t13 ns min
Minimum CS pulse width
t26 ns min
CS to SCLK setup time
t344 ns max
Delay from CS until SDATA three-state disabled
t4415 ns max Data access time after SCLK falling edge
t50.4 tSCLK ns min SCLK low pulse width
t60.4 tSCLK ns min SCLK high pulse width
t745 ns min SCLK to data valid hold time
t814 ns max SCLK falling edge to SDATA three-state
5 ns min SCLK falling edge to SDATA three-state
t94.2 ns max
CS rising edge to SDATA three-state
tPOWER-UP51 μs max Power-up time from full power-down
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Minimum fSCLK at which specifications are guaranteed.
4 The time required for the output to cross the VIH or VIL voltage.
5 See the Power-Up Times section
SCLK
V
IH
V
IL
SDATA
t
4
04973-002
Figure 2. Access Time After SCLK Falling Edge
SCLK
V
IH
V
IL
SDATA
t
7
04973-003
Figure 3. Hold Time After SCLK Falling Edge
SCLK
1.4V
SDATA
t8
04973-004
Figure 4. SCLK Falling Edge SDATA Three-State
AD7273/AD7274
Rev. 0 | Page 8 of 28
TIMING EXAMPLES
For the AD7274, if CS is brought high during the 14th SCLK
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If CS is brought high during the 16th
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and
tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ.
Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET,
where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET,
satisfying the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and
tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) +
t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
12345 13141516
SCLK
S
DAT
A
THREE-STATETHREE-
STATE TWO LEADING
ZEROS TWO TRAILING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0 ZERO ZERO
t
6
t
5
t
8
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-005
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
12345 1314
SCLK
S
DAT
A
THREE-STATETHREE-
STATE TWO LEADING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0
t
6
t
9
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-006
t
5
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
12345 1312 14 15 16
SCLK
B
CS
t
CONVERT
t
2
t
8
t
1
t
QUIET
1/THROUGHPUT
12.5(1/f
SCLK
)
t
ACQUISITION
04973-007
Figure 7. Serial Interface Timing 16 SCLK Cycle
AD7273/AD7274
Rev. 0 | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameters Ratings
VDD to AGND/DGND −0.3 V to +6 V
Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +6 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range
Commercial (B Grade) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
6-Lead TSOT Package
θJA Thermal Impedance 230°C/W
θJC Thermal Impedance 92°C/W
8-Lead MSOP Package
θJA Thermal Impedance 205.9°C/W
θJC Thermal Impedance 43.74°C/W
Lead Temperature Soldering
Reflow (10 to 30 sec) 255°C
Lead Temperature Soldering
Reflow (10 to 30 sec) 260°C
ESD 1.5 kV
1 Transient currents of up to 100 mA cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7273/AD7274
Rev. 0 | Page 10 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD 1
SDATA
2
CS
3
AGND
4
V
IN
8
DGND
7
SCLK
6
V
REF
5
AD7273/
AD7274
TOP VIEW
(Not to Scale)
04973-008
Figure 8. 8-Lead MSOP Pin Configuration
V
DD
V
IN
1
SDATA
2
3
4
8
7
6
5
DGND
AGND
CS
SCLK
V
REF
AD7273/
AD7274
TOP VIEW
(Not to Scale)
04973-009
Figure 9. 8-Lead TSOT Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
MSOP TSOT Mnemonic Description
1 1 VDD Power Supply Input. The VDD range for the AD7273/AD7274 is from 2.35 V to 3.6 V.
2 2 SDATA Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from
the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing
zeros, provided MSB first. The data stream from the AD7273 consists of two leading zeros followed
by the 10 bits of conversion data and four trailing zeros, provided MSB first.
3 7 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversion on
the AD7273/AD7274 and framing the serial data transfer.
4 8 AGND Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog signals
and any external reference signal should be referred to this AGND voltage.
5 5 VREF Voltage Reference Input. This pin becomes the reference voltage input. An external reference should
be applied at this pin. The external reference input range is 1.4 V to VDD. A 10 μF capacitor should be
tied between this pin and AGND.
6 6 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the conversion process of AD7273/AD7274.
7 3 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7273/AD7274. The DGND and
AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even
on a transient basis.
8 4 VIN Analog Input. Single-ended analog input channel. The input range is 0 to VREF.
AD7273/AD7274
Rev. 0 | Page 11 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–20
–40
–60
–80
–100
–120
0
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
FREQUENCY (kHz)
SNR (dB)
100
16384 POINT FFT
F
SAMPLE
= 3MSPS
F
IN
= 1MHz
SINAD = 71.05
THD = –80.9
SFDR = –82.2
04973-010
Figure 10. AD7274 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz
–20
–40
–60
–80
–100
–120
0
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
FREQUENCY (kHz)
SNR (dB)
100
16384 POINT FFT
FSAMPLE = 3MSPS
FIN = 1MHz
SINAD = 66.56
THD = –77.4
SFDR = –78.2
04973-011
Figure 11. AD7273 Dynamic Performance at 3 MSP, Input Tone = 1 MHz
72.2
72.0
71.0
70.8
70.6
70.4
71.2
70.2
70.0
69.8
69.6
69.4
69.2
71.4
71.6
71.8
69.0
100 15001000
INPUT FREQUENCY (kHz)
SINAD (dB)
V
DD
= 3V
V
DD
= 3.6V
F
SAMPLE
= 3MSPS
04973-012
V
DD
= 2.5V
Figure 12. AD7274 SINAD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
72.2
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
70.2
100 15001000
INPUT FREQUENCY (kHz)
SNR (dB)
V
DD
= 3V
V
DD
= 2.5V
V
DD
= 3.6V
F
SAMPLE
= 3MSPS
04973-013
Figure 13. AD7274 SNR vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
100 15001000
INPUT FREQUENCY (kHz)
THD (dB)
V
DD
= 2.5V
V
DD
= 3V
V
DD
= 3.6V
04973-014
Figure 14. THD vs. Analog Input Frequency at 3 MSPS
for Various Supply Voltages, SCLK Frequency = 48 MHz
–40
–50
–60
–70
–80
–90
100 15001000
INPUT FREQUENCY (kHz)
THD (dB)
R
IN
= 100
Ω
R
IN
= 0
Ω
R
IN
= 10
Ω
04973-015
Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Source
Impedance, SCLK Frequency = 48 MHz, Supply Voltage = 3 V
AD7273/AD7274
Rev. 0 | Page 12 of 28
–70
–11003000
SUPPLY RIPPLE FREQUENCY (MHz)
PSRR (dB)
–80
–90
–100
500 1000 1500 2000 2500
100mV p-p SINE WAVE ON AV
DD
NO DECOUPLING
04973-016
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple
Frequency Without Decoupling
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.00 4000350030002500200015001000500 CODES
INL ERROR (LSB)
V
DD
= 3V
04973-017
Figure 17. AD7274 INL Performance
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.00 4000350030002500200015001000500 CODES
DNL ERROR (LSB)
V
DD
= 3V
04973-018
Figure 18. AD7274 DNL Performance
1.0
–1.0
1.4 3.6
REFERENCE VOLTAGE (V)
INL ERROR (LSB)
04973-019
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
POSITIVE INL
NEGATIVE INL
Figure 19. Change in INL vs. Reference Voltage, 3 V Supply
1.0
–1.0
1.4 3.6
REFERENCE VOLTAGE (V)
DNL ERROR (LSB)
04973-020
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
POSITIVE DNL
NEGATIVE DNL
Figure 20. Change in DNL vs. Reference Voltage, 3 V Supply
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.6005040302010 SCLK FREQUENCY (MHz)
MAX CURRENT (mA)
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 3V
04973-021
Figure 21. Maximum Current vs. Supply Voltage
for Different SCLK Frequencies
AD7273/AD7274
Rev. 0 | Page 13 of 28
18000
02045 CODE
NUMBER OF CODES
16000
14000
12000
10000
8000
6000
4000
2000
2046 2047 2048 2049 2050
30,000 CODES
04973-022
Figure 22. Histogram of Codes for 30,000 Samples
12.0
10.0
1.4 3.6
V
REF
(V)
EFFECTIVE NUMBERS OF BITS
04973-023
11.5
11.0
10.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Figure 23. ENOB/SINAD vs. Reference Voltage
AD7273/AD7274
Rev. 0 | Page 14 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7273/
AD7274, the endpoints of the transfer function are zero scale at
0.5 LSB below the first code transition and full scale at 0.5 LSB
above the last code transition.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00 . . . 000) to (00 . . .
001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, that is, VREF – 1.5 LSB, after
adjusting for the offset error.
Tota l Unadjuste d Error ( TUE)
A comprehensive specification that includes gain, linearity, and
offset errors.
Track-and-Hold Acquisition Time
The time required for the output of the track-and-hold amplifier
to reach its final value, within ±0.5 LSB, after the end of the
conversion. See the Serial Interface section for more details.
Signal-to-Noise + Distortion Ratio (SINAD)
The measured ratio of signal to noise plus distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), including
harmonics but excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the
more levels, the smaller the quantization noise. For an ideal N-bit
converter, the SINAD is
dB76.102.6 += NSINAD
According to this equation, the SINAD is 74 dB for a 12-bit
converter and 62 dB for a 10-bit converter. However, various
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. It is
defined as:
()
1
2
6
2
5
2
4
2
3
2
2
log20dB V
VVVVV
THD ++++
=
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f /2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
for ADCs with harmonics buried in the noise floor, it is deter-
mined by a noise peak.
S
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m and
n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second-
order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7273/AD7274 are tested using the CCIF standard in
which two input frequencies are used (see fa and fb in the
Specifications section). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC V supply of frequency f .
DD S
(
)
(
)
S
PfPfPSRR log10dB
=
where Pf is the power at frequency f in the ADC output; PfS is
the power at frequency fS coupled onto the ADC VDD supply.
Aperture Delay
The measured interval between the leading edge of the sampling
clock and the point at which the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the sample is taken.
AD7273/AD7274
Rev. 0 | Page 15 of 28
CIRCUIT INFORMATION
The AD7273/AD7274 are high speed, low power, 10-/12-bit,
single supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 48 MHz clock.
The AD7273/AD7274 provide the user with an on-chip track-
and-hold ADC and a serial interface housed in an 8-lead TSOT
or an 8-lead MSOP package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and provides the clock
source for the successive approximation ADC. The analog input
range is 0 to VREF. An external reference in the range of 1.4 V to
VDD is required by the ADC.
The AD7273/AD7274 also feature a power-down option to save
power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7273/AD7274 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 and Figure 25
show simplified schematics of the ADC. Figure 24 shows the
ADC during its acquisition phase, where SW2 is closed, SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on VIN.
COMPARATOR
ACQUISITION
PHASE
V
DD
/2
SW2
V
IN
SAMPLING
CAPACITOR
AGND
A
SW1
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
04973-024
Figure 24. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see Figure 25). The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 26 shows the ADC transfer function.
COMPARATOR
ACQUISITION
PHASE
V
DD
/2
SW2
V
IN
SAMPLING
CAPACITOR
AGND
A
SW1
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
04973-025
Figure 25. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight binary.
The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is VREF/4,096 for the AD7274 and VREF/1,024 for the
AD7273. The ideal transfer characteristic for the
AD7273/AD7274 is shown in Figure 26.
000...0000V
ADC CODE
ANALOG INPUT
111...111
000...001
111...000
011...111
111...110
000...010
1LSB = V
REF
/4096 (AD7274)
1LSB = V
REF
/1024 (AD7273)
+V
REF
– 1.5LSB0.5LSB
04973-026
Figure 26. AD7273/AD7274 Transfer Characteristic
AD7273/AD7274
Rev. 0 | Page 16 of 28
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7273/
AD7274. An external reference must be applied to the ADC.
This reference can be in the range of 1.4 V to VDD. A precision
reference, such as the REF19x family or the ADR421, can be
used to supply the reference voltage to the AD7273/AD7274.
The conversion result is output in a 16-bit word with two leading
zeros followed by the 12-bit or 10-bit result. The 12-bit result from
the AD7274 is followed by two trailing zeros, and the 10-bit result
from the AD7273 is followed by four trailing zeros.
Table 7 provides some typical performance data with various
references under the same setup conditions for the AD7274.
Table 7. AD7274 Performance (Various Voltage Reference IC)
Voltage Reference
AD7274 SNR Performance
1 MHz Input
AD780 @ 2.5 V 71.3 dB
AD780 @ 3 V 70.1 dB
REF195 70.9 dB
AD7273/
AD7274
V
DD
V
IN
SERIAL
INTERFACE
0V TO V
REF
INPUT
DSP/
μ
C/
μ
P
V
REF
AGND/DGND
SCLK
CS
SDATA
0.1
μ
F 10
μ
F
10pF 0.1
μ
F
2.5V
3.6V
SUPPLY
4.6 mA
REF195
04973-027
Figure 27. AD7273/AD7274 Typical Connection Diagram
ANALOG INPUT
Figure 28 shows an equivalent circuit of the analog input
structure of the AD7273/AD7274. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. Signals exceeding this value
cause these diodes to become forward biased and to start
conducting current into the substrate. These diodes can
conduct a maximum current of 10 mA without causing
irreversible damage to the part. Capacitor C1 in Figure 28 is
typically about 4 pF and can primarily be attributed to pin
capacitance. Resistor R1 is a lumped component made up of the
on resistance of a switch. This resistor is typically about 75 Ω.
Capacitor C2 is the ADC sampling capacitor and has a capacitance
of 32 pF typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
using a band-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADCs. This may necessitate the use
of an input buffer amplifier. The AD8021 op amp is compatible
with this device; however, the choice of the op amp is a function
of the particular application.
C1
4pF
C2
R1
CONVERSION PHASE–SWITCH OPEN
TRACK PHASE–SWITCH CLOSED
D1
D2
V
DD
V
IN
04973-028
Figure 28. Equivalent Analog Input Circuit
When no amplifier is used to drive the analog input, the source
impedance should be limited to a low value. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and perfor-
mance degrades. Figure 14 shows a graph of the THD vs. the
analog input frequency for different source impedances when
using a supply voltage of 3 V and sampling at a rate of 3 MSPS.
DIGITAL INPUTS
The digital inputs applied to the AD7273/AD7274 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs can be applied at up to 6 V and are
not restricted by the VDD + 0.3 V limit of the analog inputs. For
example, if the AD7273/AD7274 were operated with a VDD of
3 V, then 5 V logic levels could be used on the digital inputs.
However, it is important to note that the data output on SDATA
still has 3 V logic levels when VDD = 3 V. Another advantage of
SCLK and CS not being restricted by the VDD + 0.3 V limit is
that power supply sequencing issues are avoided. For example,
unlike with the analog inputs, with the digital inputs, if CS or
SCLK are applied before VDD, there is no risk of latch-up.
AD7273/AD7274
Rev. 0 | Page 17 of 28
MODES OF OPERATION
The mode of operation of the AD7273/AD7274 is selected by
controlling the logic state of the CS signal during a conversion.
There are three possible modes of operation: normal mode,
partial power-down mode, and full power-down mode. The
point at which CS is pulled high after the conversion is initiated
determines which power-down mode, if any, the device enters.
Similarly, if the device is already in power-down mode, CS can
control whether the device returns to normal operation or
remains in power-down mode. These modes of operation are
designed to provide flexible power management options, which
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance
because the AD7273/AD7274 remain fully powered at all times,
eliminating worry about power-up times. Figure 29 shows the
general diagram of the operation of the AD7273/AD7274 in
this mode.
The conversion is initiated on the falling edge of CS as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, CS must remain low until at least
10 SCLK falling edges elapse after the falling edge of CS. If CS is
brought high any time after the 10th SCLK falling, but before the
16th SCLK falling edge, the part remains powered up, but the
conversion is terminated, and SDATA goes back into three-state.
For the AD7274, a minimum of 14 serial clock cycles are
required to complete the conversion and access the complete
conversion result. For the AD7273, a minimum of 12 serial
clock cycles are required to complete the conversion and access
the complete conversion result.
CS can idle high until the next conversion or low until CS
returns high before the next conversion (effectively idling CS
low). Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the quiet
time, tQUIET, has elapsed by bringing CS low again.
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. An example of this is when either
the ADC is powered down between each conversion or a series
of conversions is performed at a high throughput rate and then
the ADC is powered down for a relatively long duration between
these bursts of several conversions.
When the AD7273/AD7274 are in partial power-down mode,
all analog circuitry is powered down except the bias generation
circuit.
To enter partial power-down mode, interrupt the conversion
process by bringing CS high between the second and 10th falling
edges of SCLK, as shown in Figure 30. Once CS is brought high
in this window of SCLKs, the part enters partial power-down
mode, the conversion that was initiated by the falling edge of
CS is terminated, and SDATA goes back into three-state. If CS
is brought high before the second SCLK falling edge, the part
remains in normal mode and does not power down. This prevents
accidental power-down due to glitches on the CS line.
To exit this mode of operation and power up the AD7274/
AD7273, perform a dummy conversion. On the falling edge of
CS, the device begins to power up and continues to power up as
long as CS is held low until after the falling edge of the 10th SCLK.
The device is fully powered up once 16 SCLKs elapse; valid data
results from the next conversion, as shown in Figure 31. If CS is
brought high before the 10th falling edge of SCLK, the AD7274/
AD7273 goes into full power-down mode. Therefore, although
the device may begin to power up on the falling edge of CS, it
powers down on the rising edge of CS as long as this occurs
before the 10th SCLK falling edge.
If the AD7273/AD7274 is already in partial power-down mode
and CS is brought high before the 10th falling edges of SCLK, the
device enters full power-down mode. For more information on
the power-up times associated with partial power-down mode
in various configurations, see the Power-Up Times section.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, because power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by
a long period of inactivity and thus power-down.
When the AD7273/AD7274 are in full power-down mode, all
analog circuitry is powered down. To enter full power-down
mode put the device into partial power-down mode by bringing
CS high between the second and 10th falling edges of SCLK. In
the next conversion cycle, interrupt the conversion process in
the way shown in Figure 32 by bringing CS high before the 10th
SCLK falling edge. Once CS is brought high in this window of
SCLKs, the part powers down completely. Note that it is not
necessary to complete 16 SCLKs once CS is brought high to enter
either of the power-down modes. Glitch protection is not
available when entering full power-down mode.
To exit full power-down mode and power up the AD7273/
AD7274 again, perform a dummy conversion, similar to when
powering up from partial power-down mode. On the falling
AD7273/AD7274
Rev. 0 | Page 18 of 28
edge of CS, the device begins to power up and continues to
power up until after the falling edge of the 10th SCLK as long as
CS is held low. The power-up time required must elapse before
a conversion can be initiated, as shown in Figure 33. See the
Power-Up Times section for the power-up times associated with
the AD7273/AD7274.
POWER-UP TIMES
The AD7273/AD7274 has two power-down modes, partial
power-down and full power-down, which are described in
detail in the Modes of Operation section. This section deals
with the power-up time required when coming out of either of
these modes.
To power up from partial power-down mode, one cycle is
required. Therefore, with a SCLK frequency of up to 48 MHz,
one dummy cycle is sufficient to allow the device to power up
from partial power-down mode. Once the dummy cycle is
complete, the ADC is fully powered up and the input signal is
acquired properly. The quiet time, tQUIET, must be allowed from
the point where the bus goes back into three-state after the
dummy conversion to the next falling edge of CS.
To power up from full power-down, approximately 1 s should
be allowed from the falling edge of CS, shown in Figure 33 as
tPOWER-UP. Note that during power-up from partial power-down
mode, the track-and-hold, which is in hold mode while the part
is powered down, returns to track mode after the first SCLK
edge is received after the falling edge of CS. This is shown as
Point A in Figure 31.
When power supplies are first applied to the AD7273/AD7274,
the ADC can power up in either of the power-down modes or
in normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the part is to be kept
in partial power-down mode immediately after the supplies are
applied, two dummy cycles must be initiated. The first dummy
cycle must hold CS low until after the 10th SCLK falling edge
(see Figure 29). In the second cycle, CS must be brought high
between the second and 10th SCLK falling edges (see Figure 30).
Alternatively, if the part is to be placed into full power-down
mode after the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge (see Figure 29); the second and third
dummy cycles place the part into full power-down mode (see
Figure 32). See also the Modes of Operation section.
CS
SCLK
110121416
AD7273/AD7674
SDATA VALID DATA
04973-029
Figure 29. Normal Mode Operation
AD7273/AD7274
Rev. 0 | Page 19 of 28
SCLK
1 2 10 16
SDATA THREE-STATE
CS
04973-030
Figure 30. Entering Partial Power-Down Mode
THE PART BEGINS
TO POWER UP THE PART IS FULLY
POWERED UP, SEE POWER-
UP TIMES SECTION
CS
SDATA INVALID DATA VALID DATA
1
A
10 16 1 16
SCLK
04973-031
Figure 31. Exiting Partial Power-Down Mode
THE PART ENTERS
PARTIAL POWER DOWN THE PART ENTERS
FULL POWER DOWN
CS
SDATA INVALID DATA VALID DATA
THE PART BEGINS
TO POWER UP
1 2 10 16 1 1610
SCLK
THREE-STATE THREE-STATE
04973-032
Figure 32. Entering Full Power-Down Mode
THE PART BEGINS
TO POWER UP tPOWER-UP
CS
S
DAT
A
INVALID DATA VALID DATA
THE PART IS
FULLY POWERED UP
110161 1
SCLK
6
04973-033
Figure 33. Exiting Full Power-Down Mode
AD7273/AD7274
Rev. 0 | Page 20 of 28
POWER VS. THROUGHPUT RATE
Figure 34 shows the power consumption of the device in
normal mode, in which the part is never powered down. By
using the power-down mode of the AD7273/AD7274 when not
performing a conversion, the average power consumption of the
ADC decreases as the throughput rate decreases.
Figure 35 shows that as the throughput rate is reduced, the
device remains in its power-down state longer and the average
power consumption over time drops accordingly. For example,
if the AD7273/AD7274 are operated in continuous sampling
mode with a throughput rate of 200 kSPS and a SCLK of 48 MHz
(VDD = 3 V) and the devices are placed into power-down mode
between conversions, the power consumption is calculated as
follows. The power dissipation during normal operation is
11.6 mW (VDD = 3 V). If the power-up time is one dummy
cycle, that is, 333 ns, and the remaining conversion time is
290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW
for 623 ns during each conversion cycle. If the throughput rate
is 200 kSPS, the cycle time is 5 µs and the average power dissipated
during each cycle is 623/5,000 × 9.6 mW = 1.42 mW. Figure 35
shows the power vs. throughput rate when using the partial
power-down mode between conversions at 3 V. The power-
down mode is intended for use with throughput rates of less
than 600 kSPS, because at higher sampling rates there is no
power saving achieved by using the power-down mode.
04973-034
THROUGHPUT (kSPS)
POWER (mW)
3.40
3.80
4.20
4.60
5.00
5.40
5.80
6.20
6.60
7.00
200 400 600 800 1000 1200 1400 1600 1800 2000
V
DD
= 3V
48MHz SCLK
VARIABLE SCLK
Figure 34. Power vs. Throughput, Normal Mode
04973-035
THROUGHPUT (kSPS)
POWER (mW)
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
6.0
6.4
6.8
7.2
0 200 400 600 800 1000
V
DD
= 3V
Figure 35. Power vs. Throughput, Partial Power-Down Mode
AD7273/AD7274
Rev. 0 | Page 21 of 28
SERIAL INTERFACE
Figure 36 through Figure 38 show the detailed timing diagrams
for serial interfacing to the AD7274 and AD7273, respectively.
The serial clock provides the conversion clock and controls the
transfer of information from the AD7273/AD7274 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion is initiated at this point.
For the AD7274, the conversion requires completing 14 SCLK
cycles. Once 13 SCLK falling edges have elapsed, the track-and-
hold goes back into track mode on the next SCLK rising edge,
as shown in Figure 36 at Point B. If the rising edge of CS occurs
before 14 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the last two bits are zeros and SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
Figure 37.
For the AD7273, the conversion requires completing 12 SCLK
cycles. Once 11 SCLK falling edges elapse, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown in Figure 38 at Point B. If the rising edge of CS occurs
before 12 SCLKs elapse, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, the AD7273 clocks out four trailing
zeros for the last four bits and SDATA returns to three-state on
the 16th SCLK falling edge, as shown in Figure 38.
If the user considers a 14-SCLK cycle serial interface for the
AD7273/AD7274, CS must be brought high after the 14th SCLK
falling edge. Then the last two trailing zeros are ignored, and
SDATA goes back into three-state. In this case, the 3 MSPS
throughput can be achieved by using a 48 MHz clock frequency.
CS going low clocks out the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Therefore, the first falling clock edge on the serial
clock provides the first leading zero and clocks out the second
leading zero. The final bit in the data transfer is valid on the 16th
falling edge, because it is clocked out on the previous (15th)
falling edge.
In applications with a slower SCLK, it is possible to read data on
each SCLK rising edge. In such cases, the first falling edge of
SCLK clocks out the second leading zero and can be read on the
first rising edge. However, the first leading zero clocked out
when CS goes low is missed if read within the first falling edge.
The 15th falling edge of SCLK clocks out the last bit and can be
read on the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge elapses, CS
clocks out the first leading zero and can be read on the SCLK
rising edge. The next SCLK falling edge clocks out the second
leading zero and can be read on the following rising edge.
t
CONVERT
TWO LEADING
ZEROS
t
2
CS
SCLK
SDATA THREE-
STATE THREE-STATE
B
1/THROUGHPUT
1 2 3 4 5 13 14
ZERO DB11 DB10 DB9 DB1 DB0Z
t
6
t
1
t
QUIET
t
9
t
5
t
7
t
4
t
3
04973-036
Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle
AD7273/AD7274
Rev. 0 | Page 22 of 28
tCONVERT
CS
SCLK
SDATA
TWO LEADING
ZEROS
THREE-
STATE THREE-STATE
TWO TRAILING
ZEROS
B
1/THROUGHPUT
1 2 3 4 5 13 15 1614
DB11 DB10 DB9 DB1 DB0 ZERO ZEROZEROZ
t2
t3t4t7t5t8tQUIET
t1
t6
04973-037
Figure 37. AD7274 Serial Interface Timing Diagram 16 SCLK Cycle
t
CONVERT
SCLK
B
1 2 3 4 10 11 12 14 161513
t
2
t
3
t
4
t
7
t
8
CS
t
1
SDATA
TWO LEADING
ZEROS
THREE-
STATE THREE-STATE
FOUR TRAILING
ZEROS
1/THROUGHPUT
DB9 DB8 DB0DB1 ZERO ZERO ZERO ZEROZEROZ
t
QUIET
t
5
t
6
04973-038
Figure 38. AD7273 Serial Interface Timing Diagram
AD7273/AD7274
Rev. 0 | Page 23 of 28
MICROPROCESSOR INTERFACING
AD7273/AD7274 to ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the
AD7273/AD7274 without requiring glue logic. The SPORT0
Receive Configuration 1 register should be set up as outlined in
Table 8.
AD7273/
AD7274
1
ADSP-BF53x
1
SCLK RCLK0
SPORT0
DR0PRI
RFS0
DT0
DOUT
CS
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY
04973-039
Figure 39. Interfacing to the ADSP-BF53x
Table 8. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting Description
RCKFE = 1 Sample data with falling edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 1 Internal RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 1 Internal receive clock
RSPEN = 1 Receive enabled
SLEN = 1111 16-bit data-word (or can be set to 1101 for a
14-bit data-word)
TFSR = RFSR = 1
To implement the power-down modes, set SLEN to 1001 to
issue an 8-bit SCLK burst.
AD7273/AD7274
Rev. 0 | Page 24 of 28
APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7273/AD7274
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This design
facilitates using ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins of the AD7273/
AD7274 should be sunk into the AGND plane. Digital and
analog ground planes should be joined in only one place. If the
AD7273/AD7274 are in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at only one point, a star ground point, established as close
as possible to the ground pin on the AD7273/AD7274.
Avoid running digital lines under the device, because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7273/AD7274 to avoid
noise coupling. The power supply lines to the AD7273/AD7274
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board,
components with fast-switching signals, such as clocks, should
be shielded with digital ground, and they should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. To reduce the effects of feedthrough within the board,
traces on opposite sides of the board should run at right angles
to each other. A microstrip technique is by far the best method,
but it is not always possible to use this approach with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF ceramic capacitors in parallel with
0.1 µF capacitors to AGND/DGND. To achieve the best results
from these decoupling components, they must be placed as close
as possible to the device, ideally right up against the device. The
0.1 µF capacitors should have low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic or surface-mount types of capacitors.
Capacitors with low ESR and low ESI provide a low impedance
path to ground at high frequencies, which allows them to
handle transient currents due to internal logic switching.
EVALUATING THE AD7273/AD7274 PERFORMANCE
The recommended layout for the AD7273/AD7274 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7273/AD7274
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate the
ac and dc performance of the AD7273/AD7274.
The software allows the user to perform ac (fast Fourier trans-
form) and dc (histogram of codes) tests on the AD7273/AD7274.
The software and documentation are on a CD shipped with the
evaluation board.
AD7273/AD7274
Rev. 0 | Page 25 of 28
OUTLINE DIMENSIONS
13
56
2
8
4
7
2.90 BS C
PIN 1
INDICATOR
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.10 MAX
*0.90
0.87
0.84
SEATING
PLANE
*1.00 MAX 0.20
0.08 0.60
0.45
0.30
8°
4°
0°
2.80 BSC
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 40. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
0.80
0.60
0.40
8°
0°
4
8
1
5
4.90
BSC
PIN 1 0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature
Range
Linearity
Error (LSB)1 Package Description
Package
Option Branding
AD7274BRM −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C1V
AD7274BRMZ2−40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C34
AD7274BRMZ-REEL2−40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C34
AD7274BUJ-500RL7 −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) UJ-8 C1V
AD7274BUJZ-500RL72−40°C to +125°C ±1 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C34
AD7274BUJZ-REEL72−40°C to +125°C ±1 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C34
AD7273BRMZ2−40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C33
AD7273BRMZ-REEL2−40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C33
AD7273BUJ-REEL7 −40°C to +125°C ±0.5 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C1U
AD7273BUJZ-500RL72−40°C to +125°C ±0.5 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C33
EVAL-AD7274CB3 Evaluation Board
EVAL-AD7273CB3 Evaluation Board
EVAL-CONTROL BRD24 Control Board
1 Linearity error refers to integral nonlinearity.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete
evaluation kit, the particular ADC evaluation board (such as EVAL-AD7273CB/AD7274CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the
relevant evaluation board technical note for more information.
AD7273/AD7274
Rev. 0 | Page 26 of 28
NOTES
AD7273/AD7274
Rev. 0 | Page 27 of 28
NOTES
AD7273/AD7274
Rev. 0 | Page 28 of 28
T
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04973–0–9/05(0)
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AD7273: 3 MSPS 10-Bit ADC in TSOT and MSOP Packages
The AD7273 is a 10-bit, high speed, low power, successive-approximation ADC. The part operates from a single 2.35V to 3.6
V power supply and features throughput rates up to 3 MSPS. The part ...More
AD7273: 3 MSPS 10-Bit ADC in TSOT and MSOP Packages
Product Description
The AD7273 is a 10-bit, high speed, low power, successive-approximation ADC. The part operates from a single 2.35V to 3.6
V power supply and features throughput rates up to 3 MSPS. The part contains a low-noise, wide bandwidth track/hold
amplifier which can handle input frequencies in excess of 30 MHz.
The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at
this point. The conversion rate is determined by the SCLK. There are no pipeline delays associated with the part.
The AD7273 uses advanced design techniques to achieve very low power dissipation at high throughput rates.
The reference for the part is applied externally and can be in the range of 1.2 V to VDD. This allows the widest dynamic input
range to the ADC.
Applications
● Battery-Powered Systems
- Personal Digital Assistants
- Medical Instruments
- Mobile Communications
● Instrumentation and Control Systems
● Data Acquisition Systems
● High-Speed Modems
● Optical Sensors
On This Page:
● Resources
● Features
● Diagrams
● Specifications
● Explore Other Products
● Pricing, Packaging & Availability
● Data Sheet Rev 0, 03/2006 (pdf 1306kB)
● (About Data Sheets)
Quick Links
● Lead(Pb) - Free Data
● Evaluation Boards/Tools
Resources
● Overview
● Rarely Asked Questions
● Solutions Bulletins
Features
● Fast Throughput Rate: 3 MSPS
● Specified for VDD of 2.35 V to 3.6 V
● Low Power: 13.5 mW at 3 MSPS with 3 V Supplies
● Wide Input Bandwidth: 70 dB SNR at 1 MHz Input Frequency
● Flexible Power/Serial Clock Speed Management
● No Pipeline Delays
● High Speed Serial Interface SPI®/
QSPI™/MICROWIRE™/
DSP Compatible
● Power Down Mode: 1 µA max
● 8-Lead TSOT Package
● 8-Lead MSOP Package
● 12-Bit Version: AD7274
Diagrams
● Enlarge
● Other Diagrams
● Symbols and Footprints
Functional Block Diagram for AD7273
Specifications
Resolution (Bits) 10bit
T-Put Rate 3MSPS
# Chan 1
Supply V Single(+2.5),Single(+3),Single(+3.3)
Interface Ser,SPI
Ain Range (Vref) p-p,Uni (Vref)
Pkg Type SOP,SOT
Explore Other Products
● New Products
● Similar Products
● Related Products
AD7625 - 16-Bit, 6MSPS PulSAR Differential ADC
AD7190 - 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA
AD7699 - 16-Bit, 8-Channel, 500 kSPS PulSAR ADC
AD7356 - Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC
Subscribe to New Products Feed More
Part# Res Throughput Rate # of Inputs
AD9215-65 10 65MSPS 1
AD9215-105 10 105MSPS 1
AD9200 10 20MSPS 1
AD9203 10 40MSPS 1
AD9214-65 10 65MSPS 1
View full interactive product selection table
AD7273 10 3MSPS 1
AD7277 10 3MSPS 1
AD876 10 20MSPS 1
AD9214-105 10 105MSPS 1
AD9051 10 60MSPS 1
AD9211-200 10 200MSPS 1
AD9410 10 210MSPS 1
AD9411 10 170MSPS 1
AD9211-300 10 300MSPS 1
AD9601-200 10 200MSPS 1
Pricing, Packaging & Availability
Print Table
AD7273 Model Options
Model Status Package Pins Temp.
Range Price*
(1000
pcs.)
Production**
Availability ROHS
Compliant Samples
Cart Purchase
Cart
AD7273BRMZ Prodn 8 ld MSOP 8 Ind $3.80 01/30/2009 Y
Material
Declaration
Add To
Cart Add To
Cart
AD7273BRMZ-
REEL Prodn 8 ld MSOP 8 Ind $3.80 - Y
Material
Declaration
Contact
ADI Add To
Cart
AD7273BUJZ-
500RL7 Prodn 8 ld TSOT 8 Ind $3.80 01/30/2009 Y
Material
Declaration
Add To
Cart Add To
Cart
AD7273BUJZ-
REEL7 Prodn 8 ld TSOT 8 Ind $3.80 - Y
Material
Declaration
Contact
ADI Add To
Cart
EVAL-
AD7273CB Prodn EVALUATION
BOARDS - TBD $151.80 01/30/2009 E Contact
ADI Add To
Cart
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Model
The model number is a specific version of a generic that can be purchased or sampled.
Status
Status indicates the current lifecycle of the product. This can be one of 4 stages:
● Pre-Release: The model has not been released to general production, but samples may be available.
● Production: The model is currently being produced, and generally available for purchase and sampling.
● Last Time Buy: The model has been scheduled for obsolescence, but may still be purchased for a limited time.
● Obsolete: The specific part is obsolete and no longer available. Other models listed in the table may still be available
(if they have a status that is not obsolete).
Package Description
The package for this IC (i.e. DIP, SOIC, BGA). An Evaluation Board is a board engineered to show the performance of the
model, the part is included on the board.
For detailed drawings and chemical composition please consult our Package Site
Pin Count
Pin Count is the number of pins, balls, or pads on the device. Pin-out diagrams & pin function descriptions may be found in
the datasheet.
Temperature Range
This is the acceptable operating range of the device. The various ranges specified are as follows:
● Commercial: 0 to +70 degrees Celsius
● Military : -55 to +125 degrees Celsius
● Industrial: Temperature ranges may vary by model. Please consult the datasheet for more information.
● Automotive: -40 to +125 degrees Celsius
Price
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated
volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For
volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor.
Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
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hours of this date.Once an order has been placed, Analog Devices, Inc. will send an Order Acknowledgement email to
confirm your delivery date. It is important to note the scheduled dock date on the order entry screen. We do take orders for
items that are not in stock, so delivery may be scheduled at a future date. Also, please note the warehouse location for the
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Due to environmental concerns, ADI offers many of our products in lead-free versions. For more information about lead-free
parts, please consult our Pb (Lead) free information page.
*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated
volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For
volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor.
Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples into your cart to check sample
availability.
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