ACS8110 SSM Handler Synchronization Status Message Handler with Integrated BITS Interface ADVANCED COMMUNICATIONS COMMUNICATION Summary Description PRELIMINARY The ACS8110 SSM Handler is a single-chip, 14-channel, multi-standard Synchronization Status Message (SSM) interpreter and source prioritizing device, incorporating a multichannel BITS (or SSU/SASE) interface. Simple to configure by default, yet capable of considerable customization if required, it contains all that is needed to handle SSMs and line condition information for both Station Clocks (BITS) and Equipment Clocks (line interfaces). It produces channel priority data for use in the T4 and T0 source selection functions of a SETS device e.g. Semtech's ACS8530, to ensure that the Sync Card in a Network Element selects the most appropriate Sync source. The ACS8110 device directly implements the SSM functionality required by SONET/SDH standards, including GR-253, G.781 and ETS 300-417-6-1, and so removes the need for a complex real-time software solution with the associated processing overhead. The SSM Handler has 14 channels for handling SSM streams extracted off-chip from any mix of SONET/SDH/PDH sources, e.g. line card recovered clocks, received via a multi-protocol microprocessor (uP) interface. Four of these channels can alternatively be individually configured to receive SSMs extracted on-chip from E1 or DS1 signals by a four-channel PRI (Primary Rate Interface) deframer, providing the receive side of the integrated BITS interface. DATASHEET The SSM Handler determines the relative priority of each source by taking into account the SSM value and other line status and channel weighting considerations. Using two separate selection algorithms, it builds two Priority Tables, one for the SETS T0 path and one for the T4 path. In each Priority Table, every channel is ranked and allocated a unique sequential priority value which can be written to the matching Priority Table in the Semtech SETS device. Using these priority values (unless overridden), each prioritizer also declares a "Selected Channel". Each Selected Channel is further processed, introducing additional standards functionality, and to provide alternative source selection controls for the SETS device. To achieve specifications-defined functionality, and so as not to burden the uP, the SSM Handler runs multiple, programmable, Hold-Off and Wait-to-Restore timers. Triggered by changes in line status or SSM value, these timers control when any change to the channel prioritization is made, and inhibit unnecessary changes. For each T0 and T4 Selected Channel the device provides the associated SSM value in 6 formats, one per supported signal type. These are simultaneously made available to the uP, ready for subsequent external framing as required. Additionally, up to two SSMs (E1 or DS1 format) can be inserted by the pair of on-chip framers, providing the transmit side of the integrated BITS interface. Typical Application Figure 1 Simplified SSM and Clock Selection Control Flows in Typical SSM Handler NE Application KEY SSM flow SSM flow (effective path, actually via uP) Clock flow BITS Station Clock E1/DS1 To BITS/SLAVE SSMs and Signal Defects (RAI LOS etc), to/from SSM Handler are via uP and uP Interface. Configuration, Read/Write requests, Interrupt handling, etc. are also via uP and uP Interface, but these signal flows have been excluded for clarity. Note that the clock paths to/from the BITS LIUs are directly connected to SETS. LIU MASTER SYNC CARD 2 x PRI outputs SSMs Extracted SSMs Extracted Off-chip (from Line cards) On-chip (from BITS) 14 14 T4 Channel Prioritizer Microprocessor (uP) T4 Selected Channel T0 Channel Prioritizer T4 SSM T0 Selected Channel Data Bus Signal Defects T4 SSM On-Chip DeFramer SSM Extracted SEMTECH ACS8530 SETS Line Recovered Clocks T4 Select Off-chip Deframers Off-chip Framer On-Chip Framer 4 T0 Selected Channel Output Signal Framed with SSM T0 SSM Frame with inserted SSM Signal Defects LINE CARDS Incoming Signals ANSI or ETSI 4x PRI inputs SEMTECH ACS8110 SSM HANDLER 14 Channels of SSM Processing SSMs Extracted Off-chip From BITS/SLAVE LIU Equipment Clock T0 DPLL T4 DPLL DPLL Outgoing Clocks 2 Recovered Clocks (Station Clock) from up to 4 channels 4 T0 Select SSM (of T0 Selected Channel, via uP) SLAVE SYNC CARD F8110_001SSMFlow_03 Revision 1.01/August 2003 (c) Semtech Corp. Page 1 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Features PRELIMINARY 14 channels of SSM processing for prioritizing up to 14 reference clock sources Prioritizes any combination of ANSI/ETSI reference sources, for selection by Equipment and Station Clock generators Automatically selects input reference sources for both Equipment and Station Clock, in accordance with TR33, GR-253 and G.781 standards Uses two configurable Selection Processes, which can take account of SSM values, line status, channel lockouts, optional user-defined priority preferences, comparison with quality of Local Clock, etc. Builds two independent Priority Tables, and produces two sets of "Selected Channel" data, giving alternative options for controlling T4 and T0 PLL source selectors in a Semtech SETS device All input channels individually configurable to expect SSMs from following supported signal types: * OC-N GEN1 (ANSI hierarchy) * OC-N GEN2 (ANSI hierarchy) * DS1 GEN1 (ANSI hierarchy) * DS1 GEN2 (ANSI hierarchy) * STM-N (ETSI hierarchy) * E1 (ETSI hierarchy) * User-defined according to any of Telcordia GR-499 (DS1 ESF), ANSI T1.107, ITU-T G.704 (E1), GR-253 (SONET) or G.707 (SDH) standards Channels alternatively configurable as * "Unconnected" * "SSMs not supported" Automatically translates incoming SSM values from the above supported hierarchies into Quality Levels Accepts up to 14 SSM streams supplied by the uP interface, four of which can alternatively be supplied by the on-chip framer Deframer for on-chip extraction of SSMs from inputs on four E1/DS1 PRI input ports Framer for on-chip insertion of SSMs for two outgoing Station Clocks via 2 x DS1/E1 PRI output ports Revision 1.01/August 2003 (c) Semtech Corp. DATASHEET Framer for on-chip insertion of SSMs for two outgoing Station Clocks via 2 x DS1/E1 PRI output ports Input PRI ports supporting: * Source frame formats: ANSI DS1 ESF and SF, and ETSI E1 Basic Frame, Multiframe and Multiframe with CRC * Line decode: HDB3/B8ZS/AMI or NRZ Output PRI ports supporting: * Source frame formats: ANSI DS1 ESF and SF, ETSI E1 Multiframe with CRC * Line code: HDB3/B8ZS/AMI or bypass Optional (per channel) persistency check (configurable m out of n) on all incoming SSMs Automatically translates each "Selected Channel" Quality level to provide simultaneously a set of six SSM values, one per signal type, ready for framing into outbound signals for both Equipment and Station Clocks Channel snapshot facility - gives an instantaneous read of several parameters at various points in the processing flow through any one chosen channel Interfaces with external Line Interface Units Interfaces with Semtech's ACS8510, ACS8520, ACS8522 and ACS8530 SETS sync card devices Signal Failure monitors, per-channel, with configurable Hold-Off (tho) and Wait-To-Restore (twtr) timers Transient change timers with configurable switching time (tsw) settings for use when different designated channel types are to be switched Includes four 3-input clock multiplexers to effectively expand the number of sources a SETS device can handle Configurable microprocessor port, compliant to Intel or Motorola 8-bit multiplexed or non-multiplexed formats, Serial (SPI compatible format), and EPROM mode ETSI /ANSI pin to simplify device-wide configuration IEEE 1149.1 JTAG boundary scan 3.3 V operation with 5 V tolerant inputs (LVTTL/LVCMOS technology) Operating temperature (ambient) -40 oC to +85 oC Available in 80 pin LQFP package Page 2 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Contents PRELIMINARY DATASHEET Output Port Alarms ...........................................................33 Channel Processing Alarms .............................................33 Prioritization /Channel Selection Alarms:.......................33 T0/T4 Selected Channel Generation Alarms..................33 Electrical Specifications........................................................... 34 Maximum Ratings.............................................................34 Operating Conditions........................................................34 DC Characteristics ............................................................34 DS1/E1 Input Port Interface Timing................................36 Output Port Interface Timing ...........................................36 Jitter Characteristics.........................................................37 Reference Clock ...............................................................37 Thermal Conditions ..........................................................37 JTAG...................................................................................37 Package Information................................................................ 38 Application Information ........................................................... 39 References and Related Standards........................................ 41 Abbreviations............................................................................ 41 Trademark Acknowledgements............................................... 42 Revision Status/History ........................................................... 42 Ordering Information................................................................ 43 Disclaimers .......................................................................43 Contacts ............................................................................43 Summary Description................................................................. 1 Typical Application ...................................................................... 1 Features ...................................................................................... 2 Contents ...................................................................................... 3 Block Diagram............................................................................. 3 Functional Overview ................................................................... 4 Application Programming Interface (API) ..........................7 Supporting Tools......................................................................... 7 Evaluation board (EVB) and Graphical User Interface (GUI)based application software ................................................7 PIn Diagram ................................................................................ 7 Pin Description............................................................................ 8 Input Ports10 BITS Interface .......................................................................... 10 Output Ports ..................................................................... 10 Interrupt Request Output Pin .......................................... 11 Interrupt/Status Handling ............................................... 11 Microprocessor Interface ........................................................ 11 Microprocessor Interface Timing .................................... 11 Clock Multiplexer ..................................................................... 20 Register Map............................................................................ 21 Register Organization ...................................................... 21 Alarms/Performance Reporting.............................................. 33 Input Port Alarms ............................................................. 33 Block Diagram Figure 2 Block Diagram of the ACS8110 SSM Handler 4 ALTCLK[3:0] 4 Frame_Sync [3:0] MUX 4 SELCLK[3:0] SSM EXTRACTION (4 x E1/DS1 Input Ports) RCLK[3:0] 4 x PRI/LIU RPOS[3:0] RNEG[3:0] Inputs (from BITS) Line Decode PRIORITIZATION/CHANNEL SELECTION 4 Alarm Detection LOS, LOF, CRC RLOS[3:0] For each process, determines priority for each channel and nominates the "Selected Channel". SSM PROCESSING DS1/E1 SSM Extract DS1/E1 Deframer 14 x Channels of SSM processing 14 x Inconsistency monitors 14 x Signal failure monitors (THO, TWTR) Includes configurable Transient Change Timers Validates SSMs and generates an initial priority value per channel, based on SSM-defined quality/line conditions SSMs Extracted On-chip 14 x Initial Priority Other input parameters T4 Prioritizer ANSI_ETSI UPSEL IRQ Microprocessor Access: Input of SSMs and line conditions extracted off-chip. Access for configuration and control. Access to Status Tables e.g. to read out SSM values for insertion in outgoing signals by off-chip framers (on Line Cards). REFCLK 12.8 MHz SSMs Extracted Off-chip Microprocessor Interface 14 Ch [1:4] Ch [5:14] Channel Processing T0 Prioritizer Priority Table 1 SELECTED CHANNEL GENERATION T4 Selected Channel Processing T4 "Selected Channel" IEEE 1149.1 JTAG Selection Process 1 SSM values in all supported formats T0 "Selected Channel" Clock Generator TCLK[1:0] T4 Highest Priority Channel Selection Process 0 Priority Table 0 SSM Conversion Priority Overrides T0 Selected Channel Processing inc. Local Clock Comparison, etc. SSM Conversion T0 Highest Priority Channel Priority Overrides Data Bus SSM INSERTION: (2 E1/DS1 Output Ports) SSM Insert DS1/E1 Framer Line Encode 2 x PRI/LIU Outputs (to BITS) TPOS[1:0] TNEG[1:0] F8110_001BLOCKDIASIMPLE_04 Revision 1.01/August 2003 (c) Semtech Corp. Page 3 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Functional Overview PRELIMINARY Figure 1 presents the SSM Handler in an example Network Element, showing the SSM message and clock flows and Figure 2 shows the main functional blocks of the SSM Handler. This description refers to both Figures as it explains the device functionality and how the SSM Handler can be used to provide source selection information to a microprocessor for controlling both the T4 and T0 selectors of a Semtech SETS device. Both input selectors of the SETS device are supplied with line clocks recovered by line cards and with any Station Clocks recovered by the BITS (or SSU /SASE) port. At the same time, each of these incoming signals are given a mapping to one of the 14 "Processing Channels" of the SSM Handler. Consequently, the SSMs that these signals carry, or have assigned to them, together with any line condition information (e.g. Signal Defect), are supplied to the corresponding Processing Channel. How this is done must be determined by the User. The SETS T4 input selector is not supposed to select any incoming Station Clock, so these channels would be disabled in the T4 selection process. Figure 2 implies this configuration by not showing any BITS recovered clock path to the SETS T4 selector. Channels 1 to 4 of the SSM Handler can process SSMs that are either extracted on-chip, or received via uP interface (e.g. extracted off-chip), whereas Channels 5 to 14 process only those SSMs received via the uP interface. In the example in Figure 1, the BITS interface is using the on-chip framers to extract SSMs from the Station Clocks received on the 4 PRI input ports, and so the SSMs associated with these clocks (and line condition information) would each be assigned to one of Channels 1 to 4. For the line inputs, the SSMs are extracted off-chip and are received at the SSM Handler via the uP interface, along with any line condition information, and so these would be allocated among Channels 5 to 14, as required. The SSM Handler processes the SSMs and associated data on a per-channel basis through the Channel Processing Block (comprising several functions that are not shown for simplicity) in the SSM Processing Block, in accordance with specifications defined in the relevant Standards (see "References and Related Standards" on page 40). In this block, checks are made on the SSM value for persistency, validity, etc. and filtering ensures that only valid and persistent SSMs continue in the flow. These SSMs are monitored for inconsistency, and at the same time a signal failure monitor function, with Revision 1.01/August 2003 (c) Semtech Corp. DATASHEET programmable Hold-off and Wait-to-Restore timers, monitors any signal defect condition (LOS, RAI, etc.). The timers affect whether or not the defect qualifies for being taken into account by the selection algorithms in the Channel Prioritization further on in the flow. Each channel's valid and persistent SSM undergoes conversion, via a Look-up Table (LUT) appropriate for the signal type, to both a Standards QL Level and a ProtocolIndependent Quality Level code (PIQL code). Note...Unlike the PIQL code, the Standards QL Level is not used functionally by the SSM Handler, but is made available to the microprocessor. If the default LUT values are used, the Standards QL Level gives the Quality Level Order as defined in tables in GR -253 (ANSI) and G.781 (ETSI), which can be used in comparing relative priority between SSMs only of the same signal type. The PIQL code has an identifier for all the possible SSM values for the supported signal types including codes to accommodate conditions such as Channel Failed (as result of Signal Defect), Channel Unavailable (manually configured), etc. Provisionable codes are also included to allow for any future changes in the SSM standards. To achieve these conversions, the device has predefined Look-up Tables (LUTs) to accommodate 4-bit SSMs for OC-N Generation 1 and 2, 6-bit SSMs for DS1 Generation 1 and 2, 4-bit SSMs for STM-N or E1 (same definitions), and one LUT for User-defined SSMs of up to 8 bits. Relative priority cannot be inferred directly from the PIQL codes themselves, however the SSM Processing Block converts the PIQL codes of each channel, i.e. the source priority translated from the SSM value together with line condition information, into initial (1st Order) Priority values and outputs these for input to the Prioritization/Channel Selection block. The Prioritization/Channel Selection block comprises two Channel Prioritizers, one for the T0 path, one for the T4 path, each of which has its own Selection Process, and Transient Change Timer. Inputs to this block that affect the subsequent priority selection processes include QL Mode, 1st Order Priority (from previous block), User Configured (2nd Order) Priority, whether or not a channel is enabled, and line condition information. The SSM Handler supports both QL-enabled and QLdisabled modes in accordance with ITU-T G.781 and ETSI EN 300 417-6-1; the mode selected applies to both Prioritizers. In both modes, line conditions are taken into Page 4 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY account, to qualify sources prior to selection, along with any external commands. In QL-enabled mode, the channel priorities are then determined by the 1st Order Priority and so are based on the SSM values of the sources, whereas in QL -disabled mode, these SSM values are ignored, and Priority is then based on the 2nd Order Priorities configured by the Network Operator. In QLenabled mode, if the 1st Order Priority gives some channels equal priority, then the Selection Process uses the 2nd Order Priorities to further sort the channels. In both QL modes, if after using the 2nd Order Priorities there are still channels with equal priority, a channel index is used to ensure that the each channel finally has a unique priority value. The network operator can disable a channel by setting the 2nd Order Priority to 0. Line conditions are input to the Selection Processes via a single Signal Defect bit for each channel. The Signal Defect bit has to be set by software, since the choice of line condition information to be used as a source qualifier is a Network Operator preference. For example AIS, RAI OOF and Loss of Clock may be chosen by some Network Operators as a complete set of qualifiers, whilst others may prefer to include any other qualifier such as the outputs of the frequency and activity monitors of the SETS device. The on-chip deframers of the SSM Handler BITS ports can generate certain line condition information (e.g LOS, AIS etc.) but this is read by the uP and then written back as the Signal Defect bit for the particular channel. In this way, the software model for the BITS port channels is exactly the same as for any other channels. Each Selection Process outputs a unique 4-bit priority value for each channel (same format as Semtech SETS). This allows each Channel Prioritizer to independently output a "Highest Priority" channel, for subsequent generation of the "Selected Channel" by the next block, and a Priority Table in which each channel is given a unique priority value. Each Priority Table is made available to the uP via the uP interface. Transient change monitors ensure that the Channel Prioritizers use a soaking time so that no unnecessary changes are made to the Priority Tables and so protect the SETS device from making unnecessary clock changeovers. The switch times of the monitors are programmable, allowing different switch times to be used depending on which channel types are to be switched. The Selected Channel Generation block chooses the "Selected Channel" for each TO/T4 path and provides additional functionality for greater standards compliance. Revision 1.01/August 2003 (c) Semtech Corp. DATASHEET For each path, the Selected Channel chosen is the "Highest Priority" channel as determined by the particular Selection Process, unless overridden by a "Forced Switch" or "Manual Switch" request. In the case of the T0 path only, the quality of the Selected Channel subsequently can be compared with the quality of the Local Clock. If the Local clock quality is better, then the Channel Selected is set to 0, which means the Local Clock (Holdover) is to be used instead. The final selection for each path can then be used in controlling the associated PLL source selector on the SETS device. A basic alternative control could be provided by simply downloading the SSM Handler Priority Tables into the appropriate tables in the SETS device. In the example in Figure 1, the T4 Selected Channel output from the SSM Handler provides, via the microprocessor, control of the SETS T4 input selector. By translating the PIQL code of the selection made, the SSM Handler supplies the associated SSM in all the supported formats at the same time. From these, the uP can select directly the right format SSM (DS1 or E1) for the outgoing signal to BITS, and supply this SSM to the on-chip framer for framing into this outgoing signal. In the same way, the T0 Selected Channel output of the SSM Handler provides, via the microprocessor, control of the SETS T0 input selector. Note that the SETS T0 source selection options differ from those of the T4 - they include in addition to channels allocated to line cards, channels allocated to the PRI inputs that receive the Station Clocks from BITS, as well as the option to use the Local (Holdover) clock on SETS. Again, by translating the PIQL code for the selection made, the associated SSM is presented in registers in all supported formats at the same time, for access by the uP. This facilitates subsequent off-chip framing of this SSM in the correct format required by the line cards for a range of outgoing signal types. Network Element management software may however decide to propagate DNU/DUS instead, due the topology of the network. (The same applies to BITS). The SSM Handler's BITS interface arrangement of two outputs and four inputs allows for Master/Slave Sync card redundancy. An example Master/Slave arrangement is shown in Figure 3. Simpler arrangements can also be supported. Page 5 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Figure 3 PRELIMINARY Master/Slave Interconnect for BITS Interface. Supporting Tools DATASHEET Application Programming Interface (API) BITS/SSU A B' A' A B A B B C C' D' D A B C D' C' C D A' B' C D A to A = Cable connection A' to A' = Backplane connection D Line Interface Units SSM I/O (DS1/E1) 0 1 0 1 2 SSM Handler (MASTER) Master Sync Card BITS/SSU Interface 3 0 1 0 1 2 SSM Handler (SLAVE) Slave Sync Card BITS/SSU Interface 3 SSM Handler Output Ports [0:1] Input Ports [0:3] F8110LPB_003MASTERSLAVE_03 An API is available to allow designers to quickly realize the benefits of developing applications with the SSM Handler. The ACS8110 API is delivered as ANSI "C" compliant source code and provides a simple interface to the device.In the same way that the SSM Handler device eliminates the need for software developers to spend time learning the complexities of SSM-based clock selection, so the ACS8110 API eliminates the need for the software developers to spend time learning the details of the ACS8110 registers that facilitate this functionality. Evaluation board (EVB) and Graphical User Interface (GUI)-based application software For rapid device appraisal, Semtech can provide an EVB and a GUI-based application software package, including SSM Real-Time Emulator software. The application makes getting started simple, with intuitive screens for fast configuration, control and monitoring of all parameters relating to the SSM Handler and its operating environment, as well as bit-level access to registers (see Figure 4). Figure 4 Application Software GUI Main Menu Page Revision 1.01/August 2003 (c) Semtech Corp. Page 6 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PIn Diagram PRELIMINARY Figure 5 Pin Diagram Table 3 Complete Pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 TDO TRST TMS TDI TCK PORB TCLK1 TNEG1 TPOS1 TCLK0 TNEG0 TPOS0 GNDP VDDP IRQ ALE RDY RDB WRB CSB Pin No. VDD_AN GND_AN UPSEL0 UPSEL1 UPSEL2 ANSI_ETSI NC REFCLK VDDP GNDP NC NC RPOS0 RNEG0 GNDC VDDC RCLK0 RLOS0 RPOS1 RNEG1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Analogue supply voltage. Description 2 GND_AN GND - Analogue supply ground. 3 UPSEL0 I Pull-Down 4 UPSEL1 I Pull-Down UPSEL[2:0], Microprocessor Select: Configures the interface for a particular microprocessor type. See Table 4. 5 UPSEL2 I Pull-Down 6 ANSI_ET SI I Pull-Down Configuration Input; ANSI/ETSI mode. 1= ANSI, 0= ETSI. 7 NC NC Not Connected Do not connect. Leave to float. 8 REFCLK I Pull-Down, SchmittTrigger Reference Clock 12.8 MHz 50 ppm 9 VDDP VDD - Digital supply voltage to periphery. 10 GNDP GND - Digital supply ground to periphery. 11 NC NC Not Connected Do not connect. Leave to float. 12 NC NC Not Connected Do not connect. Leave to float. 13 RPOS0 I Pull-Up PRI Data In Positive Rail / NRZ Input Port 0. RNEG0 I Pull-Up PRI Data In Negative Rail Input Port 0. GNDC GND - Digital supply ground to main core logic. VDDC VDD - Digital supply voltage to main core logic. 17 RCLK0 I Pull-Down, SchmittTrigger PRI Clock In, Input Port 0. 18 RLOS0 I Pull-Up PRI LOS In, Input Port 0. 19 RPOS1 I Pull-Up PRI Data In, Positive Rail / NRZ Input Port 1. Symbol I/O Type Description 16, 43 VDDC VDD - Digital supply voltage to main core logic. 15, 44 GNDC GND - Digital supply ground to main core logic. 1 VDD_AN VDD - Analogue supply voltage 2 GND_AN GND - Analogue supply ground 9, 31, 51, 67 VDDP VDD - Digital supply voltage to periphery. 10, 32, 52, 68 GNDP GND - Digital supply ground to periphery. Table 2 Not Connected Pins Symbol NC Type 16 Table 1 Power Pins Pin No. - 15 Pin Description 7, 11, 12, 60 VDD 14 F8110_002PINDIA_05 Pin No. I/O VDD_AN RCLK1 RLOS1 RPOS2 RNEG2 RCLK2 RLOS2 RPOS3 RNEG3 RCLK3 RLOS3 VDDP GNDP ALTCLK0 ALTCLK1 ALTCLK2 ALTCLK3 SELCLK0 SELCLK1 SELCLK2 SELCLK3 ACS8110 SSM Handler NC A6 A5 A4 A3 A2 A1 A0 GNDP VDDP AD7 AD6 AD5 AD4 AD3 AD2 GNDC VDDC AD1 AD0 Symbol 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 17 18 19 20 DATASHEET I/O - Type -- 20 RNEG1 I Pull-Up PRI Data In, Negative Rail Input Port 1. 21 RCLK1 I Pull-Down, SchmittTrigger PRI Clock In, Input Port 1. 22 RLOS1 I Pull-Up PRI LOS In, Input Port 1. 23 RPOS2 I Pull-Up PRI Data In, Positive Rail / NRZ Input Port 2. 24 RNEG2 I Pull-Up PRI Data In, Negative Rail Input Port 2. 25 RCLK2 I Pull-Down, SchmittTrigger PRI Clock In, Input Port 2. 26 RLOS2 I Pull-Up PRI LOS In, Input Port 2. 27 RPOS3 I Pull-Up PRI Data In, Positive Rail / NRZ Input Port 3. 28 RNEG3 I Pull-Up PRI Data In, Negative Rail Input Port 3. 29 RCLK3 I Pull-Down, SchmittTrigger PRI Clock In, Input Port 3. 30 RLOS3 I Pull-Up PRI LOS In, Input, Port 3. 31 VDDP VDD - Digital supply voltage to periphery. 32 GNDP GND - Digital supply ground to periphery. 33 ALTCLK0 I Pull-Down, SchmittTrigger Alternate Clock In 0. Description Do not connect. Leave to float. Note...I = Input, O = Output, IO = Input/Output, VDD = Power, GND = Ground, NC = Not connected. All I/O pads are LVTTL/LVCMOS with internal pull-up/pull-down resistors and Schmitt Triggers as specified in the Type column. Revision 1.01/August 2003 (c) Semtech Corp. Page 7 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY Table 3 Complete Pinout (cont...) Pin No. 34 Symbol ALTCLK1 I/O I Type Table 3 Complete Pinout (cont...) Description Pull-Down, SchmittTrigger Alternate Clock In 1. 35 ALTCLK2 I Pull-Down, SchmittTrigger Alternate Clock In 2. 36 ALTCLK3 I Pull-Down, SchmittTrigger Alternate Clock In 3. 37 SELCLK0 O CMOS, 4mA, Tri-State (for JTAG only) Selected Clock Out 0. Pin No. 38 SELCLK1 O CMOS, 4mA, Tri-State (for JTAG only) Selected Clock Out 1. 39 SELCLK2 O CMOS, 4mA, Tri-State (for JTAG only) Selected Clock Out 2. 40 SELCLK3 O CMOS, 4mA, Tri-State (for JTAG only) Selected Clock Out 3. 41 AD0 IO CMOS, 4mA, Pull-Down Microprocessor Interface - Data bus, AD(0) is SDO in Serial Mode. 42 AD1 IO CMOS, 4mA, Pull-Down 43 VDDC VDD - Digital supply voltage to main core logic. 44 GNDC GND - Digital supply ground to main core logic. 45 AD2 IO CMOS, 4mA, Pull-Down Microprocessor Interface - Data bus, AD(0) is SDO in Serial Mode. 46 AD3 IO CMOS, 4mA, Pull-Down 47 AD4 IO CMOS, 4mA, Pull-Down 48 AD5 IO CMOS, 4mA, Pull-Down 49 AD6 IO CMOS, 4mA, Pull-Down 50 AD7 IO CMOS, 4mA, Pull-Down 51 VDDP VDD - 52 GNDP GND - Digital supply ground to periphery. 53 A0 IO CMOS, 4mA, Pull-Down 54 A1 IO CMOS, 4mA, Pull-Down Microprocessor Interface - Address bus. A0 is SDI in Serial Mode. A1 is CLKE in Serial Mode. 55 A2 IO CMOS, 4mA, Pull-Down 56 A3 IO CMOS, 4mA, Pull-Down 57 A4 IO CMOS, 4mA, Pull-Down 58 A5 IO CMOS, 4mA, Pull-Down 59 A6 IO CMOS, 4mA, Pull-Down 60 NC NC Not Connected Do not connect. Leave to float. 61 CSB IO CMOS, 4mA, Pull-Up Microprocessor Interface; Chip Select. This pin is asserted low by uP. 62 WRB I Pull-Up Microprocessor Interface; Write enable. Symbol I/O Type Description 63 RDB I Pull-Up Microprocessor Interface; Read enable. 64 RDY O CMOS, 4mA, Tri-State Microprocessor Interface; Ready/ DTACK flag. 65 ALE I Pull-Down, SchmittTrigger Microprocessor Interface; Address Latch Enable. Is SCLK in Serial Mode. 66 IRQ O CMOS, 4mA, Tri-State Microprocessor Interface; Interrupt Request. 67 VDDP VDD - Digital supply voltage to periphery. 68 GNDP GND - Digital supply ground to periphery. 69 TPOS0 O CMOS, 4mA, Tri-State (for JTAG only) PRI Data Out Positive Rail / NRZ Output Port 0. 70 TNEG0 O CMOS, 4mA, Tri-State (for JTAG only) PRI Data Out Negative Rail Output Port 0. 71 TCLK0 I Pull-Down, SchmittTrigger PRI Clock In Output Port 0. 72 TPOS1 O CMOS, 4mA, Tri-State (for JTAG only) PRI Data Out Positive Rail / NRZ Output Port 1. 73 TNEG1 O CMOS, 4mA, Tri-State (for JTAG only) PRI Data Out Negative Rail Output Port 1. 74 TCLK1 I Pull-Down, SchmittTrigger PRI Clock In Output Port 1. 75 PORB I Pull-Up Power-On Reset. Main asynchronous reset, active low. 76 TCK I Pull-Down, SchmittTrigger JTAG Interface. Boundary scan clock input. 77 TDI I Pull-Up JTAG Interface. Serial test data input. 78 TMS I Pull-Up JTAG Interface. Test Mode Select. 79 TRST I Pull-Up, SchmittTrigger JTAG Interface. Control Reset Input. TRST=1 to enable JTAG boundary scan. 80 TDO O CMOS, 4mA, Tri-State JTAG Interface. Serial test data output. Digital supply voltage to periphery. Revision 1.01/August 2003 (c) Semtech Corp. DATASHEET Page 8 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION BITS Interface PRELIMINARY The BITS interface has four independently configurable Input Ports connecting to four on-chip deframers which can terminate PRI signals and SSMs from four DS1 or E1 sources. It has two independently configurable output Ports and on-chip framers for supplying framed output SSMs from the selected reference, or alternatively SSMs chosen by the Network Management software (e.g. DNU), to external LIUs. For Input/Output Port timing characteristics, see "DS1/E1 Input Port Interface Timing" on page 35. Input Ports Each DS1 /E1 input port comprises the following input pin signals: RPOS - Receive data "positive" input. Frame Alignment Each Input Port, and consequently its Framer, can be configured to support Primary Rate E1, DS1 ESF and DS1 SF formats as defined in ITU Recommendation G.704. E1 Frame/Multiframe alignment is performed according to ITU Recommendation G.706, Sections 4.1 and 4.2. For DS1 SF and ESF, Frame/Multiframe alignment is performed according to ANSI T1.231 Section 6.1.2.2.1 and Telcordia TR-820 Sect 4.1.2 To provide robust frame/multiframe alignment, optional CRC-checking can be used, according to G.706, section 4.3.1. SSM Extraction E1: The Sa bit used by any particular E1 configured PRI Input is programmable between: none and 4,5,6 7 or 8. An SSM Extraction function takes in the configured serial Sa-bit stream from the deframer and outputs a 4-bit SSM value for input to the Channel Processing function. RNEG - Receive data "negative" input. RCLK - Receive clock input. RLOS - Receive loss of signal input. Line Decoding The ACS8110 SSM Handler can accept each DS1 or E1 line encoded signal as a pair of binary NRZ (i.e. full clock width) inputs RPOS and RNEG, together with a clock RCLK. The content of RPOS and RNEG represent the positive and negative pulses respectively of the incoming tertiary code. Line decoding can be selected as follows: For DS1, a bit-patterned Message extractor looks for an exact Facility Datalink (FDL) pattern 0 P6P5P4P3P2P1 0 11111111 where 11111111 is transmitted first. If found, the core 6-bit SSM (P6P5P4P3P2P1) is input to the Channel processing function, along with a message received event. Output Ports For E1: AMI, HDB3 -as per ITU G.703 section 6, or Bypassed. For DS1: AMI, B8ZS-as per ITU G.703 section 2.5, or Bypassed. Additionally, the SSM Handler has a configuration bit to bypass the line encoding. In this bypass configuration, the non-line-decoded data is accepted on the RPOS pin. It is possible to select by configuration, per input port, which edge of RCLK is used to re-time input data on RPOS and RNEG. Note...The SSM Handler does not have an analogue input interface and does not incorporate Line Interface Unit (LIU) functionality. It is expected that the LIU function is performed externally. The commercially available LIU's that would be used with SSM Handler invariably have the following functions: recovery of the positive and negative sides of the incoming three level code to give a pair of binary NRZ signals, clock recovery, and detection of LOS. As such, the SSM Handler Revision 1.01/August 2003 (c) Semtech Corp. DATASHEET does not have any clock recovery function or its own LOS detection function. Instead, it can accept an external clock on pin RCLK and LOS signal on pin RLOS. An SSM value may be sent out of each port. The SSM value to be output must first be written via software to a single byte register. For E1 mode, the output port continually transmits the 4-bit SSM value in the E1 frame configured Sa bits. For DS1 ESF, the 6-bit content of the register is converted into the 16-bit FDL format and this is continually transmitted. For DS1 SF, where specific SSM carriage is not supported, the option to squelch the output is available. Each output port can be configured as E1, or DS1 (SF or ESF), with selectable line coding of AMI or HDB3 for E1, and AMI or B8ZS for DS1 on Output Port pin signals TPOS[1:0], TNEG[1:0]. In both cases, if coding is bypassed, binary data is output on TPOS. At the pin level, the tertiary code splits onto the two pins representing positive and negative polarities of the code, where the binary output format is NRZ. Page 9 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Microprocessor Interface PRELIMINARY The SSM Handler supports 5 types of uP interface, as defined for the SETS device, via the following selectable interface modes: z z Serial mode: 4-wire Serial Peripheral Interface (SPI) compatible z Intel mode: 7-bit address and 8-bit data parallel interface, for use with the Intel 80x86 family z Motorola mode: 8-bit address and 8-bit data parallel interface, for use with the Motorola 68x0 family z Multiplexed mode z EPROM mode The uP interface mode is defined by SSM Handler input pins UPSEL[2:0]. In addition, the mode of the uP interface is configurable via the uP after power-up so long as the UPSEL[2:0] pins are configured to EPROM mode at powerup. z z Interrupt Request Output Pin The SSM Handler reports defined events/alarms to software via an interrupt request output pin. When an alarm is raised, the SSM Handler sets its corresponding interrupt status register bit. If the corresponding interrupt enable is active, then the alarm sets the interrupt request output pin to active. On detection of this pin being active, software reads the interrupt status registers one-by-one until the source of the interrupt is determined, or uses the interrupt location register to locate the specific interrupt status register and so reduce the number of accesses required to determine the source of the interrupt. The interrupt status register bit is reset by software writing a "1" to that register bit. Each bit is reset independently. The interrupt request output pin is reset to inactive, and the interrupt location registers are automatically reset, when all enabled interrupt status register bits are cleared. The SSM Handler interrupt request output pin has configurable polarity (active high or low) and whether the inactive state is high impedance or not. DATASHEET interrupt by writing a "1" to the specific register bit. A status value or status change will not cause an interrupt when disabled. However, if a status interrupt register exists (e.g. Sts_input_port), the status values will still be updated. Interrupt location registers Sts_interrupt_location. The two registers are implemented in order to minimize the number of accesses required for interrupt response. They decode the location of an interrupt. Interrupt status registers (i.e.Sts_interrupt_input_port). The registers contain the actual cause of an interrupt. An interrupt cause is cleared by writing a "1" to the specific active register bit. Status registers (i.e. Sts_input_port), where implemented. The registers contain the actual status if the interrupt is a status changed interrupt. For example, Los_defect_changed is the cause for the interrupt but does not implicate the actual status (Los_defect active or inactive). This can be extracted from the status register. Microprocessor Interface Timing CAUTION! In the following timing diagrams and data tables, the data is only Provisional. Table 4 Microprocessor Interface Mode Selection UPSEL[2:0] Mode Description 111 (7) Off Interface disabled 110 (6) Off Interface disabled 101 (5) Serial Serial uP bus interface 100 (4) Motorola Motorola interface 011 (3) Intel Intel compatible bus interface 010 (2) Multiplexed Multiplexed bus interface 001 (1) EPROM EPROM read mode 000 (0) Off Interface disabled Interrupt/Status Handling An interrupt is implemented using the following registers (examples are given for the input port interrupts): z Interrupt enable registers (e.g. Cnfg_intebl_input_port). Used for enabling an Revision 1.01/August 2003 (c) Semtech Corp. Page 10 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Motorola Mode In Motorola mode, the device is configured to interface with a microprocessor using a 680x0 type bus as parallel data + address. Figure 6 and Figure 7 show the timing diagrams of read and write accesses for this mode. Figure 6 Read Access Timing in Motorola Mode tpw1 CSB tsu2 WRB th2 X X th1 tsu1 A X address X td1 AD Z data td2 RDY (DTACK) td3 tpw2 th3 Z td4 Z Z F8110D_007ReadAccMotor_01 Table 5 Read Access Timing in Motorola Mode (for use with Figure 6) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 4 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - td1 Delay CSBfalling edge to AD valid (consecutive Read - Read) 12 ns - 40 ns Delay CSBfalling edge to AD valid (consecutive Write - Read) 16 ns - 192 ns td2 Delay CSBfalling edge to DTACKrising edge - - 13 ns td3 Delay CSBrising edge to AD high-Z - - 10 ns td4 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 CSB Low time (consecutive Read - Read) 25 ns 62 ns - CSB Low time (consecutive Write - Read) 25 ns 193 ns - RDY High time (consecutive Read - Read) 12 ns - 49 ns RDY High time (consecutive Write - Read) 12 ns - 182 ns th1 Hold A valid after CSBrising edge 0 ns - - th2 Hold WRB valid after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - tp Time between (consecutive Read - Read) accesses (CSBrising edge to CSBfalling edge) 15 ns - - tp Time between (consecutive Write - Read) accesses (CSBrising edge to CSBfalling edge) 160 ns - - tpw2 Revision 1.01/August 2003 (c) Semtech Corp. Page 11 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Figure 7 PRELIMINARY DATASHEET Write Access Timing in Motorola Mode tpw1 CSB tsu2 WRB th2 X X th1 tsu1 A X address X tsu3 AD data X td2 RDY (DTACK) th4 tpw2 th3 X td4 Z Z F8110D_008WriteAccMotor_01 Table 6 Write Access Timing in Motorola Mode (for use with Figure 7) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 4 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - tsu3 Setup AD valid before CSBrising edge 8 ns - - td2 Delay CSBfalling edge to RDYrising edge - - 13 ns td4 Delay CSBrising edge to RDY High-Z - - 7 ns tpw1 CSB Low time 25 ns - 180 ns tpw2 RDY High time 12 ns - 166 ns th1 Hold A valid after CSBrising edge 8 ns - - th2 Hold WRB Low after CSBrising edge 0 ns - - th3 Hold CSB Low after RDYfalling edge 0 ns - - th4 Hold AD valid after CSBrising edge 9 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Revision 1.01/August 2003 (c) Semtech Corp. Page 12 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Intel Mode In Intel mode, the device is configured to interface with a microprocessor using a 80x86 type bus as parallel data + address. Figure 8 and Figure 9 show the timing diagrams of read and write accesses for this mode. Figure 8 Read Access Timing in Intel Mode CSB WRB tpw1 tsu2 th2 RDB th1 tsu1 A address td1 td4 Z data AD td3 td2 tpw2 th3 td5 Z RDY F8110D_009ReadAccIntel_01 Table 7 Read Access Timing in Intel Mode (for use with Figure 8) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 4 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD valid (consecutive Read - Read) 12 ns - 40 ns Delay RDBfalling edge to AD valid (consecutive Write - Read) 12 ns - 193 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge - - 14 ns td4 Delay RDBrising edge to AD high-Z - - 10 ns td5 Delay CSBrising edge to RDY high-Z - - 11 ns tpw1 RDB Low time (consecutive Read - Read) 35 ns 60 ns - RDB Low time (consecutive Write - Read) 35 ns 195 ns - RDY Low time (consecutive Read - Read) 20 ns - 45 ns RDY Low time (consecutive Write - Read) 20 ns - 182 ns th1 Hold A valid after RDBrising edge 0 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp Time between (consecutive Read - Read) accesses (RDBrising edge to RDBfalling edge, or RDBrising edge to WRBfalling edge) 15 ns - - tp Time between (consecutive Write - Read) accesses (RDBrising edge to RDBfalling edge, or RDBrising edge to WRBfalling edge) 160 ns - - tpw2 Revision 1.01/August 2003 (c) Semtech Corp. Page 13 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Figure 9 PRELIMINARY DATASHEET Write Access Timing in Intel Mode CSB tpw1 tsu2 th2 WRB RDB th1 tsu1 address A th4 tsu3 data AD td3 td2 RDY tpw2 th3 td5 Z Z F8110D_010WriteAccIntel_01 Table 8 Write Access Timing in Intel Mode (for use with Figure 9) Symbol Parameter MIN TYP MAX tsu1 Setup A valid to CSBfalling edge 4 ns - - tsu2 Setup CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Setup AD valid before WRBrising edge 6 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 14 ns td5 Delay CSBrising edge to RDY high-Z - - 10 ns tpw1 WRB Low time 25 ns 185 ns - tpw2 RDY Low time 10 ns - 173 ns th1 Hold A valid after WRBrising edge 12 ns - - th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 Hold AD valid after WRBrising edge 4 ns - - tp Time between consecutive accesses (WRBrising edge to WRBfalling edge, or WRBrising edge to RDBfalling edge) 160 ns - - Revision 1.01/August 2003 (c) Semtech Corp. Page 14 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Multiplexed Mode In Multiplexed mode, the device is configured to interface with microprocessors (e.g., Intel's 80x86 family) which share bus signals between address and data. Figures 10 and 11 show the timing diagrams of read and write accesses. Figure 10 Read Access Timing in Multiplexed Mode tpw3 tp1 ALE tsu1 th1 CSB tsu2 WRB th2 tpw1 RDB td1 address AD X td2 RDY td4 data td3 tpw2 X th3 Z td5 Z F8110D_011ReadAccMultiplex_01 Table 9 Read Access Timing in Multiplexed Mode (for use with Figure 10) Symbol Parameter MIN TYP MAX tsu1 Setup AD address valid to ALEfalling edge 5 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td1 Delay RDBfalling edge to AD data valid (consecutive Read - Read) 12 ns - 40 ns Delay RDBfalling edge to AD data valid (consecutive Write - Read) 17 ns - 193 ns td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay RDBfalling edge to RDYfalling edge - - 15 ns td4 Delay RDBrising edge to AD data high-Z - - 10 ns td5 Delay CSBrising edge to RDY high-Z - - 10 ns tpw1 RDB Low time (consecutive Read - Read) 35 ns 60 ns - RDB Low time (consecutive Write - Read) 35 ns 200 ns - RDY Low time (consecutive Read - Read) 20 ns - 40 ns RDY Low time (consecutive Write - Read) 20 ns - 185 ns tpw3 ALE High time 5 ns - - th1 Hold AD address valid after ALEfalling edge 9 ns - - th2 Hold CSB Low after RDBrising edge 0 ns - - th3 Hold RDB Low after RDYrising edge 0 ns - - tp1 Time between ALEfalling edge and RDBfalling edge 0 ns - - tp2 Time between (consecutive Read - Read) accesses (RDBrising edge to ALErising edge) 20 ns - - tp2 Time between (consecutive Write - Read) accesses (RDBrising edge to ALErising edge) 160 ns - - tpw2 Revision 1.01/August 2003 (c) Semtech Corp. Page 15 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Figure 11 Write Access Timing in Multiplexed Mode tpw3 tp1 ALE tsu1 th1 CSB tsu2 th2 tpw1 WRB RDB tsu3 address AD X td2 RDY th4 data td3 tpw2 X th3 td5 Z Z F8110D_012WriteAccMultiplex_01 Table 10 Write Access Timing in Multiplexed Mode (For use with Figure 11) Symbol Parameter MIN TYP MAX tsu1 Set up AD address valid to ALEfalling edge 5 ns - - tsu2 Set up CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Set up AD data valid to WRBrising edge 5 ns - - td2 Delay CSBfalling edge to RDY active - - 13 ns td3 Delay WRBfalling edge to RDYfalling edge - - 15 ns td5 Delay CSBrising edge to RDY high-Z - - 9 ns tpw1 WRB Low time 30 ns 188 ns - tpw2 RDY Low time 15 ns - 173 ns tpw3 ALE High time 5 ns - - th1 Hold AD address valid after ALEfalling edge 9 ns - - th2 Hold CSB Low after WRBrising edge 0 ns - - th3 Hold WRB Low after RDYrising edge 0 ns - - th4 AD data hold valid after WRBrising edge 7 ns - - tp1 Time between ALEfalling edge and WRBfalling edge 0 ns - - tp2 Time between consecutive accesses (WRBrising edge to ALErising edge) 1600 ns - - Revision 1.01/August 2003 (c) Semtech Corp. Page 16 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Serial Mode In Serial Mode, the device is configured to interface with a serial microprocessor bus. Figure 12 and Figure 13 show the timing diagrams of read and write accesses for this mode. The serial interface can be SPI compatible. The Motorola SPI convention is such that address and data is transmitted and received MSB first. On the ACS8110, device address and data are transmitted and received LSB first. Address, read/write control and data on the SDI pin is latched into the device on the rising edge of the SCLK. During a read operation, serial data output on the SDO pin can be read out of the device on either the rising or falling edge of the SCLK depending on the logic level of CLKE. For standard Motorola SPI compliance, data should be clocked out of the SDO pin on the rising edge of the SCLK so that it may be latched into the microprocessor on the falling edge of the SCLK. The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1). Figure 12 Read Access Timing in Serial Mode CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0) = SDI R/W tpw1 A0 A1 A2 A3 A4 A5 A6 td1 AD(0)=SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 ALE=SCLK _ A(0)=SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 AD(0)=SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 F8530D_013ReadAccSerial_01 Table 11 Read Access Timing in Serial Mode (For use with Figure 12) Symbol Parameter MIN TYP MAX tsu1 Setup SDI valid to SCLKrising edge 4 ns - - tsu2 Setup CSBfalling edge to SCLKrising edge 14 ns - - td1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 18 ns Revision 1.01/August 2003 (c) Semtech Corp. Page 17 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 11 Read Access Timing in Serial Mode (For use with Figure 12) (cont...) Symbol Parameter MIN TYP MAX - - 16 ns td2 Delay CSBrising edge to SDO high-Z tpw1 SCLK Low time 22 ns - - tpw2 SCLK High time 22 ns - - th1 Hold SDI valid after SCLKrising edge 6 ns - - th2 Hold CSB Low after SCLKrising edge, for CLKE = 0 Hold CSB Low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 10 ns - - Figure 13 Write Access Timing in Serial Mode CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0)=SDI AD(0)=SDO R/W tpw1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Output not driven, pulled low by internal resistor F8110D_014WriteAccSerial_02 Table 12 Write Access Timing in Serial Mode (For use with Figure 13) Symbol Parameter MIN TYP MAX tsu1 Setup SDI valid to SCLKrising edge 4 ns - - tsu2 Setup CSBfalling edge to SCLKrising edge 14 ns - - tpw1 SCLK Low time 22 ns - - tpw2 SCLK High time 22 ns - - th1 Hold SDI valid after SCLKrising edge 6 ns - - th2 Hold CSB Low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 10 ns - - Revision 1.01/August 2003 (c) Semtech Corp. Page 18 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET EPROM Mode This mode is suitable for use with an EPROM, in which configuration data is stored (one-way communication - status information will not be accessible). A state machine internal to the ACS8110 device will perform numerous EPROM read operations to read the data out of the EPROM. In EPROM mode, the ACS8110 takes control of the bus as Master and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns) after device set-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Figure 14 shows the access timing of the device in EPROM mode. Further information can be found in the AMD AM27C64 datasheet. Figure 14 Access Timing in EPROM mode CSB (=OEB) address A tacc AD Z Z data F8110D_015ReadAccEEPROM_01 Table 13 Access Timing in EPROM mode (For use with Figure 14) Symbol tacc Parameter Delay CSBfalling edge or A change to AD valid MIN TYP MAX - - 920 ns Clock Multiplexer Each PRI input port n (n = 0 to 3) has a 3:1 multiplex function allowing selection from one of RCLK(n), ALTCLK(n) inputs or Frame_Sync(n) (8 kHz strobe extracted from the input port framers); the selected signal being output on SELCLK(n). This feature allows several SSM Handlers to be daisy-chained together, multiplexing many sources down to a few which are then fed to one SETS device, effectively expanding the number of clock inputs that can be handled by a single SETS device. Revision 1.01/August 2003 (c) Semtech Corp. Page 19 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Register Map PRELIMINARY The ACS8110 SSM Handler register block is summarized in the Register Map in Table 15. Documentation describing register functionality in detail may be made available on request. Register Paging The ACS8110 uses register paging to extend the address range beyond the nominal address space of 128 locations given by the physical interface limit. Address 7F is reserved for the page address. This can be accessed from every page of addresses. Number of Address Locations Table 14 Number of Address Locations per Reg. Page 0 No. of Registers 122 Look Up Tables e.g., Cnfg_lut_stm_e1, and the 2nd Order priority values, Cnfg_2nd_order_priority_ pt0/_pt1 SSM Positions Within a Register Where SSMs are written to or read from a register, then they have the following orientation within an 8-bit register: Register Organization Reg. Page No. DATASHEET 1 2 3 4 5 Total 117 85 66 98 82 570 Terminology RO = Read Only R/W = Read/write n/a = Not applicable "-" or shading = "Not used" X = "Not defined" Reg. 1/0B, Bits [3:1] = Bit 3, Bit 2 and Bit 1 of register address 0B (hexadecimal), with Register Page 1 (decimal) selected (Page 1 selected by writing 01 to 7F). Defaults given in Register Map show values under ANSI configuration. Configuration ("Cnfg_") Registers For fields designated "Cnfg_...". Such fields, when applied or changed via the P interface, are not synchronized in any way to any internal signals or timing of the SSM Handler. They are expected to be applied on power-up of the device. The effect of the change itself on any such field while the device is in service, is not specified. They are assumed to be static values while the SSM Handler is processing SSMs. These fields include the SSM to QL Revision 1.01/August 2003 (c) Semtech Corp. (a) If a register is used for SSMs as conveyed in E1 frame, then an entry is written: Bits [7:4] = 0, Bits [3:0] SSM value corresponding to San1, San2, San3, San4, where San1 is transmitted first, and as defined in G.704. (b) If a register is used for SSMs as conveyed in DS1 frame, then an entry is written: Bits [7:6] = 0, bits [5:0] = SSM value corresponding to P6, P5, P4, P3, P2, P1, of the DS1 bit patterned message designation 0 P6P5P4P3P2P1 0 11111111, and where in the datalink of a DS1 serial stream P1 is transmitted first. (c) If a register is used for SSMs as conveyed in STM-N frame, then an entry is written: Bits [7:4] = 0, Bits [3:0] = Bits 5 to 8 of the SOH S1 byte, where S1 byte Bit 5 is transmitted first, and as defined in G.707, section 9.2.2.11. (d) If a register is used for SSMs as conveyed in OC-N frame, then an entry is written: Bits [7:4] = 0, Bits [3:0] = Bits 5 to 8 of the SOH S1 byte, where S1 byte Bit 5 is transmitted first, and as defined in G.707, section 9.2.2.11. Registers affected by SSM positioning are: z Cntrl_ssm_insert_value z Cntrl_external_ssm_value z Cnfg_lut_stm_e1 z Cnfg_lut_ocn_gen1/ _gen2 z Cnfg_lut_ds1_gen1/ _gen2 z Cnfg_lut_user z Sts_selected_channel_pt0/ _pt1 z Sts_ssm_dus_ocn/ _ds1 z Sts_ssm_dnu_sdh_e1 z Sts_ssm_pers z Sts_ssm_filtered Page 20 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map Default (hex) Data Bit Page/ Address (hex) Register Name 0/00 10 Chip_id (Least significant byte) 0/01 81 Chip_id (Most significant byte) 0/02 01 Chip_revision (8 bits) Cntrl_ssm_insert_value Output Port 0 E1 0/04 18 (RO) = Read Only Otherwise all Read/Write Chip_id (RO) Chip_revision (RO) 7 (MSB) 6 5 4 3 2 1 0 (LSB) 0 0 0 0 SSM value bit for San1 SSM value bit for San2 SSM value bit for San3 SSM value bit for San4 0 0 SSM value bit for P6 SSM value bit for P5 SSM value bit for P4 SSM value bit for P3 SSM value bit for P2 SSM value bit for P1 Output Port 1 E1 0/05 18 0 0 0 0 SSM value bit for San1 SSM value bit for San2 SSM value bit for San3 SSM value bit for San4 0 SSM value bit for P6 SSM value bit for P5 SSM value bit for P4 SSM value bit for P3 SSM value bit for P2 SSM value bit for P1 Output Port 0 DS1 0F Output Port 1 DS1 0F 0 Cntrl_external_ssm_value Channel 1 0/06 0F Cntrl_external_ssm_value, Channel 1 Channel 2 0/07 0F Cntrl_external_ssm_value, Channel 2 Channel 3 0/08 0F Cntrl_external_ssm_value, Channel 3 Channel 4 0/09 0F Cntrl_external_ssm_value, Channel 4 Channel 5 0/0A 0F Cntrl_external_ssm_value, Channel 5 Channel 6 0/0B 0F Cntrl_external_ssm_value, Channel 6 Channel 7 0/0C 0F Cntrl_external_ssm_value, Channel 7 Channel 8 0/0D 0F Cntrl_external_ssm_value, Channel 8 Channel 9 0/0E 0F Cntrl_external_ssm_value, Channel 9 Channel 10 0/0F 0F Cntrl_external_ssm_value, Channel 10 Channel 11 0/10 0F Cntrl_external_ssm_value, Channel 11 Channel 12 0/11 0F Cntrl_external_ssm_value, Channel 12 Channel 13 0/12 0F Cntrl_external_ssm_value, Channel 13 Channel 14 0/13 0F Cntrl_signal_defect Cntrl_clear_wait_to_restore Cntrl_update_priority_status 0/14 00 Channel 8 0/15 00 0/16 00 Channel 8 0/17 00 0/18 00 Cntrl_external_ssm_value, Channel 14 Channel 7 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Update status for : Priority Table 1 Priority Table 0 Cntrl_selproc_ext_cmd_0 Selection Process 0 0/19 00 Target_channel_number (1 to 14) 00 Target_channel_number (1 to 14) Switch_request _options Cntrl_selproc_ext_cmd_1 Selection Process 1 0/1A Cntrl_selproc_lockout_pt0 Cntrl_selproc_lockout_pt1 Cnfg_intebl_input_port 0/1B 00 Channel 8 0/1C 00 0/1D 00 Channel 8 Channel 7 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 0/1E 00 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 0 0/20 00 Rai_changed Rclk_defect_ Changed Oof_ Changed Los_changed 00 2 0/22 00 Input_port_ Defect_ Changed Ais_changed 1 0/21 3 0/23 00 Cnfg_intebl_output_ports 0/24 00 Cnfg_intebl_ssm_value_ changed 0/25 00 Channel 8 0/26 00 Cnfg_intebl_received_message _ filtered_out 0/27 00 Channel 8 0/28 00 Cnfg_intebl_ssm_value_false 0/29 00 Channel 8 0/2A 00 Cnfg_intebl_ssm_inconsistency _ changed 0/2B 00 Channel 8 0/2C 00 Revision 1.01/August 2003 (c) Semtech Corp. Channel 7 Switch_request _options Channel 6 Tclk_defect_ Tclk_defect_ changed Port1 changed Port0 Channel 7 Channel 7 Channel 7 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Page 21 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Page/ Address (hex) Register Name (RO) = Read Only Otherwise all Read/Write Default (hex) Table 15 Register Map (cont...) Data Bit 7 (MSB) Cnfg_intebl_signal_failure_ changed 0/2D 00 Channel 8 0/2E 00 Cnfg_intebl_priority_table_ changed 0/2F 00 Cnfg_intebl_forcman_switch_ removed 0/30 Cnfg_intebl_selected_channel_ changed 6 5 4 3 2 1 0 (LSB) Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Table 1 Table 0 00 Table 1 Table 0 0/31 00 Table 1 Table 0 Cnfg_intebl_holdover 0/32 00 Intebl_sec_ opstate_ changed Intebl_forced_ holdover_ changed Cnfg_intebl_selproc_unstable 0/33 00 Table 1 Table 0 Sts_interrupt_location (RO) 0/34 00 Ssm_value_ false Received_ message_ filtered_out Ssm_value_ Changed Output_ports Input_port_3 Input_port_2 Input_port_1 Input_port_0 0/35 00 Selproc_ unstable Holdover Selected_ channel_ changed Forcman_ switch_ removed Priority_table_ changed Signal_failure_ Ssm_ changed inconsistancy_ changed Sts_interrupt_input_port Port 0 0/38 00 Rai_changed Rclk_defect_ changed Ais_changed 00 Los_ changed Port 2 0/3A 00 Input_port_ defect_ changed Oof_changed Port 1 0/39 Tclk_defect_ changed Output Port 1 Tclk_defect_ changed Output Port 0 Port 3 0/3B 00 Sts_interrupt_output_ports 0/3C Sts_interrupt_ssm_value_ changed 0/3D 00 Channel 8 Sts_interrupt_received_ message_filtered_out 0/3F 00 Channel 8 0/40 00 Sts_interrupt_ssm_value_false 0/41 00 Channel 8 0/42 00 0/3E Channel 7 00 Channel 7 00 Sts_interrupt_ssm_ inconsistency_changed 0/43 00 Channel 8 0/44 00 Sts_interrupt_signal_failure_ changed 0/45 00 Channel 8 0/46 00 Sts_interrupt_priority_table_ changed 0/47 Sts_interrupt_forcman_switch_ removed Channel 7 Channel 7 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 00 Table 1 Table 0 0/48 00 Table 1 Table 0 Sts_interrupt_selected_channel _changed 0/49 00 Table 1 Table 0 Sts_interrupt_holdover 0/4A 00 Sts_interrupt_ sec_opstate_ changed Forced_ holdover_ changed Sts_interrupt_selection_ process_unstable 0/4B 00 Table 1 Table 0 Port 0 0/4C XX Ais Los Channel 7 Sts_input_ports (RO) Sts_input_ports Rai Input_port_ defect Port 1 0/4D XX Port 2 0/4E XX Port 3 0/4F XX Sts_output_ports (RO) 0/50 XX Sts_ssm_inconsistency 0/51 XX 0/52 XX 0/53 XX 0/54 XX Rclk_defect Oof Sts_output_ports - TCLK_defect Output Port 1 Sts_signal_failure (RO) Channel 8 Channel 8 Revision 1.01/August 2003 (c) Semtech Corp. Channel 7 Channel 7 Output Port 0 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Page 22 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Default (hex) Data Bit Page/ Address (hex) Register Name Sts_forceman_switch_done 0/55 XX Sts_prioritizer_selection_ process_state (RO) 0/56 XX 0/57 XX Table 1 Sts_sec_operation_state (RO) 0/58 XX Sts_sec_operation_state Sec_sel_chan 0/59 XX Sec_ql 0/5A XX Sec_ssm_ocn_gen1 0/5B XX Sec_ssm_ocn_gen2 0/5C XX (RO) = Read Only Otherwise all Read/Write 7 (MSB) Sts_selected_channel_pt0 (RO) 6 5 4 3 2 1 Sts_forceman_switch_done Table 1 Table 0 Selected channel status for Priority Table 0, comprising the following (RO) sub-registers: Sec_sel_chan Sec_ql Sec_ssm_ocn_gen1 Sec_ssm_ocn_gen2 Sec_ssm_ds1_gen1 0/5D XX Sec_ssm_ds1_gen1 Sec_ssm_ds1_gen2 0/5E XX Sec_ssm_ds1_gen2 Sec_ssm_stmn_e1 0/5F XX Sec_ssm_user 0/60 XX Selproc_sel_chan 0/61 XX Selproc_sel_ql 0/62 XX Sts_selected_channel_pt1 (RO) Sec_ssm_stmn_e1 Sec_ssm_user Selproc_sel_chan, Table 0 Selproc_sel_ql Selected channel status for Priority Table 1, comprising the following (RO) sub-registers: Selproc_sel_chan Selproc_sel_chan 0/63 XX Selproc_sel_ql 0/64 XX Selproc_sel_ql Selproc_sel_ssm_ocn_gen1 0/65 XX Selproc_sel_ssm_ocn_gen1 Selproc_sel_ssm_ocn_gen2 0/66 XX Selproc_sel_ssm_ds1_gen1 0/67 XX Selproc_sel_ssm_ds1_gen1 Selproc_sel_ssm_ds1_gen2 0/68 XX Selproc_sel_ssm_ds1_gen2 Seproc_sel_ssm_stmn_e1 0/69 XX Selproc_sel_ssm_user 0/6A XX Selproc_sel_ql Seproc_sel_ssm_stmn_e1 Selproc_sel_ssm_user (Table 1) Sts_ssm_dus_ocn Sts_ssm_dus_ocn (RO) 0/6B 0F Sts_ssm_dus_ds1 (RO) 0/6C 1F Sts_ssm_dnu_sdh_e1 (RO) 0/6D 0F Sts_prioritizer_status_priority_ values_pt0 (RO) (Priority Table 0) 0/70 XX (Priority value) Channel 2 (Priority value) Channel 1 0/71 XX (Priority value) Channel 4 (Priority value) Channel 3 0/72 XX (Priority value) Channel 6 (Priority value) Channel 5 0/73 XX (Priority value) Channel 8 (Priority value) Channel 7 0/74 XX (Priority value) Channel 10 (Priority value) Channel 9 0/75 XX (Priority value) Channel 12 (Priority value) Channel 11 0/76 XX (Priority value) Channel 14 (Priority value) Channel 13 0/77 XX (Priority value) Channel 2 (Priority value) Channel 1 0/78 XX (Priority value) Channel 4 (Priority value) Channel 3 0/79 XX (Priority value) Channel 6 (Priority value) Channel 5 0/7A XX (Priority value) Channel 8 (Priority value) Channel 7 0/7B XX (Priority value) Channel 10 (Priority value) Channel 9 0/7C XX (Priority value) Channel 12 (Priority value) Channel 11 0/7D XX (Priority value) Channel 14 Sts_prioritizer_status_priority_ values_pt1 (RO) (Priority Table 1) Cnfg_protection_key 0/7E Sts_ssm_dus_ds1 Sts_ssm_dnu_sdh_e1 85 (Priority value) Channel 13 Cnfg_protection_key Page_address Page_address 0/7F 00 Chip_id (RO) 1/00 10 Chip_id (Least significant byte) 1/01 81 Chip_id (Most significant byte) 1/02 01 Input Port 0 Cnfg_input_port_a 1/04 81 Chip_revision (RO) 0 (LSB) Sts_forceman_switch_done Table 0 Cnfg_input_port_b 1/05 01 Input Port 1 Cnfg_input_port_a 1/06 81 Cnfg_input_port_b 1/07 01 Input Port 2 Cnfg_input_port_a 1/08 81 Cnfg_input_port_b 1/09 01 Revision 1.01/August 2003 (c) Semtech Corp. Chip_revision (8 bits) E1_sabit_select Inhibit_ crcalign Line_code_ bypass E1_sabit_select Inhibit_ crcalign Line_code_ bypass E1_sabit_select Inhibit_ crcalign Line_code_ bypass Page 23 Line_code_ select Multiframe_ format Ds1_e1_select Disable Rclk_polarity Los_polarity Line_code_ select Multiframe_ format Ds1_e1_select Disable Rclk_polarity Los_polarity Line_code_ select Multiframe_ format Ds1_e1_select Disable Rclk_polarity Los_polarity www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Page/ Address (hex) Register Name (RO) = Read Only Otherwise all Read/Write Default (hex) Table 15 Register Map (cont...) Input Port 3 Cnfg_input_port_a 1/0A 81 Cnfg_input_port_b 1/0B 01 Output Port 0 Cnfg_output_port_a 1/0C Data Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) E1_sabit_select Inhibit_ crcalign Line_code_ bypass Line_code_ select Disable Rclk_polarity Los_polarity E1_sabit_select Ais_insert Line_code_ bypass Line_code_ select Ds1_ multiframe_ format Ds1_e1_select Squelch Squelch_on_ clock_fail Config_tclk_ polarity Insert_rai 91 Cnfg_output_port_b 1/0D 00 E1_sabit_select Ais_insert Multiframe_ format Ds1_e1_select Output Port 1 Cnfg_output_port_a 1/0E Line_code_ bypass Line_code_ select Ds1_ multiframe_ format Ds1_e1_select 91 Cnfg_output_port_b 1/0F 00 Squelch Squelch_on_ clock_fail Config_tclk_ polarity Insert_rai Cnfg_ql_mode Cnfg_interrupt _inactive_ state Cnfg_interrupt _polarity Cnfg_output_port_payload 1/10 FF Cnfg_general 1/11 06 Cnfg_clock_mux 1/12 00 Cnfg_signal_type 1/13 33 Cnfg_signal_type, Channel 2 Cnfg_signal_type, Channel 1 1/14 33 Cnfg_signal_type, Channel 4 Cnfg_signal_type, Channel 3 1/15 11 Cnfg_signal_type, Channel 6 Cnfg_signal_type, Channel 5 1/16 11 Cnfg_signal_type, Channel 8 Cnfg_signal_type, Channel 7 1/17 11 Cnfg_signal_type, Channel 10 Cnfg_signal_type, Channel 9 1/18 11 Cnfg_signal_type, Channel 12 Cnfg_signal_type, Channel 11 Cnfg_signal_type, Channel 14 1/19 11 Cnfg_message_source 1/1A 00 Cnfg_bypass_pers_check 1/1B F0 1/1C 3F Cnfg_output_port_payload Cnfg_forced_ holdover Clock output on pin SELCLK 3 Channel 8 Cnfg_pers_check_value_ stm_e1 1/1D 33 ocn_gen1 1/1E 88 Channel 7 Clock output on pin SELCLK 2 Cnfg_ql_comp _selchan_ enable Clock output on pin SELCLK 1 Clock output on pin SELCLK 0 Cnfg_signal_type, Channel 13 Channel 4 Channel 3 Channel 2 Channel 1 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Cnfg_pers_check_stm_e1: X value Cnfg_pers_check_stm_e1: Y value Cnfg_pers_check_ocn_gen1: X value Cnfg_pers_check_ocn_gen1: Y value ocn_gen2 1/1F 88 Cnfg_pers_check_ocn_gen2: X value Cnfg_pers_check_ocn_gen2: Y value ds1_gen1 1/20 7A Cnfg_pers_check_ds1_gen1: X value Cnfg_pers_check_ds1_gen1: Y value ds1_gen2 1/21 7A Cnfg_pers_check_ds1_gen2: X value Cnfg_pers_check_ds1_gen2: Y value user 1/22 7A Cnfg_pers_check_user: X value 1/23 00 Channel 8 Channel 7 1/24 00 Cnfg_bypass_filter Cnfg_ssm_not_supp_type Cnfg_ssm_inconsistency_units Cnfg_ssm_inconsistency_time Cnfg_pers_check_user: Y value Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 1/25 55 Channel 4 Channel 3 Channel 2 Channel 1 1/26 55 Channel 8 Channel 7 Channel 6 Channel 5 1/27 55 Channel 12 Channel 11 Channel 10 Channel 9 1/28 05 Channel 14 Channel 13 1/29 00 Channel 8 1/2A 00 1/2B 64 1/2C 64 Cnfg_ssm_inconsistency_time, Channel 2 1/2D 64 Cnfg_ssm_inconsistency_time, Channel 3 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Cnfg_ssm_inconsistency_time, Channel 1 1/2E 64 Cnfg_ssm_inconsistency_time, Channel 4 1/2F 64 Cnfg_ssm_inconsistency_time, Channel 5 1/30 64 Cnfg_ssm_inconsistency_time, Channel 6 1/31 64 Cnfg_ssm_inconsistency_time, Channel 7 1/32 64 Cnfg_ssm_inconsistency_time, Channel 8 1/33 64 Cnfg_ssm_inconsistency_time, Channel 9 1/34 64 Cnfg_ssm_inconsistency_time, Channel 10 1/35 64 Cnfg_ssm_inconsistency_time, Channel 11 1/36 64 Cnfg_ssm_inconsistency_time, Channel 12 1/37 64 Cnfg_ssm_inconsistency_time, Channel 13 1/38 64 Cnfg_ssm_inconsistency_time, Channel 14 Revision 1.01/August 2003 (c) Semtech Corp. Page 24 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Page/ Address (hex) Default (hex) Register Name (RO) = Read Only Otherwise all Read/Write Cnfg_sigfail_time_select 1/39 00 Data Bit 7 (MSB) 6 5 4 Channel 4 3 2 Channel 3 1 0 (LSB) Channel 2 Channel 1 Channel 5 1/3A 00 Channel 8 Channel 7 Channel 6 1/3B 00 Channel 12 Channel 11 Channel 10 Channel 9 1/3C 00 Channel 14 Channel 13 Cnfg_sigfail_units Configuration Set 0 1/3D 00 tho units twtr units Configuration Set 1 1/3E 00 tho units twtr units Configuration Set 2 1/3F 00 tho units twtr units Configuration Set 3 1/40 00 tho units twtr units Cnfg_sigfail_ho_time Configuration Set 0 1/41 19 Cnfg_sigfail_ho_time, Configuration Set 0 Configuration Set 1 1/42 19 Cnfg_sigfail_ho_time, Configuration Set 1 Configuration Set 2 1/43 19 Cnfg_sigfail_ho_time, Configuration Set 2 Configuration Set 3 1/44 19 Cnfg_sigfail_ho_time, Configuration Set 3 Cnfg_sigfail_wtr_time Configuration Set 0 1/45 64 Cnfg_sigfail_wtr_time, Configuration Set 0 Configuration Set 1 1/46 64 Cnfg_sigfail_wtr_time, Configuration Set 1 Configuration Set 2 1/47 64 Cnfg_sigfail_wtr_time, Configuration Set 2 Configuration Set 3 1/48 64 Cnfg_tsw_channel_type_pt0 Cnfg_tsw_channel_type_pt1 1/50 F0 1/51 3F Cnfg_sigfail_wtr_time, Configuration Set 3 Channel 8 Channel 8 Channel 7 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 1/52 FF 1/53 3F Cnfg_tsw_a 1/54 0A Cnfg_tsw_a_to_b Cnfg_tsw_b 1/55 00 Cnfg_tsw_b_to_a Cnfg_tsw_b_to_b Cnfg_2nd_order_priority_pt0 1/57 FF Cnfg_2nd_order_priority_pt0, Channel 2 Cnfg_2nd_order_priority_pt0, Channel 1 1/58 FF Cnfg_2nd_order_priority_pt0, Channel 4 Cnfg_2nd_order_priority_pt0, Channel 3 1/59 FF Cnfg_2nd_order_priority_pt0, Channel 6 Cnfg_2nd_order_priority_pt0, Channel 5 1/5A FF Cnfg_2nd_order_priority_pt0, Channel 8 Cnfg_2nd_order_priority_pt0, Channel 7 1/5B FF Cnfg_2nd_order_priority_pt0, Channel 10 Cnfg_2nd_order_priority_pt0, Channel 9 1/5C Cnfg_tsw_a_to_a FF Cnfg_2nd_order_priority_pt0, Channel 12 Cnfg_2nd_order_priority_pt0, Channel 11 1/5D FF Cnfg_2nd_order_priority_pt0, Channel 14 Cnfg_2nd_order_priority_pt0, Channel 13 1/5E FF Cnfg_2nd_order_priority_pt1, Channel 2 Cnfg_2nd_order_priority_pt1, Channel 1 1/5F FF Cnfg_2nd_order_priority_pt1, Channel 4 Cnfg_2nd_order_priority_pt1, Channel 3 1/60 FF Cnfg_2nd_order_priority_pt1, Channel 6 Cnfg_2nd_order_priority_pt1, Channel 5 1/61 FF Cnfg_2nd_order_priority_pt1, Channel 8 Cnfg_2nd_order_priority_pt1, Channel 7 1/62 FF Cnfg_2nd_order_priority_pt1, Channel 10 Cnfg_2nd_order_priority_pt1, Channel 9 1/63 FF Cnfg_2nd_order_priority_pt1, Channel 12 Cnfg_2nd_order_priority_pt1, Channel 11 1/64 FF Cnfg_2nd_order_priority_pt1, Channel 14 Cnfg_2nd_order_priority_pt1, Channel 13 Cnfg_ql_prov1 1/65 0A cnfg_ql_prov1_offset cnfg_ql_prov1_ql_code Cnfg_ql_prov2 1/66 0F cnfg_ql_prov2_offset cnfg_ql_prov2_ql_code Cnfg_ql_local_clock 1/67 07 Cnfg_ql_comp_channel_enable 1/68 FF 1/69 3F Cnfg_2nd_order_priority_pt1 Cnfg_ql_fixed_value Cnfg_ql_local_clock Channel 8 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 1/6A 0F Cnfg_ql_fixed_value Channel 1 1/6B 0F Cnfg_ql_fixed_value Channel 2 1/6C 0F Cnfg_ql_fixed_value Channel 3 1/6D 0F Cnfg_ql_fixed_value Channel 4 1/6E 0F Cnfg_ql_fixed_value Channel 5 1/6F 0F Cnfg_ql_fixed_value Channel 6 1/70 0F Cnfg_ql_fixed_value Channel 7 1/71 0F Cnfg_ql_fixed_value Channel 8 1/72 0F Cnfg_ql_fixed_value Channel 9 1/73 0F Cnfg_ql_fixed_value Channel 10 1/74 0F Cnfg_ql_fixed_value Channel 11 1/75 0F Cnfg_ql_fixed_value Channel 12 Revision 1.01/August 2003 (c) Semtech Corp. Page 25 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Default (hex) Data Bit Page/ Address (hex) Register Name 1/76 0F 1/77 0F 1/78 00 Channel 8 1/79 00 Cnfg_output_ql 1/7A 00 Cnfg_upsel (uP mode select) 1/7D XX Cnfg_protection_key 1/7E (RO) = Read Only Otherwise all Read/Write Cnfg_ql_fixed_value cont... Cnfg_ql_overwrite 7 (MSB) 6 5 4 3 2 1 Cnfg_ql_fixed_value Channel 14 Channel 7 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 14 Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Cnfg_ gen2_gen1_ mapping Cnfg_upsel 85 Cnfg_protection_key Page_address Page_address 1/7F 01 Cnfg_ql_to_ql_lut_ansi 2/00 01 2/01 02 Output_ql_ansi_for_input_ql-stu (Input QL Code 2) 2/02 03 Output_ql_ansi_for_input_ql-st2 (Input QL Code 3) 2/03 04 Output_ql_ansi_for_input_ql-tnc (Input QL Code 4) 2/04 05 Output_ql_ansi_for_input_ql-st3e (Input QL Code 5) Cnfg_ql_to_ql_lut_etsi 0 (LSB) Cnfg_ql_fixed_value Channel 13 Output_ql_ansi_for_input_ql-prs (Input QL Code 1) 2/05 06 Output_ql_ansi_for_input_ql-st3 (Input QL Code 6) 2/06 07 Output_ql_ansi_for_input_ql-smc (Input QL Code 7) 2/07 08 Output_ql_ansi_for_input_ql-st4 (Input QL Code 8) 2/08 09 Output_ql_ansi_for_input_ql-pno (Input QL Code 9) Output_ql_ansi_for_input_ql-dus (Input QL Code 10) 2/09 0A 2/0A 01 Output_ql_ansi_for_input_ql-prc (Input QL Code 11) 2/0B 04 Output_ql_ansi_for_input_ql-ssu_a (Input QL Code 12) 2/0C 06 Output_ql_ansi_for_input_ql-ssu_b (Input QL Code 13) 2/0D 07 Output_ql_ansi_for_input_ql-sec (Input QL Code 14) 2/0E Output_ql_ansi_for_input_ql-dnu (Input QL Code 15) 0A 2/0F 0A Output_ql_ansi_for_input_ql-inv (Input QL Code 16) 2/10 0A Output_ql_ansi_for_input_ql-failed (Input QL Code 17) 2/11 0A Output_ql_ansi_for_input_ql-unav (Input QL Code 18) 2/12 0A Output_ql_ansi_for_input_ql-nsupp (Input QL Code 19) Output_ql_ansi_for_input_ql-unc (Input QL Code 20) 2/13 0A 2/14 02 Output_ql_ansi_for_input_ql-unk (Input QL Code 21) 2/15 09 Output_ql_ansi_for_input_ql-pno2 (Input QL Code 22) 2/20 0B Output_ql_etsi_for_input_ql-prs (Input QL Code 1) 2/21 0C Output_ql_etsi_for_input_ql-stu (Input QL Code 2) 2/22 0C Output_ql_etsi_for_input_ql-st2 (Input QL Code 3) 2/23 0D Output_ql_etsi_for_input_ql-tnc (Input QL Code 4) 2/24 0D Output_ql_etsi_for_input_ql-st3e (Input QL Code 5) 2/25 0E Output_ql_etsi_for_input_ql-st3 (Input QL Code 6) 2/26 0E Output_ql_etsi_for_input_ql-smc (Input QL Code 7) 2/27 0F Output_ql_etsi_for_input_ql-st4 (Input QL Code 8) 2/28 0F Output_ql_etsi_for_input_ql-pno (Input QL Code 9) 2/29 0F Output_ql_etsi_for_input_ql-dus (Input QL Code 10) 2/2A 0B Output_ql_etsi_for_input_ql-prc (Input QL Code 11) 2/2B 0C Output_ql_etsi_for_input_ql-ssu_a (Input QL Code 12) 2/2C 0D Output_ql_etsi_for_input_ql-ssu_b (Input QL Code 13) 2/2D 0E Output_ql_etsi_for_input_ql-sec (Input QL Code 14) 2/2E Output_ql_etsi_for_input_ql-dnu (Input QL Code 15) 0F 2/2F 0F Output_ql_etsi_for_input_ql-inv (Input QL Code 16) 2/30 0F Output_ql_etsi_for_input_ql-failed (Input QL Code 17) 2/31 0F Output_ql_etsi_for_input_ql-unav (Input QL Code 18) 2/32 0F Output_ql_etsi_for_input_ql-nsupp (Input QL Code 19) 2/33 0F Output_ql_etsi_for_input_ql-unc (Input QL Code 20) 2/34 0C Output_ql_etsi_for_input_ql-unk (Input QL Code 21) 2/35 0F Output_ql_etsi_for_input_ql-pno2 (Input QL Code 22) Revision 1.01/August 2003 (c) Semtech Corp. Page 26 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Default (hex) Cnfg_ql_to_ql_lut_user Data Bit Page/ Address (hex) Register Name (RO) = Read Only Otherwise all Read/Write 2/40 0F 2/41 0F Output_ql_user_for_input_ql-stu (Input QL Code 2) 2/42 0F Output_ql_user_for_input_ql-st2 (Input QL Code 3) 2/43 0F Output_ql_user_for_input_ql-tnc (Input QL Code 4) 2/44 0F Output_ql_user_for_input_ql-st3e (Input QL Code 5) 2/45 0F Output_ql_user_for_input_ql-st3 (Input QL Code 6) 2/46 0F Output_ql_user_for_input_ql-smc (Input QL Code 7) 7 (MSB) 6 5 4 3 2 0 (LSB) 2/47 0F Output_ql_user_for_input_ql-st4 (Input QL Code 8) 2/48 0F Output_ql_user_for_input_ql-pno (Input QL Code 9) 2/49 0F Output_ql_user_for_input_ql-dus (Input QL Code 10) 2/4A 0F Output_ql_user_for_input_ql-prc (Input QL Code 11) 2/4B 0F Output_ql_user_for_input_ql-ssu_a (Input QL Code 12) 2/4C 0F Output_ql_user_for_input_ql-ssu_b (Input QL Code 13) 2/4D 0F Output_ql_user_for_input_ql-sec (Input QL Code 14) 2/4E Output_ql_user_for_input_ql-dnu (Input QL Code 15) 0F 2/4F 0F Output_ql_user_for_input_ql-inv (Input QL Code 16) 2/50 0F Output_ql_user_for_input_ql-failed (Input QL Code 17) 2/51 0F Output_ql_user_for_input_ql-unav (Input QL Code 18) 2/52 0F Output_ql_user_for_input_ql-nsupp (Input QL Code 19) 2/53 0F Output_ql_user_for_input_ql-unc (Input QL Code 20) 2/54 0F Output_ql_user_for_input_ql-unk (Input QL Code 21) 2/55 0F Sts_crc_count (RO) Input Port 0 2/60 00 LSB Input Port 0 MSB Input Port 0 Output_ql_user_for_input_ql-pno2 (Input QL Code 22) 2/61 00 Input Port 1 2/62 00 LSB Input Port 1 2/63 00 MSB Input Port 1 Input Port 2 2/64 00 LSB Input Port 2 2/65 00 MSB Input Port 2 Input Port 3 2/66 00 LSB Input Port 3 2/67 00 MSB Input Port 3 Input Port 3 Cntrl_crc_count_strobe 2/68 00 Cntrl_channel_snapshot 2/70 00 Sts_channel_ snapshot_ ready Sts_ssm_pers 2/71 FF Sts_ssm_pers Sts_ssm_filtered 2/72 FF Sts_ssm_filtered Input Port 2 2/73 10 Sts_ql_lut_code Sts_ql_lut_stds 2/74 1F Sts_ql_lut_stds Sts_ql_adaptn 2/75 10 Sts_ql_adaptn Sts_ql_sd_tt 2/76 10 Sts_ql_sd_tt Sts_ql_sig_fail 2/77 10 Sts_ql_sig_fail Cnfg_protection_key 2/7E 85 Page_address 2/7F 02 Entry 0 3/00 02 Input Port 1 Cnfg_protection_key Page_address Table_entry_0_ql_code 3/01 02 Table_entry_0_ql_level Entry 1 3/02 01 Table_entry_1_ql_code 3/03 01 Table_entry_1_ql_level Entry 2 3/04 10 Table_entry_2_ql_code 3/05 1F Table_entry_2_ql_level Entry 3 3/06 10 Table_entry_3_ql_code 3/07 1F Table_entry_3_ql_level Entry 4 3/08 10 Table_entry_4_ql_code 3/09 1F Table_entry_4_ql_level Entry 5 3/0A 10 Table_entry_5_ql_code 3/0B 1F Table_entry_5_ql_level Revision 1.01/August 2003 (c) Semtech Corp. Input Port 0 Cntrl_channel_snapshot_channel Sts_ql_lut_code Cnfg_lut_ocn_gen1 1 Output_ql_user_for_input_ql-prs (Input QL Code 1) Page 27 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Cnfg_lut_ocn_gen1 cont.Entry 6 3/0C Default (hex) Register Name (RO) = Read Only Otherwise all Read/Write Page/ Address (hex) Table 15 Register Map (cont...) Data Bit 7 (MSB) 6 5 4 3 10 3/0D 1F Entry 7 3/0E 03 1 Table_entry_6_ql_level 3/0F 03 Table_entry_7_ql_level 10 Table_entry_8_ql_code 3/11 1F Table_entry_8_ql_level Entry 9 3/12 10 Table_entry_9_ql_code 3/13 1F Table_entry_9_ql_level Entry 10 3/14 06 Table_entry_10_ql_code 3/15 04 Table_entry_10_ql_level Entry 11 3/16 10 Table_entry_11_ql_code 3/17 1F Table_entry_11_ql_level Entry 12 3/18 07 Table_entry_12_ql_code 3/19 05 Table_entry_12_ql_level Entry 13 3/1A 10 Table_entry_13_ql_code 3/1B 1F Table_entry_13_ql_level Entry 14 3/1C 09 Table_entry_14_ql_code 3/1D 08 Table_entry_14_ql_level 0A Table_entry_15_ql_code 3/1F 07 Table_entry_15_ql_level Entry 0 3/40 02 Table_entry_0_ql_code 3/41 02 Table_entry_0_ql_level Entry 1 3/42 01 Table_entry_1_ql_code 3/43 01 Table_entry_1_ql_level Entry 2 3/44 10 Table_entry_2_ql_code 3/45 1F Table_entry_2_ql_level Entry 3 3/46 10 Table_entry_3_ql_code 3/47 1F Table_entry_3_ql_level Entry 4 3/48 04 Table_entry_4_ql_code 3/49 04 Table_entry_4_ql_level Entry 5 3/4A 10 Table_entry_5_ql_code 3/4B 1F Table_entry_5_ql_level Entry 6 3/4C 10 Table_entry_6_ql_code 3/4D 1F Entry 7 3/4E 03 Table_entry_6_ql_level Table_entry_7_ql_code 3/4F 03 Table_entry_7_ql_level Entry 8 3/50 10 Table_entry_8_ql_code 3/51 1F Table_entry_8_ql_level Entry 9 3/52 10 Table_entry_9_ql_code 3/53 1F Table_entry_9_ql_level Entry 10 3/54 06 Table_entry_10_ql_code 3/55 06 Table_entry_10_ql_level Entry 11 3/56 10 Table_entry_11_ql_code 3/57 1F Table_entry_11_ql_level Entry 12 3/58 07 Table_entry_12_ql_code 3/59 07 Table_entry_12_ql_level Entry 13 3/5A 05 Table_entry_13_ql_code 3/5B 05 Table_entry_13_ql_level Entry 14 3/5C 09 Table_entry_14_ql_code Table_entry_14_ql_level 3/5D 0A Entry 15 3/5E 0A 3/5F 09 Cnfg_protection_key 3/7E 85 Page_address 3/7F 03 Revision 1.01/August 2003 (c) Semtech Corp. 0 (LSB) Table_entry_7_ql_code Entry 8 3/10 Entry 15 3/1E Cnfg_lut_ocn_gen2 2 Table_entry_6_ql_code Table_entry_15_ql_code Table_entry_15_ql_level Cnfg_protection_key Page_address Page 28 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Cnfg_lut_ds1_gen1 Default (hex) Register Name (RO) = Read Only Otherwise all Read/Write Page/ Address (hex) Table 15 Register Map (cont...) Entry 0 4/00 02 4/01 01 4/02 01 Entry 1 4/03 04 4/04 02 4/05 02 Entry 2 4/06 06 4/07 03 4/08 03 Entry 3 4/09 3C 4/0A 10 4/0B 1F Entry 4 4/0C 3E Data Bit 7 (MSB) 6 5 1F Entry 5 4/0F 08 4/10 06 4/11 04 Entry 6 4/12 11 4/13 07 4/14 05 Entry 7 4/15 14 4/16 08 4/17 06 Entry 8 4/18 18 4/19 0A 4/1A 07 Entry 9 4/1B 20 4/1C 09 18 4/1F 0A 4/20 07 Entry 11 4/21 18 4/22 0A 4/23 07 Entry 12 4/24 18 4/25 0A 4/26 07 Entry 13 4/27 18 4/28 0A 4/29 07 Entry 14 4/2A 18 4/2B 0A 4/2C 07 Cnfg_lut_ds1_gen2 0A 4/2F 07 Entry 0 4/40 02 4/41 01 4/42 01 Entry 1 4/43 04 4/44 02 4/45 02 Entry 2 4/46 06 Revision 1.01/August 2003 (c) Semtech Corp. 1 0 (LSB) Table_entry_0_ql_level Table_entry_1_ssm_code Table_entry_1_ql_code Table_entry_1_ql_level Table_entry_2_ssm_code Table_entry_2_ql_code Table_entry_2_ql_level Table_entry_3_ssm_code Table_entry_3_ql_code Table_entry_3_ql_level Table_entry_4_ssm_code Table_entry_4_ql_code Table_entry_4_ql_level Table_entry_5_ssm_code Table_entry_5_ql_code Table_entry_5_ql_level Table_entry_6_ssm_code Table_entry_6_ql_code Table_entry_6_ql_level Table_entry_7_ssm_code Table_entry_7_ql_code Table_entry_7_ql_level Table_entry_8_ssm_code Table_entry_8_ql_code Table_entry_8_ql_level Table_entry_9_ssm_code Table_entry_9_ql_code Table_entry_9_ql_level Table_entry_10_ssm_code Table_entry_10_ql_code Table_entry_10_ql_level Table_entry_11_ssm_code Table_entry_11_ql_code Table_entry_11_ql_level Table_entry_12_ssm_code Table_entry_12_ql_code Table_entry_12_ql_level Table_entry_13_ssm_code Table_entry_13_ql_code Table_entry_13_ql_level Table_entry_14_ssm_code Table_entry_14_ql_code Table_entry_14_ql_level Entry 15 4/2D 18 4/2E 2 Table_entry_0_ql_code 4/1D 08 Entry 10 4/1E 3 Table_entry_0_ssm_code 4/0D 10 4/0E 4 Table_entry_15_ssm_code Table_entry_15_ql_code Table_entry_15_ql_level Table_entry_0_ssm_code Table_entry_0_ql_code Table_entry_0_ql_level Table_entry_1_ssm_code Table_entry_1_ql_code Table_entry_1_ql_level Table_entry_2_ssm_code Page 29 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Page/ Address (hex) Default (hex) Register Name (RO) = Read Only Otherwise all Read/Write Cnfg_lut_ds1_gen2 cont... 4/47 03 4/48 03 Entry 3 4/49 3C 4/4A 04 4/4B 04 Entry 4 4/4C 3E Data Bit 7 (MSB) 6 5 4 3 05 Entry 5 4/4F 08 4/50 06 4/51 06 Entry 6 4/52 11 4/53 07 4/54 07 Entry 7 4/55 14 4/56 08 4/57 08 Entry 8 4/58 18 4/59 0A 4/5A 09 Entry 9 4/5B 20 4/5C 09 18 4/5F 0A 4/60 09 Entry 11 4/61 18 4/62 0A 4/63 09 Entry 12 4/64 18 4/65 0A 4/66 09 Entry 13 4/67 18 4/68 0A 4/69 09 Entry 14 4/6A 18 4/6B 0A 4/6C 09 Table_entry_3_ql_code Table_entry_3_ql_level Table_entry_4_ssm_code Table_entry_4_ql_code Table_entry_4_ql_level Table_entry_5_ssm_code Table_entry_5_ql_code Table_entry_5_ql_level Table_entry_6_ssm_code Table_entry_6_ql_code Table_entry_6_ql_level Table_entry_7_ssm_code Table_entry_7_ql_code Table_entry_7_ql_level Table_entry_8_ssm_code Table_entry_8_ql_code Table_entry_8_ql_level Table_entry_9_ssm_code Table_entry_9_ql_code Table_entry_9_ql_level Table_entry_10_ssm_code Table_entry_10_ql_code Table_entry_10_ql_level Table_entry_11_ssm_code Table_entry_11_ql_code Table_entry_11_ql_level Table_entry_12_ssm_code Table_entry_12_ql_code Table_entry_12_ql_level Table_entry_13_ssm_code Table_entry_13_ql_code Table_entry_13_ql_level Table_entry_14_ssm_code Table_entry_14_ql_code Table_entry_14_ql_level Entry 15 4/6D 18 Cnfg_protection_key Page_address Cnfg_lut_stm_e1 4/6E 0A 4/6F 09 4/7E 85 4/7F 04 Entry 0 5/00 10 Table_entry_15_ssm_code Table_entry_15_ql_code Table_entry_15_ql_level Cnfg_protection_key Page_address Table_entry_0_ql_code 5/01 1F Table_entry_0_ql_level Entry 1 5/02 10 Table_entry_1_ql_code 5/03 1F Table_entry_1_ql_level Entry 2 5/04 0B Table_entry_2_ql_code 5/05 01 Table_entry_2_ql_level Entry 3 5/06 10 Table_entry_3_ql_code 5/07 1F Table_entry_3_ql_level Entry 4 5/08 0C Table_entry_4_ql_code 5/09 02 Table_entry_4_ql_level Entry 5 5/0A 10 Table_entry_5_ql_code 5/0B 1F Table_entry_5_ql_level Revision 1.01/August 2003 (c) Semtech Corp. 0 (LSB) Table_entry_2_ql_level 4/5D 0A Entry 10 4/5E 1 Table_entry_3_ssm_code 4/4D 05 4/4E 2 Table_entry_2_ql_code Page 30 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Cnfg_lut_stm_e1 cont... Entry 6 5/0C Default (hex) Register Name (RO) = Read Only Otherwise all Read/Write Page/ Address (hex) Table 15 Register Map (cont...) Data Bit 7 (MSB) 6 5 4 3 2 10 5/0D 1F Entry 7 5/0E 10 Table_entry_6_ql_level 5/0F 1F Table_entry_7_ql_level 0D Table_entry_8_ql_code 5/11 03 Table_entry_8_ql_level Entry 9 5/12 10 Table_entry_9_ql_code 5/13 0F Table_entry_9_ql_level Entry 10 5/14 10 Table_entry_10_ql_code 5/15 0F Table_entry_10_ql_level Entry 11 5/16 0E Table_entry_11_ql_code 5/17 04 Table_entry_11_ql_level Entry 12 5/18 10 Table_entry_12_ql_code 5/19 1F Table_entry_12_ql_level Entry 13 5/1A 10 Table_entry_13_ql_code 5/1B 1F Table_entry_13_ql_level Entry 14 5/1C 10 Table_entry_14_ql_code 5/1D 1F Cnfg_lut_user Table_entry_14_ql_level 0F 5/1F 05 Entry 0 5/40 FF 5/41 10 5/42 1F Entry 1 5/43 FF 5/44 10 5/45 1F Entry 2 5/46 FF 5/47 10 5/48 1F Entry 3 5/49 FF 5/4A 10 5/4B 1F Entry 4 5/4C FF Table_entry_15_ql_code Table_entry_15_ql_level Table_entry_0_ssm_code Table_entry_0_ql_code Table_entry_0_ql_level Table_entry_1_ssm_code Table_entry_1_ql_code Table_entry_1_ql_level Table_entry_2_ssm_code Table_entry_2_ql_code Table_entry_2_ql_level Table_entry_3_ssm_code Table_entry_3_ql_code Table_entry_3_ql_level Table_entry_4_ssm_code 5/4D 10 5/4E 1F Entry 5 5/4F FF 5/50 10 5/51 1F Entry 6 5/52 FF 5/53 10 5/54 1F Entry 7 5/55 FF 5/56 10 5/57 1F Entry 8 5/58 FF 5/59 10 5/5A 1F Entry 9 5/5B FF 5/5C 10 Table_entry_4_ql_code Table_entry_4_ql_level Table_entry_5_ssm_code Table_entry_5_ql_code Table_entry_5_ql_level Table_entry_6_ssm_code Table_entry_6_ql_code Table_entry_6_ql_level Table_entry_7_ssm_code Table_entry_7_ql_code Table_entry_7_ql_level Table_entry_8_ssm_code Table_entry_8_ql_code Table_entry_8_ql_level Table_entry_9_ssm_code Table_entry_9_ql_code Table_entry_9_ql_level 5/5D 1F Entry 10 5/5E FF 5/5F 10 5/60 1F Entry 11 5/61 FF 5/62 10 Revision 1.01/August 2003 (c) Semtech Corp. 0 (LSB) Table_entry_7_ql_code Entry 8 5/10 Entry 15 5/1E 1 Table_entry_6_ql_code Table_entry_10_ssm_code Table_entry_10_ql_code Table_entry_10_ql_level Table_entry_11_ssm_code Table_entry_11_ql_code Page 31 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 15 Register Map (cont...) Page/ Address (hex) Default (hex) Register Name 5/63 1F Entry 12 5/64 FF 5/65 10 5/66 1F Entry 13 5/67 FF (RO) = Read Only Otherwise all Read/Write Cnfg_lut_user cont... 5/68 10 5/69 1F Entry 14 5/6A FF 5/6B 10 5/6C 1F Data Bit 7 (MSB) 6 5 4 5/6E 10 1F Cnfg_protection_key 5/7E 85 Page_address 5/7F 05 2 1 0 (LSB) Table_entry_11_ql_level Table_entry_12_ssm_code Table_entry_12_ql_code Table_entry_12_ql_level Table_entry_13_ssm_code Table_entry_13_ql_code Table_entry_13_ql_level Table_entry_14_ssm_code Table_entry_14_ql_code Table_entry_14_ql_level Entry 15 5/6D FF 5/6F 3 Table_entry_15_ssm_code Table_entry_15_ql_code Table_entry_15_ql_level Cnfg_protection_key Page_address Alarms/Performance Reporting Channel Processing Alarms The SSM Handler monitors for the following defect conditions, and if present, reports these conditions individually using an interrupt mechanism, via the uP interface: Input Port Alarms z z z z z z Loss of Signal Defect (LOS) Receive Clock Fail defect Alarm Indication Signal Defect (AIS) Out of Frame Defect (OOF) Input Port Defect (Logical OR of the four previous defect conditions) Remote Alarm Indication (RAI) Each PRI output port signal is monitored for Transmit Clock Fail Defect. Revision 1.01/August 2003 (c) Semtech Corp. Synchronization Signal Failure (SSF) z SSM Inconsistent z SSM changed z Message filtered out z Clock Quality invalid (SSM value false) Prioritization /Channel Selection Alarms: A counter records Cyclic Redundancy Check (CRC) errors for performance reporting purposes. Output Port Alarms z z Priority Table changed z Selection Process unstable z Forced / Manual Switch removed T0/T4 Selected Channel Generation Alarms z Selected Channel changed z SEC operation state changed (Entered / Left Holdover) (T0 only) z Forced Holdover changed (T0 only) Page 32 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Electrical Specifications PRELIMINARY DATASHEET Maximum Ratings Important Note: The Absolute Maximum Ratings, Table 16, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 16 Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Supply Voltage VDDC, VDD_AN, VDDP VDD -0.5 3.6 V Input Voltage (non-supply pins) VIN -0.5 5.5 V VOUT - 3.6 V TA -40 +85 oC TSTOR -50 +150 oC Output Voltage (non-supply pins) Ambient Operating Temperature Range Storage Temperature Operating Conditions Table 17 Operating Conditions Parameter Symbol Minimum Typical Maximum Units VDD 3.0 3.3 3.6 V Ambient Temperature Range TA -40 - +85 oC Supply Current IDD - 50 100 mA Total Power Dissipation PTOT - - 330 mW Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Input Current IIN - - 10 A Supply Voltage VDDC, VDD_AN, VDDP DC Characteristics Table 18 DC Characteristics: LVTTL/LVCMOS Input Port Across all operating conditions, unless otherwise stated Parameter Revision 1.01/August 2003 (c) Semtech Corp. Page 33 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 19 DC Characteristics: LVTTL/LVCMOS Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Pull-up Resistor PU 53 70 113 k Input Current IIN - - 68 Table 20 DC Characteristics: LVTTL/LVCMOS Input Port with Internal Pull-up and Schmitt Trigger Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Pull-up Resistor PU 53 70 113 k Input Current IIN - - 68 Schmitt Trigger Low to High Threshold V T+ 1.47 1.5 1.5 V Schmitt Trigger High to Low Threshold V T- 0.89 0.93 0.95 V Table 21 DC Characteristics: LVTTL/LVCMOS Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Pull-down Resistor PD 43 58 118 k Input Current IIN - - 84 A Table 22 DC Characteristics: LVTTL/LVCMOS Input Port with Internal Pull-down and Schmitt Trigger Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VIN High VIH 2 - - V VIN Low VIL - - 0.8 V Pull-down Resistor PD 43 58 118 k Input Current IIN - - 84 A Schmitt Trigger Low to High Threshold V T+ 1.47 1.5 1.5 V Schmitt Trigger High to Low Threshold V T- 0.89 0.93 0.95 V Revision 1.01/August 2003 (c) Semtech Corp. Page 34 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Table 23 DC Characteristics: LVTTL/LVCMOS Output Port Across all operating conditions, unless otherwise stated Parameter Symbol Minimum Typical Maximum Units VOUT Low (lOL = 4 mA) VOL 0 - 0.4 V VOUT High (lOL = 4 mA) VOH 2.4 - - V ID - - 4 mA Drive Current DS1/E1 Input Port Interface Timing Output Port Interface Timing Figure 15 Input Port Timing Figure 16 Output Port Timing thigh tlow Tbit thigh RCLKn F8110D_016IpPortTiming_01, 100% TCLKn tlow Tbit F8110D_017OpPortTiming_01, 100% td RPOSn TPOSn RNEGn n = 0, 1, 2, 3 tsu TNEGn n = 0, 1, th F8110D_016IpPortTiming_01 Table 25 Output Port Timing Characteristics Table 24 Input Port Timing Characteristics Symbol Min Typ F8110D_017OpPortTiming_01 Symbol Max Min Typ Tbit (E1) 488 ns Tbit (E1) 488 ns Tbit (DS1) 648 ns Tbit (DS1) 648 ns tsu 5 ns td 2 ns th 5 ns thigh 100 ns thigh 100 ns tlow 100 ns tlow 100 ns Note...The clock edge to which tsu and th are relative, can be configured to either the positive or negative edge. In Figure 15, it is shown relative to the positive edge, Revision 1.01/August 2003 (c) Semtech Corp. Max 10 ns Note...The clock edge to which td is relative, can be configured to either the positive or negative edge. In Figure 16, it is shown relative to the positive edge. Page 35 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Jitter Characteristics PRELIMINARY Clock timing and any associated jitter is passed through from input to output pins of the SSM Handler, only for the following paths: DATASHEET coverage must exceed 50% of the area of the PCB covered by the underside of the package. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. 1.ALTCLK(n) to SELCLK(n), n = 0 to 3 JTAG 2.RCLK(n) to SELCLK(n), n = 0 to 3 3.TCLK(n) to TPOS(n), TNEG(n), n = 0 to 1 There is no intrinsic jitter on these paths. Reference Clock 12.8 MHz 50 ppm non temperature compensated crystal oscillator is required to provide the reference clock on REFCLK pin. Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper The JTAG connections on the ACS8110 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1[5], with the following minor exception, and the user should refer to the standard for further information. The output boundary scan cells do not capture data from the core, and so do not support INTEST. However this does not affect board testing. The TRST pin is implemented with a pull-up resistor as per IEEE 1149.1[5], therefore, for normal device operation (not in JTAG mode) either TRST must be grounded via a pull-down resistor, or the TCK signal must be applied. The JTAG timing diagram is shown in Figure 17. Figure 17 JTAG Timing tCYC TCK tSUR tHT TMS TDI tDOD TDO F8110D_022JTAGTiming_01 Table 26 JTAG Timing (for use with Figure 17) Parameter Symbol Minimum Typical Maximum Units Cycle Time tCYC 50 - - ns TMS/TDI to TCK rising edge time tSUR 3 - - ns TCK rising to TMS/TDI hold time tHT 23 - - ns tDOD - - 5 ns TCK falling to TDO valid . Revision 1.01/August 2003 (c) Semtech Corp. Page 36 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Package Information PRELIMINARY DATASHEET Figure 18 LQFP Package D 2 D1 1 3 AN2 AN3 1 Section A-A R1 S E 1 2 R2 B AN1 E1 A A B 3 AN4 L 4 L1 5 1 2 3 b A Section B-B 7 e A2 7 c c1 7 Seating plane A1 6 b1 7 b 8 Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm. 2 To be determined at seating plane. 3 Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4 Details of pin 1 identifier are optional but will be located within the zone indicated. 5 Exact shape of corners can vary. 6 A1 is defined as the distance from the seating plane to the lowest point of the package body. 7 These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8 Shows plating. Table 27 80 Pin LQFP Package Dimension Data (for use with Figure 18) Units: mm or stated otherwise D/E D1/ E1 A Min. - - - 0.05 1.35 - Nom. Max. 14.00 12.00 - - A1 A2 e AN1 AN2 AN3 AN4 - 11 11 2 0.10 1.40 0.50 12 12 6 1.60 0.15 1.45 Revision 1.01/August 2003 (c) Semtech Corp. - 13 13 10 0 R1 R2 L L1 - - 0.5 - 3.5 0.20 0.20 0.60 1.00 (ref) 7 Page 37 - - 0.75 - S b b1 c c1 0.20 0.215 0.222 0.135 0.126 - 0.220 0.235 0.150 0.127 - 0.225 0.245 0.166 0.128 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Figure 19 Typical 80-Pin LQFP Footprint 16. 16.3 mm 12.6 mm 12. 15.0 mm ((1) 15. 1.85 mm Notes: (i) Solderable to this limit (1). Pitch ch 0.5 m mm (ii) Square package - dimensions apply in both X and Y directions. idth h 0.22 .22 m mm Widt (iii) Typical example. The user is responsible for ensuring compatibility with PCB manufacturing process, etc. F8110LPBD_029LQFootprt80_01 Application Information Figure 20 SSM Handler as Part of the Semtech Synchronization Family of Devices Multiple Line cards mP/Serial Bus Line Card LOS SSMs Line info Recovered Clock Master Clock Master Sync Slave Clock Slave Sync Stand-by Clock Stand-by Sync Frame Sync Multi Frame Sync ACS8515 ACS8525 ACS8526 ACS8527 FRAMER SERDES E1/DS1 LINE CARD PROTECTION To/from SONET/SDH/PDH Network CMU Low Jitter up to 622 MHz Low Jitter/Low Skew Clock Distribution Backplane Slave Sync Card Master Sync Card Input CLK Sources Config. Priorities mP/Serial Bus Line info SSM Primary Ref. Input/ output RDATA TDATA TCLK ACS8510 ACS8520 ACS8522 ACS8530 Priorities TCLK RCLK Line I/F Unit SETS Output CLKs ACS8110 SSM HANDLER Clock Distribution SEC SetsLinecardGenApp_05 Revision 1.01/August 2003 (c) Semtech Corp. Page 38 www.semtech.com Revision 1.01/August 2003 (c) Semtech Corp. Page 39 Y , , X , , X ) . ) . - ) . ] ] \ G ; B X ) ) Y ' ( - 0 \ ) ) [ + ) ) ! ! " # ! " # $ % E 9 # E $ " ! 9 % # H G H H H H H H G G G G G G : : : : " ! 6 6 6 6 7 7 7 7 8 8 8 8 B ; B B B B B B ; ; ; ; ; ; 8 8 8 8 > > > > B B B B B B B B B B B B B B @ @ @ @ @ @ @ @ = = @ @ 5 5 5 5 @ @ 5 5 5 5 8 8 8 8 8 8 8 8 Z : : 0 A A A A A A A A ; ; 9 9 X Y ? Z 1 - ( 0 . W / Y Z 0 / ? / / ( ? / 0 ( - / ? 3 . . ( 2 1 . - . . & . . / - UV QR . ST OP K K MN M KL IJ . 1 ? - - 0 / ( . - ? / . / -1 ( - 1 . -0 -/ : 0 -. ; ? 6 4 4 4 / - - < 5 5 5 = 6 6 6 - > 7 > > > 7 7 7 ( D > > 6 @ B - 8 8 8 C 6 B 6 < < 9 F > A # ! " $ % $ $ $ E 9 % # $ ? ! , + * ' ( & " # $ % ) ADVANCED COMMUNICATION Y ^ Y ACS8110 SSM Handler PRELIMINARY DATASHEET Figure 21 Typical Application Schematic www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Abbreviations AIS Alarm Indication Signal AMI Alternate Mark Inversion B8ZS Bipolar with 8-Zero Substitution BITS Building Integrated Timing Supply CMU Clock Multiplier Unit CRC Cyclic Redundancy Check DS1 1544 kb/s interface rate E1 2048 kb/s interface rate ESF Extended Super Frame FDL Facility Datalink HDB3 High Density Bipolar Order 3 LAPD Link Access Protocol B LIU Line Interface Unit LOF Loss of Frame Alignment LOS Loss Of Input NE Network Element NRZ Non Return to Zero OOF Out of Frame Alignment RZ Return to Zero SASE Stand Alone Synchronization Element SEC SDH Equipment Clock SETS Synchronous Equipment Timing source SF Super Frame SSD Synchronization Signal Defect SSF Synchronization Signal Failure SSM Synchronization Status Message SSU Synchronization Supply Unit STM1 Synchronous Transport Module Level 1 Revision 1.01/August 2003 (c) Semtech Corp. PRELIMINARY DATASHEET References and Related Standards [1] ANSI T1.403 (1995) Network-to-customer Installation - DS1 Metallic Interface [2] ANSI T1.107-199x Digital Hierarchy - Format Specifications [3] Committee T1 -Telecommunications Report No. 33 (04/94) A Technical Report on Synchronization Network Management Using Synchronization Status Messages [4] ETSI EN 300 417-6-1 v1.1.3 (05/99) Transmission and Multiplexing (TM; Generic Requirements of Transport Functionality of Equipment; Part 6-1: Synchronization Layer Functions [5] IEEE 1149.1 (1990) Standard Test Access Port and Boundary-Scan Architecture [6] ITU-T G.803 (06/97) Architecture of transport networks based on the synchronous digital hierarchy (SDH) [7] ITU-T G.810 (08/96) Definition and Terminology Synchronization Networks [8] ITU-T G.812 (06/98) Timing requirements at the outputs of slave clocks suitable for plesiochronous operation of international digital links [9] ITU-T G.813 (08/96) Timing characteristics of SDH equipment slave clocks (SEC) [10] ITU-T G.783 (04/97 Characteristics of synchronous digital hierarchy (501-I) equipment functional blocks [11] ITU-T G.703 (09/91) Physical / Electrical Characteristics of hierarchical Digital Interfaces [12] ITU-T G.704 (10/98) Synchronous Frame structures used at 1544, 6312, 2948, 8448 and 44736 kbit/s Hierarchical Levels [13] ITU-T G.706 (04/91) Frame Alignment and CRC procedures Relating to Basic Frame structures in Rec. G.704. [14] ITU-T G.707 (03/96) Network mode Interface for the Synchronous Digital Hierarchy (SDH) Page 40 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION PRELIMINARY DATASHEET Trademark Acknowledgements [15] ITU-T G.775 (10/98) Loss of Signal (LOS), Alarm Indication Signal (AIS) and Remote Defect Indication (RDI) defect detection and clearance criteria for PDH signals Semtech Corp. and the Semtech S logo are registered trademarks of Semtech Corporation. [16] ITU-T G.781 (06/99) Digital Transmission Systems - Digital Networks- SDH Network Characteristics: Synchronization Layer Functions AMD is a registered trademark of Advanced Micro Devices, Inc. [17] Telcordia GR-253-CORE (12/97) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria Intel is the registered trademark of Intel Corporation [18] Telcordia GR-436-CORE (06/94) Digital Network Synchronization Plan Telcordia is a registered trademark of Telcordia Technologies. Motorola is a registered trademark of Motorola, Inc. [19] Telcordia GR-499-CORE (12/98) Transport Systems Generic Requirements (TSGR): Common Requirements [20] Telcordia GR-1244-CORE Clocks for the Synchronized Network: Common Generic Criteria Revision Status/History The Revision Status, as shown in top center of the document, may be TARGET, PRELIMINARY, or FINAL, and refers to the status of the Device (not the document), within the design cycle. TARGET status is used when the design is being realized but is not yet physically available, and the document content reflects the intention of the design. The document is raised to PRELIMINARY status when initial prototype devices are physically available, and the document content more accurately represents the realization of the design. The document is only raised to FINAL status after the device has been fully characterized, and the document content updated with measured, rather than simulated parameter values. This is a PRELIMINARY release (Revision 1.01) of the ACS8110 DATASHEET. Changes made for this document revision are given in Table 28, together with a brief summary of previous revisions. For specific changes between earlier revisions, refer (where available) to those earlier revisions. Always use the current version of the datasheet. Table 28 Revision History Revision Reference Description of changes 0.01/ May 2003 All pages Internal TARGET release. 1.00/ June 2003 All pages First release of Datasheet at PRELIMINARY status. 1.01/August 2003 All pages New template. Register Map (Reg 1/0C and 1/0E) Bits [7:4] is E1_sabit_select. Revision 1.01/August 2003 (c) Semtech Corp. Page 41 www.semtech.com ACS8110 SSM Handler ADVANCED COMMUNICATION Ordering Information PRELIMINARY DATASHEET Table 29 Parts List Part Number ACS8110 Description SSM Handler Synchronization Status Message Handler with Integrated BITS Interface Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards. Contacts For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: sales@semtech.com Internet: http://www.semtech.com USA: Mailing Address: Street Address: Tel: +1 805 498 2111, acsupport@semtech.com P.O. Box 6097, Camarillo, CA 93011-6097 200 Flynn Road, Camarillo, CA 93012-8790 Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601 ISO9001 CERTIFIED Revision 1.01/August 2003 (c) Semtech Corp. Page 42 www.semtech.com