AK4480EF - Asahi Kasei Microsystems Co., Ltd. (AKM)

[AK4480]

MS1146-E-01 2010/02

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GENERAL DESCRIPTION

The AK4480 is a 32-bit DAC, which corresponds to Blu-ray Disc systems. An internal circuit includes

newly developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and

wide dynamic range. The AK4480 has full differential SCF outputs, removing the need for AC coupling

capacitors and increasing performance for systems with excessive clock jitter. The AK4480 accepts

216kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including Blu-ray Discs and

SACDs.

FEATURES

• 128x Over Sampling

• Sampling Rate: 30kHz ∼ 216kHz

• 32Bit 8x Digital Filter

- Ripple: ±0.005dB, Attenuation: 70dB

- Minimum delay option GD=7/fs

- Sharp Roll-off Filter

- Slow Roll-off Filter

• High Tolerance to Clock Jitter

• Low Distortion Differential Output

• DSD Data Input

• Digital De-emphasis for 32, 44.1, 48kHz Sampling

• Soft Mute

• Digital Attenuator (Linear 256 steps)

• Mono Mode

• External Digital Filter Mode

• THD+N: -100dB

• DR, S/N: 114dB (117dB when Mono mode)

• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD

• Master Clock:

30kHz ~ 32kHz: 1152fs

30kHz ~ 54kHz: 512fs or 768fs

30kHz ~ 108kHz: 256fs or 384fs

108kHz ~ 216kHz: 128fs or 192fs

• Power Supply: 4.75 ∼ 5.25V

• Digital Input Level: TTL

• Package: 30pin VSOP

AK4480

High Performance 114dB 32-Bit DAC

[AK4480]

MS1146-E-01 2010/02

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■ Block Diagram

MCLK

SDA TA/DSDL

LRCK/DSDR/WCK

CSN/SMUTE

BICK/DCLK

CCLK/DEM0

CDTI/DEM1

DZF

R

VSS1

VDD

R

PDN AVDD

SCF

Clock

Divider

VSS3DVDD

DIN

R

DINL

BCK

CAD0/SD CAD1/DIF0

PSN DZFL/DIF1 DIF2

VSS2

VDDL

AOUTRN

VREFHL

VREFLL

VREFL

R

VREFLL

VSS4

AOUTLP

AOUTLN

AOUTRP

PCM

Data

Interface

DSD

Data

Interface

External

DF

Interface

8X

Interpolator

Control

Register

DATT

Soft Mute

Δ

Σ

Modulator

Bias

Vref

Block Diagram

[AK4480]

MS1146-E-01 2010/02

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■ Ordering Guide

AK4480EF −10 ∼ +70°C 30pin VSOP (0.65mm pitch)

AKD4480 Evaluation Board for AK4480

■ Pin Layout

6

5

4

3

2

1 SMUTE/CSN

SD/CAD0

DEM1/CDTI

DEM0/CCLK

DIF0/CAD1

D IF1/DZFL

7

PSN 8

LRCK/DSDR/WCK

SDATA/DSDL/DINL

BICK/DLCK/BCK

PDN

DVDD

VSS4

MCLK

AVDD

AK4480

Top

View

10

9

ACKS/DZFR

AOUTRP

AOUTRN 11

VSS1 12

VSS3

AOUTLP

AOUTLN

VSS2

25

26

27

28

29

30

24

23

21

22

20

19

DIF2/DINR

VDDR 13

VREFHR 14

VDDL

VREFHL

18

17

VREFLR 15 VREFLL 16

[AK4480]

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PIN/FUNCTION

No. Pin Name I/O Function

SMUTE I

Soft Mute in Parallel Control Mode

When this pin goes to “H”, soft mute cycle is initiated.

When returning to “L”, the output mute releases.

1

CSN I Chip Select in Serial Control Mode

SD I Digital Filter Select Pin

2 CAD0 I Chip Address 0 in Serial Control Mode

DEM0 I De-emphasis Enable 0 in Parallel Control Mode

3 CCLK I Control Data Clock in Serial Control Mode

DEM1 I De-emphasis Enable 1 in Parallel Control Mode

4 CDTI I Control Data Input in Serial Control Mode

DIF0 I Digital Input Format 0 in PCM Mode

5 CAD1 I Chip Address 1 in Serial Control Mode

DIF1 I Digital Input Format 1 in PCM Mode

6 DZFL O Left Channel Zero Input Detect in Serial Control Mode

DIF2 I Digital Input Format 2 in PCM Mode

7 DINR I Rch Audio Serial Data Input in External DF Mode.

8 PSN I Parallel/Serial Select (Internal pull-up pin)

“L”: Serial Control Mode, “H”: Parallel Control Mode

ACKS I Clock Auto Setting Mode Pin

9 DZFR O Rch Zero Input Detect in Serial Control Mode

10 AOUTRP O Right Channel Positive Analog Output

11 AOUTRN O Right Channel Negative Analog Output

12 VSS1 - Connected to VSS2/3/4 Ground

13 VDDR - Right Channel Analog Power Supply, 4.75~5.25V

14 VREFHR I Right Channel High Level Voltage Reference Input

15 VREFLR I Right Channel Low Level Voltage Reference Input

16 VREFLL I Left Channel Low Level Voltage Reference Input

17 VREFHL I Left Channel High Level Voltage Reference Input

18 VDDL - Left Channel Analog Power Supply, 4.75~5.25V

19 VSS2 - Ground (connected to VSS1/3/4 ground)

20 AOUTLN O Left Channel Negative Analog Output

21 AOUTLP O Left Channel Positive Analog Output

22 VSS3 - Ground (connected to VSS1/2/4 ground)

23 AVDD - Analog Power Supply, 4.75 to 5.25V

24 MCLK I Master Clock Input

25 VSS4 - Connected to VSS1/2/3 Ground

26 DVDD - Digital Power Supply, 4.75 ∼ 5.25V

27 PDN I

Power-Down Mode

When at “L”, the AK4480 is in power-down mode and is held in reset.

The AK4480 should always be reset upon power-up.

Note: All input pins except internal pull-up/down pins must not be left floating.

[AK4480]

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PIN/FUNCTION (Continued)

No. Pin Name I/O Function

BICK I Audio Serial Data Clock in PCM Mode

DCLK I Audio Serial Data Clock in DSD Mode

28

BCK I Audio Serial Data Clock in EXDF Mode

SDATA I Audio Serial Data Input in PCM Mode

DSDL I Lch Audio Serial Data Clock in DSD Mode

29

DINL I Lch Audio Serial Data Clock in EXDF Mode

LRCK I L/R Clock in PCM Mode

DSDR I Rch Audio Serial Data Input Pin in DSD Mode

30

WCK I Word Clock Pin in EXDF Mode

Note: All input pins except internal pull-up/down pins must not be left floating.

■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

(1) Parallel Mode (PCM Mode only)

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

(2) Serial Mode

1. PCM Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

DIF2, PSN These pins must be connected to VSS4.

Digital DZFL, DZFR These pins must be open.

2. DSD Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

DIF2, PSN These pins must be connected to VSS4.

Digital DZFL, DZFR These pins must be open.

3. Ex DF Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.

Analog AOUTRP, AOUTRN These pins must be open.

DIF2, PSN These pins must be connected to VSS4.

Digital DZFL, DZFR These pins must be open.

[AK4480]

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ABSOLUTE MAXIMUM RATINGS

(VSS1-4 =0V; Note 1)

Parameter Symbol min max Units

Power Supplies:

Analog

Digital

AVDD

VDDL/R

DVDD

−0.3

6.0

V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Digital Input Voltage VIND −0.3 DVDD+0.3 V

Ambient Temperature (Power applied) Ta −10 70 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. VSS1-4 must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1-4 =0V; Note 1)

Parameter Symbol min typ max Units

Power Supplies

(Note 3)

Analog

Digital

AVDD

VDDL/R

DVDD

4.75

5.0

5.25

V

Voltage

Reference

(Note 4)

VREFHL/R

VREFLL/R

VREFHL/R

VREFLL/R

AVDD−0.5

-

VSS

AVDD

-

V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD, VDDL/R and DVDD is not critical.

Note 4. The VREFLL/R pin must be the same voltage as VSS.

The analog output voltage scales with the voltage of (VREFH − VREFL).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

[AK4480]

MS1146-E-01 2010/02

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;

Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;

Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)

Parameter min typ max Units

Resolution - - 32 Bits

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz

0dBFS

−60dBFS

-

-100

-51

-93

-

dB

fs=96kHz

BW=40kHz

0dBFS

−60dBFS

-

97

-48

-

dB

THD+N

fs=192kHz

BW=40kHz

BW=80kHz

0dBFS

−60dBFS

97

-48

-45

-

dB

Dynamic Range (−60dBFS with A-weighted) (Note 6) 108 114 dB

S/N (A-weighted) (Note 7) 108 114 dB

Interchannel Isolation (1kHz) 100 110 dB

DC Accuracy

Interchannel Gain Mismatch - 0 0.3 dB

Gain Drift (Note 8) - 20 - ppm/°C

Output Voltage (Note 9) ±2.25 ±2.4 ±2.55 Vpp

Load Capacitance - - 25 pF

Load Resistance (Note 10) 2 - - kΩ

Power Supplies

Power Supply Current

Normal operation (PDN pin = “H”)

AVDD + VDDL/R

DVDD (fs ≤ 96kHz)

DVDD (fs = 192kHz)

-

30

15

24

45

-

36

mA

Power down (PDN pin = “L”) (Note 11)

AVDD+VDDL/R+DVDD

-

10

100

μA

Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.

Note 6. Figure 20 External LPF Circuit Example 2. 100dB for 16-bit data.

Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.

Note 8. The voltage on (VREFH − VREFL) is held +5V externally.

Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.4Vpp × (VREFHL/R − VREFLL/R)/5.

Note 10. Regarding Load Resistance, AC load is 2kΩ (min) with a DC cut capacitor. Please refer to Figure 20. The load

resistance is 4k ohm (min) to ground when without a DC cut capacitor. Please refer to Figure 19. Load Resistance

is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected output pin.

Therefore the capacitive load must be minimized.

Note 11. In the power down mode. P/S pin = DVDD, and all other digital input pins including clock pins

(MCLK, BICK and LRCK) are held VSS4.

[AK4480]

MS1146-E-01 2010/02

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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit =“0”,

SD bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12) PB 0 - 20.0 kHz

Frequency Response ±0.05dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 12) SB 24.1 kHz

Passband Ripple PR -0.005 +0.0001 dB

Stopband Attenuation SA 70 dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz -0.2 - +0.2 dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit =“0”,

SD bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12) PB 0 - 43.5 kHz

Frequency Response

±0.05dB

−6.0dB

0

-

48.0

43.5

-

kHz

Stopband (Note 12) SB 52.5 - kHz

Passband Ripple PR -0.005 - +0.0001 dB

Stopband Attenuation SA 70 - - dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz -0.3 - +0.3 dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit =“0”, SD

bit=“0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 12) PB 0 - 87.0 kHz

Frequency Response

±0.05dB

−6.0dB

0

-

96.0

87.0

-

kHz

Stopband (Note 12) SB 105 kHz

Passband Ripple PR -0.005 - +0.0001 dB

Stopband Attenuation SA 70 - - dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz -1 - +0.1 dB

Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@±0.01dB), SB=0.546×fs.

Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data

of both channels to input register to the output of analog signal.

[AK4480]

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SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”,

SD bit = “0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14) PB 0 - 8.1 kHz

Frequency Response

±0.07dB

−3.0dB 0

-

18.2

8.1

-

kHz

Stopband (Note 14) SB 39.2 - - kHz

Passband Ripple PR -0.07 - +0.02 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz -5 - +0.1 dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode DEM=OFF; SLOW bit=“1”, SD

bit = “0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14) PB 0 - 17.7 kHz

Frequency Response

±0.07dB

−3.0dB 0

-

39.6

17.7

-

kHz

Stopband (Note 14) SB 85.3 - - kHz

Passband Ripple PR -0.07 - +0.02 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz -4 - +0.1 dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”, SD

bit = “0”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14) PB 0 - 35.5 kHz

Frequency Response

±0.07dB

−3.0dB 0

-

79.1

35.5

-

kHz

Stopband (Note 14) SB 171 - - kHz

Passband Ripple PR -0.07 - +0.02 dB

Stopband Attenuation SA 73 - - dB

Group Delay (Note 13) GD - 27 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz -5 - +0.1 dB

Note 14. The passband and stopband frequencies scale with fs. For example, PB=0.185×fs (@±0.04dB), SB=0.888×fs.

[AK4480]

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MINIMUM DELAY FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14)±0.01dB PB 0 - 20.0 kHz

Frequency Response

±0.06dB

−6.0dB 0

-

22.05

20.0

-

kHz

Stopband (Note 14) SB 24.1 - - kHz

Passband Ripple PR -0.0052 - +0.0006 dB

Stopband Attenuation SA 70 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz -0.2 - +0.2 dB

MINIMUM DELAY FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit = “0”,

SD bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14)±0.01dB PB 0 - 43.5 kHz

Frequency Response

±0.06dB

−6.0dB 0

-

48.0

43.5

-

kHz

Stopband (Note 14) SB 52.5 - - kHz

Passband Ripple PR -0.0052 - +0.0006 dB

Stopband Attenuation SA 70 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz -0.3 - +0.3 dB

MINIMUM DELAY FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD

bit=“1”)

Parameter Symbol min typ max Units

Digital Filter

Passband (Note 14)±0.01dB PB 0 - 87.0 kHz

Frequency Response

±0.06dB

−6.0dB 0

-

96.0

87.0

-

kHz

Stopband (Note 14) SB 105 - - kHz

Passband Ripple PR -0.0052 - +0.0006 dB

Stopband Attenuation SA 70 - - dB

Group Delay (Note 13) GD - 7 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz -1 - +0.1 dB

[AK4480]

MS1146-E-01 2010/02

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DC CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)

Parameter Symbol min typ max Units

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

2.2

-

0.8

V

High-Level Output Voltage (Iout=−100μA)

Low-Level Output Voltage (Iout=100μA)

VOH

VOL

DVDD−0.5

-

0.5

V

Input Leakage Current (Note 15) Iin - - ±10 μA

Note 15. The TEST1/CAD0 pin is an internal pull-down pin, and the P/S pin is an internal pull-up pin, nominally 100kΩ.

Therefore TEST1/CAD0 pin and P/S pin are not included.

[AK4480]

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SWITCHING CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)

Parameter Symbol min typ max Units

Master Clock Timing

Frequency

Duty Cycle

fCLK

dCLK

7.7

40

41.472

60

MHz

%

LRCK Frequency (Note 16)

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

Duty Cycle

fsn

fsd

fsq

Duty

30

54

108

45

54

108

216

55

kHz

%

PCM Audio Interface Timing

BICK Period

1152fs, 512fs or 768fs

256fs or 384fs

128fs or 192fs

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 17)

LRCK Edge to BICK “↑” (Note 17)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fsn

1/64fsd

1/64fsq

30

20

ns

External Digital Filter Mode

BICK Period

BCK Pulse Width Low

BCK Pulse Width High

BCK “↑” to WCK Edge

WCK Edge to BCK “↑”

WCK Pulse Width Low

WCK Pulse Width High

DATA Hold Time

DATA Setup Time

tB

tBL

tBH

tBW

tWB

tWCK

tWCH

tDH

tDS

27

10

5

54

5

ns

DSD Audio Interface Timing

DCLK Period

DCLK Pulse Width Low

DCLK Pulse Width High

DCLK Edge to DSDL/R (Note 18)

tDCK

tDCKL

tDCKH

tDDD

-

160

−20

1/64fs

20

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 19)

tPD

150

ns

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Note 16. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4480 should be reset by the

PDN pin or RSTN bit.

Note 17. BICK rising edge must not occur at the same time as LRCK edge.

Note 18. DSD data transmitting device must meet this time.

Note 19. The AK4480 can be reset by bringing the PDN pin “L” to “H” upon power-up.

■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH

LRCK VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

1/fs

VIH

WCK VIL

tB

tBL

VIH

tBH

BCK VIL

Clock Timing

[AK4480]

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tLRB

LRCK

VIH

BICK VIL

tSDS

VIH

SDATA VIL

tSDH

VIH

VIL

tBLR

Audio Interface Timing (PCM Mode)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

tDDD

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

[AK4480]

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tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Timing

[AK4480]

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tPD

PDN VIL

Power Down & Reset Timing

tWB

WCK

VIH

BCK VIL

tDS

VIH

DATA VIL

tDH

VIH

VIL

tBW

External Digital Filter I/F mode

[AK4480]

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OPERATION OVERVIEW

■ D/A Conversion Mode

In serial mode, the AK4480 can covert both PCM and DSD data. The D/P bit controls PCM/DSD mode. When DSD

mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK,

LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4480 should be reset by RSTN bit. It takes

about 2/fs ~ 3/fs to change the mode. In parallel mode, the AK4480 can only convert PCM data.

D/P bit Interface

0 PCM

1 DSD

Table 1. PCM/DSD Mode Control

When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter

(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When

switching internal and external digital filters, the AK4480 must be reset by RSTN bit. A Digital filter switching takes

2~3k/fs.

Ex DF bit Interface

0 PCM

1 EX DF I/F

Table 2. Digital Filter Control (DP bit = “0”)

■ System Clock

[1] PCM Mode

The external clocks, which are required to operate the AK4480, are MCLK, BICK and LRCK. MCLK should be

synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator. There are two modes for setting MCLK frequency, Manual Setting Mode and Auto Setting Mode.

In auto setting mode, sampling speed and MCLK frequency are detected automatically and then the initial master clock is

set to the appropriate frequency (Table 3). When external clocks are changed, the AK4480 should be reset by the PDN pin

or RSTN bit.

The AK4480 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation

mode, and the analog output goes to AVDD/2 (typ). When MCLK and LRCK are input again, the AK4480 is powered up.

After exiting reset following power-up, the AK4480 is not fully operational until MCLK and LRCK are input.

The MCLK frequency corresponding to each sampling speed should be provided (Table 3).

(1) Parallel Mode (P/S pin = “H”)

1. Manual Setting Mode (ACKS pin = “L”)

The MCLK frequency corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. Quad

speed mode is not supported in this mode.

[AK4480]

MS1146-E-01 2010/02

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LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

88.2kHz 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 5.6448MHz

96.0kHz 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 6.1440MHz

Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)(N/A: Not available)

32kHz ~ 96kHz sampling rates are supported (Table 4). However, when the sampling rate is 32kHz ~ 48kHz, DR and S/N

will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

ACKS pin MCLK DR,S/N

L 256fs/384fs/512fs/768fs 114dB

H 256fs/384fs 111dB

H 512fs/768fs 114dB

Table 4. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)

2. Auto Setting Mode (ACKS pin = “H”)

MCLK frequency and the sampling speed are detected automatically (Table 5). MCLK with appropriate frequency should

be input externally for each speed (Table 6).

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs/256fs 768fs/384fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 5. Sampling Speed (Auto Setting Mode @Parallel Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A

Normal

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 6. System Clock Example (Auto Setting Mode @Parallel Mode) (N/A: Not available)

MCLK= 256fs/384fs supports sampling rate of 32kHz ~ 96kHz (Table 7). However, when the sampling rate is 32kHz ~

48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

ACKS pin MCLK DR,S/N

L 256fs/384fs/512fs/768fs 114dB

H 256fs/384fs 111dB

H 512fs/768fs 114dB

Table 7. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)

[AK4480]

MS1146-E-01 2010/02

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(2) Serial Mode (P/S pin = “L”)

1. Manual Setting Mode (ACKS bit = “0”)

MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 8). The MCLK frequency

corresponding to each sampling speed should be provided (Table 9). The AK4480 is set to Manual Setting Mode at

power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4480 should be reset by RSTN bit.

DFS1 bit DFS0 bit Sampling Rate (fs)

0 0 Normal Speed Mode 30kHz ∼ 54kHz

0 1 Double Speed Mode 54kHz ∼ 108kHz

1 0 Quad Speed Mode

120kHz ∼ 216kHz

(default)

Table 8. Sampling Speed (Manual Setting Mode @Serial Mode)

LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

88.2kHz 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 5.6448MHz

96.0kHz 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 6.1440MHz

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A 11.2896MHz

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A 12.2880MHz

Table 9. System Clock Example (Manual Setting Mode @Serial Mode)

2. Auto Setting Mode (ACKS bit = “1”)

MCLK frequency and the sampling speed are detected automatically (Table 10) and DFS1-0 bits are ignored. The MCLK

frequency corresponding to each sampling speed should be provided (Table 11).

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs/256fs 768fs/384fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 10. Sampling Speed (Auto Setting Mode @Serial Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A

Normal

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 11. System Clock Example (Auto Setting Mode @Serial Mode)

[AK4480]

MS1146-E-01 2010/02

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MCLK= 256fs/384fs supports sampling rate of 32kHz ~ 96kHz (Table 12). However, when the sampling rate is 32kHz ~

48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

ACKS bit MCLK DR,S/N

0 256fs/384fs/512fs/768fs 114dB

1 256fs/384fs 111dB

1 512fs/768fs 114dB

Table 12. Relationship between MCLK Frequency and DR, S/N (fs = 44.1kHz)

[2] DSD Mode

The external clocks, which are required to operate the AK4480, are MCLK and DCLK. MCLK should be synchronized

with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.

The AK4480 is automatically placed in reset state when MCLK is stopped during a normal operation, and the analog

output becomes AVDD/2 (typ).

DCKS bit MCLK Frequency DCLK Frequency

0 512fs 64fs (default)

1 768fs 64fs

Table 13. System Clock (DSD Mode)

[AK4480]

MS1146-E-01 2010/02

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■ Audio Interface Format

[1] PCM Mode

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the

DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 14. In all formats the serial

data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and

16-bit MSB justified formats by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 Input Format BICK Figure

0 0 0 0 16bit LSB justified

≥ 32fs Figure 1

1 0 0 1 20bit LSB justified

≥ 48fs Figure 2

2 0 1 0 24bit MSB justified

≥ 48fs Figure 3 (default)

3 0 1 1 24bit I2S Compatible ≥ 48fs Figure 4

4 1 0 0 24bit LSB justified

≥ 48fs Figure 2

5 1 0 1 32bit LSB justified

≥ 64fs Figure 5

6 1 1 0 32bit MSB justified

≥64fs Figure 6

7 1 1 1 32bit I2S Compatible ≥ 64fs Figure 7

Table 14. Audio Interface Format

SDAT

A

BICK

LRCK

SDAT

A

15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3210 1514

(

32fs

)

(

64fs

)

014

115 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 Don’t care Don’t care

15:MSB, 0:LSB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

SDAT

A

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Do n ’t care Do n’t care

19:MSB, 0:LSB

SDAT

A

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Don’t care Don’t care

22 21 22 21

Lch Data Rch Data

8

23 23

8

Figure 2. Mode 1/4 Timing

[AK4480]

MS1146-E-01 2010/02

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LRCK

BICK

(

64fs

)

SDAT

A

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t care23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don’t care

23 2223

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDAT

A

031 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 10Don’t care

23

Lch Data Rch Data

23 25 322423 25

22 1 0Don’t care23 23

Figure 4. Mode 3 Timing

LRCK

BICK(128fs)

SDAT A

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1

031 1

BICK(64fs)

SDAT A

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

031 1

Figure 5. Mode 5 Timing

[AK4480]

MS1146-E-01 2010/02

- 23 -

LRCK

BICK(128fs)

SDAT A

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0

31

1

30 031 30 12 11 10 0 3112 11 10

BICK(64fs)

SDAT A

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

Figure 6. Mode 6 Timing

LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1

31 031 13 12 11 0 13 12 11

BICK(64fs)

SDATA

0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0

0

1

31 9031 212019 9 021 20 19

31: MSB, 0:LSB

81

28 1

2

Lch Data Rch Dat a

Figure 7. Mode 7 Timing

[2] DSD Mode

In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can

invert the polarity of DCLK.

DCLK (64fs)

DCKB=1

DCLK (64fs)

DCKB=0

DSDL,DSDR

Normal

DSDL,DSDR

Phase M odulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 8. DSD Mode Timing

[AK4480]

MS1146-E-01 2010/02

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[3] External Digital Filter Mode (EX DF I/F Mode)

DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL

and DINR pins. Three formats are available (Table 16) by DIF2-0 bits setting. The data is latched on the rising edge of

BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each

sampling speed are shown in Table 15.

MCLK&BCK [MHz] WCK

Sampling

Speed[kHz] 128fs 192fs 256fs 384fs 512fs 768fs

ECS

N/A N/A N/A N/A 22.5792 33.8688 16fs

44.1(30~54) 32 48 DW

0 (default)

N/A N/A 11.2896 16.9344 N/A 33.8688 8fs

44.1(30~54) 32 48 96 DW

1

N/A N/A 24.576 36.864 N/A N/A 8fs

96(54~108) 32 48 DW

0

12.288 18.432 N/A 36.864 N/A N/A 4fs

96(54~108) 32 48 96 DW

1

24.576 36.864 N/A N/A N/A N/A 4fs

192(108~216) 32 48 DW

0

N/A 36.864 N/A N/A N/A N/A 2fs

192(108~216) 96 DW

1

Table 15. System Clock Example (EX DF I/F mode) (N/A: Not available)

Mode DIF2 DIF1 DIF0 Input Format

0 0 0 0 16bit LSB justified

1 0 0 1 N/A

2 0 1 0 N/A

3 0 1 1 N/A

4 1 0 0 24bit LSB justified

5 1 0 1 32bit LSB justified (default)

6 1 1 0 N/A

7 1 1 1 N/A

Table 16. Audio Interface Format (EX DF I/F mode) (N/A: Not available)

[AK4480]

MS1146-E-01 2010/02

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BCK

WCK

DINL or

DINR 23 22

BCK

0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1

21 20 17 16

0 5 1 6 7 8 47 48 49 65 92 93 94

95 0 1

31 30

31 0

15 14 6 5 4 3 2 1 0

Don’t care Don’t care

DINL or

DINR 2 31

24

Don’t care Don’t care

BCK

0 5

1 6 7 8 23 24 25 17 44 45 46

47 0 1

31 0

Don’t care

DINL or

DINR 2 31Don’t care Don’t care Don’t car

e

1/16fs or 1/8fs or 1/4fs or 1/2fs

Figure 9. EX DF I/F Mode Timing

[AK4480]

MS1146-E-01 2010/02

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■ D/A Conversion Mode Switching Timing

RSTN bit

D/A Data

D/A Mod e

≥4/fs

≥0

PCM Data DSD Data

P CM M ode DSD Mode

Figure 10. D/A Mode Switching Timing (PCM to DSD)

RSTN bit

D/A Data

D/A Mod e

≥4/fs

DS D Da ta PCM Data

DSD Mode PCM Mode

Figure 11. D/A Mode Switching Timing (DSD to PCM)

Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty

range at the SACD format book (Scarlet Book).

■ De-emphasis Filter

A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs). It is enabled and

disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is

always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are

switched.

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF (default)

1 0 48kHz

1 1 32kHz

Table 17. De-emphasis Control

■ Output Volume (PCM and DSD)

The AK4480 includes channel independent digital output volume control (ATT) with 255 levels at linear step including

MUTE. This volume control is in front of the DAC and it can attenuate the input data from 0dB to –48dB and mute. When

changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions.

Transition Time

Sampling Speed 1 Level 255 to 0

Normal Speed Mode 4LRCK 1020LRCK

Double Speed Mode 8LRCK 2040LRCK

Quad Speed Mode 16LRCK 4080LRCK

DSD Mode 4LRCK 1020LRCK

Table 18. ATT Transition Time

[AK4480]

MS1146-E-01 2010/02

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■ Zero Detection (PCM and DSD)

The AK4480 has channel-independent zero detect function. When the input data at each channel is continuously zeros for

8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L” if

the input data of each channel is not zero after becoming “H”. When the RSTN bit is “0”, the DZF pins of both channels

become “H”. The DZF pins of both channels become “L” in 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to

“1”, the DZF pins of both channels go to “H” only when the input data for both channels are continuously zeros for 8192

LRCK cycles. The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels

are always “L”. The DZFB bit can invert the polarity of the DZF pin.

■ Mono Output (PSM, DSD, Ex DF I/F)

The AK4480 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is

available for any audio format.

MONO bit SELLR bit Lch Out Rch Out

0 0 Lch In Rch In

0 1 Rch In Lch In

1 0 Lch In Lch In

1 1 Rch In Rch In

Table 19. MONO Mode Output Select

[AK4480]

MS1146-E-01 2010/02

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■ Soft Mute Operation (PCM and DSD)

The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,

the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the

SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation

gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before

attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.

The soft mute is effective for changing the signal source without stopping the signal transmission.

SM U T E pin or

SMU TE bit

A

ttenuation

D ZF pin

ATT_Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

(2)

Notes:

(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in

Normal Speed Mode.

(2) The analog output corresponding to the digital input has group delay (GD).

(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued

and returned to ATT level by the same cycle.

(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel

goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.

Figure 12. Soft Mute Function

■ System Reset

The AK4480 should be reset once by bringing the PDN pin = “L” upon power-up. The analog block exits power-down

mode by MCLK input and the digital block exits power-down mode after the internal counter counts MCLK for 4/fs.

[AK4480]

MS1146-E-01 2010/02

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■ Power ON/OFF timing

The AK4480 is placed in power-down mode by bringing the PDN pin “L” and the registers are initialized. The analog

outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN signal, the analog output should be muted

externally if the click noise influences system application.

The AK4480 can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding

analog outputs become AVDD/2 (typ). As some click noise occurs at the edge of RSTN signal, the analog output should

be muted externally if the click noise influences system application.

PDN pin

Power

Reset

Normal Operation

Clock In

MCLK,LRCK,BICK

DAC In

(Digital)

DAC Out

(Analog)

Ex ternal

Mute Mute ON

(6)

DZFL/DZFR

Don’t care

“0”data

GD

(2)

(4)

(5)

(7)

GD

(4)

Mute ON

“0”data

Don’t care

Internal

State

(3) (3)

(1)

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) Analog outputs are floating (Hi-Z) in power-down mode.

(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).

(6) Mute the analog output externally if click noise (3) adversely affect system performance

The timing example is shown in this figure.

(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”). (DZFB bit = “0”)

Figure 13. Power-down/up Sequence Example

[AK4480]

MS1146-E-01 2010/02

- 30 -

■ Reset Function

(1) RESET by RSTN bit = “0”

When RSTN bit = “0”, the AK4480’s digital section is powered down but the internal register values are not initialized.

The analog outputs become VCML/R voltage and DZF pins of both channels become “H”. Figure 14 shows the example

of reset by RSTN bit.

Internal

State

RSTN bit

Digital Block

P

d

Normal Op eration

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(1) (3)

DZFL/DZFR

(3) (1)

(2)

Normal Operation

2/fs(5)

Internal

RSTN Timing

2~3/fs (6)3~4/fs (6)

Don’t care

(4)

Notes:

(1) The analog output corresponding to digital input has group delay (GD).

(2) The analog outputs are VCOM voltage when RSTN bit = “0”.

(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.

This noise is output even if “0” data is input.

(4) The DZF pins become “H” when the RSTN bit is set to “0”, and return to “L” in 2/fs after the RSTN bit is changed

to “1”.

(5) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”

to the internal RSTN bit “1”.

(6) Mute the analog output externally if click noise (3) or Hi-z output (2) influences system applications. The timing

example is shown in this figure.

Figure 14. Reset Sequence Example 1

[AK4480]

MS1146-E-01 2010/02

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(2) RESET by MCLK or LRCK/WCK stop

The AK4480 is automatically placed in reset state when MCLK or LRCK is stopped during PCM mode (RSTN pin

=“H”), and the analog outputs become AVDD/2 (typ). When MCLK and LRCK are input again, the AK4480 exit reset

state and starts the operation. Zero detect function is not available when MCLK or LRCK is stopped. The AK4480 is set to

reset state automatically and the analog outputs become Hi-Z when MCLK is stopped in DSD mode, and when MCLK or

WCK is stopped in external digital filter mode.

Normal Operation

Intern al

State Reset Normal Operation

GD GD

D/A Out

(Analog)

D/A In

(Digital)

Cl ock In

MCLK, LRCK

(2)

(3)

External

MUTE (6)

VCOM

(2)

MCLK or LRCK Stop

PDN pin

Pow er-down

(4) (4)

(4)

Hi-Z

(6) (6)

(5)

(1)

AVDD pin

DVDD pin

Notes:

(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.

(2) The analog output corresponding to digital input has group delay (GD).

(3) The digital data can be stopped. Click noise after MCLK or LRCK/WCK is input again can be reduced by

inputting “0” data during this period.

(4) Click noise occurs within 3 ∼ 4LRCK cycles from rising edge (↑ ) of PDN signal or MCLK inputs. This noise is

output even if “0” data is input.

(5) MCLK, BICK and LRCK/WCK clocks can be stopped in reset mode (MCLK or LRCK/WCK stopped).

(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown

in this figure.

Figure 15. Reset sequence example 2

[AK4480]

MS1146-E-01 2010/02

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■ Register Control Interface

Functions of the AK4480 can be controlled in parallel control mode (by pins) and serial control mode (by registers). In

parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state

of the PSN pin is changed, the AK4480 should be reset by the PDN pin. The serial control interface is enabled by the PSN

pin = “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this

interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and

Control data (MSB first, 8-bits). The AK4480 latches the data on the rising edge of CCLK, so data should be clocked in on

the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max).

Function Parallel Control Mode Serial Control Mode

Audio Format Y Y

Auto Setting Mode - Y

De-emphasis Y Y

SMUTE Y Y

DSD Mode - Y

EX DF I/F - Y

Zero Detection - Y

Sharp Roll Off Filter Y Y

Slow Roll Off Filter - Y

Minimum delay Filter Y Y

Digital Attenuator - Y

Table 20. Function List (Y: Available, -: Not available)

Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is

reset by the RSTN bit, but the registers are not initialized.

CDTI

CCLK

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

CSN

C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)

R/W: READ/WRITE (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 16. Control I/F Timing

* The AK4480 does not support the read command.

* When the AK4480 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control

registers is prohibited.

* The control data can not be written when the CCLK rising edge is 15 times and less or 17 times and more during CSN is

“L”.

[AK4480]

MS1146-E-01 2010/02

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Function List

Function Default Address Bit PCM DSD Ex DF I/F

Attenuation Level 0dB 03H

04H

ATT7-0 Y Y -

External Digital Filter I/F Mode Disable 00H EXDF Y - Y

Ex DF I/F mode clock setting 16fs(fs=44.1kHz) 00H ESC - - Y

Audio Data Interface Modes 24bit MSB justified 00H DIF2-0 Y - Y

Data Zero Detect Enable Disable 01H DZFE Y Y -

Data Zero Detect Mode Separated 01H DZFM Y Y

Minimum delay Filter Enable Sharp roll-off filter 01H SD Y - -

De-emphasis Response OFF 01H DEM1-0 Y - -

Soft Mute Enable Normal Operation 01H SMUTE Y Y -

DSD/PCM Mode Select PCM mode 02H DP Y Y -

Master Clock Frequency Select at

DSD mode

512fs 02H DCKS

- Y -

MONO mode Stereo mode select Stereo 02H MONO Y Y Y

Inverting Enable of DZF “H” active 02H DZFB Y Y -

The data selection of L channel and

R channel

R channel 02H SELLR Y Y Y

(Y: Available, -: Not available)

Table 21. Function List

[AK4480]

MS1146-E-01 2010/02

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■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS EXDF ECS 0 DIF2 DIF1 DIF0 RSTN

01H Control 2 DZFE DZFM SD DFS1 DFS0 DEM1 DEM0 SMUTE

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR SLOW

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

05H Control 4 INVL INVR 0 0 0 0 0 0

Notes:

Data must not be written into addresses from 05H to 1FH.

When the PDN pin goes to “L”, the registers are initialized to their default values.

When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default

values.

When the state of the PSN pin is changed, the AK4480 should be reset by the PDN pin.

■ Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS EXDF ECS 0 DIF2 DIF1 DIF0 RSTN

Default 0 0 0 0 0 1 0 1

RSTN: Internal Timing Reset

0: Reset. All registers are not initialized.

1: Normal Operation (default)

When internal clocks are changed, the AK4480 should be reset by the PDN pin or RSTN bit.

DIF2-0: Audio Data Interface Modes (Table 14)

Initial value is “010” (Mode 2: 24-bit MSB justified).

ECS: Ex DF I/F mode clock setting (Table 15)

0: BCK 32fs setting. MCLK, BCK are 512fs, 256fs and 128fs (default)

1: No BCK 32fs setting. MCLK, BCK are 768fs, 384fs and 192fs.

EXDF: External Digital Filter I/F Mode (PCM only)

0: Disable: Internal Digital Filter mode (default)

1: Enable: External Digital Filter mode

ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)

0: Disable: Manual Setting Mode (default)

1: Enable: Auto Setting Mode

When ACKS bit is “1”, sampling frequency and MCLK frequency is detected automatically.

[AK4480]

MS1146-E-01 2010/02

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 DZFE DZFM SD DFS1 DFS0 DEM1 DEM0 SMUTE

Default 0 0 1 0 0 0 1 0

SMUTE: Soft Mute Enable

0: Normal Operation (default)

1: DAC outputs soft-muted.

DEM1-0: De-emphasis Response (Table 17)

Initial value is “01” (OFF).

SD: Minimum delay Filter Enable

0: Sharp roll-off filter (default)

1: Minimum delay filter

SD SLOW Mode

0 0 Sharp roll-off filter

0 1 Slow roll-off filter

1 0 Minimum delay filter (default)

1 1 Reserved

Table 22. Digital Filter setting

DFS1-0: Sampling Speed Control (Table 8)

The default is “00” (Normal Speed). A click noise occurs when switching DFS1-0 bits.

DZFM: Data Zero Detect Mode

0: Channel Separated Mode (default)

1: Channel ANDed Mode

If the DZFM bit is set to “1”, the DZF pins of both channels become “H” only when the input data at both

channels are continuously zeros for 8192 LRCK cycles.

DZFE: Data Zero Detect Enable

0: Disable (default)

1: Enable

Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are

always “L”.

[AK4480]

MS1146-E-01 2010/02

- 36 -

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR SLOW

Default 0 0 0 0 0 0 0 0

SLOW: Slow Roll-off Filter Enable

0: (default)

1: Slow roll-off filter

SELLR: The data selection of L channel and R channel, when MONO mode

0: All channel output R channel data, when MONO mode. (default)

1: All channel output L channel data, when MONO mode.

It is enabled when MONO bit is “1”, and outputs Rch’s date to both channels when “0”, outputs Lch’s data

to both channels when “1”.

DZFB: Inverting Enable of DZF

0: DZF pin goes “H” at Zero Detection (default)

1: DZF pin goes “L” at Zero Detection

DZFB setting is valid regardless of the DZFE bit setting.

MONO: MONO mode Stereo mode select

0: Stereo mode (default)

1: MONO mode

When MONO bit is “1”, MONO mode is enabled.

DCKB: Polarity of DCLK (DSD Only)

0: DSD data is output from DCLK falling edge. (default)

1: DSD data is output from DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (default)

1: 768fs

DP: DSD/PCM Mode Select

0: PCM Mode (default)

1: DSD Mode

When D/P bit is changed, the AK4480 should be reset by RSTN bit.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

ATT = 20 log10 (ATT_DATA / 255) [dB]

FFH: 0dB (default)

00H: Mute

[AK4480]

MS1146-E-01 2010/02

- 37 -

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

05H Control 4 INVL INVR 0 0 0 0 0 0

Default 0 0 0 0 0 0 0 0

INVR: AOUTR Output Phase Invert

0: Disable (default)

1: Enable

INVL: AOUTL Output Phase Invert

0: Disable (default)

1: Enable

[AK4480]

MS1146-E-01 2010/02

- 38 -

SYSTEM DESIGN

Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit

examples. An evaluation board (AKD4480) demonstrates the optimum layout, power supply arrangements and

measurement results.

6

5

4

3

2

1 CSN

CAD0

CDTI

CCLK

C

AD1

DZFL

7

PSN 8

LRCK

SDATA

BICK

PDN

DVDD

VSS4

MCLK

AVDD

AK4480

Top

View

10

9 DZFR

AOUTRP

AOUTRN

11

VSS1 12

VSS3

AOUTLP

AOUTLN

VSS2

2

5

2

6

27

28

29

30

24

23

21

22

20

19

DIF2

VDD

R

13

VREFH

R

14

VDDL

VREFHL

18

17

VREFLR 15 VREFLL 16

A

nalog 5.0V

Ceramic Ca

p

acitor

+ Electrol

y

tic Ca p acitor

Lch

LPF Lch

Mute

Micro-

Con troller

Lc h Out

10u +

Rch

LPF

Rch

Mute

Rc h Out

A

nal og

Grou nd

Digital

Ground

DSP

Digital 5.0V

+

0.1u

10u

Notes:

- Power lines of AVDD and DVDD should be distributed separately from regulators with keeping low impedance.

- VSS1/2/3/4 must be connected to the same analog ground plane.

- When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the

capacitive load.

- All input pins except pull-down/pull-up pins should not be allowed to float.

Figure 17. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)

[AK4480]

MS1146-E-01 2010/02

- 39 -

Analog Ground

D igi tal Gr ound

System

Controller

SD/CAD0

DEM0/CCLK3

DEM1/CDTI4

DIF0/CAD1

5

DIF1/DZFL6

DIF2

7

PSN 8

ACKS/DZFR

9

AOUTRP

10

AOUTRN11

VSS1 12

VDRR

13

SDATA 29

BICK 28

PDN 27

DVDD 26

VSS4 25

MCLK 24

AVDD 23

VSS3 22

AOUTLP 21

A

OUTLN 20

VSS2 19

VDDL

AK4480

18

14

15

17

16

VREFHR

VREFLR

VREFHL

VREFLL

SMUTE/CSN LRCK 30

2

1

Figure 18. Ground Layout

1. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD

respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in

system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from regulators with keeping low

impedance. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be connected

to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to

the supply pin.

2. Voltage Reference

The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is

normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R

should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency

noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the

VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4480.

3. Analog Outputs

The analog outputs are full differential outputs and 2.4Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around

AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.

If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external

summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive

full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for

000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio

passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.

[AK4480]

MS1146-E-01 2010/02

- 40 -

3.9k 4.7k

150

3.9k 150

4.7k 470p

+Vop

470p

-Vop

AOUT-

AOUT+

3.9n Ana log

Out

AK4480

Figure 19. External LPF Circuit Example 1 for PCM (fc = 99.0kHz, Q=0.680)

Frequency Response Gain

20kHz −0.036dB

40kHz −0.225dB

80kHz −1.855dB

Table 23. Frequency Response of External LPF Circuit Example 1 for PCM

330

100u 180

A

OUTL-

10k

3.9

n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1u 10u

10u

NJM5534D

330

100u 180

A

OUTL+

10k

3.9n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1

u

10u

NJM5534D 0.1u

+

NJM5534D

0.1u 10u

100

4

3

2

1.0n

620

560

7

+

-

+

-

+

-

+

1.0n

Lch

-15

+15

6

560

Figure 20. External LPF Circuit Example 2 for PCM

1

st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -

Q 0.637 - -

Gain +3.9dB -0.88dB +3.02dB

20kHz -0.025 -0.021 -0.046dB

40kHz -0.106 -0.085 -0.191dB

Frequency

Response 80kHz -0.517 -0.331 -0.848dB

Table 24. Frequency Response of External LPF Circuit Example 2 for PCM

[AK4480]

MS1146-E-01 2010/02

- 41 -

It is recommended in SACD format book (the Scarlet Book) that the filter response at SACD playback is an analog low

pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum -30dB/Oct. The AK4480 can achieve this

filter response by combination of the internal filter (Table 25) and an external filter (Figure 21).

Frequency Gain

20kHz −0.4dB

50kHz −2.8dB

100kHz −15.5dB

Table 25. Internal Filter Response at DSD Mode

1.8k 4.3k

1.0k

1.8k 1.0k

4.3k 270p

+Vop

270p

-Vop

AOUT-

AOUT+

3300p Analo

g

Out

2.0k

2200

p

-

+

2.4Vpp

5.42Vpp

2.4Vpp

Figure 21. External 3rd Order LPF Circuit Example for DSD

Frequency Gain

20kHz −0.05dB

50kHz −0.51dB

100kHz −16.8dB

DC gain = 1.07dB

Table 26. 3rd Order LPF (Figure 21) Response

[AK4480]

MS1146-E-01 2010/02

- 42 -

PACKAGE

Det ail A

NO TE : Dimension "*" does not include mold flash.

0.22±0.1 0.65

*9.7±0.1 1.5MAX

A

115

16

30

30pin VS OP (Unit: m m )

5.6±0.1

7.6±0.2

0.45±0.2

-0.0 5

+0.10

0.3

0.15

0.12 M

0.08

1.2±0.10

0.10 +0.10

-0.05

■ Material & Lead finish

Package molding compound: Epoxy, Halogen (bromine and chlorine) free

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

[AK4480]

MS1146-E-01 2010/02

- 43 -

MARKING

AK4480EF

XXXXXXXXX

1) Pin #1 indication

2) AKM Logo

3) Date Code: XXXXXXX(7 digits)

4) Marking Code: AK4480

5) Audio 4 pro Logo

Date (YY/MM/DD) Revision Reason Page Contents

10/01/28 00 First Edition

10/02/17 01 Error Correct 3, 4 Pin No.9 was changed.

TST2/DZFR pin → ACKS/DZFR pin

17 OPERATION OVERVIEW

■ System Clock/[1] PCM Mode

(1) Parallel Mode, 1. Manual Setting Mode

Descriptions about the DFS0 pin were deleted.

Table 3 was deleted.

18 Table 4 and descriptions were added.

2. Auto Setting Mode

Descriptions about the DFS0 pin were deleted.

20 (2) Serial Mode, 2. Auto Setting Mode

Table 12: ACKS pin → ACKS bit

REVISION HISTORY

[AK4480]

MS1146-E-01 2010/02

- 44 -

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use

of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or

strategic materials.

z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or

other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places

the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer

or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all

claims arising from the use of said product in the absence of such notification.