LT3582/LT3582-5/LT3582-12
1
3582512fb
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Boost and Single Inductor
Inverting DC/DC Converters with
Optional I2C Programing and OTP
The LT
®
3582/LT3582-5/LT3582-12 are dual DC/DC converters
featuring positive and negative outputs and integrated feedback
resistors. The LT3582, with its built-in One Time Programming
(OTP), has confi gurable output settings via the I2C interface,
including output voltage settings, power-up sequencing,
power-down discharge, and output voltage ramp rates. LT3582
settings can be changed adaptively in the fi nal product, or set
during manufacturing and made permanent using the built in
non-volatile OTP memory. The positive output voltage can be
set between 3.2V and 12.775V in 25mV steps. The negative
output voltage can be set between –1.2V and –13.95V in
–50mV steps. The LT3582-5 and LT3582-12 are pre-confi gured
at the factory for ±5V and ±12V outputs respectively, and as
such, don’t require the use of the I2C interface.
The LT3582 series includes two monolithic converters,
one Boost and one Inverting. The Boost converter has an
integrated power switch and output disconnect switch.
The Inverting converter uses a single inductor topology
and includes an integrated power switch. Both Boost
and Inverting converters use a novel** control scheme
resulting in low output voltage ripple while allowing for high
conversion effi ciency over a wide load current range. The
LT3582 series is available in a 16-pin 3mm × 3mm QFN.
±12V Supplies from a Single 5V Input
n Output Voltages:
3.2V to 12.775V and –1.2V to –13.95V (LT3582)
5V and –5V (LT3582-5)
12V and –12V (LT3582-12)
n Digitally Re-Programmable (LT3582) via I2C for:
Output Voltages
Power Sequencing
Output Voltage Ramp Rates
n Power-Up Defaults Settable with Non-Volatile OTP
(LT3582)
n I2C Compatible Interface (Standard Mode*)
n All Power Switches Integrated
350mA Current Limit (Boost)
600mA Current Limit (Inverting)
n All Feedback Resistors Integrated
n Input Voltage Range: 2.55V to 5.5V
n Low Quiescent Current
325A in Active Mode
0.01A in Shutdown Mode
n Integrated Output Disconnect
n Tiny 16-Pin 3mm × 3mm QFN Package
n AMOLED Power
n CCD Power
n General Purpose DC/DC Conversion
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
* Input thresholds are reduced to allow communication with low voltage digital ICs.
(See Electrical Characteristics).
** Patent Pending
Effi ciency and Power Loss
LT3582
VIN
SWP
CAPP
VNEG
–12V
85mA
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
VOUTP
SHDN
INPUT
4.5V TO 5.5V
VPOS
12V
80mA
6.8µH
10µF
10nF10nF
RAMPNRAMPP
4.7µF
4.7µF
1µF
6.8µH
3582512 TA01a
I2C
INTERFACE
OPTIONAL ON
LT3582-5/LT3582-12
LOAD CURRENT (mA)
0.1
35
EFFICIENCY (%)
POWER LOSS (mW)
45
350
300
250
200
150
100
50
0
55
65
75
85
95
1 10 100
3582512 TA01b
VOUTP
VOUTN
LT3582/LT3582-5/LT3582-12
2
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
VIN Voltage ..................................................................6V
SWP Voltage .............................................................15V
SWN Voltage ........................................................ –16.5V
CAPP Voltage ............................................................15V
CAPP-VOUTP Voltage .................................... –0.8V to 8V
ICAPP-VOUTP ....................................................... ±300mA
VOUTP Voltage ...........................................................15V
VOUTN Voltage ......................................................–16.5V
RAMPP Voltage ..........................................................3V
RAMPN Voltage ..........................................................3V
SHDN Voltage ................................................ –0.5 to 6V
VPP Voltage ...................................................–0.2 to 16V
SDA, CA, SCL Voltage .................................... –0.5 to 6V
Operating Junction Temperature Range (Notes 3, 5)
LT3582E ............................................ –40°C to 125°C
Storage Temperature Range .............. –65°C to 150°C
(Note 1)
16 15 14 13
5 6 7 8
TOP VIEW
17
GND
UD PACKAGE
16-PIN (3mm × 3mm) PLASTIC QFN
9
10
11
12
4
3
2
1CA
VOUTN
SWN
SWN
SWP
CAPP
CAPP
VOUTP
SCL
SDA
VPP
GND
VIN
RAMPN
RAMPP
SHDN
TJMAX = 125°C, θJA = 68°C/W
EXPOSED PAD (PIN #17) IS GND, MUST BE SOLDERED TO PCB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN_MIN Minimum Operating Voltage l2.4 2.475 2.55 V
VIN_MAX Maximum Operating Voltage l5.5 V
IVIN VIN Quiescent Current Ramp Current Confi gured to 1A,
SWOFF Bit Active
325 450 µA
IVIN_SHDN VIN Quiescent Current in Shutdown VSHDN = 0 0.01 0.5 µA
ICAPP_SHDN CAPP Quiescent Current in Shutdown VSHDN = 0, VCAPP = 5.0V, VOUTP = 0V 0 0.5 µA
TOFF_MINP Minimum Switch Off Time Boost Switch 100 ns
TOFF_MINN Minimum Switch Off Time Inverting Switch 125 ns
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3582EUD#PBF LT3582EUD#TRPBF LDDB 16-Pin (3mm × 3mm) Plastic QFN –40°C to 125°C
LT3582EUD-5#PBF LT3582EUD-5#TRPBF LDVG 16-Pin (3mm × 3mm) Plastic QFN –40°C to 125°C
LT3582EUD-12#PBF LT3582EUD-12#TRPBF LDVH 16-Pin (3mm × 3mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
LT3582/LT3582-5/LT3582-12
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Switching Regulator Characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TON_MAX Maximum Switch On-Time Inverting and Boost Switches 10 µs
ILIMIT_P Boost Switch Current Limit l285 350 430 mA
ILIMIT_N Inverting Switch Current Limit l490 600 720 mA
RON_P Boost Switch On-Resistance ISWP = 200mA 500 mΩ
RON_N Inverting Switch On-Resistance ISWN = –400mA 560 mΩ
IOFF_P Boost Switch Leakage Current into
SWP Pin
VSWP = 5V 0.01 0.5 µA
IOFF_N Inverting Switch Leakage Current Out of
SWN Pin
VIN = 5.0, VSWN = 0.0 0.01 1 µA
RON_DIS Output Disconnect Switch
On-Resistance
VCAPP = 10V, RAMPP > 1.4V 1.4 Ω
ILIMIT_DIS Output Disconnect Current Limit l124 155 186 mA
IVOUTP_PDS VOUTP Power-Down Discharge Current VOUTP = 8V 2.4 4.8 8.8 mA
ICAPP_PDS CAPP Power-Down Discharge Current CAPP = 8V 1.2 2.4 4.4 mA
IVOUTN_PDS VOUTN Power-Down Discharge Current VOUTN = –8V –1.4 –2.8 –4.2 mA
TSTART-UP Confi guration Start-Up Delay VIN> VIN_MIN and SHDN > VSHDN_VIH to I2C
Enabled and Power-Up Sequencing Start
l64 128 s
Programmable Output Characteristics (Note 6)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VVOUTP Positive Output Voltage LT3582-5
LT3582-12
l
l
4.95
11.88
5
12
5.05
12.1
V
V
N_VOUTP Positive VOUTP Resolution (Note 2) 9 Bits
VVOUTP_LSB VOUTP LSB (Note 2) 25 mV
VVOUTP_FS VOUTP Full-Scale Voltage (Note 2) Code = BFh, VPLUS = 1 l12.56 12.775 12.94 V
VVOUTP_MIN VOUTP Minimum Voltage (Note 2) Code = 00h, VPLUS = 0 l3.152 3.20 3.248 V
VVOUTP_LR VOUTP Line Regulation Code = BFh, 2.575 < VIN < 5.5 –0.02 %/V
VVOUTN Negative Output Voltage LT3582-5
LT3582-12
l
l
–5.075
–12.1
–5
–12
–4.925
–11.868
V
V
N_VOUTN Negative VOUTN Resolution (Note 2) 8 Bits
VVOUTN_LSB VOUTN LSB (Note 2) –50 mV
VVOUTN_FS VOUTN Full-Scale Voltage (Note 2) Code = FFh l–14.2 –13.95 –13.7 V
VVOUTN_MIN VOUTN Minimum Voltage (Note 2) Code = 00h l–1.23 –1.205 –1.18 V
VVOUTN_LR VOUTN Line Regulation Code = FFh, 2.575 < VIN < 5.5 –0.01 %/V
INL_VOUTP VOUTP Integral Nonlinearity (Notes 2, 4) l±0.6 LSB
DNL_VOUTP VOUTP Differential Nonlinearity (Notes 2, 4) l±0.6 LSB
INL_VOUTN VOUTN Integral Nonlinearity (Note 2) l±0.85 LSB
DNL_VOUTN VOUTN Differential Nonlinearity (Note 2) l±0.85 LSB
IRAMP00 RAMPP/RAMPN Pull-Up Current
IRMP Code = 00
VRAMPP = 0.0V
VRAMPN = 0.0V
l0.7 1.0 1.3 µA
IRAMP01 RAMPP/RAMPN Pull-Up Current (Note 2)
IRMP Code = 01
VRAMPP = 0.0V
VRAMPN = 0.0V
l1.4 2.0 2.6 µA
LT3582/LT3582-5/LT3582-12
4
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IRAMP10 RAMPP/RAMPN Pull-Up Current (Note 2)
IRMP Code = 10
VRAMPP = 0.0V
VRAMPN = 0.0V
l2.8 4.0 5.2 µA
IRAMP11 RAMPP/RAMPN Pull-Up Current (Note 2)
IRMP Code = 11
VRAMPP = 0.0V
VRAMPN = 0.0V
l5.6 8.0 10.4 µA
VVPLUS VOUTP Voltage Increase When VPLUS Bit is
Set from 0 to 1 (Note 2)
25 mV
Input/Output Pin Characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSHDN_VIH SHDN Input Voltage High l1.1 V
VSHDN_VIL SHDN Input Voltage Low l0.3 V
VHYST_SHDN SHDN Input Hysteresis 50 mV
ISHDN_BIAS SHDN Pin Bias Current VSHDN = 1V 2.5 4.5 6.5 µA
VCA_VIH CA Input Voltage High l0.7 × VIN V
VCA_VIL CA Input Voltage Low l0.3 × VIN V
VSDA_VIH SDA Input Voltage High l1.25 V
VSDA_VIL SDA Input Voltage Low l0.85 V
VSCL_VIH SCL Input Voltage High l1.25 V
VSCL_VIL SCL Input Voltage Low l0.85 V
VHYST Input Hysteresis SDA, SCL Pins 80 mV
ILEAK_CA CA Input Leakage Current CA = 0V and 5.5V l±1 µA
ILEAK_SCL SCL Input Leakage Current SCL = 0V and 5.5V l±1 µA
ILEAK_SDA SDA Input Leakage Current SDA = 0V and 5.5V l±1 µA
CIN Input Capacitance SDA, SCL Pins 3 pF
VSDA_OL SDA Output Low Voltage 3mA into SDA Pin l0.4 V
VPP_RANGE VPP Voltage Range for OTP Write (Note 2) 13 15 V
VPPUVLO Undervoltage Lockout for VPP Pin (Note 2) l12.05 12.45 12.85 V
I2C Timing Characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL Serial Clock Frequency l100 kHz
tLOW Serial Clock Low Period l4.7 µs
tHIGH Serial Clock High Period l4.0 µs
tBUF Bus Free Time Between Stop and Start l4.7 µs
tHD,STA Start Condition Hold Time l4.0 µs
tSU,STA Start Condition Setup Time l4.7 µs
tSU,STO Stop Condition Setup Time l4.0 µs
tHD,DATXMIT Data Hold Time Transmitting LT3582 Sending Data to Host l300 ns
tHD,DATRCV Data Hold Time Receiving LT3582 Receiving Data from Host l0ns
tSU,DAT Data Setup Time l250 ns
tFSDA Fall Time 400pF Load, VIN ≥ 2.5V l250 ns
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VSHDN = VIN unless otherwise noted. (Note 3)
Programmable Output Characteristics
LT3582/LT3582-5/LT3582-12
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: LT3582 only.
Note 3: The LT3582E is guaranteed to meet performance specifi cations
from 0°C to 125°C junction temperature. Specifi cations over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlations with statistical process controls.
Note 4: These specifi cations apply to the VP trim bits in REG0 using a
50mV LSB and do not include the additional VPLUS trim bit. See
Registers
and OTP
in the Applications Information section.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specifi ed maximum operating junction temperature may impair device
reliability.
Note 6: Output voltage is measured under non-switching test conditions
approximating a moderate load current from the output.
LT3582/LT3582-5/LT3582-12
6
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TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequencies (Figure 13) Load Regulation (Figure 13) Output Voltage (Figure 13)
Quiescent Current – Not Switching Switch Resistance Switch Current Limit
VOUTP and VOUTN Pin Current
During Normal Operation
Output Disconnect PMOS Current
Limit During Normal Operation
Output Disconnect PMOS
On-Resistance
TA = 25°C unless otherwise noted.
LOAD CURRENT (mA)
020406080
10
FREQUENCY (kHz)
100
1000
10000
100
3582512 G01
VOUTP
VOUTN
LOAD CURRENT (mA)
020406080
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
∆VOUT/VOUT (%)
1.00
100
3582512 G02
VOUTP
VOUTN
TEMPERATURE (°C)
–50 –25 0 5025 75 100
–0.45
–0.30
–0.15
0
0.15
0.30
0.45
∆VOUT/VOUT (%)
125
3582512 G03
VOUTP
VOUTN
VIN (V)
2.5 3 3.5 4.54 5 5.5
250
270
290
310
330
350
370
390
QUIESCENT CURRENT (µA)
3582512 G04
INPUT VOLTAGE (V)
2.5 3 3.5 4.54 5 5.5
0
0.1
0.2
0.3
0.4
0.5
0.6
O.7
SWITCH RESISTANCE ()
3582512 G05
VOUTN
VOUTP
TEMPERATURE (°C)
–50 –25 0 5025 75 125100
200
300
400
500
600
700
SWITCH CURRENT LIMIT (mA)
3582512 G06
SWN
SWP
|VOUT| (V)
0 2.5 5 107.5 12.5 15
–20
–40
–60
–80
–100
0
20
40
60
80
PIN CURRENT (µA)
3582512 G07
CURRENT OUT
OF VOUTN PIN
CURRENT INTO
VOUTP PIN
VP CODE
SET TO 5V
VP CODE
SET TO 12V
VN CODE
SET TO –5V
VN CODE
SET TO –12V
TEMPERATURE (°C)
–50 –25 0 5025 75 100 125
120
100
140
160
180
200
PMOS CURRENT LIMIT (mA)
3582512 G08
VCAPP (V)
24 861012
0.5
0
1
1.5
2
2.5
ON-RESISTANCE ()
3582512 G09
LT3582/LT3582-5/LT3582-12
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TYPICAL PERFORMANCE CHARACTERISTICS
Switching Waveform at 1mA Load
(Boost)
Switching Waveform at 10mA
Load (Boost)
Switching Waveform at 100mA
Load (Boost)
Switching Waveform at 1mA Load
(Inverting)
Switching Waveform at 10mA
Load (Inverting)
Load Transient, VOUTN, 30mA to
60mA to 30mA Steps
Load Transient, VOUTP
, 30mA to
60mA to 30mA Steps
Power-Up Sequencing Waveforms
(PUSEQ = 11)
Power-Down Discharge
Waveforms
(PUSEQ = 11, PDDIS = 1)
3582512 G10
VVOUTP
10mV/DIV
AC COUPLED
VSWP
5V/DIV
IL2
0.2A/DIV
5μs/DIV 3582512 G11
VVOUTP
10mV/DIV
AC COUPLED
VSWP
5V/DIV
IL2
0.2A/DIV
2μs/DIV 3582512 G12
VVOUTP
10mV/DIV
AC COUPLED
VSWP
5V/DIV
IL2
0.2A/DIV
200ns/DIV
3582512 G13
VVOUTN
20mV/DIV
AC COUPLED
VSWN
10V/DIV
IL1
0.2A/DIV
5μs/DIV 3582512 G14
VVOUTN
50mV/DIV
AC COUPLED
VSWN
10V/DIV
IL1
0.2A/DIV
5μs/DIV 3582512 G15
LOAD
CURRENT
–20mA/DIV
VVOUTN
0.1V/DIV
AC COUPLED
IL1
0.2A/DIV
50
μ
s/DIV
3582512 G16
LOAD
CURRENT
20mA/DIV
VOUTP
0.2V/DIV
AC COUPLED
IL2
0.2A/DIV
50μs/DIV 3582512 G17
VRAMPN
1V/DIV
VRAMPP
1V/DIV
VVOUTP
5V/DIV
VVOUTN
5V/DIV
5ms/DIV 3582512 G18
VRAMPP
1V/DIV
VRAMPN
1V/DIV
VVOUTN
5V/DIV
VVOUTP
5V/DIV
5ms/DIV
Note: All waveforms on this page apply to Figure 13.
LT3582/LT3582-5/LT3582-12
8
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PIN FUNCTIONS
CA (Pin 1): I2C Address Select Pin. Tie this pin to VIN to set
the 7-bit address to 0110 001. Tie to GND for 1000 101.
VOUTN (Pin 2): Negative Output Voltage Pin. When the con-
verter is operating, this pin is regulated to the programmed
negative output voltage. Place a ceramic capacitor from
this pin to GND.
SWN (Pins 3, 4): Negative Switching Node for the In-
verting Converter. This is the drain of the internal PMOS
power switch. Connect one end of the Inverting inductor
to these pins. Keep the trace area on these pins as small
as possible.
VIN (Pin 5): Input Supply Pin and Source of the PMOS
Power Switch. This pin must be bypassed locally with a
ceramic capacitor. The operating voltage range of this pin
is 2.55V to 5.5V.
RAMPN (Pin 6): Soft-Start Ramp Pin for the Inverting
Converter. Place a capacitor from this pin to GND. A
programmable current of 1A to 8A (LT3582) or 1µA
(LT3582-5/LT3582-12) charges this pin during start-up,
limiting the ramp rate of VOUTN. This pin is discharged to
GND during shutdown.
RAMPP (Pin 7): Soft-Start Ramp Pin for the Boost Convert-
er. Place a capacitor from this pin to GND. A programmable
current of 1A to 8A (LT3582) or 1µA (LT3582-5/LT3582-12)
charges this pin during start-up, limiting the ramp rate of
VOUTP. This pin is discharged to GND in shutdown.
SHDN (Pin 8): Shutdown Pin. Drive this pin to 1.1V or
higher to enable the part. Drive to 0.3V or lower to shut
down. Includes an integrated 222k pull-down resistor.
VOUTP (Pin 9): Output of the Boost Converter Output
Disconnect Circuit. A ceramic capacitor should be placed
from this node to GND. During shutdown, this pin is
disconnected from the Boost network which allows this
pin to discharge to GND, assuming a load is present to
discharge the capacitance.
CAPP (Pins 10, 11): Connect the Boost output capacitor
from these pins to GND. During shutdown, the voltage on
these pins will remain close to the input voltage due to
the path through the Boost inductor and Schottky. During
normal operation, CAPP will be boosted slightly higher
than the programmed output voltage.
SWP (Pin 12): Positive Switching Node for the Boost
Converter. This is the drain of the internal NMOS power
switch. Connect one end of the Boost inductor to this pin.
Keep the trace area on this pin as small as possible.
GND (Pin 13): Ground Pin. Tie to a local ground plane.
Proper PCB layout is required to achieve advertised per-
formance; see the Applications Information section for
more information.
VPP (Pin 14): Programming Voltage Pin. Drive this pin
to 13-15V when programming the OTP memory. Float
otherwise. A bypass capacitor should be placed from this
node to GND if VPP is used for programming. If VPP falls
below 13V during OTP programming, an internal FAULT
bit, which can be read through the I2C interface, can be
set high.
SDA (Pin 15): I2C Bidirectional Data Pin. Tie to GND or
VIN if unused.
SCL (Pin 16): I
2C Clock Pin. Tie to GND or VIN if un-
used.
Exposed Pad (Pin 17): Ground Pin. Tie to a local ground
plane. Proper PCB layout is required to achieve advertised
performance; see the Applications Information section for
more information.
LT3582/LT3582-5/LT3582-12
9
3582512fb
BLOCK DIAGRAM
+
–
+
–
VIN
SWN
SWN
FBN
VCN VCP
OTP
RAMPN
RAMPP
VOUTN
3582512 BD
CAPP
GND
SHDNCHIP ENABLE
222k
VPP
SCL
SDA
CA
OTP
SWP CAPP VOUTP
–
+
–
+
+
–
–
+
–
+
+
2V
OTP ADJUST
OTP ADJUST
0.80V
0.75V
CAPP VOUTP
VOUTN
VIN
FBP
FBN
50mV
2V
OUTPUT SEQUENCING
BY OTP
IPEAK TOFF
CONTROL
IPEAK TOFF
CONTROL
QS
QR
QS
QR
VARIABLE DELAY VARIABLE DELAY
–
+
+
–
+
DISCONNECT
CONTROL
SERIAL INTERFACE,
LOGIC AND OTP
OUTPUT SEQUENCING
VIN
0.80V
FBP
LT3582/LT3582-5/LT3582-12
10
3582512fb
OPERATION
The LT3582 series are dual DC/DC converters, each contain-
ing both a Boost and an Inverting converter. Operation can
be best understood by referring to the Block Diagram. The
Boost and Inverting converters each use a novel control
technique, which simultaneously varies both peak inductor
current and switch off time. This results in high effi ciency
over a large load range and low output voltage ripple. In
addition, this technique further minimizes output ripple
when the switching frequency is in the audio band.
Boost Converter: The Boost converter uses a grounded
source NMOS power transistor as the main switching ele-
ment. The current in the NMOS is constantly monitored and
controlled, along with the off-time of the switch to achieve
regulation of VOUTP. The VOUTP voltage is divided by the
internal programmable (LT3582 only) resistor divider to
create FBP. The voltage on FBP is compared to an internal
reference and amplifi ed, creating an error signal on the
VCP node which commands the appropriate peak inductor
current and off time for the subsequent switching cycle.
Inverting Converter: The Inverting converter uses a power
PMOS transistor with the source connected to VIN. This
topology requires only one external inductor, instead of
the normally required two inductors plus fl ying capacitor.
Regulation is achieved in a similar manner as the Boost.
Output Power-Up Sequencing: After an initial start-up
delay (TSTART-UP = 64s typical), the outputs VOUTP and
VOUTN rise (in magnitude) simultaneously with the LT3582-5/
LT3582-12 or in one of four selectable sequences with
the LT3582. Using the I2C interface, the LT3582 outputs
can be confi gured such that (1) they both rise simultane-
ously, (2) VOUTP rises to regulation before VOUTN rises, (3)
VOUTN rises to regulation before VOUTP rises, or (4) neither
output rises. The outputs of the LT3582-5 and LT3582-12
are pre-confi gured to rise simultaneously.
The ramp rates of the outputs are proportional to the ramp
rates of their respective RAMP pins. A capacitor is placed
between each RAMP pin and ground. The RAMP pins are
discharged during shutdown. Once enabled, confi gurable
(LT3582) or pre-confi gured (LT3582-5/LT3582-12) cur-
rents charge each RAMP pin in the desired sequence
causing the outputs to rise.
Output Power-Down Discharge: The power-down dis-
charge feature is permanently enabled on the LT3582-5
and LT3582-12 and can be enabled or disabled through
I2C on the LT3582. Upon SHDN falling, and when power-
down discharge is enabled, internal transistors will acti-
vate to assist in discharging the outputs toward ground.
When power-down discharge is disabled, the chip powers
down immediately after SHDN falls and the outputs will
discharge on their own depending on their external load
capacitances and currents.
OTP Memory (LT3582 Only): The LT3582 includes 22 bits
of user programmable output settings and 1 programming
lockout bit. Parameters such as positive and negative output
voltages and power sequencing settings can be changed
in real time with the integrated I2C interface. Settings can
then be made permanent by programming to the on-chip
non-volatile OTP (One Time Programmable) memory.
LT3582/LT3582-5/LT3582-12
11
3582512fb
APPLICATIONS INFORMATION
Figure 1. Data Transfer Over I2C Bus
I2C Interface
The LT3582 series contains an I2C compatible interface
allowing it to be digitally confi gured. The use of this interface
is optional for the LT3582-5 and LT3582-12 as these parts
are pre-confi gured at the factory. The CA, SDA and SCL
pins can be grounded if the I2C interface is unused.
The I2C interface has reduced input threshold voltages to
allow for direct communication with low voltage digital
ICs (see Electrical Characteristics). I2C communication
is disabled when SHDN is low. After SHDN rises, I2C
communication is re-enabled after a delay of 64s (typical).
The chip is a read-write slave device which allows the user
to read the current settings and, for the LT3582, write
new ones. Most settings can be made permanent via the
One-Time-Programmable memory. The chip will always
enable using the data stored in OTP and the LT3582 can
be reconfi gured after power-up.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a START
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 1. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between transmitter and receiver to indicate that the most
recent byte of data was received. The transmitter always
releases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it pulls down the SDA line
so that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge
by leaving SDA high, then the master may abort the
transmission by generating a STOP condition. When the
master is receiving data from the slave, the master pulls
down the SDA line during the clock pulse to indicate receipt
of the data. After the last byte has been received the master
leaves the SDA line HIGH (not acknowledge) and issues a
stop condition to terminate the transmission.
Device Addressing
The LT3582 series supports two 7-bit chip addresses
depending on the logic state of the CA pin. The addresses
are 0110 001 (CA = 1) and 1000 101 (CA = 0). Also, there
are seven internal data byte locations as shown in Table 1.
OTP0-OTP2 are the OTP memory bytes. REG0-REG2
are the corresponding volatile registers used for storing
alternate settings. Finally, the Command Register (CMDR)
is used for additional control of the chip.
3582512 F01
SCL
SDA
R/WCHIP
ADDRESS
START
CONDITION
STOP
CONDITION
ACK DATA ACK DATA
1-7
B7 - B0B7 - B0A6 - A0
891-7 8 91-7 8
S P
9
ACK
LT3582/LT3582-5/LT3582-12
12
3582512fb
All data bytes can be read from their assigned register
addresses. Since they share the same register addresses,
reads of the OTP and REG data bytes are differentiated
by their corresponding RSEL (Register Select) bits in the
CMDR register. All data written to register addresses 0-2 is
stored in REGO-REG2. Regardless of the RSEL bits, OTP
bytes cannot be written directly. See the OTP Programming
section for more information.
Data Transfer Protocol
The LT3582 series supports 8-bit data transfers in the
transaction formats shown in Figures 2 and 3. Multiple
data bytes can only be transferred by issuing multiple
transactions.
Figure 2 shows the required format for writing a byte of
data to the LT3582 series. Again, the chip address depends
on the CA pin logic state.
S CHIP ADDR WA REG ADDR A DATA A P
0110 001 OR
1000 101
0 0 00000b2:b0 0 b7:b0 0
FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW)
FROM SLAVE TO MASTER A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
Figure 2. I2C Byte Write Transaction
A byte of data is read from the LT3582 series using the
format shown in Figure 3. This transaction requires four I2C
bytes to read one byte of chip data and must be repeated
for each subsequent byte of data that is read.
S CHIP ADDR WA REG ADDR A
0110 001 OR
1000 101
0 0 00000b2:b0 0
LT3582 Chip Confi guration
Settings such as output voltages and sequencing are
digitally programmable. The chip uses settings from either
the REG or OTP bytes, depending on the states of the
corresponding RSEL bits (0 for OTP and 1 for REG).
During shutdown the RSEL bits are reset low. As a result,
the initial confi guration comes from the OTP data bytes.
After power-up, the confi guration can be changed by writing
new settings to the appropriate REG data byte(s) then
setting the corresponding RSEL bit(s).
Finally, data in the REG bytes can be permanently
programmed to OTP by applying voltage to the VPP pin
and setting the WOTP bit in the Command Register. See
the
OTP Programming
section for more information.
LT3582-5/LT3582-12 Chip Confi guration
The LT3582-5/LT3582-12 are shipped from the factory with
the OTP memory pre-programmed and LOCKed which
prohibits subsequent changes to the confi guration. The
confi guration can still be read through the I2C bus and
the RST and SWOFF bits of the CMDR register (described
later) are functional. The following sections describe the
various confi gurable features of the LT3582. The LT3582-5
and LT3582-12 are pre-confi gured as follows: VP and VN
are programmed for ±5V or ±12V respectively, LOCK = 1,
IRMP = 00, PDDIS = 1, PUSEQ = 11 and VPLUS may be 1
or 0. Since LOCK = 1, subsequent confi guration changes
are prohibited. See
Confi guration Lockout (LOCK Bit)
for
more information.
Registers and OTP
The registers and OTP bytes for the LT3582 series are
organized as shown in Table 1. The CMDR is reset to 00h
upon power-up, during shutdown and during undervoltage
and thermal lockouts.
REG0-REG2 are never reset and must
always be loaded with valid data before use.
The LT3582’s
OTP memory is shipped with all 0’s, and as a result, the
PUSEQ bits are confi gured to disable the outputs. The
PUSEQ bits must be reconfi gured to enable the outputs.
APPLICATIONS INFORMATION
S CHIP ADDR R A DATA AP
0110 001 OR
1000 101
1 0 b7:b0 1
Figure 3. I2C Byte Read Transaction
LT3582/LT3582-5/LT3582-12
13
3582512fb
CMDR: The Command Register is used to control various
functions of the chip. During shutdown and power-up the
CMDR is initialized to 00h.
The RSEL (Register Select) bits are functional only for
the LT3582. The LT3582-5 and LT3582-12 function as if
the RSEL bits are always “0”. These bits perform three
functions:
• Each RSEL bit instructs the chip whether to use the
confi guration data from the corresponding OTP byte
(RSELx = 0) or the REG byte (RSELx = 1). Changing an
RSELx bit immediately updates the chip confi guration.
• Each RSEL bit determines if I2C reads return data from
the corresponding OTP byte (RSELx = 0) or the REG
byte (RSELx = 1).
• OTP programming only programs data to the bytes with
corresponding RSEL bits set high.
Setting the SWOFF bit immediately disables the Boost
and Inverting power switches and opens the output dis-
connect PMOS switch. It is recommended to set this bit
before writing new confi guration data. This can prevent
unexpected chip behavior while modifying the confi gura-
tion and also forces a soft-start after SWOFF is cleared
(see
Soft-Start and Power-Up Sequencing
). Writing “1”
to the RST bit resets the internal I2C logic and the CMDR
register. Reading bit 6 of the CMDR returns the FAULT bit
indicating if an OTP programming attempt may have failed.
FAULT is cleared during reset, power-up, or by writing a “1”
to the CF (Clear Fault) bit. Conditions that set the FAULT
bit are (1) OTP programming in which the VPP voltage
is too low or (2) attempted OTP programming when the
LOCK bit is set.
OTP write attempts that set the FAULT bit
due to low VPP voltage should be considered failures and
the device should be discarded. Attempts to re-program
the OTP memory after the FAULT bit has been set are not
recommended.
Finally, setting the WOTP bit starts the
OTP programming.
Table 1: LT3582 Series Register Map
REGISTER
ADDRESS
REGIS-
TER
NAME
BIT BIT
NAME
DESCRIPTION
00h REG0/
OTP0
7:0 VPVOUTP Output Voltage (00h=3.2V,
BFh = 12.75V)
01h REG1/
OTP1
7:0 VNVOUTN Output Voltage (00h=1.2V,
FFh = 13.95V)
7 - Reserved, Write to 0
6 LOCK Lockout Bit: See the
OTP
Programming Lockout
Section.
02h REG2/
OTP2
5V
PLUS VOUTP Output Voltage Bit: Increase
VOUTP by ~25mV
4:3 IRMP RAMPP and RAMPN Pull-Up
Current: IRAMP = (2) IRMP µA
2 PDDIS Power-Down Discharge Enable.
PUSEQ Must be 11 if Set.
1:0 PUSEQ Power-Up Sequencing: 00 =
Outputs Disabled, 01 = VOUTN
Ramp 1st, 10 = VOUTP Ramp 1st,
11 = Both Ramp Together
7 WOTP Write OTP Memory
6 CF/
FAULT
Clear Fault/OTP Programming
Fault
5 RST Reset
4 SWOFF Switches-Off
04h CMDR 3 - Reserved, Write to 0
2 RSEL2 Register Select 2 (0 = OTP2,
1 = REG2)
1 RSEL1 Register Select 1 (0 = OTP1,
1 = REG1)
0 RSEL0 Register Select 0 (0 = OTP0,
1 = REG0)
OTP0/REG0 and OTP1/REG1: Data in addresses 00h and
01h is used to set the output voltages of the Boost and
Inverting converters respectively. See
Setting the Output
Voltages
for more information.
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
14
3582512fb
OTP2/REG2: Data in address 02h confi gures the output
voltage sequencing, sets a fi ne voltage adjust for VOUTP,
and determines if further OTP programming is permitted or
not. Proper uses of the bits in address 02h are discussed
in the following sections.
Setting the Output Voltages (VP , VPLUS and VN Bits)
The LT3582 series contains two resistor dividers which are
programmable in the LT3582, to set the output voltages.
The positive output voltage VOUTP is adjustable in 25mV
steps by setting the VP bits in REG0/OTP0 in addition to
the VPLUS bit in REG2/OTP2.
V
OUTP = 3.2V + (VP • 50mV) + (VPLUS • 25mV)
where:
V
P = an integer value from 0 to 191
V
PLUS = 0 or 1
The VOUTN voltage is adjustable in –50mV steps by setting
the VN bits in REG1/OTP1.
V
OUTN = –1.2V – (VN • 50mV)
where:
V
N = an integer value from 0 to 255
Dynamically Changing the Output Voltage (LT3582 Only):
After output regulation has been reached, it’s possible to
change the output voltages by writing new values to the
VN or VP bits. When reducing the magnitude of an out-
put voltage, it will decay at a rate dependent on the load
current and capacitance. Confi guring a large increase in
magnitude of an output voltage can cause a large increase
in switch current to charge the output capacitor. Before
reconfi guring the outputs, consider forcing a soft-start
by asserting the SWOFF bit before writing the new VP or
VN codes. Subsequently clearing SWOFF initiates the new
soft-start sequence.
Soft-Start/Output Voltage Ramping (IRMP Bits)
The LT3582 series contains soft-start circuitry to control the
output voltage ramp rates, therefore limiting peak switch
currents during start-up. High switch currents are inherent
in switching regulators during start-up since the feedback
loop is saturated due to VOUT being far from its fi nal value.
The regulator tries to charge the output capacitor as quickly
as possible which results in large currents.
Capacitors must be connected from RAMPP and RAMPN
to ground for soft-start. During shutdown or when the
SWOFF bit is set, the RAMP capacitors are discharged
to ground. After SHDN rises or SWOFF is cleared, the
capacitors are charged by programmable (LT3582 only)
currents, thus creating linear voltage ramps. The VOUT
voltages ramp in proportion to their respective RAMP
voltages according to:
VOUT _RAMP _RATE =VOUT
0.8V
⎛
⎝
⎜⎞
⎠
⎟•IRAMP
CRAMP
⎛
⎝
⎜⎞
⎠
⎟Volts / Sec
Proportionality Constant
RAMP pin ramp rate (V/Sec)
where:
IRAMP = RAMP pin charging current set by IRMP
bits (1A, 2A, 4A or 8A for LT3582,
1µA for LT3582-5/LT3582-12)
CRAMP = External RAMP pin capacitor (Farads)
VOUT = Output voltage during regulation
For example, selecting IRAMP = 1A, CRAMP = 10nF and
VOUTP = 12V results in a power-up ramp rate of 1.5Volt/ms
(see Figure 6).
Ramp rates less than 1-10V/ms generally result in good
start-up characteristics. The outputs should linearly follow
the RAMPx voltages with no distortions. Figure 7 shows
an excessive start-up ramp rate of ~120V/ms in which
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
15
3582512fb
several start-up issues have occurred: A) the expected
VOUTP ramp up path is not followed B) inductor current
ringing occurs C) the VOUTP ramp rate is limited due to
the output disconnect current limit being reached D) ad-
ditional ringing occurs when the CAPP pin starts charging
E) output voltage overshoot occurs because the inductor
currents are maximized during the output ramp-up.
In some cases it may be desirable to use only one RAMP
pin capacitor. In cases where PUSEQ = 11 (see the
Power-
Up Sequencing
section) the RAMPP and RAMPN pins
can be connected together and to a single capacitor. In
this case the capacitor will charge with twice the current
confi gured by the IRMP bits.
Ramping VOUTP from Ground: The LT3582 series has
the unique ability to generate a smooth VOUTP voltage
ramp starting from ground and continuing all the way up
to regulation (see Figure 6). This ability is not possible
with typical Boost converters in which the output is taken
from the cathode of the Schottky diode (CAPP node in
Figure 5).
L1
D1
SWP
C1
VOUTP
C3
VIN
C2
CAPP
LT3582
SERIES
DISCONNECT
CONTROL LOAD
3582512 F05
APPLICATIONS INFORMATION
The LT3582 series incorporates an output disconnect
PMOS allowing VOUTP to be grounded during shutdown.
Once enabled, the Disconnect Control circuit actively
drives the PMOS gate allowing VOUTP to ramp up linearly
as shown in Figure 6. Once VOUTP reaches regulation,
the PMOS is fully turned “on” to reduce resistance and
improve effi ciency.
Power-Up Sequencing (PUSEQ bits)
Once enabled, the part requires a delay of TSTART-UP (64s
typ) to properly confi gure itself. Once confi gured, the order
in which VOUTP and VOUTN ramp to regulation is controlled
by the PUSEQ bits. The combinations available for the
LT3582 are shown in Table 2. The LT3582-5/LT3582-12
are pre-confi gured with the 11 combination.
Table 2. Power-Up Sequences
PUSEQ[1:0] Power-Up Sequence
00 Outputs are disabled, neither output ramps up
01 VOUTN ramps up 1st, followed by VOUTP
10 VOUTP ramps up 1st, followed by VOUTN
11 Both VOUTP and VOUTN ramp-up starting at the same time.
Selecting the 01 or 10 combinations cause one of the out-
puts to start ramping shortly after SHDN rises. The ramp
rate of VOUT is controlled by the RAMP pin as discussed
in the Soft-Start section. After VOUT nears its target regula-
Figure 5. Boost Converter Topology
Figure 6. VOUTP Soft-Start Ramping from Ground
Figure 7. VOUTP Soft-Start with Excessive Ramp Rate
3582512 F06
CAPP
2V/DIV
IL2
0.2A/DIV
VRAMPP
0.2V/DIV
VOUTP
2V/DIV
1ms/DIV
3582512 F07
VOUTP
3V/DIV
VRAMPP
0.5V/DIV
CAPP
3V/DIV
IL2
0.2A/DIV
50μs/DIV
A
C
E
BD
LT3582/LT3582-5/LT3582-12
16
3582512fb
tion voltage, the remaining output is activated and ramps
under control of its respective RAMP pin (see Figure 8).
The power-up sequencing concludes when both outputs
have reached regulation.
Evaluating PUSEQ Settings (LT3582 Only): After SHDN
rises, the LT3582 uses the PUSEQ confi guration found
in OTP. The effects of differing PUSEQ settings can be
observed without writing to OTP by taking the following
actions:
1. Write the SWOFF bit high, stopping both converters
and discharging the RAMP pins.
2. Write the desired settings to the PUSEQ bits in REG2.
3. Set the RSEL2 bit high which selects the REG2 con-
fi guration settings.
4. Write SWOFF low which restarts both converters.
This will initiate the desired power-up sequence that can
be observed with an oscilloscope.
Power-Down Discharge (PDDIS bit)
The PDDIS bit is used to enable power-down discharge.
This bit is pre-confi gured to a “1” for the LT3582-5 and
LT3582-12, thus enabling power-down discharge.Setting
PDDIS = 0 disables the power-down discharge causing
the chip to shut down immediately after SHDN falls.
APPLICATIONS INFORMATION
The PDDIS bit must only be set in conjunction with
PUSEQ being set to 11. Driving SHDN low, with power-
down discharge enabled (PDDIS = 1) causes the chip to
power-down after fi rst discharging the output voltages.
Specifi cally, driving SHDN low causes the following se-
quence of events to happen:
1. Both converters are turned off.
2. Discharge currents are enabled to discharge the output
capacitors
• See Electrical Characteristics for IVOUTP-PDS and
ICAPP-PDS which help discharge VOUTP and CAPP
• See Electrical Characteristics for IVOUTN-PDS which
helps discharge VOUTN
3. The chip waits until the output voltages have discharged
to within ~0.5V to ~1.5V of ground.
4. Discharge currents are disabled and the LT3582 powers
down.
Since the LT3582 series won’t power-down until both
outputs are discharged (when power-down sequencing is
enabled), make sure VOUTP and VOUTN can be grounded.
This is not a problem in most topologies. However, read
the section
Output Disconnect Operating Limits
for ad-
ditional information.
Figure 8. Power-Up Sequencing (PUSEQ = 10)
3582512 F08
VVOUTP
5V/DIV
VVOUTN
5V/DIV
VRAMPP
0.5V/DIV
VRAMPN
0.5V/DIV
5ms/DIV
RAMPN
RAMPP
LT3582/LT3582-5/LT3582-12
17
3582512fb
Confi guration Lockout (LOCK bit)
After a desired confi guration is programmed into OTP, the
LOCK bit can be set to prohibit subsequent changes to the
confi guration. The LT3582-5 and LT3582-12 are precon-
fi gured with the LOCK bit set to a logic “1” which:
• Forces the chip to use the OTP confi guration only.
• Forces all I2C reads from addresses 0-2 to return OTP
data.
• Prohibits any further programming of the OTP memory.
Any further attempts to program OTP leaves the OTP
memory unchanged and sets the FAULT bit in the
CMDR.
The LOCK OTP bit is set by programming a logic “1” into
bit 6 of OTP2. Regardless of the RSEL2 setting, I2C reads
of the LOCK bit always indicate the LOCKed or unlocked
state of the OTP memory.
OTP Programming (LT3582 only)
The LT3582 contains One Time Programmable non-vola-
tile memory to permanently store the chip confi guration.
Before programming, it’s recommended to set the SWOFF
bit to disable switching activity and prevent unexpected
chip behavior while the confi guration is being changed.
Programming involves the transfer of information from
the REG bytes to the OTP bytes. Therefore, valid data must
fi rst be written to the desired REG bytes. After the REG
bytes are written, they are selected by setting the cor-
responding RSEL bits in the CMDR. This forces the chip
into the desired confi guration and selects those bytes for
programming to OTP. After 15V has been applied to VPP,
the WOTP bit is set in the CMDR to start the programming.
Finally, the WOTP bit is cleared to fi nish the programming.
An example programming algorithm is given below.
OTP programming draws about 3mA to 6mA per bit from
the VPP pin. It is possible to program all 23 bits simultane-
ously (up to ~138mA), but it is recommended that one byte
is programmed at a time to reduce noise on VPP caused
by the sudden change in current. A 1-10F VPP bypass
capacitor is also recommended to prevent voltage droop
after programming begins. Also, avoid hot-plugging VPP
which results in very fast voltage ramp rates and can lead
to excessive voltage on the VPP pin.
Example OTP Programming Algorithm:
1. Apply 15V to the VP-P pin. This can be done at any
time before step 5.
2. Write 50h to the CMDR. This disables the power
switches during programming by setting the SWOFF
bit in the CMDR. This also clears the FAULT bit.
3. Write desired data to REG0-REG2.
4. Write 11h to the CMDR. This selects REG0 for pro-
gramming while keeping the switches off.
5. Write 91h to the CMDR. This programs the REG0 data
to OTP0.
6. Write 11h to the CMDR. This command can be sent im-
mediately after step 5. This stops the programming.
7. Read the CMDR and verify that the FAULT bit is not
set.
8. Repeat steps 4-7 for the remaining bytes that need
programming.
9. Write 10h to the CMDR. This selects the OTP data for
read verifi cation.
10. Read the OTP data and verify the contents.
11. Write 00h to CMDR. This enables the power switches
and the chip will operate from the OTP confi gura-
tion.
12. Float the VPP pin. This can be done at any time after
step 8.
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
18
3582512fb
Choosing Inductors
Several series of inductors that work well with the LT3582
series are listed in Table 3. This table is not complete, and
there are many other manufacturers and parts that can
be used. Consult each manufacturer for more detailed
information and for their entire selection of related parts,
as many different sizes and shapes are available.
Table 3. Inductor Manufacturers
Coilcraft LPS3008-LPS4018 Series,
XPL2010 Series
www.coilcraft.com
Murata LQH32C, LQH43C Series www.murata.com
Sumida CDRH26D09, CDRH26D11,
CDRH3D14 Series
www.sumida.com
TDK VLF and VLCF Series www.tdk.com
Würth
Elektronik
WE-TPC Series Type T, TH,
XS and S
www.we-online.com
Inductances of 2.2H to 10µH typically result in a good
tradeoff between inductor size and system performance.
More inductance typically yields an increase in effi ciency
at the expense of increased output ripple. Less inductance
may be used in a given application depending on required
effi ciency and output current. For higher effi ciency, choose
inductors with high frequency core material, such as ferrite,
to reduce core losses. Also to improve effi ciency, choose
inductors with more volume for a given inductance. The
inductor should have low DCR (copper-wire resistance)
to reduce I2R losses, and must be able to handle the peak
inductor current without saturating. To minimize radiated
noise, use a toroidal or shielded inductor (note that the
inductance of shielded types will drop more as current
increases, and will saturate more easily).
Peak Current Rating: Real inductors can experience a drop
in inductance as current and temperature increase. The
inductors should have saturation current ratings higher
than the peak inductor currents. The peak inductor cur-
rents can be calculated as:
IPK ≅ILIMIT +VLSWON •TOS
LmA
where:
IPK = Peak inductor current
ILIMIT = Typically 350mA for Boost and 600mA
for Inverting
L = Inductance in µH
VLSWON = Maximum inductor voltage when the
power switch is “on.” Typically max VIN
for the Boost and Inverting converters.
TOS = 100 for Boost and 125 for Inverting
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
19
3582512fb
Maximum Load Currents: Use one of the following equa-
tions to estimate the maximum output load current for the
positive and negative output voltages:
IOUTP =
VIN(MIN)
VOUTP
⎛
⎝
⎜⎞
⎠
⎟•IPK –TOFF _MIN •(V
OUTP +0.5 – VIN(MIN))
2•L
⎛
⎝
⎜⎞
⎠
⎟•0.8η
or IOUTN =
VIN(MIN)
VIN(MIN)+|V
OUTN |
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟•IPK –TOFF _MIN •(|V
OUTN |+0.5)
2•L
⎛
⎝
⎜⎞
⎠
⎟•0.8η
where:
VOUT = Regulation voltage
VIN(MIN) = Minimum input voltage.
IPK = Peak inductor current. See the
Peak
Current Rating
section. Use minimum
I
LIMIT rating for these calculations.
η = Power conversion effi ciency (about 88%
for Boost or 78% for Inverting)
TOFF_MIN = Minimum switch off time. Typically 100ns
for Boost and 125ns for Inverting.
IOUT = Output load current
For example, if VOUTP = 10V, VOUTN = –10V, VIN = 5V, and
L = 4.7H then IOUTP = 117mA and IOUTN = 105mA.
Note: The 155mA (Typ) current limit of the output dis-
connect PMOS (see Electrical Characteristics) may limit
maximum IOUTP unless CAPP is shorted to VOUTP. See the
Improving Boost Converter Effi ciency
section.
Maximum Slew Rate: Lower inductance causes higher
current slew rates which can lead to current limit over-
shoot. Choose an inductance higher than LMIN to limit
the overshoot:
L
MIN = VIN(MAX) • 0.2µH
where VIN(MAX) is the maximum input voltage. Using the
previous example VIN = 3V, LMIN = 0.6H.
Capacitor Selection
The small size and low ESR of ceramic capacitors makes
them suitable for most LT3582 series applications. X5R
and X7R types are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 4.7F input capaci-
tor and a 2.2F to 10F output capacitor are suffi cient for
most LT3582 series applications. Always use a capacitor
with a suffi cient voltage rating. Many capacitors rated at
2.2F to 10F, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired output voltage.
Generally a 1206 capacitor will be adequate. A 0.22F to
1F capacitor placed on the CAPP node is recommended
to fi lter the inductor current while the larger 2.2F to 10F
placed on the VOUTP and VOUTN nodes will give excellent
transient response and stability. Avoid placing large value
capacitors (generally > 6.8F) on both CAPP and VOUTP.
This confi guration can be less stable since it creates two
poles, one at the CAPP pin and the other at the VOUTP
pin, which can be near each other in frequency. Table 4
shows a list of several capacitor manufacturers. Consult
the manufacturers for more detailed information and for
their entire selection of related parts.
Table 4. Ceramic Capacitor Manufacturers
MANUFACTURER PHONE URL
Kemet 408-986-0424 www.kemet.com
Murata 814-237-1431 www.murata.com
Taiyo Yuden 408-573-4150 www.t-yuden.com
TDK 847-803-6100 www.tdk.com
Diode Selection
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3582 series. The Diodes Inc. B0540WS is a very good
choice in a small SOD-323 package. This diode is rated to
handle an average forward current of 500mA and performs
well across a wide temperature range. Schottky diodes
with very low forward voltage drops are also available.
These diodes may improve effi ciency at moderate and cold
temperatures, but will likely reduce effi ciency at higher
temperatures due to excessive reverse leakage currents.
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
20
3582512fb
Output Disconnect Operating Limits
The LT3582 series has a PMOS output disconnect switch
connected between CAPP and VOUTP. During normal
operation, the switch is closed and current is internally
limited to about 155mA (see Figure 9). Make sure that the
output load current doesn’t exceed the PMOS current limit.
Exceeding the current limit causes a signifi cant rise in PMOS
power consumption which may damage the device.
During shutdown, the PMOS switch is open and CAPP is
isolated from VOUTP up to a voltage difference of 5-5.5V.
In most cases this allows VOUTP to discharge to ground.
However, when the Boost inductor input exceeds 5.5V, the
CAPP-VOUTP voltage may exceed 5V allowing some current
fl ow through the PMOS switch. In addition, applying CAPP-
VOUTP voltages in excess of 5.7V(typical) may activate
internal protection circuitry which turns the PMOS “on”
(see Figure 10). If the current is not limited, this can lead
to a sharp increase in the PMOS power consumption and
may damage the device. If this situation cannot be avoided,
limit PMOS power consumption to less than 1/3 Watt (about
50mA at 7V) to avoid damaging the device. Refer to the
Absolute Maximum Ratings table for maximum limits on
CAPP-VOUTP voltages and currents.
Improving Boost Converter Effi ciency
The effi ciency of the Boost converter can be improved by
shorting the CAPP pin to the VOUTP pin (see Figure 11). The
power loss in the PMOS disconnect circuit is then made
negligible. In most applications, the associated CAPP pin
capacitor can be removed and the larger VOUTP capacitor
can adequately fi lter the output voltage.
APPLICATIONS INFORMATION
LT3582
VIN
CAPP
CAPP
VOUTP
SDA
VPP
CASHDN
GND
SWN
SWN
VOUTN
3582512 F12
SCL
SWP
81
16
15
14
9
10
11
5
12
76
2
13
3
4
RAMPNRAMPP
C1 ILOAD
Figure 10. PMOS Current vs Voltage During Shutdown
Figure 11. Improved Effi ciency
ICAPP-VOUTP
20µA/DIV
VCAPP-VOUTP 1V/DIV 3582512 F11
Figure 9. PMOS Current vs Voltage During Normal Operation
CAPP-VOUTP (mV)
0 100 200 400300 500
0
20
40
100
80
120
140
60
160
180
PMOS CURRENT (mA)
3582512 F10
LT3582/LT3582-5/LT3582-12
21
3582512fb
APPLICATIONS INFORMATION
Note that the ripple voltage on VOUTP will typically increase
in this confi guration since the output disconnect PMOS,
when not shorted, helps to create an RC fi lter at the
output. Also, if the VOUTP pin is shorted to CAPP, the
power-down discharge should not be enabled. VOUTP
cannot be discharged to ground during shutdown due to
the path from VIN to VOUTP through the external inductor
and diode. Finally, due to the path from VIN to VOUTP ,
current will fl ow through the integrated feedback resistor
whenever voltage is present on VIN.
Inrush Current
When the Boost inductor input voltage (usually VIN) is
stepped from ground to the operating voltage, a high
level of inrush current may fl ow through the inductor
and Schottky diode into the CAPP capacitor. Conditions
that increase inrush current include a larger more abrupt
voltage step at the inductor input, larger CAPP capacitors
and inductors with low inductances and/or low saturation
currents. For circuits that use output capacitor values within
the recommended range and have input voltages of less
than 5V, inrush current remains low, posing no hazard to
the devices. In cases where there are large input voltage
steps (more than 5V) and/or a large CAPP capacitor is
used, inrush current should be measured to ensure safe
operation.
Thermal Lockout
If the die temperature reaches approximately 147°C, the
part will go into thermal lockout. In this event, the chip
is reset which turns off the power switches and starts to
discharge the RAMP capacitors. The part will be re-enabled
when the die temperature drops by about 3.5°C.
Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement. To
maximize effi ciency, switch rise and fall times are made as
short as possible. To prevent electromagnetic interference
(EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have sharp rising and falling edges.
Minimize the length and area of all traces connected to
the SWP/SWN pins and always use a ground plane under
the switching regulator to minimize interplane coupling.
Suggested component placement is shown in Figure 12.
Make sure to include the ground plane cuts as shown in
Figure 12. The switching action of the regulators can cause
large current steps in the ground plane. The cuts reduce
noise by recombining the current steps into a continuous
fl ow under the chip, thus reducing di/dt related ground
noise in the ground plane.
Figure 12. Suggested Component Placement (Not to Scale)
GROUND PLANE
VIAS TO GROUND PLANE UNDER
PIN 17 REQUIRED TO IMPROVE
THERMAL PERFORMANCE
3582512 F13
VOUTP
COUTP
CCAPP
COUTN
VOUTN
GND
VIN
CIN
CVPP
(OPT)
CA
16
1
2
3
4
56 7 8
15 14 13
12
11
10
9
SCL SDA VPP
L1
L2
17
SHDN
LT3582/LT3582-5/LT3582-12
22
3582512fb
LT3582
VIN
SWP
CAPP
VNEG
–12V
85mA
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
VOUTP
SHDN
INPUT
4.5V TO 5.5V
VPOS
12V
80mA
L1
6.8µH
D1
C2
4.7µF
C6
10nF
C5
10nF
RAMPNRAMPP
C3
C1
4.7µF
C4
1µF
D2
L2
6.8µH
REG0/OTP0 = B0h
REG1/OTP1 = D8h
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT XPL2010-682
C1: 4.7µF, 6.3V, X5R, 0805
C2: 4.7µF, 16V, X5R, 0805
C3: 1s 4.7µF OR 2s 4.7µF OR 10µF
16V, X5R, 0805
C4: 1µF, 16V, X5R, 0603
C5-C6: 10nF, 0603
3582512 TA05a
I2C
INTERFACE
OPTIONAL ON
LT3582-12
LOAD CURRENT (mA)
02040 8060
15
10
5
0
20
25
OUTPUT RIPPLE (mV)
3582512 TA05b
LOAD CURRENT (mA)
200408060
40
20
0
60
80
OUTPUT RIPPLE (mV)
3582512 TA05c
4.7µF 16V 0805 X5R
10µF 16V 0805 X5R
2× 4.7µF 16V 0805 X5R
Figure 13. ±12V Outputs from a Single 5V Input
VOUTP Ripple VOUTN Ripple and C2 Selection
Also See Typical Characteristics and Front Page for Additional Data
APPLICATIONS INFORMATION
LT3582/LT3582-5/LT3582-12
23
3582512fb
TYPICAL APPLICATION
LT3582
VIN
SWP
CAPP
VNEG
–5V
100mA (VIN ≥ 2.7V)
125mA (VIN ≥ 3.3V)
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
VOUTP
SHDN
INPUT
2.7V TO 3.8V
VPOS
5V
100mA (VIN ≥ 2.7V)
124mA (VIN ≥ 3.3V)
REG0/OTP0 = 24h
REG1/OTP1 = 4Ch
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7µF, 6.3V, X5R, 0805
C2-C3: 10µF, 6.3V, X5R 0805
C4: 1µF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
L1
6.8µH
D1
C2
10µF
C6
22nF
C5
22nF
RAMPNRAMPP
C1
4.7µF
C3
10µF
D2 C4
1µF
L2
6.8µH
3582512 TA02a
I2C
INTERFACE
OPTIONAL ON
LT3582-5
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85
100
90
80
70
60
50
40
30
20
10
0
55
75
95
1 10 100
3582512 TA02b
VIN = 3.3V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85
180
160
140
120
100
80
60
40
20
0
55
75
95
1 10 100
3582512 TA02c
VIN = 3.3V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85
300
250
200
150
100
50
0
55
75
95
1 10 100
3582512 TA02d
VIN = 3.3V
±5V Outputs from a Single 2.7V to 3.8V Input
Effi ciency and Power Loss, Load from VOUTP to GND Effi ciency and Power Loss, Load from VOUTN to GND
Effi ciency and Power Loss, Load from VOUTP to VOUTN
LT3582/LT3582-5/LT3582-12
24
3582512fb
TYPICAL APPLICATION
LT3582
VIN
SWP
CAPP
VNEG
–5V
100mA (VIN ≥ 2.7V)
125mA (VIN ≥ 3.3V)
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
VOUTP
SHDN
INPUT
2.7V TO 3.8V
VPOS
5V
110mA (VIN ≥ 2.7V)
150mA (VIN ≥ 3.3V)
REG0/OTP0 = 24h
REG1/OTP1 = 4Ch
REG2/OTP2 = 03h
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7µF, 6.3V, X5R, 0805
C2-C3: 10µF, 6.3V, X5R, 0805
C4: 1µF, 6.3V, X5R, 0603
C5-C6: 22nF, 0603
L1
6.8µH
D1
C2
10µF
RAMPNRAMPP
C1
4.7µF
C6
22nF
C5
22nF
D2 C3
10µF
L2
6.8µH
3582512 TA03
I2C
INTERFACE
OPTIONAL ON
LT3582-5
±5V Outputs from a Single 2.7V to 3.8V Input (Improved Effi ciency)
Effi ciency and Power Loss, Load from VOUTP to GND
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85
80
70
60
50
40
30
20
10
0
55
75
95
1 10 100
3582512 TA03a
VIN = 3.3V
LT3582/LT3582-5/LT3582-12
25
3582512fb
TYPICAL APPLICATION
LT3582
VIN
SWP
CAPP
VNEG
–5V
100mA
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
I2C
INTERFACE
VOUTP
SHDN
INPUT
2.7V TO 5.5V
VPOS
12V
38mA (VIN = 2.7)
58mA (VIN = 3.6)
95mA (VIN = 5.5)
REG0/OTP0 = B0h
REG1/OTP1 = 4Ch
REG2/OTP2 = 0Bh
D1-D2: DIODES INC. B0540WS-7
L1-L2: COILCRAFT LPS4018-682ML
C1: 4.7µF, 6.3V, X5R, 0805
C2: 10µF, 6.3V, X5R, 0805
C3: 4.7µF, 16V, X5R, 0805
C4: 1µF, 16V, X5R, 0603
C5-C6: 22nF, 0603
L1
6.8µH
D1
C2
10µF
RAMPNRAMPP
C1
4.7µF
C6
22nF
C5
22nF
D2 C4
1µF
C3
4.7µF
L2
6.8µH
3582512 TA04a
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85 80
90
100
70
60
50
40
30
20
10
0
55
75
95
1 10 100
3582512 TA04b
VIN = 3.6V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85
180
160
140
120
100
80
60
40
20
0
55
75
95
1 10 100
3582512 TA04c
VIN = 3.6V
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
35
45
65
85 160
180
200
140
120
100
80
60
40
20
0
55
75
95
1 10 100
3582512 TA04d
VIN = 3.6V
12V and –5V Outputs from a Single 2.7V to 5.5V Input
Effi ciency and Power Loss, Load from VOUTP to VOUTN
Effi ciency and Power Loss, Load from VOUTP to GND Effi ciency and Power Loss, Load from VOUTN to GND
LT3582/LT3582-5/LT3582-12
26
3582512fb
PACKAGE DESCRIPTION
3.00 p 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 p 0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.45 p 0.10
(4-SIDES)
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
15 16
2
0.50 BSC
0.200 REF
2.10 p 0.05
3.50 p 0.05
0.70 p0.05
0.00 – 0.05
(UD16) QFN 0904
0.25 p0.05
0.50 BSC
PACKAGE OUTLINE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
LT3582/LT3582-5/LT3582-12
27
3582512fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 11/09 Revised Title and Add text to Description
Revised Pin Confi guration
Added Text to I2C Interface Section
Revised Typical Application Drawings
1
2
11
22, 23, 24
(Revision history begins at Rev B)
LT3582/LT3582-5/LT3582-12
28
3582512fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
LT 0110 REV B • PRINTED IN USA
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TYPICAL APPLICATION
LT3582
VIN
SWP
CAPP
VNEG
–5V
90mA
CAPP
VPP
SDA
SCL
CA
GND
SWN
SWN
VOUTN
I2C
INTERFACE
VOUTP
SHDN
INPUT
2.7V TO 4.2V
VPOS
4.6V
100mA
L1
1.5µH
D1
C2
10µF
C6
10nF
C5
10nF
RAMPNRAMPP
C3
10µF
C1
10µF
D2 C4
10µF
L2
1.5µH
REG0/OTP0 = 1Ch
REG1/OTP1 = 4Ch
REG2/OTP2 = 07h
D1-D2: PANASONIC M21D3800L LOW VF SCHOTTKY
L1-L2: TDK MLP3216S1R5L
C1-C4: TAIYO YUDEN JMK212BJ106MK, 6.3V, X5R 0805
C5-C6: 0402 X5R
3582512 TA06a
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (mW)
30
40
60
80
350
300
250
200
150
100
50
0
50
70
90
1 10 100
3582512 TA06b
VIN = 3.3V
Tiny AMOLED Power Supply is 0.8mm (Max) Thin Effi ciency and Power Loss, Load from VOUTP to VOUTN
