NJU8715 PRELIMINARY Switching Driver with Regulator for Class-D Headphone Amplifier PACKAGE OUTLINE GENERAL DESCRIPTION The NJU8715 is a switching driver with regulator for class-D headphone amplifier. It incorporates an optimum regulator for the driver of headphone amplifier, class-D line amplifier and a beep amplifier. The NJU8715 converts 1bit digital signal of the PWM or the PDM to an analog signal output through a simple external LC low-pass filter. The NJU8715 provides a completed digital system and high power-efficiency with class-D operation. Therefore, it is suitable for portable audio applications. NJU8715KN1 FEATURES 2-channel 1bit Audio Signal Input Headphone Output Built-in Class D Line Amplifier Built-in Regulator for Driver Beep Function Logic Operating Voltage 1.9 to 2.6V (VDD) Regulator Operating Voltage 4.0 to 5.75V (VG) 1.9 to 4.0V (VREG) C-MOS Technology Package Outline QFN28 28 ENVG ENREG EN2 EN1 VDD MCK VSS PIN CONFIGURATION 1 MODEB BEEPIN DIN2 DIN1 OBEEP1 VSS OUT1 VDD Charge Pump Regulator VDDO1 VSS DIN1 VREGO CFB VCONT VREG VG CH CL BLOCK DIAGRAM VREF VDDO1 VREGO VREG VCONT VREF CFB VDDO2 CL CH VG NC OBEEP2 VSS OUT2 Pre Driver Level Shifter HP Amp OUT1 Level Shifter Pre Driver LINE Amp Level Shifter Pre Driver HP Amp DIN2 Level Shifter Pre Driver LINE Amp BEEPIN Level Shifter MCK VSS VDDO2 OUT2 Ver.2005-03-09 BEEP Amp OBEEP1 BEEP Amp OBEEP2 MODEB ENVG ENREG EN2 EN1 Control Logic VSS -1- NJU8715 TERMINAL DESCRIPTION No. SYMBOL I/O 1 MODE B I 2 3 4 5 6, 16, 22 BEEPIN DIN2 DIN1 OBEEP1 VSS I I I O - 7 OUT1 O 8 9 10 11 12 13 14 VDDO1 VREGO VREG VCONT VREF CFB VDDO2 O I I O I - 15 OUT2 O 17 18 19 20 21 OBEEP2 NC VG CH CL O - 23 MCK I 24 25 26 VDD EN1 EN2 I I 27 ENREG I 28 ENVG I Function BEEP Output Level Control Terminal H: -39dBm, L: -48dBm The load of 16 (Note.1) BEEP Signal Input Terminal Audio Signal Input Terminal 2 Audio Signal Input Terminal 1 BEEP Output Terminal 1 Power GND: VSS=0V (Note.2) Output Terminal 1 This terminal outputs DIN1 terminal input data. Driving Power Supply 1 Regulator Output Terminal Regulator Input Terminal Regulator Output Voltage Control Terminal Reference Voltage Output Terminal Regulator Output Voltage Sense Terminal Driving Power Supply 2 Output Terminal 2 This terminal outputs DIN2 terminal input data. BEEP Output Terminal 2 Non connection Pre-driver Power supply + Capacitor Connection Terminal for the charge pump - Capacitor Connection Terminal for the charge pump Master Clock Input Terminal The condition of the data input terminal is latched on the rising edge of this signal. Operation Power Supply HP/LINE/BEEP Mode Control Terminal 1 (with pull-down resistor) HP/LINE/BEEP Mode Control Terminal 2 (with pull-down resistor) Regulator Enable Terminal (with pull-down resistor) H : ON, L : OFF Charging pump Enable Terminal (with pull-down resistor) H : ON, L : OFF Note.1) 0dBm0.775Vrms Note.2) VSS(Terminal No.6,16,22) should be connected at the nearest point to the IC. INPUT TERMINAL STRUCTURE MCK, DIN1, DIN2, BEEPIN, MODEB Terminal VDD Input Terminal VSS -- 2 2 -- EN1, EN2, ENREG, ENVG Terminal VDD Input Terminal VSS Ver.2005-03-09 NJU8715 NJU3555 FUNCTIONAL DESCRIPTION (1) Power Supply VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD. VG : Power supply for pre-driver which drives the transistor gates of output drivers. When ENVG=H, charge pump generates double the voltage of VDD, which is supplied to VG terminal through the inside. When ENVG=L, charge pump is halted, and VG terminal accepts the external power supply. VREG : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is provided to the drivers. Furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by connecting de-coupling capacitor to get highly smoothed power supply. (2) Regulator Output Voltage Control Terminal (VCONT) VCONT is the control terminal for regulator output voltage. As VREG output voltage is variable from 0V by external DC voltage, driver output level can be used as sound volume. (3) Regulator Enable Signal (ENREG) The regulator is halted at "L" level, and works at "H" level. (4) Charging pump Enable Signal (ENVG) The charge pump is halted at "L" level, and works at "H" level. (5) HP/LINE/BEEP Mode Control Terminal (EN1 / EN2) Each mode can be selected by a combination setting of EN1 and EN2. The following table shows each output condition of each mode. Mode Standby Mode LINE Mode HP Mode BEEP Mode Input EN1 EN2 L L L H H L H H HP Amp. HiZ HiZ Active HiZ Output LINE Amp. HiZ Active HiZ HiZ BEEP Amp. HiZ HiZ HiZ Active (6) BEEP Signal Input (BEEPIN) (7) BEEP Signal Output (OBEEP1 / OBEEP2) BEEP signal is output in a square wave. (8) Master Clock (MCK) Master clock (MCK) synchronizes the audio signal inputs(DIN1, DIN2). The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are latched on the rising edge of MCK. During the standby condition, MCK requires "L" level to avoid unnecessary power consumption. In addition, MCK requires jitter-free or fewer jitter because the jitter could lead to poor S/N ratio. (9) Signal output (OUT1 / OUT2) OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage. Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2 terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals via 2nd-order or higher LC filter. Ver.2005-03-09 -3- NJU8715 POWER ON/DOWN SEQUENCE The pop-noise can be effectively suppressed with the following sequence when power ON and DOWN. (1) Power ON / Power DOWN Sequence (ENVG=H: Using internal VG) < Power On sequence > 1) Input the MCK after the start-up of VDD. After of 100ms delay or more from MCK input, set ENVG at "H" level. 2) Set ENSEG at "H" level after 5ms delay or more.(at 0.1F for the charge pump and 1F for the smoothing capacitor) 3) After setting ENREG at "H" level, input audio signals(DIN1, DIN2). 4) Set EN1 at "H" level and EN2 at "L" level after audio signal input. The audio signal input must be "Sound-less data" until VCONT reaches a steady state. 5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target VCONT voltage is short, it may cause a pop-noise. < Power Down sequence > The sequence must be executed in inverse order of the power ON sequence. VDD, VREG ENVG VG ENREG 100ms or more 100ms or more VCONT EN1 EN2 MCK DIN1, DIN2 Undefined Data* OUT1, OUT2 High impedance Sound-less Data Audio Data Sound-les Data Audio signal output Undefined Data* High impedance * : Do not set DIN1 and DIN2 at "H" level before the start-up of VDD. -- 4 4 -- Ver.2005-03-09 NJU8715 NJU3555 (2)Power ON / Power DOWN Sequence(ENVG=L, VG: Externally applied) < Power ON sequence > 1) Input the MCK after the start-up of VDD. Apply VG after the start-up VDD.(As shown in the following sequence, VG increases to VDD through a internal protection diode after VDD is turned on.) 2) Set ENREG at "H" level after the start-up of VG. 3) After setting ENREG at "H" level, input audio signals(DIN1, DIN2). 4) Set EN1 at "H" level and EN2 at "L" level after audio signal input. The audio signal input must be "Sound-less data" until VCONT reaches a steady state. 5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target VCONT voltage is short, it may cause a pop-noise. < Power DOWN sequence > The sequence must be executed in inverse order of the power ON sequence. VDD, VREG ENVG VG ENREG 100ms or more 100ms or more VCONT EN1 EN2 MCK DIN1, DIN2 Undefined Data* OUT1, OUT2 High impedance Sound-less Data Audio data Audio signal output Sound-less Data Undefined Data* High impedance * : Do not set DIN1 and DIN2 at "H" level before the start-up of VDD. Ver.2005-03-09 -5- NJU8715 ABSOLUTE MAXIMUM RATINGS PARAMETER (Ta=25C) UNIT SYMBOL RATING VDD -0.3 ~ +2.75 V VREG -0.3 ~ +5.5 V VG VDD ~ +6.0 V Input Voltage Vin -0.3 ~ VDD+0.3 V Operating Temperature Ta -20 ~ +85 C Tstg -40 ~ +125 C PD 640 mW Supply Voltage Storage Temperature Power Dissipation Note.3) The relations of VDDO1,VDDO2<VG, VREG<VG and VDD<VG must be maintained during operations. Note.4) All voltage values are specified as VSS=VSSO=0V. Note.5) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note.6) De-coupling capacitors for "VDD-VSS", "VDDO1-VSSO" and "VDDO2-VSS" should be connected for stable operation. -- 6 6 -- Ver.2005-03-09 NJU8715 NJU3555 ELECTRICAL CHARACTERISTICS (1) DC CHARACTERISTICS PARAMETER SYMBOL VDD Supply Voltage VDD VG Supply Voltage VG HP Driver High side Resistance (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) CONDITIONS MIN TYP MAX UNIT 1.9 2.0 2.6 V VG: Externally applied 4.0 5.0 5.75 V RHPH OUT1, 2=VDDO1, 2-0.1V - 1.2 2 HP Driver Low side Resistance RHPL OUT1, 2=0.1V - 1.2 2 Line Driver High side Resistance RLINEH OUT1, 2=VDDO1, 2-0.1V VDDO1, 2=2.75V 7.7 11 14.3 Line Driver Low side Resistance RLINEL OUT1, 2=0.1V VDDO1, 2=2.75V 7.7 11 14.3 VBEEPL MODEB=L -50 (2.45) -48 (3.08) -46 (3.88) MODEB=H -41 (6.91) -39 (8.70) -37 (10.95) (mVrms) - - 1 A - 0.95 1.6 BEEP Output Voltage VBEEPH Power Supply Current At Standby IST IDD1 Power Supply Current At Operating (Mute signal input) IREG1 IDD2 IREG2 IG2 VIH Digital Input Voltage VIL Standby Mode Stopping MCK,DIN1,DIN2,BEEPIN ENREG=L Using internal VG HP Mode No-load operating, MCK=256fs DIN1,DIN2=16fs, ENREG=H VG: Externally applied, HP Mode No-load operating, MCK=256fs, DIN1,DIN2=16fs,ENREG=H VG=5V MCK, DIN1, DIN2 BEEPIN, MODEB EN1, EN2, ENREG, ENVG Input Leakage Current ILK MCK, DIN1, DIN2 BEEPIN, MODEB Pull-down Resistance RPD EN1, EN2, ENREG, ENVG Ver.2005-03-09 dBm mA - 0.70 1.2 - 0.05 0.10 - 0.70 1.2 - 0.75 1.2 0.7VDD - VDD V 0 - 0.3VDD V - - 1 A 150 300 450 k mA -7- NJU8715 (2) REGULATOR CHARACTERISTICS PARAMETER SYMBOL (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) CONDITIONS MIN TYP MAX UNIT VREGH HP MODE 1.9 2.15 4.0 V VREGL LINE MODE 3.0 - 4.0 V 1.9 2.0 2.1 V 0.23 0.33 0.43 V 2.8 2.9 3.0 V 0.38 0.48 0.58 V Input Voltage VDDOH1 VDDOH2 Output Voltage VDDOL1 VDDOL2 HP MODE VCONT=1.5V, VREG=2.5V HP MODE VCONT=0.5V, VREG=2.5V LINE MODE VCONT=1.5V, VREG=3.5V LINE MODE VCONT=0.5V, VREG=3.5V Output Current IOUT 70 - - mA Sink Current ISINK 60 - - mA Dropout Voltage VIO Iout=70mA VDDO1, 2=1.7V - - 0.2 V Ripple Rejection RR Vr=0.1Vrms, Iout=70mA fr=1kHz 36 44 - dB Load Regulation Voltage VLR IREGO=0 ~ 24.3mArms - - 520 Vrms Residual Voltage VMIN VCONT=0.1V - - 10 mV 0 - VREG V VCONT VCONT The following figure shows a representative example of VCONT versus VREGO. At VCONT=1.5V: VREGO=2.0V(VREG=2.5V) in HP MODE, VREGO=2.9V(VREG=3.5V) in LINE MODE. At VCONT=0.5V: VREGO=0.33V(VREG=2.5V) in HP MODE, VREGO=0.48V(VREG=3.5V) in LINE MODE. 4.0 3.5 VREGO (V) 3.0 2.5 LINE MODE 2.0 1.5 1.0 HP MODE 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VCONT (V) -- 8 8 -- Ver.2005-03-09 NJU8715 NJU3555 (3) AC CHARACTERISTICS * * Master Clock PARAMETER (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) SYMBOL CONDITIONS MIN TYP MAX UNIT Frequency fMCKI 8 - 50 MHz Pulse Width (H) tMCKH 8 - - ns Pulse Width (L) tMCKL 8 - - ns MIN TYP MAX UNIT Digital Audio Data PARAMETER SYMBOL DIN1, DIN2 Setup Time tDS 5 - - ns DIN1, DIN2 Hold Time tDH 5 - - ns tEr, tEf - - 50 ns EN1, EN2, ENREG, ENVG, BEEPIN, MODEB Rise Time, Fall Time CONDITIONS tMCKH 0.7VDD MCK 0.3VDD tMCKL 0.7VDD DIN1, DIN2 0.3VDD tDS tDH MCK, DIN1, DIN2 Timing chart 0.7VDD 0.3VDD tEr tEf EN1, EN2, ENREG, ENVG, BEEPIN, MODEB Timing chart Ver.2005-03-09 -9- NJU8715 APPLICATION CIRCUIT (1) Using Internal VG (ENVG=H) OBEEP1 MCK 47H BEEPIN VREG 16 Head Phone 2.2F 10F Regulator Input 220F 0.22F OUT1 DIN2 4.7k DIN1 VSS VSS OBEEP2 47H 1F 1F VDDO1 VDDO2 4.7k VREGO 220F 0.22F NJU8715 CFB 220F OUT2 16 Head Phone VREGO Control Signal VCONT 10F VREF -- 10 10 -- VSS 100F 2.2F MODEB EN2 EN1 1F VG ENVG CL VDD VDD ENREG 0.1F CH Ver.2005-03-09 NJU8715 NJU3555 (2) VG: Externally applied (ENVG=L) OBEEP1 MCK 47H DIN1 BEEPIN 4.7k 0.22F DIN2 VREG 16 Head Phone 2.2F 10F Regulator Input 220F OUT1 VSS VSS OBEEP2 47H 1F VDDO1 1F 220F VDDO2 4.7k VREGO 0.22F NJU8715 CFB 220F OUT2 16 Head Phone VREGO Control Signal VCONT 10F VREF CH VSS 100F 2.2F MODEB EN2 EN1 ENVG 1F VG ENREG CL VG VDD VDD Note.7) CH and CL pins must be opened when VG externally applied. Note.8) De-coupling capacitors must be connected between each power supply pin and GND pin. The capacitor value should be adjusted on the application circuit and the temperature. It may malfunction if capacity value is small. Note.9) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is recommened for high power efficiency. Note.10) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2005-03-09 - 11 - Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NJR: NJU8715KN1