NJU8715
-1-
Ver.2005-03-09
Switching Driver with Regulator
for Class-D Headphone Amplifier
GENERAL DESCRIPTION
The NJU8715 is a switching driver with regulator for
class-D headphone amplifier. It incorporates an
optimum regulator for the driver of headphone amplifier,
class–D line amplifier and a beep amplifier. The
NJU8715 converts 1bit digital signal of the PWM or the
PDM to an analog signal output through a simple
external LC low-pass filter.
The NJU8715 provides a completed digital system
and high power-efficiency with class-D operation.
Therefore, it is suitable for portable audio applications.
FEATURES
2-channel 1bit Audio Signal Input
Headphone Output
Built-in Class D Line Amplifier
Built-in Regulator for Driver
Beep Function
Logic Operating Voltage 1.9 to 2.6V (VDD)
Regulator Operating Voltage 4.0 to 5.75V (VG)
1.9 to 4.0V (VREG)
C-MOS Technology
Package Outline QFN28
BLOCK DIAGR AM
PACKAGE OUTLINE
PIN CONFIGURATION
NJU8715KN1
MODEB
BEEPIN
DIN2
DIN1
OBEEP1
VSS
OUT1
VDDO1
VREGO
VREG
VCONT
VREF
CFB
VDDO2
ENVG
ENREG
EN2
EN1
VDD
MCK
VSS
CL
CH
VG
NC
OBEEP2
VSS
OUT2
28
1
BEEPIN
DIN1
MC
K
VDD
VSS
DIN2
OUT1
VREGO
VREG
OBEEP1
OBEEP2
CFB
CH
EN1
ENREG
EN2
ENVG
MODEB
VREF
Level Shifter
Control Logic
Regulato
r
VSS
VDDO1
OUT2
VSS
VDDO2
VCONT
CL
Charge
Pum
p
VG
Pre Driver
Level Shifte
r
Level Shifte
r
Level Shifter
Level Shifter
Pre Driver
Pre Driver
Pre Driver
HP Amp
HP Amp
LINE Amp
LINE Amp
BEEP Amp
BEEP Amp
PRELIMINARY
NJU8715
- 2 -
- 2 - Ver.2005-03-09
TERMINAL DESCRI PTION
No. SYMBOL I/O Function
1 MODE B I
BEEP Output Level Control Terminal
H: -39dBm, L: -48dBm The load of 16Ω (Note.1)
2 BEEPIN I BEEP Signal Input Terminal
3 DIN2 I Audio Signal Input Terminal 2
4 DIN1 I Audio Signal Input Terminal 1
5 OBEEP1 O BEEP Output Terminal 1
6, 16, 22 VSS - Power GND: VSS=0V (Note.2)
7 OUT1 O
Output Terminal 1
This terminal outputs DIN1 terminal input data.
8 VDDO1 - Driving Power Supply 1
9 VREGO O Regulator Output Terminal
10 VREG I Regulator Input Terminal
11 VCONT I Regulator Output Voltage Control Terminal
12 VREF O Reference Voltage Output Terminal
13 CFB I Regulator Output Voltage Sense Terminal
14 VDDO2 - Driving Power Supply 2
15 OUT2 O
Output Terminal 2
This terminal outputs DIN2 terminal input data.
17 OBEEP2 O BEEP Output Terminal 2
18 NC - Non connection
19 VG - Pre-driver Power supply
20 CH - + Capacitor Connection Terminal for the charge pump
21 CL - - Capacitor Connection Terminal for the charge pump
23 MCK I
Master Clock Input Terminal
The condition of the data input terminal is latched on the rising
edge of this signal.
24 VDD - Operation Power Supply
25 EN1 I HP/LINE/BEEP Mode Control Terminal 1 (with pull-down resistor)
26 EN2 I HP/LINE/BEEP Mode Control Terminal 2 (with pull-down resistor)
27 ENREG I
Regulator Enable Terminal (with pull-down resistor)
H : ON, L : OFF
28 ENVG I
Charging pump Enable Terminal (with pull-down resistor)
H : ON, L : OFF
Note.1) 0dBm≅0.775Vrms
Note.2) VSS(Terminal No.6,16,22) should be connected at the nearest point to the IC.
INPUT TERMIN AL STRUCTURE
MCK, DIN1, DIN2, BEEPIN, MODEB Terminal
VDD
VSS
Input
Terminal
VDD
VSS
Input
Terminal
EN1, EN2, ENREG, ENVG Terminal
NJU3555NJU8715
-3-
Ver.2005-03-09
FUNCTIONAL DESCRIPTION
(1) Power Supply
VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD.
VG : Power supply for pre-driver which drives the transistor gates of output drivers.
When ENVG=H, charge pump generates double the voltage of VDD, which is supplied to VG terminal
through the inside.
When ENVG=L, charge pump is halted, and VG terminal accepts the external power supply.
VREG : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of
regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is
provided to the drivers. Furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by
connecting de-coupling capacitor to get highly smoothed power supply.
(2) Regulator Output Voltage Control Terminal (VCONT)
VCONT is the control terminal for regulator output voltage. As VREG output voltage is variable from 0V by
external DC voltage, driver output level can be used as sound volume.
(3) Regulator Enable Signal (ENREG)
The regulator is halted at “L” level, and works at “H” level.
(4) Charging pump Enable Signal (ENVG)
The charge pump is halted at “L” level, and works at “H” level.
(5) HP/LINE/BEEP Mode Control Terminal (EN1 / EN2)
Each mode can be selected by a combination setting of EN1 and EN2.
The following table shows each output condition of each mode.
Input Output
Mode EN1 EN2 HP Amp. LINE Amp. BEEP Amp.
Standby Mode L L HiZ HiZ HiZ
LINE Mode L H HiZ Active HiZ
HP Mode H L Active HiZ HiZ
BEEP Mode H H HiZ HiZ Active
(6) BEEP Signal Input (BEEPIN)
(7) BEEP Signal Output (OBEEP1 / OBEEP2)
BEEP signal is output in a square wave.
(8) Master Clock (MCK)
Master clock (MCK) synchronizes the audio signal inputs(DIN1, DIN2). The setup time and the hold time should
be kept in the AC characteristics because DIN1 and DIN2 are latched on the rising edge of MCK. During the
standby condition, MCK requires “L” level to avoid unnecessary power consumption. In addition, MCK requires
jitter-free or fewer jitter because the jitter could lead to poor S/N ratio.
(9) Signal output (OUT1 / OUT2)
OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage.
Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2
terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals
via 2nd-order or higher LC filter.
NJU8715
- 4 -
- 4 - Ver.2005-03-09
POWER ON/DOWN SEQUE NCE
The pop-noise can be effectively suppressed with the following sequence when power ON and DOWN.
(1) Power ON / Power DOWN Sequence (ENVG=H: Using internal VG)
< Power On sequence >
1) Input the MCK after the start-up of VDD. After of 100ms delay or more from MCK input, set ENVG at “H”
level.
2) Set ENSEG at “H” level after 5ms delay or more.(at 0.1µF for the charge pump and 1µF for the smoothing
capacitor)
3) After setting ENREG at ”H” level, input audio signals(DIN1, DIN2).
4) Set EN1 at “H” level and EN2 at “L” level after audio signal input. The audio signal input must be
“Sound-less data” until VCONT reaches a steady state.
5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target
VCONT voltage is short, it may cause a pop-noise.
< Power Down sequence >
The sequence must be executed in inverse order of the power ON sequence.
* : Do not set DIN1 and DIN2 at “H” level before the start-up of VDD.
High impedance
EN2
DIN1, DIN2 Audio Data
VCONT
MC
K
Sound-les
Data
Sound-less
Data
OUT1, OUT2Audio signal output
High impedance
ENREG
VG
EN1
100ms or more 100ms or more
VDD, VREG
ENVG
Undefined
Data*
Undefined
Data*
NJU3555NJU8715
-5-
Ver.2005-03-09
(2)Power ON / Power DOWN Sequence(ENVG=L, VG: Externally applied)
< Power ON sequence >
1) Input the MCK after the start-up of VDD.
Apply VG after the start-up VDD.(As shown in the following sequence, VG increases to VDD through a
internal protection diode after VDD is turned on.)
2) Set ENREG at “H” level after the start-up of VG.
3) After setting ENREG at ”H” level, input audio signals(DIN1, DIN2).
4) Set EN1 at “H” level and EN2 at “L” level after audio signal input. The audio signal input must be
“Sound-less data” until VCONT reaches a steady state.
5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target
VCONT voltage is short, it may cause a pop-noise.
< Power DOWN sequence >
The sequence must be executed in inverse order of the power ON sequence.
* : Do not set DIN1 and DIN2 at “H” level before the start-up of VDD.
High impedance
EN2
DIN1, DIN2 Audio data
VCONT
MC
K
Sound-less
Data
Sound-less
Data
OUT1, OUT2Audio signal output
High impedance
ENREG
VG
EN1
100ms or more 100ms or more
VDD, VREG
ENVG
Undefined
Data*
Undefined
Data*
NJU8715
- 6 -
- 6 - Ver.2005-03-09
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER SYMBOL RATING UNIT
VDD -0.3 ~ +2.75 V
VREG -0.3 ~ +5.5 V
Supply Voltage
VG V
DD ~ +6.0 V
Input Voltage Vin -0.3 ~ VDD+0.3 V
Operating Temperature Ta -20 ~ +85 °C
Storage Temperature Tstg -40 ~ +125 °C
Power Dissipation PD 640 mW
Note.3) The relations of VDDO1,VDDO2<VG, VREG<VG and VDD<VG must be maintained during operations.
Note.4) All voltage values are specified as VSS=VSSO=0V.
Note.5) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed.
Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond
the electrical characteristics conditions will cause malfunction and poor reliability.
Note.6) De-coupling capacitors for “VDD-VSS”, “VDDO1-VSSO” and “VDDO2-VSS” should be connected for stable
operation.
NJU3555NJU8715
-7-
Ver.2005-03-09
ELECT RICAL C HARACTERIST ICS
(1) DC CHARACTERISTICS
(Ta=25°C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V,
Load Impedance=16Ω, fS=44.1kHz, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage VDD 1.9 2.0 2.6 V
VG Supply Voltage VG V
G: Externally applied 4.0 5.0 5.75 V
HP Driver
High side Resistance RHPH OUT1, 2=VDDO1, 2-0.1V - 1.2 2 Ω
HP Driver
Low side Resistance RHPL OUT1, 2=0.1V - 1.2 2 Ω
Line Driver
High side Resistance RLINEH OUT1, 2=VDDO1, 2-0.1V
VDDO1, 2=2.75V 7.7 11 14.3 Ω
Line Driver
Low side Resistance RLINEL OUT1, 2=0.1V
VDDO1, 2=2.75V 7.7 11 14.3 Ω
VBEEPL MODEB=L -50
(2.45)
-48
(3.08)
-46
(3.88)
BEEP Output Voltage
VBEEPH MODEB=H -41
(6.91)
-39
(8.70)
-37
(10.95)
dBm
(mVrms)
Power Supply Current
At Standby IST
Standby Mode
Stopping
MCK,DIN1,DIN2,BEEPIN
ENREG=L
- - 1 µA
IDD1 - 0.95 1.6
IREG1
Using internal VG
HP Mode
No-load operating,
MCK=256fs
DIN1,DIN2=16fs, ENREG=H - 0.70 1.2
mA
IDD2 - 0.05 0.10
IREG2 - 0.70 1.2
Power Supply Current
At Operating
(Mute signal input)
IG2
VG: Externally applied,
HP Mode
No-load operating,
MCK=256fs,
DIN1,DIN2=16fs,ENREG=H
VG=5V - 0.75 1.2
mA
VIH 0.7VDD - VDD V
Digital Input Voltage
VIL
MCK, DIN1, DIN2
BEEPIN, MODEB
EN1, EN2, ENREG, ENVG 0 -
0.3
VDD
V
Input Leakage Current ILK MCK, DIN1, DIN2
BEEPIN, MODEB - - ±1 µA
Pull-down Resistance RPD EN1, EN2, ENREG, ENVG 150 300 450 kΩ
NJU8715
- 8 -
- 8 - Ver.2005-03-09
(2) REGULATOR CHARACTERISTICS
(Ta=25°C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V,
Load Impedance=16Ω, fS=44.1kHz, unless otherwise noted)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
VREGH HP MODE 1.9 2.15 4.0 V
Input Voltage
VREGL LINE MODE 3.0 - 4.0 V
VDDOH1 HP MODE
VCONT=1.5V, VREG=2.5V 1.9 2.0 2.1 V
VDDOH2 HP MODE
VCONT=0.5V, VREG=2.5V 0.23 0.33 0.43 V
VDDOL1 LINE MODE
VCONT=1.5V, VREG=3.5V 2.8 2.9 3.0 V
Output Voltage
VDDOL2 LINE MODE
VCONT=0.5V, VREG=3.5V 0.38 0.48 0.58 V
Output Current IOUT 70 - - mA
Sink Current ISINK 60 - - mA
Dropout Voltage ∆VIO Iout=70mA
VDDO1, 2=1.7V - - 0.2 V
Ripple Rejection RR Vr=0.1Vrms, Iout=70mA
fr=1kHz 36 44 - dB
Load Regulation Voltage VLR I
REGO=0 ~ 24.3mArms - - 520 µVrms
Residual Voltage VMIN V
CONT=0.1V - - 10 mV
VCONT VCONT 0 - VREG V
The following figure shows a representative example of VCONT versus VREGO.
At VCONT=1.5V: VREGO=2.0V(VREG=2.5V) in HP MODE, VREGO=2.9V(VREG=3.5V) in LINE MODE.
At VCONT=0.5V: VREGO=0.33V(VREG=2.5V) in HP MODE, VREGO=0.48V(VREG=3.5V) in LINE MODE.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
LINE MODE
HP MODE
VCONT (V)
V
R
EGO
(
V
)
NJU3555NJU8715
-9-
Ver.2005-03-09
(3) AC CHARACTERISTICS
(Ta=25°C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V,
Load Impedance=16Ω, fS=44.1kHz, unless otherwise noted)
• Master Clock
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Frequency fMCKI 8 - 50 MHz
Pulse Width (H) tMCKH 8 -
-
ns
Pulse Width (L) tMCKL 8 -
-
ns
• Digital Audio Data
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
DIN1, DIN2 Setup Time tDS 5 - - ns
DIN1, DIN2 Hold Time tDH 5 -
-
ns
EN1, EN2, ENREG, ENVG,
BEEPIN, MODEB
Rise Time, Fall Time
tEr, tEf - -
50
ns
tMCKH
MC
K
tMCKL
0.7VDD
0.3VDD
0.7VDD
0.3VDD
tEr tEf
EN1, EN2, ENREG, ENVG, BEEPIN, MODEB Timing chart
tDS tDH
DIN1, DIN2
MCK, DIN1, DIN2 Timing chart
0.7VDD
0.3VDD
NJU8715
- 10 -
- 10 - Ver.2005-03-09
APPLICATIO N CIRCUIT
(1) Using Internal VG (ENVG=H)
Regulator
Input
NJU8715
VDD
VSS
VREG
VSS
VSS
OUT1
OBEEP1
MCK
DIN1
DIN2
BEEPIN
2.2
µ
F
10µF
2.2
µ
F
100µF
VDD
CFB
VREGO
VDDO1
VDDO2
VREF
ENREG
ENVG
EN1
EN2
MODEB
CL
CH
VG
Head Phone
16Ω
0.1µF
1µF
220µF
47µH
4.7kΩ
220µF
0.22
µ
F
OUT2
OBEEP2
Head Phone
16Ω
47µH
4.7kΩ
220µF
0.22
µ
F
VCONT VREGO
Control Signal
10µF 1µF
1µF
NJU3555NJU8715
-11-
Ver.2005-03-09
(2) VG: Externally applied (ENVG=L)
Note.7) CH and CL pins must be opened when VG externally applied.
Note.8) De-coupling capacitors must be connected between each power supply pin and GND pin.
The capacitor value should be adjusted on the application circuit and the temperature. It may
malfunction if capacity value is small.
Note.9) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a
low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is
recommened for high power efficiency.
Note.10) The above circuit shows only application example and does not guarantee the any electrical
characteristics. Therefore, please consider and check the circuit carefully to fit your application.
1µF
VG
Regulator
Input
NJU8715
VDD
VSS
VREG
VSS
VSS
OUT1
OBEEP1
MCK
DIN1
DIN2
BEEPIN
2.2
µ
F
10µF
2.2
µ
F
100µF
VDD
CFB
VREGO
VDDO1
VDDO2
VREF
ENREG
ENVG
EN1
EN2
MODEB
CL
CH
VG
220µF
OUT2
OBEEP2
VCONT VREGO
Control Signal
10µF 1µF
1µF
Head Phone
16Ω
47µH
4.7kΩ
220µF
0.22
µ
F
Head Phone
16Ω
47µH
4.7kΩ
220µF
0.22
µ
F
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
