K7N163245A 512Kx36/32 & 1Mx18 Pipelined NtRAMTM
- 15 - Rev 2.0
May 2002
K7N161845A
AC TIMING CHARACTERISTICS
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER SYMBOL -25 -22 -20 -16 -13 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Cycle Time tCYC 4.0 -4.4 -5.0 -6.0 -7.5 -ns
Clock Access Time tCD -2.6 -2.8 -3.2 -3.5 -4.2 ns
Output Enable to Data Valid tOE -2.6 -2.8 -3.2 -3.5 -4.2 ns
Clock High to Output Low-Z tLZC 1.5 -1.5 -1.5 -1.5 -1.5 -ns
Output Hold from Clock High tOH 1.5 -1.5 -1.5 -1.5 -1.5 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-0-0-ns
Output Enable High to Output High-Z tHZOE -2.6 -2.8 -3.0 -3.0 -3.5 ns
Clock High to Output High-Z tHZC -2.6 -2.8 -3.0 -3.0 -3.5 ns
Clock High Pulse Width tCH 1.7 -2.0 -2.0 -2.2 -3.0 -ns
Clock Low Pulse Width tCL 1.7 -2.0 -2.0 -2.2 -3.0 -ns
Address Setup to Clock High tAS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
CKE Setup to Clock High tCES 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Data Setup to Clock High tDS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Write Setup to Clock High (WE, BWX)tWS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Address Advance Setup to Clock High tADVS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Chip Select Setup to Clock High tCSS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Address Hold from Clock High tAH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
CKE Hold from Clock High tCEH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Data Hold from Clock High tDH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Write Hold from Clock High (WE, BWX)tWH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-2-2-cycle
(VDD=2.5V ±5%, TA=0 to 70°C)
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
1538Ω5pF*
+2.5V
1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=VDDQ/2
30pF*