NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Features * Write Latency = Read Latency -1 CAS Latency and Frequency * Programmable Burst Length: 4 and 8 Speed Sorts -5 DDR2 -400 -3.7 DDR2 -533 Units Bin (CL-tRCD-TRP) 3-3-3 4-4-4 tck max. Clock Frequency 200 266 MHz Data Rate 400 533 Mb/s/pin CAS Latency 3 4 tck tRCD 15 15 ns tRP 15 15 ns tRC 60 60 ns * Programmable Sequential / Interleave Burst * OCD (Off-Chip Driver Impedance Adjustment) * ODT (On-Die Termination) * 4 bit prefetch architecture * 1k page size for x 4 & x 8, 2k page size for x16 * Data-Strobes: Bidirectional, Differential * Strong and Weak Strength Data-Output Driver * Auto-Refresh and Self-Refresh * Power Saving Power-Down modes * 7.8 s max. Average Periodic Refresh Interval * Packages: * 1.8V 0.1V Power Supply Voltage 60 pin FBGA for x4/x8 components 84 pin FBPA for x8/x16 components * 4 internal memory banks * Programmable CAS Latency: 3, 4 and 5 * Programmable Additive Latency: 0, 1, 2, 3 and 4 Description These devices operate with a single 1.8V +/-0.1V power supply and are available in FBGA packages. The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a highspeed CMOS Double Data Rate 2 SDRAM containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The 512Mb chip is organized as either 32Mbit x 4 I/O x 4 bank, 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 533 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength dataoutput driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. A 16 bit address bus for x4 and x8 organised components and a 15 bit address bus for x16 components is used to convey row, column, and bank address devices. REV 1.1 11/2004 1 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Pin Configuration - 60 balls 0.8mmx0.8mm Pitch FBGA Package (x4/x8) <Top View > See the balls through the package. x4 1 2 3 7 8 9 VDD NC VSS A VSSQ DQS VDDQ NC VSSQ DM B DQS VSSQ NC VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ NC VSSQ DQ3 D DQ2 VSSQ NC VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10 A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 VDD A12 NC,A14 L NC,A15 NC,A13 1 2 3 7 8 9 VDD NU/RDQS VSS A VSSQ DQS VDDQ DQ6 VSSQ DM/RDQS B DQS VSSQ DQ7 VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 D DQ2 VSSQ DQ5 VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10 A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC,A14 L NC,A15 NC,A13 NC,BA2 VSS VDD VSS x8 NC,BA2 VSS VDD REV 1.1 11/2004 VDD VSS 2 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Pin Configuration - 84balls 0.8mmx0.8mm Pitch FBGA Package (x8) <Top View > See the balls through the package. x8 1 2 3 7 8 9 VDD NC VSS D VSSQ NC VDDQ NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC VDD NU,RDQS VSS H VSSQ DQS VDDQ DQ6 VSSQ DM,RDQS J DQS VSSQ DQ7 VDDQ DQ1 VDDQ K VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 L DQ2 VSSQ DQ5 VDDL VREF VSS M VSSDL CK VDD CKE0 WE N RAS CK ODT0 NC,BA2 BA0 BA1 P CAS CS0 CS1 CKE1 A10 A1 R A2 A0 VDD VSS A3 A5 T A6 A4 ODT1 A7 A9 U A11 A8 VSS A12 A14 V A15 A13 VDD REV 1.1 11/2004 3 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Pin Configuration - 84 balls 0.8mmx0.8mm Pitch FBGA Package (x16) <Top View > See the balls through the package. x 16 1 2 3 7 8 9 VDD NC VSS A VSSQ UDQS VDDQ UDQ6 VSSQ UDM B UDQS VSSQ UDQ7 VDDQ UDQ1 VDDQ C VDDQ UDQ0 VDDQ UDQ4 VSSQ DQ3 D UDQ2 VSSQ UDQ5 VDD NC VSS E VSSQ LDQS VDDQ LDQ6 VSSQ LDM F LDQS VSSQ LDQ7 VDDQ LDQ1 VDDQ G VDDQ LDQ0 VDDQ LDQ4 VSSQ LDQ3 H LDQ2 VSSQ LDQ5 VDDL VREF VSS J VSSDL CK VDD CKE WE K RAS CK ODT BA0 BA1 L CAS CS A10 A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC,A14 R NC,A15 NC,A13 RFU VSS VDD REV 1.1 11/2004 VDD VSS 4 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Input/Output Functional Description Symbol Type Function Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and SelfRefresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for SelfRefresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE are disabled during Self-Refresh. CS Input Chip Select: All command are masked when CS is registered high. CS provides for external rank selection on systems with multiple memory ranks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM, LDM, UDM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM and UDM are the input mask signals for x16 components and control the lower or upper bytes. For x8 components the data mask function is disabled, when RDQS / RQDS are enabled by EMRS(1) command. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A13 Input Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the opcode during Mode Register Set commands. Row address A13 is used on x4 and x8 components only. DQx, LDQx,UDQx Input/Output Data Inputs/Output: Bi-directional data bus. DQ0~DQ3 for x4 components, DQ0~DQ7 for x8 components, LDQ0~LDQ7 and UDQ0~UDQ7 for x16 components Input/Output Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the x16, LDQS corresponds to the data on LDQ0 - LDQ7; UDQS corresponds to the data on UDQ0-UDQ7. The data strobes DQS, LDQS, UDQS may be used in single ended mode or paired with the optional complementary signals DQS, LDQS, UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. Input/Output Read Data Strobe: For the x8 components a RDQS, RDQS pair can be enabled via the EMRS(1) for read timing. RDQS, RDQS is not supported on x4 and x16 components. RDQS, RDQS are edge-aligned with read data. If RDQS, RDQS is enabled, the DM function is disabled on x8 components. Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS and DM signal for x4 and DQ, DQS, DQS, RDQS, RDQS and DM for x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT. CK, CK DQS, (DQS) LDQS, (LDQS), UDQS,(UDQS) RDQS, (RDQS) ODT NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8V +/- 0.1V VSSQ Supply DQ Ground VDDL Supply DLL Power Supply: 1.8V +/- 0.1V VSSDL Supply DLL Ground VDD Supply Power Supply: 1.8V +/- 0.1V VSS Supply Ground REV 1.1 11/2004 5 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Input/Output Functional Description Symbol Type VREF Supply (BA2), (A14~A15) - REV 1.1 11/2004 Function SSTL_1.8 reference voltage BA2, A14 ~ A15 are additional address pins for future generation DRAMs and are not connected on this component. 6 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Ordering Information Speed Org. Part Number NT5TU128M4AB-5A 128M x 4 NT5TU128M4AB-37B NT5TU64M8AF-5A NT5TU64M8AF-37B Package Clock (MHz) CL-tRCD-tRP 60ball BGA 0.8mmx0.8mm Pitch 200 3-3-3 266 4-4-4 84ball BGA 0.8mmx0.8mm Pitch 200 3-3-3 266 4-4-4 200 3-3-3 266 4-4-4 200 3-3-3 266 4-4-4 64M x 8 NT5TU64M8AB-5A NT5TU64M8AB-37B NT5TU32MHAF-5A 32M x 16 NT5TU32MHAF-37B 60ball BGA 0.8mmx0.8mm Pitch 84ball BGA 0.8mmx0.8mm Pitch Note: REV 1.1 11/2004 7 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Control Logic Bank1 CK, CK DLL Bank0 Memory Array (16384 x 512 x 16) Data 16 8192 4 DQS DQS COL0,1 I/O Gating DM Mask Logic 16 16 512 (x16) Write FIFO & Drivers Input Register 1 Mask 1 4 Column Decoder 9 11 2 DQS Generator Column-Address Counter/Latch 16 COL0,1 2 Data 1 1 1 1 1 1 4 4 4 4 4 4 4 4 DQ0-DQ3, DM DQS DQS 1 Receivers 2 2 Bank Control Logic 16 Address Register A0-A13, BA0, BA1 Refresh Counter Sense Amplifiers 4 4 4 4 Drivers 16384 14 16 16 Bank3 MUX 16 Bank0 Row-Address Latch & Decoder Mode Registers Row-Address MUX AP Bank2 Read Latch CKE CK CK CS WE CAS RAS Command Decode Block Diagram (128Mb x 4) 4 CK, CK COL0,1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.1 11/2004 8 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Control Logic CK, CK DLL Bank0 Memory Array (16384 x256x32) 32 2 2 8192 Bank Control Logic 16 Address Register A0-A13, BA0, BA1 Refresh Counter Sense Amplifiers 32 256 (x32) DQS DQS Input Register Write Mask 1 FIFO 1 & Drivers 1 4 1 1 8 8 8 8 8 8 8 8 8 Column-Address Counter/Latch 1 DQS Generator 32 Column Decoder 10 8 COL0,1 I/O Gating DM Mask Logic Drivers Data 8 8 8 8 32 COL0,1 Data 2 DQ0-DQ7, DM DQS DQS 1 1 1 1 Receivers 16384 14 16 Bank3 MUX 16 16 Bank2 Read Latch Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS AP Command Decode Block Diagram (64Mb x 8) 8 CK, CK COL0,1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.1 11/2004 9 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Control Logic CK, CK DLL Bank0 Memory Array (8192 x 256 x 64) Data 64 16384 16 DQS DQS COL0,1 I/O Gating DM Mask Logic 64 64 256 (x64) Write FIFO & Drivers Input Register 2 Mask 2 8 Column Decoder 8 10 1 DQS Generator 64 Column-Address Counter/Latch COL0 Data 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 2 Receivers 2 2 Bank Control Logic 15 Address Register A0-A12, BA0, BA1 Refresh Counter Sense Amplifiers 16 16 16 16 Drivers 8192 13 15 Bank3 MUX 15 15 Bank2 Read Latch Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS AP Command Decode Block Diagram (32Mb x 16) LDQ0-LDQ7 LDM UDQ0-UDQ7 UDM LDQS LDQS UDQS UDQS 16 CK, CK COL0,1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. REV 1.1 11/2004 10 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Functional Description The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4n prefetch architecture, with an interface designed to transfer four data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 4n-bit wide, one clock cycle data transfer at the internal DRAM core and four corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accesses (BA0 & BA1 select the banks, A0-A13 select the row for x4 and x8 components, A0~A12 select the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. - VDD,VDDL and VDDQ are driven from a signle power converter output, AND - VTT is limited to 0.95 V max, AND - VREF tracks VDDQ/2 or - Apply VDD before or at the same time as VDDL, - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & VREF. at least one of these two sets of conditions must be met. 2. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 s. 3. Apply NOP or Deselect commands & take CKE high. 4. Wait minimum of 400ns, then issue a Precharge-all command. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "low" to BA0 and BA2 and "high" to BA1) 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "low" to BA2 and "high" to BA0 and BA1) 7. Issue EMRS(1) command to enable DLL. (To issue "DLL Enable" command, provide "low" to A0 and "high" to BA0 and "low" to BA1,BA2 and A13~A15) 8. Issue MRS command (Mode Register Set) for "DLL reset". (To issue DLL reset command, provide "high" to A8 and "low" to BA0 ~ BA2 and A13 ~ A15) 9. Issue Precharge-All command. 10. Issue 2 or more Auto-Refresh commands. 11. Issue a MRS command with low on A8 to initialize device operation. (i.e. to programm operating paramters with out resetting the DLL) 12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1). 13. The DDR2 SDRAM is now read for normal operation. REV 1.1 11/2004 11 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Example CK, CK CKE ODT "low" NOP Command tMRS tRP 400 ns PRE ALL CMD EMRS Extended Mode Register Set with DLL enable tMRS MRS Mode Register Set with DLL reset tRP PRE ALL CMD tRFC tRFC 1st Auto refresh min. 200 cycles to lock the DLL 2nd Auto refresh tMRS MRS EMRS OCD Follow OCD flowchart Register Definition Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MRS) and Extended Node Registers (EMRS(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. Also any programmig of EMRS(2) or EMRS(3) must be followed by programming of MRS and EMRS(1). After initial power up, all MRS and EMRS Commands must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycles before the Mode Register Set Command can be issued. Either MRS or EMRS Commands are activated by the low signals of CS, RAS, CAS and WE at the positive edge of the clock. When both bank addresses BA0 and BA1 are low, the DDR2 SDRAM enables the MRS command. When the bank addresses BA0 is high and BA1 low, the DDR2 SDRAM enables the EMRS(1) command. The address input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and DLL Reset do not affect array contents, which means reinitializazion including those can be executed any time after power-up without affecting array contents. Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst sequence, test mode, DLL reset, WR (write recovery) and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharged (idle) mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge mode. With address bit A12 two Power-Down modes can be selected, a "standard mode" and a "low-power" Power-Down mode, where the DLL is disabled. Addess bit A13 and all "higher" address bits (including BA2) have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities. REV 1.1 11/2004 12 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM MRS Mode Register Operation Table (Address Input For Mode Set) BA2 BA1 BA0 0* 0* A13~ A12 A11 A15 0* 0* A10 PD A9 WR A8 A7 DLL TM A8 DLL Reset A7 Mode 0 No 0 Normal 1 Yes 1 Test A12 0 1 BA1 Active Power-Down Mode Select Fast exit (use tXARD) Slow exit (use tXARDS) BA0 MRS mode 0 0 MRS 0 1 EMRS(1) 1 0 EMRS(2): Reserved 1 1 EMRS(3): Reserved A11 A10 A9 A6 A5 A4 CAS Latency A3 A2 BT A1 Address Field A0 Mode Register Burst Length Burst Type A2 A1 A0 Burst Length 0 Sequential 0 1 0 4 1 Interleave 0 1 1 8 WR **) A6 A5 A4 Latency 0 0 Reserved 0 0 0 Reserved 0 0 0 1 2 0 0 1 Reserved 0 1 0 3 0 1 0 2 (optional) ***) 0 1 1 4 0 1 1 3 1 0 0 5 1 0 0 4 0 1 5 1 0 1 6 1 1 1 0 Reserved 1 1 0 Reserved 1 1 1 Reserved 1 1 1 Reserved *) Must be programmed to 0 when setting the mode register. A13 ~ A15 and BA2 are reserved for future use and must be programmed to 0 when setting the mode register MRS **) The programmability of WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time when the device starts precharge internally. WR must be programmed to fullfil the minimum reqirement for the analogue tWR timing. ***) CAS Latency = 2 is implemented in this design, but functionality is not tested and guaranteed. REV 1.1 11/2004 13 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Extended Mode Register Set (EMRS(1)) The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS, WE, BA1 and high on BA0, while controlling the state of the address pins.. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. EMRS(1) Extended Mode Register Operation Table (Address Input For Mode Set) BA2 BA1 BA0 A13~A15 A12 A11 A10 0* 0* 1 A9 Qoff RDQS DQS 0* A8 A7 OCD program A6 A5 Rtt A4 A3 A2 Additive latency Rtt A1 A0 Address Field Extended Mode Register D.I.C DLL A6 A2 Rtt (nom.) A11 RDQS,(RQDS) Enable 0 ODT disabled 0 Disable 0 1 75 ohm 1 Enable 1 0 150 ohm 1 1 Reserved A12 Qoff a) 0 Output buffers enabled 1 Output buffers disabled a) Disables DQ, DQS, DQS, RDQS, RDQS BA1 BA0 MRS mode 0 0 MRS 0 1 EMRS(1) 1 0 1 1 EMRS(2): Reserved EMRS(3): Reserved A9 0 A8 0 1 0 1 0 1 0 0 1 1 1 1 Disable A5 A4 A3 AdditiveLatency 0 0 0 0 1 Disable 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved OCD Cal. Mode Exit, maintain setting 0 0 Enable Enable OCD Calibration Program 0 DLL Enable 0 0 A10 DQS,(RDQS) Disable A7 0 A0 Drive (1) Drive (0) Adjust mode a) Output Driver Impedence Control Driver Size 0 Normal 100% 1 Weak 60% A1 OCD Calibration default b) a) When Adjust mode is issued, AL from previously set value must be applied b) After setting to default, OCD mode needs to be exited by setting A9~A7 to 000. Refer to the following 2.2.2.5 section for detailed information. *) must be programmed to 0 for compatibility with future DDR2 memory products. REV 1.1 11/2004 14 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables ODT (On-Die termination) and sets the Rtt value. A3~A5 are used for additive latency settings and A7 ~ A9 enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals, A11 disables or enables RDQS. Address bit A12 have to be set to "low" for normal operation. With A12 set to "high" the SDRAM outputs are disabled and in Hi-Z. "High" on BA0 and "low" for BA1 have to be set to access the EMRS(1). A13 and all "higher" address bits (including BA2) have to be set to "low" for compatibility with other DDR2 memory products with higher memory densities. Refer to the table for specific codes on the previous page. Single-ended and Differential Data Strobe Signals The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by A10 & A11 address bits in EMRS. RDQS and RDQS are available in x8 components only. If RDQS is enabled in x8 components, the DM function is disabled. RDQS is active for reads and don't care for writes : EMRS Stobe Function Matrix Signaling A11 (RDQS Enable) A10 (DQS Enable) RDQS/DM RDQS DQS DQS 0 (Disable) 0 (Enable) DM Hi-Z DQS DQS differential DQS signals 0 (Disable) 1 (Disable) DM Hi-Z DQS Hi-Z single-ended DQS signals 1 (Enable) 0 (Enable) RDQS RDQS DQS DQS differential DQS signals 1 (Enable) 1 (Disable) RDQS Hi-Z DQS Hi-Z single-ended DQS signals DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Less clock cycles may result in a violation of the tAC or tDQSCK parameters. Output Disable (Qoff) Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current. EMRS(2) and EMRS(3) Extended Mode Registers The Extended Mode Registers EMRS(2) and EMRS(3) are reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. REV 1.1 11/2004 15 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive (1) EMRS: Drive(0) DQ & DQS High; DQS Low DQ & DQS Low; DQS High ALL OK ALL OK Test Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS : EMRS : Enter Adjus t Mode Enter Adjust Mode BL=4 cod e inpu t to all DQs BL =4 code input to all DQs Inc, Dec, or NOP Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End REV 1.1 11/2004 16 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS (and RDQS) signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS (and RDQS) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as '000' in order to maintain the default or calibrated value. Off- Chip-Driver program A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive(1) DQ, DQS, (RDQS) high and DQS, (RDQS) low Drive(0) DQ, DQS, (RDQS) low and DQS, (RDQS) high Adjust mode OCD calibration default OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied. Off- Chip-Driver Adjust Program 4 bit burst code inputs to all DQs DT0 DT1 DT2 DT3 0 0 0 0 1 0 0 1 1 REV 1.1 11/2004 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 Other Combinations 0 1 0 0 0 1 0 1 0 Operation Pull-up driver strength NOP (no operation) Pull-down driver strength NOP (no operation) Increase by 1 step NOP Decrease by 1 step NOP NOP Increase by 1 step NOP Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Decrease by 1 step Reserved Reserved 17 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). Burst length of 4 have to be programmed in the MRS for OCD impedance adjustment. CK, CK CMD NOP EMRS(1) NOP NOP WL NOP NOP NOP EMRS(1) NOP tWR DQS DQS_in tDS tDH DQ_in DT0 DT1 DT2 DT3 DM OCD calibration mode exit OCD adjust mode Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram. CK, CK CMD EMRS(1) NOP NOP NOP NOP NOP NOP tOIT tOIT DQS_in EMRS(1) DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1) DQS high for Drive(0) DQ_in OCD calibration mode exit Enter Drive Mode REV 1.1 11/2004 18 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM On-Die Termination (ODT) ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each DQ, DQS, DQS and DM for x4 and DQ, DQS, DQS, DM, RDQS (DM and RDQS share the same pin), and RDQS for x8 configuration via the ODT control pin, where DQS is terminated only when enabled in the EMRS(1) by address bit A10 = 0. For x8 configuration RDQS is only terminated, when enabled in the EMRS(1) by address bits A10 = 0 and A11 = 1. For x16 configuration ODT is applied to each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT control pin, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in SelfRefresh mode. Funtional Prepresentation of ODT VDDQ VDDQ sw1 sw2 Rval1 Rval2 DRAM Input Buffer Input Pin Rval1 Rval2 sw1 sw2 VSSQ VSSQ Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS(1) address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. REV 1.1 11/2004 19 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device organisations (x4, x8 and x16). To activate termination of any of these pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2. EMRS(1) Adress Bit A10 EMRS(1) Adress Bit A11 DQ0~DQ3 DQS DQS DM x4 components: X X 0 X X X X X DQ0~DQ7 x8 components: X X X 0 X X X 1 DM 0 X 1 0 LDQ0~LDQ7 UDQ0~UDQ7 LDQS LDQS UDQS UDQS LDM UDM x16 components: X X X 0 X 0 X X X X X X X X X X Input Pin DQS DQS RDQS RDQS REV 1.1 11/2004 20 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM ODT Timing for Active / Standby (Idle) Mode and Standard Active Power-Down Mode T-n T-5 T-6 T-4 T-3 T-2 T-1 T0 CK, CK tIS CKE tIS tAXPD (>=6 tck) tIS tIS ODT tANPD (>=3 tck) tAOND (2 tck) tAOFD (2.5 tck) Rtt tAON(min) DQ tAOF(min) tAOF(max) tAON(max) ODT1 1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings have to be applied. 2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND. 3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is when the bus is in high impedance. Both are measured from tAOFD. ODT Timing for Precharge Power-Down and Low Power Power-Down Mode T-7 T-6 T-5 T-4 T-3 T-2 T0 T-1 T1 CK, CK CKE tAXPD < 6 tck tIS ODT tANPD < 3 tck tIS tAOFPD,min tAOFPD,max DQ Rtt tAONPD,min tAONPD,max ODT2 1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied. REV 1.1 11/2004 21 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank for x4 and x8 organised components. For x16 components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2 T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tn+3 CK, CK Internal RAS-CAS delay tRCDmin. Address Bank A Bank A Bank B Col. Addr. Row Addr. Row Addr. Bank A to Bank B delay tRRD. additive latency AL=2 RAS-RAS delay tRRD. Command Bank A Activate Posted CAS Read A Bank B Activate Bank B Col. Addr. Bank A Addr. Bank B Addr. Bank A Row Addr. Bank A Precharge Bank B Precharge Bank A Activate Read A Begins Posted CAS Read B tRP Row Precharge Time (Bank A) tRAS Row Active Time (Bank A) tRC Row Cycle Time (Bank A) ACT REV 1.1 11/2004 22 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 1 kByte (defined by CA0-CA9 & CA11). In case of a 4-bit burst operation (burst length = 4) the page length of 1 kByte is divided into 512 uniquely addressable segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments (defined by CA0-CA8) beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9 & A11). The second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. In case of a 8-bit burst operation (burst length = 8) the page length of 1 kByte is divided into 256 uniquely addressable double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 double segments (defined by CA0-CA7) beginning with the column address supplied to the deivce during the Read or Write Command ( CA0-CA9 & CA11). A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. For 8 bit burst operation (BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles. Burst interruption is allowed with 8 bit burst operation. For details see the "Burst Interrupt" - Section of this datasheet. Example: Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T12 CK, CK CMD READ A NOP tCCD READ B NOP READ C NOP NOP NOP NOP NO tCCD DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout C0 Dout C1 Dout C2 Dout C3 RB REV 1.1 11/2004 23 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Examples: Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 2 0 1 Activate Bank A Read Bank A -1 3 4 5 6 7 8 9 10 11 12 CK, CK CMD Write Bank A AL = 2 DQS, DQS WL = RL -1 = 4 CL = 3 tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tRAC" PostCAS1 Read followed by a write to the same bank, Activate to Read delay < tRCDmin: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8 2 0 1 Activate Bank A Read Bank A 3 4 5 6 7 8 9 10 11 12 CK, CK CMD DQS, DQS Write Bank A AL = 2 WL = RL -1 = 4 CL = 3 tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 " tRAC" PostCAS3 REV 1.1 11/2004 24 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Read followed by a write to the same bank, Activate to Read delay = tRCDmin: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK Read Bank A Activate Bank A CMD Write Bank A tRCD>tRCDmin. WL = 3 DQS, DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 "tRAC" PostCAS5 Read followed by a write to the same bank, Activate to Read delay > tRCDmin: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK CMD Read Bank A Activate Bank A Write Bank A tRCD>tRCDmin. WL = 3 DQS, DQS RL = 4 DQ Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 "tRAC" PostCAS5 REV 1.1 11/2004 25 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the "Burst Interruption " section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) x 00 0, 1, 2, 3 0, 1, 2, 3 x 01 1, 2, 3, 0 1, 0, 3, 2 x 10 2, 3, 0, 1 2, 3, 0, 1 x 11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 4 8 Note: 1) Page length is a function of I/O organization 128Mb X 4 organization (CA0-CA9, CA11); Page Length = 1 kByte 64Mb X 8 organization (CA0-CA9 ); Page Length = 1 kByte 32Mb X 16 organization (CA0-CA9); Page Length = 2 kByte 2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components REV 1.1 11/2004 26 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS(1)) Basic Burst Read Timing t CH t CL t CK CLK CLK, CLK CLK t DQSCK t AC DQS DQS, DQS DQS t RPRE t RPST t LZ DQ Dout t DQSQmax t QH Dout t HZ Dout Dout t DQSQmax t QH DO-Read Examples: Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS AL = 2 DQ CL = 3 RL = 5 Dout A0 Dout A1 Dout A2 Dout A3 BRead523 Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8) REV 1.1 11/2004 27 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS CL = 3 RL = 3 DQ's Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 BRead303 Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4 T0 T3 T1 T4 T5 T6 T7 T8 T9 CK, CK CMD Posted CAS READ A NOP NOP Posted CAS WRITE A NOP NOP NOP NOP NOP BL/2 + 2 DQS, DQS WL = RL - 1 = 4 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3 BRBW514 The minimum time from the burst read command to the burst write command is defined by a read-to-write turnaround time, which is BL/2 + 2 clocks. Seamless Burst Read Operation : RL = 5, AL = 2, CL = 3, BL = 4 REV 1.1 11/2004 28 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP Post CAS READ B NOP NOP NOP NOP NOP NOP DQS, DQS AL = 2 CL = 3 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 SBR523 The seamless burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Seamless Burst Read Operation : RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting) T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK CMD Post CAS READ A NOP NOP NOP Post CAS READ B NOP NOP NOP NO NOP DQS, DQS CL = 3 DQ RL = 3 Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A4 Dout A7 Dout B0 Dout B1 Dout B2 Dout B3 Dou SBR_BL8 The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. REV 1.1 11/2004 29 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (tWR) and is the time needed to store the write data into the memory array. tWR is an analog timing parameter (see the AC table in this specification) and is not the programmed value for WR in the MRS. Basic Burst Write Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE Din Din Din t DS Din t DH Example:. Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP <= tDQSS DQS, DQS REV 1.1 11/2004 NOP Precharge Completion of the Burst Write tWR WL = RL-1 = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 30 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP Bank A Activate Completion of the Burst Write <= tDQSS DQS, DQS tRP tWR WL = RL-1 = 2 DQ Precharge NOP DIN A0 DIN A1 DIN A2 DIN A3 BW322 Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6 CMD NOP NOP NOP NOP Post CAS READ A NOP NOP NOP NOP DQS, DQS AL=2 tWTR WL = RL - 1 = 4 DQ CL=3 DIN A0 DIN A1 DIN A2 DIN A3 RL=5 BWBR The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. REV 1.1 11/2004 31 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Seamless Burst Write Operation : RL = 5, WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS WRITE A NOP Post CAS WRITE B NOP NOP NOP NOP NOP NOP DQS, DQS WL = RL - 1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. Seamless Burst Write Operation : RL = 3, WL = 2, BL = 8, non interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CM D WRITE A NO P NO P NO P WRITE B NO P NO P NO P NO P DQS, DQS D Q WL = RL - 1 = 2 DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 D SBW_BL8 The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. REV 1.1 11/2004 32 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Write Data Mask One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16 components are supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is high during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1). Write Data Mask Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE DQ Din Din Din Din t DS t DH DM don't care Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD WRITE A NOP NOP NOP NOP NOP NOP Precharge Bank A Activate <= tDQSS DQS, DQS WL = RL-1 = 2 DQ tWR tRP DIN A0 DIN A1 DIN A2 DIN A3 DM DM REV 1.1 11/2004 33 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. Examples: Read Burst Interrupt Timing Example : (CL = 3, AL = 0, RL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP READ B NOP NOP NOP NOP NOP NOP DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 D RBI REV 1.1 11/2004 34 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Write Burst Interrupt Timing Example : ( CL = 3, AL = 0, WL = 2, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD NOP WRITE A NOP NOP NOP WRITE B NOP NOP NOP DQS, DQS DQ Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7 WBI REV 1.1 11/2004 35 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued Bank Selection for Precharge by Address Bit A10 BA0 BA1 Precharge Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH Don't Care Don't Care all banks Burst Read Operation Followed by a Precharge The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and 533 speed sorts): Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible precharge, the Precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum tRAS timing is satisfied. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins. (2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied. For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks. REV 1.1 11/2004 36 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Examples: Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge Bank A Activate NOP NOP tRP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge NOP NOP AL + BL/2 clks Bank A Activate tRP DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 >=tRC >=tRTP first 4-bit prefetch REV 1.1 11/2004 BR-P413(8) second 4-bit prefetch 37 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge AL + BL/2 clks NOP Bank A Activate NOP tRP DQS, DQS CL = 3 AL = 2 RL = 5 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP BR-P523 Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP Precharge A AL + BL/2 clocks NOP NOP NOP Bank A Activate tRP DQS, DQS AL = 2 CL = 4 RL = 6 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 4 >=tRC >=tRTP REV 1.1 11/2004 BR-P624 38 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP Precharge NOP NOP AL + BL/2 clks + 1 Bank A Activate tRP DQS, DQS CL = 4 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >=tRAS >=tRTP first 4-bit prefetch REV 1.1 11/2004 BR-P404(8) second 4-bit prefetch 39 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (t WR ) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the MRS. Examples: Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS tWR WL = 3 DQ DIN A0 DIN A1 DIN A2 DIN A3 BW-P3 Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS tWR WL = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW-P4 REV 1.1 11/2004 40 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-matically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Com-mand is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays thepprecharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command. Burst Read with Auto-Precharge If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. REV 1.1 11/2004 41 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Examples: Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit) RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP NOP NOP Bank Activate A10 ="high" AL + BL/2 Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRAS tRCmin. BR-AP5231 Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit): RL = 5 ( AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP Bank Activate NOP NOP A10 ="high" tRAS(min) Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRC BR-AP5232 REV 1.1 11/2004 42 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP A10 ="high" NOP NOP NOP AL + BL/2 NOP Bank Activate tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >= tRTP BR-AP413(8)2 second 4-bit prefetch first 4-bit prefetch Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP A10 ="high" NOP NOP NOP NOP NOP NOP Bank Activate NOP AL + tRTP + tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRP tRTP BR-AP4133 first 4-bit prefetch REV 1.1 11/2004 43 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. In DDR2 SDRAMs the write recovery time delay (WR ) has to be programmed into the MRS mode register. As long as the analog twr timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL. Examples: Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 CK, CK CMD WRITE w/AP NOP A10 ="high" NOP NOP NOP NOP NOP Completion of the Burst Write NOP Bank A Activate Auto-Precharge Begins DQS, DQS WR WL = RL-1 = 2 tRP tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 tRCmin. >=tRASmin. BW-AP223 REV 1.1 11/2004 44 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Burst Write with Auto-Precharge (WR + tRP Limit) : WL = 4, tDAL = 6 (WR = 3, tRP = 3), BL = 4 T0 T3 T4 T5 T6 NOP NOP NOP T8 T7 T12 T9 CK, CK CMD Posted CAS WRITE w/AP A10 ="high" NOP NOP NOP Bank A Activate NOP Completion of the Burst Write Auto-Precharge Begins DQS, DQS tRP WR WL = RL-1 = 4 tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 >=tRC >=tRAS BW-AP423 Concurrent Auto-Precharge DDR2 devices support the "Concurrent Auto-Precharge" feature. A Read with Auto-Precharge enabled, or a Write with AutoPrecharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between Read data and Write data must be avoided externally and on the internal data bus. The minimum delay from a Read or Write command with Auto-Precharge enabled, to a command to a different bank, is summarized in the table below. As defined, the WL = RL - 1 for DDR2 devices which allows the command gap and corresponding data gaps to be minimized. From Command WRITE w/AP Read w/AP Minimum Delay with Concurrent Auto-Precharge Support Units Read or Read w/AP (CL -1) + (BL/2) + tWTR tCK Write ot Write w/AP BL/2 tCK Precharge or Activate 1 tCK Read or Read w/AP BL/2 tCK Write or Write w/AP BL/2 + 2 tCK Precharge or Activate 1 tCK To Command (different bank, non-interrupting command) Note 1) 1) Note: 1) This rule only applies to a selective Precharge command to another banks, a Precharge-All command is illegal REV 1.1 11/2004 45 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Refresh SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways : by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to controlles for distributed refresh timing. For example, a 512Mbit DDR2 SDRAM has 8192 rows resulting in a tREFI of 7,8 s. Auto-Refresh Command Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto-Refresh command. The DDR2 SDRAM requires AutoRefresh cycles at an average periodic interval of tREFI (maximum). When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the AutoRefresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the Auto-Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI. T0 T1 T2 T3 CK, CK "high" CKE CMD Precharge NOP > = t RFC > = t RFC > = t RP NOP AUTO REFRESH NOP AUTO REFRESH NOP NOP ANY AR REV 1.1 11/2004 46 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the tXSRD timing is satisfied. T0 T1 T2 T3 T4 T5 Tm Tn Tr CK/CK tRP* tis tis >=tXSRD CKE tis tAOFD >= tXSNR ODT CMD Self Refresh Entry NOP CK/CK may be halted Non-Read Command Read Command CK/CK must be stable * = Device must be in the "All banks idle" state to entering Self Refresh mode. ODT must be turned off prior to entering Self Refresh mode. tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command. tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns. The miminum CKE low time is defined by the tCKEmin. timing parameter. Since CKE is an SSTL input, VREF must be maintained during Self Refresh. Power-Down REV 1.1 11/2004 47 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if powerdown occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet. Power-Down Entry Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with AutoPrecharge command is allowed after RL + BL/2 is satisfied. Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In case the DDR2 SDRAM enters the Precharge Power-down mode. Examples: REV 1.1 11/2004 48 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Active Power-Down Mode Entry and Exit after an Activate Command T0 T1 T2 Tn Tn+1 Tn+2 CK, CK CMD NOP Activate NOP Valid Command NOP NOP NOP tIS CKE tIS tXARD or tXARDS *) Act.PD 0 Active Power-Down Exit Active Power-Down Entry note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn T8 Tn+1 Tn+2 CK, CK CMD READ READ w/AP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Command tIS CKE RL + BL/2 tIS DQS, DQS AL = 1 DQ tXARD or tXARDS *) CL = 3 RL = 4 Dout A0 Dout A1 Dout A2 Dout A3 Active Power-Down Entry Active Power-Down Exit Act.PD 1 note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4 REV 1.1 11/2004 49 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CM D NO P WRIT E NO P NO P NO P CKE NO P NO P NO P NO P NO P tIS WL + BL/2 + tWTR tXARD or tXARDS *) tWTR D Q Valid Command tIS DQS, DQS WL = RL - 1 = 2 NO P DIN A0 DIN A1 DIN A2 DIN A3 Active Power-Down Entry Active Power-Down Exit Act.PD 2 note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Precharge Power Down Mode Entry and Exit T0 T1 T2 T3 Tn Tn+1 Tn+2 CK, CK CMD Precharge *) NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE tIS tXP tRP Precharge Power-Down Entry Precharge Power-Down Exit *) "Precharge" may be an external command or an internal precharge following Write with AP. REV 1.1 11/2004 PrePD 50 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't care. Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions: a) During Self-Refresh operation b) DRAM is in Precharge Power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. Example: Input frequency change during Precharge Power-Down mode T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 Ty+2 Tz Ty+3 K NOP NOP NOP NOP NOP NOP NOP NOP tRP tAOFD NOP tXP Minimum 2 clocks required before changing the frequency Frequency Change occurs here Stable new clock before power-down exit DLL RESET NOP Valid Command 200 clocks ODT is off during DLL RESET Frequ.Ch. REV 1.1 11/2004 51 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Asynchronous CKE Low Event DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tdelay specification. Asynchronous CKE Low Event stable clocks CK, CK tdelay CKE CKE drops low due to an asynchronous reset event REV 1.1 11/2004 Clocks can be turned off after this point 52 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Truth Table Command Truth Table CKE RAS CAS WE BA0 A13-A11 A10 BA1 Function Previous Cycle Current Cycle CS (Extended) Mode Register Set H H L L L L BA Auto-Refresh H H L L L H X X X X 1 Self-Refresh Entry H L L L L H X X X X 1 Self-Refresh Exit L H H X X X X X X X 1 Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Write H H L H L L BA Column L Column 1,2,3 Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3 Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 Power Down Entry H X X X H L X X X X 1,4 L H H H H X X X X X X X 1,4 L H H H Power Down Exit L H A9 - A0 OP Code Notes 1, 2 Row Address 1, 2 1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2. Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BxA selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" insection 2.4.6 for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in section 2.7. 5. The state of ODT does not affect the states decribed in this table. The ODT function is not available during Self Refresh. 6. "X" means "H or L (but a defined logic level)". 7. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restartet through the specified initialization sequence before normal operation can continue. REV 1.1 11/2004 53 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Clock Enable (CKE) Truth Table for Synchronous Transistions CKE Current State2 Command (N) 3,12 Previous Cycle 1 (N-1) Current Cycle 1 (N) RAS, CAS, WE, CS L L L H Action (N) 3 Notes X Maintain Power-Down 11, 13, 15 DESELECT or NOP Power-Down Exit 4, 8, 11, 13 11, 15 Power-Down L L X Maintain Self Refresh L H DESELECT or NOP Self Refresh Exit 4, 5, 9 H L DESELECT or NOP Active Power-Down Entry 4,8,10,11, 13 H L DESELECT or NOP Precharge Power-Down Entry 4,8,10,11 H L AUTOREFRESH Self Refresh Entry 6, 9, 11, 13 H H Self Refresh Bank(s) Active All Banks Idle Any State other than listed above 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Refer to the Command Truth Table 7 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N). All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occuring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements. CKE must be maintained high while the device is in OCD calibration mode. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restartet through the specified initialization sequence before normal operation can continue. Data Mask (DM) Truth Table Name (Function) DM DQs Notes Write Enable L Valid 1 Write Inhibit H X 1 1. Used to mask write data; provided coincident with the corresponding data. REV 1.1 11/2004 54 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Operating Conditions Absolute Maximum Ratings Symbol Rating Units Notes Voltage on VDD pin relative to VSS -1.0 to + 2.3 V 1 VDDQ Voltage on VDDQ pin relative to VSS -0.5 to + 2.3 V 1 VDDL Voltage on VDDL pin relative to VSS -0.5 to + 2.3 V 1 VIN, VOUT Voltage on any pin relative to VSS -0.5 to + 2.3 V 1 Storage Temperature -55 to + 100 C 1, 2 VDD TSTG Parameter 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. DRAM Component Operating Temperature Range Symbol TOPER Parameter Operating Temperature Rating Units Notes 0 to 85 oC 1, 2 1. Operating Temperature is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all other specifcation parameters. 3. Outside of this temperature range, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. 4. Some application may require to operate the DRAM up to 95oC case temperature. In this case above 85oC case temperature the Auto-Refresh command frequency has to be reduced to tREFI = 3.9 s and some AC timing parameter will reach or exceed their specified limit values. 5. Self-Refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the DRAM is below 85 oC case temperature before initiating self-refresh operation. REV 1.1 11/2004 55 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM AC & DC Operating Conditions DC Operating Conditions Recommended DC Operating Conditions (SSTL_18) Rating Symbol Parameter Units Notes 1.9 V 1 1.8 1.9 V 1 1.7 1.8 1.9 V 1 Input Reference Voltage 0.49 * VDDQ 0.5 * VDDQ 0.51 * VDDQ V 2, 3 Termination Voltage VREF - 0.04 VREF VREF + 0.04 V 4 Min. Typ. Max. Supply Voltage 1.7 1.8 Supply Voltage for DLL 1.7 VDDQ Supply Voltage for Output VREF VDD VDDDL VTT 1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc). 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in die dc level of VREF. ODT DC Electrical Characteristrics: Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 1 Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 150 ohm Rtt2(eff) 120 150 180 1 Deviation of VM with respect to VDDQ / 2 delta VM - 3.75 + 3.75 % 2 1) Measurement Definition for Rtt(eff): Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Defintion for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =(( 2* VM / VDDQ) - 1 ) x 100% REV 1.1 11/2004 56 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterisation. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care. Single-ended DC & AC Logic Input Levels Symbol Parameter VIH (dc) DC input logic high VIL (dc) DC input low VIH (ac) AC input logic high VIL (ac) AC input low Min. Max. Units VREF + 0.125 VDDQ + 0.3 V - 0.3 VREF - 0.125 V VREF + 0.250 - V - VREF - 0.250 V Single-ended AC Input Test Conditions Symbol Value Units Notes Input reference voltage 0.5 * VDDQ V 1, 2 VSWING(max) Input signal maximum peak to peak swing 1.0 V 1, 2 1.0 V / ns 3, 4 VREF SLEW Condition Input signal minimum slew rate 1. This timing and slew rate definition is valid for all single-ended signls execpt tis, tih, tds, tdh. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure. 4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Start of Falling Edge Input Timing Start of Rising Edge Input Timing VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VIL(ac) max VSS delta TF Falling Slew = delta TR VIH (dc) min - V IL(ac) max Rising Slew = delta TF REV 1.1 11/2004 VIH(ac) min - VIL(dc) max delta TR 57 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Differential DC and AC Input and Output Logic Levels Symbol Parameter min. max. Units Notes VIN(dc) DC input signal voltage -0.3 VDDQ + 0.3 1 VID(dc) DC differential input voltage 0.25 VDDQ + 0.6 2 VID(ac) AC differential input voltage 0.5 VDDQ + 0.6 V 3 VIX(ac) AC differential cross point input voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 4 VOX(ac) AC differential cross point output voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 5 notes: 1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS,etc. 2) VID(dc) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). 3) VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). 4) The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross. VDDQ VTR Crossing Point VID VCP VIX or VOX VSSQ SSTL18_3 REV 1.1 11/2004 58 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Output Buffer Levels Output AC Test Conditions Symbol Parameter SSTL_18 Class II Units VOH Minimum Required Output Pull-up under AC Test Load VTT + 0.603 V VOL Maximum Required Output Pull-down under AC Test Load VTT - 0.603 V VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V Notes 1 1. The VDDQ of the device under test is referenced. Output DC Current Drive Symbol Parameter Class II Units Notes IOH Output Minimum Source DC Current, nominal -13.4 mA 1, 3, 4 IOL Output Minimum Sink DC Current, nominal 13.4 mA 2, 3, 4 1. VDDQ = 1.7 V ; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V ; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. OCD Default Setting Table Symbol Description min. nominal max. Unit 12.6 18 23.4 Ohms 1,2 - 4 Ohms 1,2, 3 Ohms 6 V / ns 1, 4, 5 - Output Impedance - Pull-up / Pull down mismatch 0 - Output Impedance step size for OCD calibration 0 Sout Output Slew Rate 1.5 1.5 - 5.0 Notes 1) Absolute Specification: 0 C TCASE 85 C ; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V. 2) Impedance measurement condition for output source dc current : VDDQ = 1.7V, VOUT = 1420 mV; (VOUT-VDDQ)/IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current : VDDQ = 1.7 V; VOUT = -280mV; VOUT / IOL must be less than 23.4 ohms for values of VOUT between 0V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. 4) Slew rates measured from Vil(AC) to Vih(AC) with the load specified in Section 8.2. 5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterisation. 6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 +/- 0.75 ohms under nominal conditions. REV 1.1 11/2004 59 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Default Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A7~A9 = '111'. Figures in Section 5.3.5 and 5.3.6 show the driver characteristics graphically and the tables sow the same data suitable for input into simulation tools. Full Strength Default Pullup Driver Characteristics Voltage (V) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Minimum (23.4 Ohms) Nomal Default low (18 Ohms) Nomal Default high (18 Ohms) Maximum (12.6 Ohms) -8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6 -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6 -11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8 -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1 The driver characteristics evaluetion conditions are: Nominal Default 25oC (Tcase) , VDDQ = 1.8 V, typical process Minimum Toper(max.), VDDQ = 1.7V, slow-slow process Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process 0 Pullup current (mA) -20 -40 Minimum Nominal Default Low Nominal Default High Maximum -60 -80 -100 -120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VDDQ to VOUT (V) REV 1.1 11/2004 60 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Full Strength Default Pulldown Driver Characteristics Voltage (V) Minimum (23.4 Ohms) Nomal Default low (18 Ohms) Nomal Default high (18 Ohms) Maximum (12.6 Ohms) 8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.4 52.6 54.2 55.9 57.1 58.4 59.6 60.9 15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 The driver characteristics evaluetion conditions are: Nominal Default 25oC (Tcase) , VDDQ = 1.8 V, typical process Minimum Toper(max), VDDQ = 1.7V, slow-slow process Maximum 0 oC (Tcase). VDDQ = 1.9 V, fast-fast process Pulldown current (mA) 120 100 80 Minimum Nominal Default Low Nominal Default High Maximum 60 40 20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOUT to VSSQ (V) REV 1.1 11/2004 61 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedire, 1.5 ohm maximum step size guarantedd by specification). Real system calibration error needs to be added to these values. It must be understodd that these V-I curves are represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characterisitcs tables and figure. in such a situation, the timing paramters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy and uncertainty with DQ to DQ variation, the it is recommende that only the default values to be used. The nominal maximum ad minmum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. Full Strength Calibrated Pulldown Driver Characteristics Nominal Minimum (21 Ohms) Nomal Low (18.75 Ohms) Nominal (18 ohms) Nomal High (17.25 Ohms) Nominal Maximum (15 Ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 Voltage (V) The driver characteristics evaluetion conditions are: Nominal 25oC (Tcase) , VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum Toper(max), VDDQ = 1.7 V, any process Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process Full Strength Calibrated Pullup Driver Characteristics Nominal Minimum (21 Ohms) Nomal Low (18.75 Ohms) Nominal (18 ohms) Nomal High (17.25 Ohms) Nominal Maximum (15 Ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.5 -17.4 -20.0 0.4 -18.3 -21.0 -21.2 -23.0 -27.0 Voltage (V) The driver characteristics evaluetion conditions are: Nominal 25oC (Tcase) , VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25oC (Tcase), VDDQ = 1.8V, any process Nominal Minimum Toper(max), VDDQ = 1.7 V, any process Nominal Maximum 0oC (Tcase), VDDQ = 1.9 V, any process REV 1.1 11/2004 62 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Input / Output Capacitance Symbol CCK CDCK CI Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins min. max. Units 1.0 2.0 pF - 0.25 pF 1.0 2.0 pF - 0.25 pF CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 3.0 4.0 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS - 0.5 pF Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A0~A13, BA0, BA1), RAS, CAS, CS, WE, CKE and ODT pins. The V-I characterisitcs for pins with clamps is shown in the following table : REV 1.1 11/2004 Voltage across clamp (V) Minimum Power Clamp Current (mA) Minimum Ground Clamp Current (mA) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 63 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM IDD Specifications and Measurement Conditions IDD Specifications ( VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) Symbol Parameter/Condition I/O -5 DDR2 -400 -3.7 DDR2 -533 typ. max. typ. max. Unit Notes IDD0 Operating Current x4/ x8 x16 55 60 65 70 60 65 70 75 mA 1, 2 IDD1 Operating Current x4/ x8 x16 60 65 70 75 65 75 80 90 mA 1, 2 IDD2P Precharge Power-Down Current all 2 3 3 4 mA 1, 2 IDD2N Precharge Standby Current all 24 28 30 36 mA 1, 2 IDD2Q Precharge Quiet Standby Current: all 14 19 18 25 mA 1, 2 Active Power-Down MRS(12)=0 IDD3P Standby MRS(12)=1 Current all 8 11 10 15 mA 1, 2 all 3 5 3 5 mA 1, 2 IDD3N Active Standby Current x4/x8 x16 26 27 31 33 33 35 40 42 mA 1, 2 IDD4R Operating Current Burst Read x4/ x8 x16 60 80 70 95 75 90 90 110 mA 1, 2 IDD4W Operating Current Burst Write x4/ x8 x16 65 80 75 95 80 95 90 110 mA 1, 2 Burst Auto-Refresh Current IDD5B (tRFC=tRFCmin) x4/ x8 x16 105 110 125 130 110 115 135 150 mA 1, 2 all 2.6 5.5 2.6 5.5 mA 1, 2 Distributed Auto-Refresh Current IDD5D (tRFC=tREFI) IDD6 Self-Refresh Current for standard products x4/ x8 x16 2 3 2 3 mA 1, 2 IDD7 Operating Current x4/ x8 x16 150 180 175 200 160 190 185 210 mA 1 1. IDD specifications are tested after the device is properly initialized. IDD parameters are specified with ODT disabled. 2. Input slew rate = 1 V/ns. REV 1.1 11/2004 64 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM IDD Measurement Conditions ( VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) Symbol Parameter/Condition IDD0 Operating Current - One bank Active - Precharge tCK =tCKmin.; tRC = tRCmin; tRAS = tRASmin; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING; Data bus inputs are SWITCHING; IDD1 Operating Current - One bank Active - Read - Precharge IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL = 0; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus inputs are SWITCHING; IDD2P Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE, Data Bus inputs are FLOATING. IDD2N Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are SWICHTING; Data bus inputs are SWITCHING. IDD2Q Precharge Quiet Standby Current:All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. IDD3P(0) Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit); IDD3P(1) Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit); IDD3N Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH; CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD4R Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. IDD4W Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD5B Burst Auto-Refresh Current: tCK = tCKmin.; Refresh command every tRFC = tRFCmin interval; CKE is HIGH, CS is HIGH between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING. IDD5D Distributed Auto-Refresh Current: tCK = tCKmin.; Refresh command every tREFI interval; CKE is HIGH, CS is HIGH between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING IDD6 Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING. Operating Bank Interleave Read Current: IDD7 1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin., tRC = TRCmin.; tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTS. 2. Timing pattern: - DDR2 -400 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D - DDR2 -533 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D - DDR2 -667 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D 3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT 1. 2. 3. 4. IDD specifications are tested after the device is properly initialized. IDD parameter are specified with ODT disabled. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD : LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.); STABLE is defined as inputs are stable at a HIGH or LOW level FLOATING is defined as inputs are VREF = VDDQ / 2 SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control signals, and inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including mask or strobes 5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table. REV 1.1 11/2004 65 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM IDD Measurement Conditions (cont'd) For testing the IDD parameters, the following timing parameters are used: Parameter Symbol -5 DDR2 -400 -3.7 DDR2 -533 3-3-3 4-4-4 Unit CAS Latency CLmin 3 4 tCK Clock Cycle Time tCKmin 3 3.75 ns tRCDmin 15 15 ns tRCmin 60 60 ns x4 & x8 tRRDmin 7.5 7.5 ns x16 tRRDmin 10 10 ns ns Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period tRASmin 45 45 tRASmax 70000 70000 ns tRPmin 15 15 ns tRFCmin 105 105 ns tREFI 7.8 7.8 s Average periodic Refresh interval ODT (On Die Termination) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-strate or driving "0" or "1", as long a ODT is enabled during a given period of time. ODT current per terminated input pin : Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. IODTO IODTT EMRS(1) State min. typ. max. Unit A6 = 0, A2 = 1 5 6 7.5 mA/DQ A6 = 1, A2 = 0 2.5 3 3.75 mA/DQ A6 = 0, A2 = 1 10 12 15 mA/DQ A6 = 1, A2 = 0 5 6 7.5 mA/DQ note: For power consumption calculations the ODT duty cycle has to be taken into account REV 1.1 11/2004 66 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Electrical Characteristics & AC Timing - Absolute Specification Timing Parameter by Speed Grade ( VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) (notes 1-4) Symbol Unit Notes max min max DQ output access time from CK / CK - 600 + 600 -500 +500 ps DQS output access time from CK / CK - 500 + 500 -450 +450 ps tCH CK, CK high-level width 0.45 0.55 0.45 0.55 tCK tCL CK, CK low-level width 0.45 0.55 0.45 0.55 tCK tHP Clock half period tCK Clock cycle time tIS tDQSCK min (tCL, tCH) min (tCL, tCH) 5 CL = 3 5000 8000 5000 8000 ps 6 CL = 4 & 5 5000 8000 3750 8000 ps 6 Address and control input setup time 350 - 250 - ps 7 tIH Address and control input hold time 475 - 375 - ps 7 tDH DQ and DM input hold time 150 - 100 - ps 8 tDS DQ and DM input setup time 275 - 225 - ps 8 tIPW Address and control input pulse width (each input) 0.6 - 0.6 - tCK tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK - tACmax - tACmax ps 9 tACmin tACmax tACmin tACmax ps 9 DQS-DQ skew (for DQS & associated DQ signals) - 350 - 300 ps tQHS Data hold skew factor - 450 - 400 ps tQH Data output hold time from DQS tHP-tQHS - tHP-tQHS - tHZ Data-out high-impedence time from CK / CK tLZ Data-out low-impedence time from CK / CK tDQSQ 11/2004 Parameter -3.7 DDR2 -533 min tAC REV 1.1 -5 DDR2 -400 tDQSS Write command to 1st DQS latching transition WL -0.25 WL +0.25 WL -0.25 WL +0.25 tCK tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tWPRES Write preamble setup time 0 - 0 - ps tWPRE Write preamble 0.25 - 0.25 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 10 tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 9 tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 9 tRAS Active to Precharge command 45 70000 45 70000 ns 11 tRC Active to Active/Auto-Refresh command period 60 - 60 - ns tRFC Auto-Refresh to Active/Auto-Refresh command period 105 - 105 - ns 12 67 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Symbol -5 DDR2 -400 Parameter -3.7 DDR2 -533 Unit Notes min max min max Active to Read or Write (with and without Auto-Precharge) delay 15 - 15 - ns tRP Precharge command period 15 - 15 - ns Active bank A to Active bank B command period x4 & x8 (1k page size) 7.5 - 7.5 - ns tRRD x16 (2k page size) 10 - 10 - ns tRCD tCCD CAS A to CAS B command period 2 tWR Write recovery time 15 tDAL 2 13 tCK - 15 - ns Auto-Precharge write recovery + precharge time WR+tRP - WR+tRP - tCK 14 tWTR Internal Write to Read command delay 10 - 7.5 - ns 15 tRTP Internal Read to Precharge command delay 7.5 - 7.5 - ns 2 - 2 - tCK 16 6 - AL - 6 - AL - tCK 16 2 - 2 - tCK 200 - 200 - tCK tXARD Exit power down to any valid command (other than NOP or Deselect) tXARDS Exit active power-down mode to Read command (slow exit, lower power) tXP Exit precharge power-down to any valid command (other than NOP or Deselect) tXSRD Exit Self-Refresh to Read command tXSNR Exit Self-Refresh to non-Read command tRFC+10 - tRFC+10 tCKE CKE minimum high and low pulse width 3 - 3 - tCK tREFI Average periodic refresh Interval - 7.8 - 7.8 s tOIT OCD drive mode output delay 0 12 0 12 ns tIS+tCK +tIH - tIS+tCK +tIH - ns tDELAY Minimum time clocks remain ON after CKE asynchronously drops LOW ns 17 Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restartet through the specified initialization sequence before normal operation can continue. REV 1.1 11/2004 68 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Symbol Parameter / Condition tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power-Down Modes) tAOFD ODT turn-off delay tAOF ODT turn-off min. max. Units 2 2 tCK tAC(min) tAC(max) + 1ns ns tAC(min) + 2ns 2 tCK + tAC(max) + 1ns ns 2.5 2.5 tCK tAC(min) tAC(max) + 0.6ns ns tAC(min) + 2ns 2.5 tCK + tAC(max) + 1ns ns tAOFPD ODT turn-off (Power-Down Modes) tANPD ODT to Power Down Mode Entry Latency 3 - tCK tAXPD ODT Power Down Exit Latency 8 - tCK REV 1.1 11/2004 Notes 18 19 69 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Notes for Electrical Characteristics & AC Timing 1. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. For other slew rates see Section 8 of this datasheet. 2. The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS, tIS, tiH,tDS, tDH is VREF. For tIS, tiH, tDS, tDH input reference levels see section 8.3 of this datasheet 3. Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW. 4. The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements. 5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH. 6. For input frequency change during DRAM operation, see the 2.11 section of this datasheet. 7. For timing definition, slew rate and slew rate derating see Section 8.3 8. For timing definition, slew rate and slew rate derating see Section 8.3 9. The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are guaranteed by design and characterisation, but are not tested on each device. 10. The maximum limit for this parameter is not a device limit. The device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 11. tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 * tREFI 12. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 13. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter tRAP for activate command to read or write command with Auto-Precharge is not neccessary anymore. 14. For each of the terms, if not allready an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 15. tWTR is at least two clocks independent of operation frequency. 16. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active power-down mode" (MRS, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active powerdown mode" (MRS, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 17. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during power-down, a specific procedure is required as describes in section 2.12. 18. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 19. ODT turn off time min is when the device starts to turn off ODT resistance ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. REV 1.1 11/2004 70 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating Reference Load for Timing Measurements The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterisation. VDDQ CK, CK DUT DQ DQS DQS RDQS RDQS 25 Ohm Vtt = VDDQ / 2 Timing Reference Points The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true ( e.g. DQS) and the complement (e.g. DQS) signal. Slewrate Measurements Output Slewrate With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. Input Slewrate - Differential signals Input slewrate for differential signals ( CK / CK, DQS / DQS, RDQS / RDQS) for rising edges are measured from f.e. CK - CK = -250 mV to CK - CK = + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling edges. Input Slewrate - Single ended signals Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: VREF -125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges. For slew rate definition of the input and data setup and hold parameters see section 8.3 of this datasheet. REV 1.1 11/2004 71 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Input and Data Setup and Hold Time Timing Definition for Input Setup (tIS) and Hold Time (tIH) Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test CK CK t IS t t IH IS t IH V DDQ V IH(ac) min V IH(dc) min V REF V IL(dc) max V IL(ac) max V SS Timing Definition for Data Setup (tDS) and Hold Time (tDH) DQS Differential Input Waveform DQS Single-ended Input Waveform DQS V REF t DS t DH t t DS DH VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS 1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level tothe differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-endeddata strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing Vref for a falling signal applied to the device under test. 2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under test REV 1.1 11/2004 72 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Slew Rate Definition for Input and Data Setup and Hold Times Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, (fig. A) If the actual signal is always earlier than the nominal slew rate line between shaded `dc to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `dc to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(fig.B) Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref.(fig. A). If the actual signal is always later than the nominal slew rate line between shaded `dc to Vref region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to Vref region', the slew rate of a tangent line to the actual signal from the dc level to Vref level is used for derating value.(fig.B) t t S t H S t t H S t t H S t H VDDQ VIH(ac) min dc to ac region VIH(ac) min dc to ac region VIH(dc) min VIH(dc) min dc to Vref region dc to Vref region VREF VREF dc to Vref region dc to Vref region VIL(dc) max dc to ac region Delta TFS Delta TRH Delta TRS Delta TFS VIH(dc)min - VIL(ac)min Setup Slew Rate = Delta TRS VREF - VIL(dc)max = Delta TRH VIH(dc)min - VREF Hold Slew Rate = Delta TFH VIL(ac) max VIL(ac) max VSS VSS Delta TFS falling signal rising signal rising signal falling signal 11/2004 Delta TRH Delta TRS Delta TFH tangent line [VIL(dc)max - VIL(ac)max] Setup Slew Rate = Delta TFS tangent line [VIH(dc)min - VIL(ac)min] Setup Slew Rate = Delta TRS tangent line [REF - VIL(dc)max] Hold Slew Rate = Delta TRH tangent line [VIH(dc)min - VREF] Hold Slew Rate fig. A REV 1.1 VIL(dc) max dc to ac region Delta TFH VIL(dc)max - VIL(ac)max Setup Slew Rate = Hold Slew Rate VDDQ = Delta TFH falling signal rising signal rising signal falling signal fig. B 73 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Input Setup (tIS) and Hold (tIH) Time DeratingTable CK, CK Differential Slew Rate 1.5 V/ns Command / Address Slew rate 2.0 V/ns 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 tIS tIH 187 179 167 150 125 83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450 94 89 83 75 45 21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS 217 209 197 180 155 113 30 19 5 -13 -37 -80 -145 -255 -320 -495 -770 -1420 tIH 124 119 113 105 75 51 30 16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 1.0 V/ns tIS 247 239 227 210 185 143 60 49 35 17 -7 -50 -115 -225 -290 -465 -740 -1390 tIH 154 149 143 135 105 81 60 46 29 6 -23 -65 -128 -232 -315 -440 -648 -1065 1. All units in ps. 2. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table. Data Setup (tDS) and Hold Time (tDH) Derating Table DQS, DQS Differential Slew Rate DQ Slewrate (V/ns) 4.0 V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 tDS 125 83 0 - tDH 45 21 0 - 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS 125 83 0 -11 - 45 21 0 -14 - 125 83 45 21 95 12 1 -13 -31 - 93 12 -2 -19 -42 - 24 13 -1 -19 -43 - 24 10 -7 -30 -49 - 25 11 -7 -31 -74 - 22 5 -18 -47 -89 - 23 17 5 -6 17 6 -19 -35 -7 -23 5 -11 -62 -77 -50 -65 -38 -53 -127 -140 -115 -128 -103 -116 0 0 -14 -31 - tDS tDH 0.8 V/ns tDS -11 -25 - tDH 1.0 V/ns tDS tDH 1. All units in ps. 2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table. REV 1.1 11/2004 74 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Overshoot and Undershoot Specification AC Overshoot / Undershoot Specification for Address and Control Pins DDR2 -400 DDR2 -533 Units Maximum peak amplitude allowed for overshoot area 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 V Maximum overshoot area above VDD 0.75 0.56 V.ns Maximum undershoot area below VSS 0.75 0.56 V.ns Parameter Maximum Amplitude Volts (V) Overshoot Area VDD VSS Maximum Amplitude Undershoot Area Time (ns) AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins DDR2 -400 DDR2 -533 Units Maximum peak amplitude allowed for overshoot area 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 V Maximum overshoot area above VDDQ 0.38 0.28 V.ns Maximum undershoot area below VSSQ 0.38 0.28 V.ns Parameter Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) REV 1.1 11/2004 75 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Package Dimensions (60 balls; 0.8mmx0.8mm Pitch; CSP Package) 10.0 8.0 10.5 0.80 0.80 Dia. 0.40 0.35 0.10 1.15 Note : All dimensions are typical unless otherwise stated. Unit : Millimeters REV 1.1 11/2004 76 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Package Dimensions (84 balls; 0.8mmx0.8mm Pitch; CSP Package) 10.0 11.2 12.5 0.80 0.80 Dia. 0.40 0.35 1.15 0.10 Note : All dimensions are typical unless otherwise stated. Unit : Millimeters REV 1.1 11/2004 77 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM Revision Log Rev Date 0.1 08/2003 Preliminary Release 1.0 09/2004 Added Idd to specification 1.1 11/2004 Added derating values and x4/x8 60 balls and 84 balls pin configuration REV 1.1 11/2004 Modification 78 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU128M4AB NT5TU64M8AF/NT5TU64M8AB NT5TU32MHAF 512Mb DDR2 SDRAM (R) Nanya Technology Corporation. All rights reserved. Printed in Taiwan, R.O.C., 2004 The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both. NANYA NANYA logo Other company, product and service names may be trademarks or service marks of others. NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com REV 1.1 11/2004 79 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.